WO2023084180A1 - Ensemble de circuits pour compenser un décalage de gain et/ou de phase entre des chemins de surveillance de tension et de courant - Google Patents

Ensemble de circuits pour compenser un décalage de gain et/ou de phase entre des chemins de surveillance de tension et de courant Download PDF

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Publication number
WO2023084180A1
WO2023084180A1 PCT/GB2022/052395 GB2022052395W WO2023084180A1 WO 2023084180 A1 WO2023084180 A1 WO 2023084180A1 GB 2022052395 W GB2022052395 W GB 2022052395W WO 2023084180 A1 WO2023084180 A1 WO 2023084180A1
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WIPO (PCT)
Prior art keywords
circuitry
monitoring path
compensation
impedance
voltage
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PCT/GB2022/052395
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English (en)
Inventor
Ryan A Hellman
Viral Parikh
Siddharth MARU
Tejasvi Das
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Cirrus Logic International Semiconductor Limited
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Priority claimed from US17/690,327 external-priority patent/US11644521B1/en
Application filed by Cirrus Logic International Semiconductor Limited filed Critical Cirrus Logic International Semiconductor Limited
Priority to GB2402495.2A priority Critical patent/GB2626678A/en
Publication of WO2023084180A1 publication Critical patent/WO2023084180A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R29/00—Monitoring arrangements; Testing arrangements
    • H04R29/001—Monitoring arrangements; Testing arrangements for loudspeakers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/007—Protection circuits for transducers

Definitions

  • the present disclosure relates to circuitry comprising voltage and current monitoring paths.
  • Driver circuitry for driving loads such as audio transducers (e.g. speakers) or haptic transducers (e.g. actuators such as linear resonant actuators) often includes voltage detection (VMON) and current detection (IMON) circuit blocks, for detecting, respectively, a voltage across the load and a current through the load while the transducer is being driven by a playback signal such as an audio signal or a haptic waveform.
  • VMON voltage detection
  • IMON current detection
  • a playback signal is a drive signal that drives the transducer to generate a desired output such as an audio or haptic output.
  • the detected voltage and current can be used to calculate, estimate or otherwise determine an impedance of the transducer, which may be a complex impedance having resistive, inductive and capacitive components.
  • the determined impedance may be used in applications such as speaker protection while the playback signal is being provided to the transducer.
  • Figure 1 is a schematic diagram showing an example of circuitry that includes voltage and current monitoring paths for monitoring a voltage across a load and a current through the load during operation of the circuitry to drive the load.
  • the circuitry which may be implemented as an integrated circuit (IC), is shown generally at 100 in Figure 1.
  • the circuitry 100 includes driver circuitry 110 configured to receive an input signal and to output a drive signal for driving a load 120 external to the IC.
  • the driver circuitry 110 may comprise pulse width modulator (PWM) circuitry and class D amplifier circuitry
  • PWM pulse width modulator
  • the load 120 which in this example is represented by a series combination of an inductor and a resistor, may be a transducer such as a speaker, an actuator (e.g. a resonant actuator such as a linear resonant actuator) or the like.
  • the circuitry 100 includes first and second terminals (e.g. contact pins, pads, balls or the like) 112, 114 for coupling the circuitry 100 to the external load 120.
  • first terminal 112 is coupled to the output of the driver circuitry 110 and the second terminal 114 is coupled to a first terminal of a current sense resistor 130, such that when the load 120 is coupled to the first and second terminals 112, 114, the load 120 is coupled in series between the output of the driver circuitry 110 and the current sense resistor 130.
  • a voltage monitoring path 140 is coupled to the load 120.
  • the voltage monitoring path 140 comprises analog front end (AFE) circuitry 142 having inputs that are coupled in parallel with the load 120 and an output that is coupled to an input of analog to digital converter (ADC) circuitry 144.
  • AFE analog front end
  • ADC analog to digital converter
  • FIG. 1 An output of the ADC circuitry 144 of the voltage monitoring path 140 is coupled to a first input of processing circuitry 150.
  • the current sense resistor 130 is coupled in series with the load 120 (when the load 120 is coupled to the first and second terminals 112, 114). In the illustrated example the current sense resistor 130 is connected in series between the load 120 and common mode buffer circuitry 160, but it will be appreciated that in some examples the common mode buffer circuitry 160 may be omitted, in which case the current sense resistor 130 may be coupled in series between the load and a ground or Ov supply node or rail.
  • a current monitoring path 170 is coupled to the current sense resistor 130.
  • the current monitoring path 170 comprises analog front end (AFE) circuitry 172 having inputs that are coupled in parallel with the current sense resistor 130 and an output that is coupled to an input of analog to digital converter (ADC) circuitry 174.
  • AFE analog front end
  • ADC analog to digital converter
  • FIG. 1 An output of the ADC circuitry 174 of the current monitoring path 170 is coupled to a second input of the processing circuitry 150.
  • a reference signal of a predefined frequency and amplitude is supplied to the driver circuitry 110 to drive the load 120.
  • the reference signal may be, for example, a sinusoidal voltage waveform of a predefined peak-to-peak amplitude and a predefined frequency, and may be generated by reference signal generator circuitry 180, or alternatively may be a stored signal that is retrieved from memory or the like.
  • the voltage monitoring path 140 outputs a signal (e.g. a voltage) V mO n indicative of the voltage across the load 120 to the processing circuitry 150, and the current monitoring path 170 outputs a signal (e.g. a voltage) l mO n indicative of the current through the load 120.
  • the processing circuitry 150 generates an estimate Z es tof the impedance of the load 120 based on the signals V mO n, Imon received from the voltage monitoring path 140 and the current monitoring path 170 respectively. Additionally, the processing circuitry 150 may generate individual estimates for the resistance and reactance of the load 120 using amplitude and phase information from the signals received from the voltage monitoring path 140 and the current monitoring path 170, and these estimates may be provided to downstream circuitry (not shown) for further use and/or processing.
  • the estimate Z es t of the impedance of the load 120 may be used for a wide range of purposes during normal operation of the circuitry 100 to drive the load based on a drive signal output by the driver circuitry 110.
  • the estimated impedance Z es t may be used, in combination with one or both of the signals V mO n, Imon, for estimating the position of a moving mass of the linear resonant actuator.
  • the load 120 is a speaker the estimated impedance Z es t may be used, in combination with one or both of the signals V mO n, Imon, in a speaker protection system to prevent damage to the speaker by limiting its excursion.
  • the invention provides circuitry comprising: a voltage monitoring path; a current monitoring path; a reference element of a predefined impedance; and processing circuitry, wherein in operation of the circuitry in a calibration mode of operation: the voltage monitoring path is operative to output a signal indicative of a voltage across the reference element in response to a reference signal applied to the reference element; the current monitoring path is operative to output a signal indicative of a current through the reference element in response to the reference signal; an the processing circuitry is operative to: receive the signal indicative of the voltage across the reference element and the signal indicative of the current through the reference element; generate an estimate of an impedance of the reference element; and determine a compensation parameter for an element of the circuitry for compensating for a difference between the estimate of the impedance and the predefined impedance of the reference element.
  • the circuitry may be configured to apply the compensation parameter in operation of the circuitry in a load driving mode of operation.
  • the compensation parameter may be a frequency domain compensation parameter.
  • the processing circuitry may comprise: a first conversion block for converting the signal indicative of the voltage across the reference element into a first frequency domain complex vector; and a second conversion block for converting the signal indicative of the current through the reference element into a second frequency domain complex vector.
  • the processing circuitry may comprise a calculation block configured to generate the estimate of the impedance of the reference element based on the first and second frequency domain complex vectors and to compare the generated estimate to the predefined impedance of the reference element.
  • the circuitry may further comprise a compensation block configured to apply the compensation parameter to the first frequency domain complex vector or the second frequency domain complex vector.
  • the calculation block may be configured to calculate a gain mismatch p by dividing a ratio of the magnitude of the first complex vector to the magnitude of the second complex vector by the magnitude of the predefined impedance, and to calculate a phase mismatch ⁇ t> by subtracting the phase of a ratio of the first complex vector to the second complex vector from the phase of the predefined impedance.
  • the calculation block may be configured to calculate a first compensation coefficient BR and a second compensation coefficient Bi, where: and the compensation parameter may comprise a compensation vector comprising the first and second compensation coefficients.
  • the compensation parameter may comprise a compensation vector comprising first and second temperature-dependent compensation coefficients.
  • the calculation block may be configured to select the first and second temperaturedependent compensation coefficients based on a detected temperature.
  • the temperature-dependent compensation coefficients may comprise predefined polynomials.
  • the compensation parameter may be a time domain compensation parameter.
  • the compensation parameter may comprise a parameter of an analog element of the voltage monitoring path or the current monitoring path.
  • the voltage monitoring path and the current monitoring path may each comprise analog front end (AFE) circuitry and analog to digital converter (ADC) circuitry.
  • AFE analog front end
  • ADC analog to digital converter
  • the compensation parameter may comprise a parameter of the AFE circuitry or the ADC circuitry.
  • the compensation parameter may comprise one or more of: a resistance of a resistor of filter circuitry of the AFE circuitry of the voltage monitoring path or the current monitoring path; a capacitance of a capacitor of filter circuitry of the AFE circuitry of the voltage monitoring path or the current monitoring path; and a transconductance of amplifier circuitry of the AFE circuitry of the voltage monitoring path or the current monitoring path.
  • the compensation parameter may comprise one or more of: a resistance of a resistor of a feedback network of amplifier circuitry of the AFE circuitry of the voltage monitoring path or the current monitoring path; and a reference voltage for the ADC circuitry of the voltage monitoring path or the current monitoring path.
  • the circuitry may be configured to apply the compensation parameter in operation of the circuitry in the compensation mode of operation.
  • the processing circuitry may be operative to: with the compensation parameter applied, generate an estimate of an impedance of the reference element; and compare the estimate of the impedance and the predefined impedance of the reference element.
  • the reference element may comprise a tantalum nitride resistor.
  • the circuitry may further comprise load selector circuitry for selectively coupling the voltage and current monitoring paths to the reference element or to a load according to the mode of operation of the circuitry.
  • the load selector circuitry may comprise a controllable switch network.
  • the current monitoring path may comprises a plurality of selectable current sense resistors.
  • the processing circuitry may be operative to determine a first compensation parameter with a first one of the plurality selectable current sense resistors selected
  • the processing circuitry may be operable to: generate a first estimate of an impedance of a load coupled to the circuitry with the first one of the plurality selectable current sense resistors selected; and determine a second compensation parameter if a second estimate of the impedance of the load generated by the processing circuitry with a second one of the of the plurality of selectable current sense resistors selected differs from the first estimate of the impedance of the load.
  • the invention provides an integrated circuit comprising circuitry according to the first aspect.
  • the invention provides a host device comprising circuitry according to the first aspect, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
  • the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
  • Figure 1 is a schematic representation of circuitry including voltage and current monitoring paths
  • Figure 2 is a schematic representation of circuitry including voltage and current monitoring paths and compensation circuitry for compensating for gain and/or phase mismatch between the voltage and current monitoring paths;
  • Figure 3 is a schematic representation of circuitry including voltage and current monitoring paths and alternative compensation circuitry for compensating for gain and/or phase mismatch between the voltage and current monitoring paths;
  • FIG. 4 is a is a schematic diagram illustrating example analog front end (AFE) circuitry for the voltage and/or current monitoring path of the circuitry of Figure 3;
  • AFE analog front end
  • Figure 5 is a schematic representation of is a schematic diagram illustrating an example analog to digital converter (ADC) arrangement.
  • ADC analog to digital converter
  • an estimate Z es t of the impedance of the load 120 can be generated by the processing circuitry 150, e.g. by dividing a value of, or representing, the signal V mO n output by the voltage monitoring path 140 by a value of, or representing, the signal l mO n output by the current monitoring path 170.
  • An estimate of the resistance of the load at a given frequency 120 can be generated (e.g., by the processing circuitry 150) by taking the real part of the result of this division, i.e., Re(Vmon/lmon ) and an estimate of the inductance of the load at a given frequency 120 can be generated (e.g., by the processing circuitry 150) by taking the imaginary part of the result of this division, i.e., lrn(V m on/lmon).
  • the voltage monitoring path 140 may apply a gain to the signal received at the inputs of its AFE 142, such that the digital signal V mO n output by the voltage monitoring path 140 is a scaled digital representation of the voltage across the load 120.
  • the current monitoring path 170 may apply a gain to the signal received at the inputs of its AFE 172, such that the digital signal l mO n output by the current monitoring path 170 is a scaled digital representation of the current through the load 120.
  • the gain applied by the voltage monitoring path 140 differs from the gain applied by the current monitoring path 170 (i.e., if there is a gain mismatch between the two paths), the accuracy of the estimate Z es t of the load impedance, and the accuracy of the estimates of the load resistance and load inductance will be adversely affected, because of the different scaling applied to the voltage across the load 120 and the current through the load 120 as a result of the gain mismatch between the voltage monitoring path 140 and the current monitoring path 170.
  • Figure 2 is a schematic representation of circuitry including voltage and current monitoring paths and compensation circuitry for compensating for gain and/or phase mismatch between the voltage and current monitoring paths.
  • the circuitry shown generally at 200 in Figure 2, shares some elements in common with the driver circuitry 100 of Figure 1 , and such common elements are denoted by common reference numerals in Figures 1 and 2, and will not be described again in detail here.
  • the circuitry 200 may be implemented as an integrated circuit (I C) , for example.
  • the circuitry 200 is operable in a calibration mode and a load driving mode.
  • the circuitry 200 is operable to measure or otherwise quantify a gain and/or a phase mismatch between a voltage monitoring path 130 and a current monitoring path 170, and to compensate for any such gain and/or phase mismatch.
  • the circuitry 200 is operable to drive an external load 120 (e.g. a transducer such as a speaker or an actuator) with a drive signal, and to monitor the voltage across the load 120 and the current through the load 120.
  • an external load 120 e.g. a transducer such as a speaker or an actuator
  • the circuitry 200 includes driver circuitry 110 of the kind described above with reference to Figure 1 , configured to supply a drive signal to the load 120 during operation of the circuitry 200 in the load driving mode.
  • the circuitry 200 further includes a voltage monitoring path 140, a current sense resistor 130 and a current monitoring path 170 of the kind described above with reference to Figure 1 .
  • the circuitry 200 includes load selector circuitry 210 for selectively coupling either the first and second terminals 112, 114 (and hence the external load 120) or a reference element 220 of a predetermined known impedance to the voltage monitoring path 140 and the current sense resistor 130.
  • the load selector circuitry 210 may comprise, for example, a controllable switch network comprising switches that can be opened or closed to couple either the first and second terminals 112, 114 or the reference element 210 to the voltage monitoring path 140 and the current sense resistor 130.
  • Those skilled in the art will readily understand how to implement suitable load selector circuitry 210.
  • the reference element 220 may have a small temperature coefficient, such that its impedance changes little with temperature, and may have high stability, such that its impedance changes little over time.
  • the reference element 220 may be, for example, a tantalum nitride resistor, which may be integrated into an IC with the other elements of the compensation circuitry 200.
  • An output of the ADC circuitry 144 of the voltage monitoring path 140 is coupled to a first input of processing circuitry 230, such that in use of the circuitry 200 during its calibration mode of operation, the voltage monitoring path 140 is configured to output a digital signal Vmon indicative of the voltage across the reference element 220 to the processing circuitry 230.
  • the voltage monitoring path 140 is configured to output a digital signal output a digital signal V mO n indicative of the voltage across the load 120 to the processing circuitry 230.
  • An output of the ADC circuitry 174 of the current monitoring path 170 is coupled to a second input of the processing circuitry 230, such that in use of the circuitry 200 during its calibration mode of operation, the current monitoring path 170 is configured to output a digital signal l mO n indicative of the current through the reference element 220 to the processing circuitry 230.
  • the current monitoring path 170 is configured to output a digital signal output a digital signal Imon indicative of the current through the load 120 to the processing circuitry 230.
  • the processing circuitry 230 includes a first discrete Fourier transform (DFT) block 232, having an input that is coupled to an output of the voltage monitoring path 140, and a first amplitude/phase compensation block 234 having an input that is coupled to an output of the first DFT block 232.
  • An output of the first amplitude/phase compensation block 234 is coupled to a first input of a calculation block 250.
  • DFT discrete Fourier transform
  • the processing circuitry 230 further includes a second DFT block 242, having an input that is coupled to an output of the current monitoring path 170, and a second amplitude/phase compensation block 244 having an input that is coupled to an output of the second DFT block 242.
  • An output of the second amplitude/phase compensation block 234 is coupled to a second input of the calculation block 250.
  • the compensation circuitry 200 further includes reference signal generator circuitry 260, which in this example is configured to generate a digital reference signal.
  • An output of the reference signal generator circuitry 260 is coupled to an input of digital to analog converter (DAC) circuitry 270, which is configured to convert the digital reference signal into an analog reference signal.
  • An output of the DAC circuitry 270 is coupled to a first terminal of the reference element 220, such that the DAC circuitry 270 supplies the analog reference signal to the reference element 220.
  • DAC digital to analog converter
  • the load selector circuitry 210 couples the reference element 220 to the voltage monitoring path 140 and the current sense resistor 130.
  • the reference signal generator circuitry 260 generates a digital reference signal (e.g. a digital representation of a sinusoid) of known amplitude and frequency, which is converted into an analog reference signal by the DAC circuitry 270 and applied to the reference element 220.
  • a digital signal V mO n representing a voltage across the reference element 220 as a result of the applied reference signal is generated by the voltage monitoring path 140 and output to the first DFT block 232.
  • the first DFT block 232 converts the digital time domain signal V mO n into a frequency domain signal VmonDFT, which is output to the first amplitude/phase compensation block 234.
  • a digital signal l mO n representing a current through the reference element 220 as a result of the applied reference signal is generated by the current monitoring path 170 and output to the second DFT block 242.
  • the second DFT block 242 converts the digital time domain signal l mO n into a frequency domain signal ImonDFT, which is output to the second amplitude/phase compensation block 244.
  • the calculation block 250 receives the frequency domain signals VmonDFT, ImonDFT output by the first and second amplitude/phase compensation blocks 234, 244 and, based on these received signals, calculates an estimate Z es t of the impedance of the reference element 220. The calculation block 250 then compares this estimate of the impedance of the reference element 220 to the predefined impedance Zknown of the reference element 220. If the calculated estimate of the impedance is equal to the predefined impedance (or is within a defined tolerance range around the predefined impedance), the calculation block 250 may determine that there is no gain or phase mismatch between the voltage monitoring path 140 and the current monitoring path 170 and thus that no compensation is required.
  • the calculation block 250 may determine that there is a gain and/or a phase mismatch between the voltage monitoring path 140 and the current monitoring path 170 and thus that compensation is required.
  • the calculation block 250 determines, during operation of the circuitry 200 in its calibration mode, compensation coefficients to be applied by the first and/or the second gain and phase compensation blocks 234, 244 during operation of the circuitry 200 in its load driving mode.
  • the first DFT block 232 generates a frequency domain representation VmonDFT of the digital time domain signal V mO n.
  • the calculation block 250 calculates a complex impedance vector for the reference element 220 based on the first and second complex vectors Vr+jVi, Ir+jli output by the first and second DFT blocks 232, 242 respectively by dividing the first complex vector Vr+jVi by the second complex vector Ir+jli, i.e.
  • the estimated impedance Z es t is equal to (or is within a defined tolerance range of) the predefined impedance Zknown. If the estimated impedance Z es t is not equal to (or is outside a defined tolerance range of) the predefined impedance Zknown then a gain or phase mismatch exists between the voltage monitoring path 140 and the current monitoring path 170.
  • a gain mismatch can be defined as a ratio of the amplitude of the signal V mO n to the amplitude of the signal l mO n when the signals input to the AFE 142 of the voltage monitoring path 140 and to the AFE 172 of the current monitoring path 170 are identical.
  • a phase mismatch ⁇ t> can be defined as a difference between the phase of the signal Vmon and the phase of the signal l mon .
  • the phase mismatch ⁇ t> can be directly calculated by the calculation block 250 from the first and second complex vectors Vr+jVi, Ir+jli output by the first and second DFT blocks respectively, by subtracting the phase of a ratio of the first complex vector to the second complex vector from the phase of the predefined impedance Zknown , i.e: (lr +jli) (3)
  • the time domain signal Vmon can be represented in the frequency domain as a vector product of the first complex vector Vr+jVi (representing the signal in the absence of any gain or phase mismatch) and a mismatch vector pcos ⁇ t> + jpsinc representing any gain mismatch p and any phase mismatch ⁇ t>, i.e.
  • VmonDFT (Vr+jVi)(Pcos ⁇ t> + jpsinO) (4)
  • Compensation coefficients BR and Bi can be calculated by the calculation block 150 as follows:
  • Vmoncmp (Vr+jVi)(Pcos ⁇ t> + jpsin ⁇ t>)(
  • cosO - j sinO) Vr+jVi
  • the compensation coefficients BRV and Biv calculated by the calculation block 150 during operation of the circuitry 200 in its calibration mode can be stored and applied, by the first amplitude /phase compensation block, to the complex vector VmonDFT generated and output by the first DFT block 232 during operation of the circuitry 200 in its load driving mode to compensate for any gain and/or phase mismatch between the voltage monitoring path 140 and the current monitoring path 170.
  • the compensation vector BRv+jBivto the complex vector VmonDFT has the effect of rotating the vector VmonDFT to compensate for the gain and/or phase mismatch.
  • the first amplitude /phase compensation block 234 may be said to perform vector rotation on the vector VmonDFT.
  • This vector rotation operation improves the accuracy of the estimate Z es t of the load impedance and the accuracy of any estimate of the resistance and/or inductance of the load 120 generated by the calculation block 250 during operation of the circuitry 200 in its load driving mode.
  • the compensation coefficients BRV and Biv described above are applied by the first amplitude /phase compensation block 234 to the frequency domain representation of the signal output by the voltage monitoring path 140.
  • compensation coefficients BRI and Bn to be applied by the second amplitude /phase compensation block 244 to the frequency domain representation of the signal output by the current monitoring path 170 could be generated by the calculation block 250 using a process similar to that described above.
  • Such compensation coefficients BRI and Bn could be applied instead of or in addition to the compensation coefficients BRV and Biv during operation of the circuitry 200 in its load driving mode to perform vector rotation of the vector ImonDFT.
  • the gain and/or phase mismatch between the voltage monitoring path 140 and the current monitoring path 170 may vary with temperature.
  • temperaturedependent compensation coefficients may be defined:
  • the temperature-dependent compensation coefficients may be predefined and stored, e.g. in a memory 280 that forms part of the circuitry 200 or a host device incorporating the circuitry 200.
  • the appropriate temperature-dependent compensation coefficient for the prevailing temperature T (as detected, for example, by a temperature sensor 290 that forms part of the circuitry 200 or a host device incorporating the circuitry 200) may then be selected retrieved by the calculation block 250 and used to determine or generate the compensation parameter (i.e. the compensation vector) to be applied by the first and/or second amplitude/phase compensation blocks 234, 244 to compensate for a detected gain and/or phase mismatch.
  • gain and or/phase mismatch compensation is performed digitally in the frequency domain, by determining, during operation of the circuitry 200 in its calibration mode, one or more compensation parameters (which in this example are the compensation coefficients BRV and Biv and/or BRI and Bn) for compensating for a difference between the estimated impedance Z es t and the predefined impedance Zknown of the reference load 220, and applying the determined compensation parameter(s) during operation of the circuitry 200 in its load driving mode.
  • one or more compensation parameters which in this example are the compensation coefficients BRV and Biv and/or BRI and Bn
  • gain and/or phase mismatch compensation may be performed in the time domain.
  • Figure 3 is a schematic representation of circuitry including voltage and current monitoring paths and alternative compensation circuitry for compensating for gain and/or phase mismatch between the voltage and current monitoring paths.
  • the circuitry shown generally at 300 in Figure 3, shares some elements in common with the driver circuitry 200 of Figure 2, and such common elements are denoted by common reference numerals in Figures 2 and 3, and will not be described again in detail here.
  • the circuitry 300 may be implemented as an integrated circuit (I C), for example.
  • the circuitry 300 differs from the circuitry 200 in that its compensation circuitry 330 does not include first and second amplitude /phase compensation blocks. Instead, the outputs of the first and second DFT blocks 232, 242 are coupled directly to inputs of the calculation block 250.
  • the calculation block 250 is configured to determine, based on a difference between the estimated impedance Z es t of the reference load 220 (which is determined based on the signals VmonDFT and ImonDFT output by the first and second DFT blocks 232, 242 as described above) and the predefined impedance Zknown of the reference load 220, one or more compensation parameters to be applied to analog elements of the voltage monitoring path 130 and/or the current monitoring path 170.
  • the analog front end (AFE) circuitry 142, 172 of the voltage and current monitoring paths 140, 170 may include filter circuitry for attenuating out-of-band components.
  • the AFE circuitry 142, 172 may include filter circuitry for attenuating components of the drive signal output by the driver circuitry 110 that are outside of the audio frequency range, e.g. components above 20kHz.
  • the filter circuitry in the AFE circuitry 142, 172 may also act as an antialiasing filter for the ADC circuitry 144, 172.
  • the circuitry 200, 300 may include one or more additional current sense resistors, e.g., additional current sense resistors 130-1 , 130-n (shown in dashed outline in Figures 2 and 3) that can be selectively coupled to the current monitoring path 170 in place of or in addition to the current sense resistor 130 (e.g., by means of suitable switches) for use in different applications of the circuitry 200, 300 and/or with different loads 120.
  • additional current sense resistors e.g., additional current sense resistors 130-1 , 130-n (shown in dashed outline in Figures 2 and 3) that can be selectively coupled to the current monitoring path 170 in place of or in addition to the current sense resistor 130 (e.g., by means of suitable switches) for use in different applications of the circuitry 200, 300 and/or with different loads 120.
  • a first one 130-1 of the additional current sense resistors may be selected and coupled to the current monitoring path 170 in place of the current sense resistor 130 when a first load 120 (e.g., a speaker) is coupled to the circuitry 200, 300, and a different one 130-n of the additional current sense resistors may be selected and coupled to the current monitoring path 170 when a different load 120 is coupled to the circuitry 200, 300.
  • a first load 120 e.g., a speaker
  • one of the additional current sense resistors 130-1 , 130-n may be selected in place of (or in addition to) the current sense resistor 130 after calibration of the circuitry 200, 300 using the reference element 220 as described above, and after a first estimate of the the impedance of the load 120 has been determined by the calculation block 250 during operation of the circuitry 200, 300 in its load driving mode.
  • FIG. 4 is a schematic diagram illustrating example AFE circuitry 142 for the voltage monitoring path 140 of the circuitry 300.
  • the AFE circuitry 172 of the current monitoring path 170 may have the same configuration.
  • the AFE circuitry 142 in this example comprises amplifier circuitry 410 having first and second inputs configured to be coupled to the load 120 or reference load 220 (depending on the operating mode of the circuitry 300.
  • a feedback arrangement is provided by an input resistor 412 coupled to a first input of the amplifier circuitry 410 and a feedback resistor 414 coupled between an output of the amplifier circuitry 410 and the input resistor 412.
  • a gain of the amplifier circuitry 410 is dependent upon a ratio of the resistance of feedback resistor 414 to the resistance of the input resistor 412.
  • the resistance of the feedback resistor 414 may be variable to permit adjustment of the gain of the amplifier circuitry 414.
  • the feedback resistor 414 may be implemented by a metal-oxide semiconductor (MOS) device whose drain-source resistance can be adjusted by adjusting a voltage applied to the gate of the MOS device.
  • MOS metal-oxide semiconductor
  • the feedback resistor 414 may be implemented as a switched resistor arrangement comprising a plurality of switched resistors coupled in parallel, such that the total resistance of the switched resistor arrangement can be controlled by selectively opening and closing switches associated with the individual resistors.
  • the resistance of the input resistor 412 may be variable to permit adjustment of the gain of the amplifier circuitry 414.
  • a variable input resistor be implemented by a metal-oxide semiconductor (MOS) device or a switched resistor arrangement of the kind described above.
  • Filter circuitry 420 is coupled to an output of the amplifier circuitry 410.
  • the filter circuitry 420 comprises a resistor 422 having a first terminal coupled to an input of the filter circuitry 420 and a second terminal coupled to an output of the filter circuitry 420, and a capacitor 424 coupled between the second terminal of the resistor 422 and a ground or Ov connection. It will be appreciated, however, that other configurations of filter circuitry could be employed.
  • the frequency and phase response of the filter circuitry 420 are determined by the resistance of the resistor 422 and the capacitance of the capacitor 424.
  • the resistance of the resistor 422 and the capacitance of the capacitor 424 may be variable to permit adjustment of the frequency and phase response of the filter circuitry 420.
  • the resistor 422 may be implemented by a MOS device or a switched resistor arrangement of the kind described above.
  • the capacitor 424 may be implemented by a switched capacitor arrangement comprising a plurality of switched capacitors coupled in parallel, such that the total capacitance of the switched capacitor arrangement can be controlled by selectively opening and closing switches associated with the individual capacitors.
  • a transconductance of the amplifier circuitry 410 may be variable so as to adjust the bandwidth of the AFE circuitry 142. Adjusting the bandwidth of the AFE circuitry 142 also changes the position of poles in the phase response of the AFE circuitry 142.
  • Figure 5 is a schematic diagram illustrating an example ADC arrangement for the ADC circuitry 144 of the voltage monitoring path 140 of the circuitry 300.
  • the ADC circuitry 174 of the current monitoring path 170 may have the same configuration.
  • the ADC circuitry 144 receives a reference voltage V re f, which in this example is provided by low dropout regulator (LDO) circuitry 510.
  • LDO low dropout regulator
  • the calculation block 250 is configured to determine, based on a difference between the estimated impedance Z es t of the reference load 220 and the predefined impedance Zknown of the reference load 220, one or more compensation parameters to be applied to analog elements of the voltage monitoring path 130 and/or the current monitoring path 170.
  • the calculation block 250 may determine a capacitance of the capacitor 424 and/or a resistance of the resistor 422 of the filter circuitry 420 required to move a pole of the phase response of the filter circuitry 420 to compensate for the phase mismatch, and may output appropriate control signals to the filter circuitry 420 to adjust the capacitance of the capacitor 424 and/or the resistance of the resistor 422 accordingly.
  • the calculation block 250 may determine a transconductance of the amplifier circuitry 410 of the AFE circuitry 142 required to move a pole of the phase response of the AFE circuitry 142 to compensate for the phase mismatch.
  • the calculation block 250 may determine a resistance of the feedback resistor 414 and/or a resistance of the input resistor 412 required to adjust the gain of the AFE circuitry 142, and may output appropriate control signals to the AFE circuitry 142 to adjust the resistance of the feedback resistor 414 and/or the input resistor 412 accordingly.
  • the calculation block 250 may determine a reference voltage Vref to be applied to the ADC circuitry 144 to adjust the gain of the ADC 144 to compensate for the gain mismatch, and may output appropriate control signals to the LDO circuitry 510 (or other circuitry that supplies the reference voltage V re f to the ADC circuitry 144) to adjust the reference voltage V re f accordingly.
  • the calculation circuitry 250 is described as determining compensation parameters that are be applied to analog elements of the voltage monitoring path 140, but it will be appreciated by those skilled in the art that the calculation circuitry 250 could, alternatively or additionally, determine compensation parameters that are applied to analog elements of the current monitoring path 170.
  • the circuitry 200, 300 may perform a verification cycle to confirm that the applied compensation parameter(s) have achieved the desired compensation effect.
  • the reference signal may again be applied to the reference element 220, and the calculation block 250 may determine an estimated impedance Z es t of the reference load 220, based on the signals output by the first and second DFT blocks 232, 242.
  • This estimated impedance Zest is then compared by the calculation block 250 to the predefined impedance Zknown of the reference element 220. If the estimated impedance Z es t is equal to (or is within a defined tolerance range of) the predefined impedance Zknown, the compensation parameters that have been applied have achieved the desired compensation effect, and the circuitry 200, 300 can now switch to operation in its load driving mode.
  • the estimated impedance Z es t is not equal to (or is outside a defined tolerance range of) the predefined impedance Zknown then a gain or phase mismatch still exists between the voltage monitoring path 140 and the current monitoring path 170, and new compensation parameters may be calculated in the manner described above.
  • the circuitry 200, 300 may be configured to perform calibration in the manner described above in response to particular trigger events, e.g. on start-up or power on of the circuitry 200, 300 or in response to a change in operating conditions, e.g. a change in ambient temperature, supply voltage or the like. Additionally or alternatively, the circuitry may be configured to perform calibration in the manner described above periodically or in accordance with a predefined schedule.
  • determining one or more compensation parameters and applying the determined compensation parameter(s) in operation of the circuitry 200, 300 in its load driving mode of operation improves the accuracy of an estimate Z es t of the load impedance and the accuracy of any estimate of the resistance and/or inductance of the load 120 generated by the calculation block 250 during operation of the circuitry 200, 300 in its load driving mode, as any gain and/or phase mismatch between the voltage monitoring path 140 and the current monitoring path 170 is compensated for by the application of the compensation parameter(s).
  • circuitry described above with reference to the accompanying drawings may be incorporated in a host device such as a laptop, notebook, netbook or tablet computer, a gaming device such as a games console or a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player or some other portable device, or may be incorporated in an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a VR or AR device, a mobile telephone, a portable audio player or other portable device.
  • a host device such as a laptop, notebook, netbook or tablet computer
  • a gaming device such as a games console or a controller for a games console
  • VR virtual reality
  • AR augmented reality
  • processor control code for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier.
  • a non-volatile carrier medium such as a disk, CD- or DVD-ROM
  • programmed memory such as read only memory (Firmware)
  • a data carrier such as an optical or electrical signal carrier.
  • embodiments will be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array).
  • the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA.
  • the code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays.
  • the code may comprise code for a hardware description language such as VerilogTM or VHDL (Very high speed integrated circuit Hardware Description Language).
  • VerilogTM Very high speed integrated circuit Hardware Description Language
  • VHDL Very high speed integrated circuit Hardware Description Language
  • the code may be distributed between a plurality of coupled components in communication with one another.
  • the embodiments may also be implemented using code running on a field-(re)programmable analogue array or similar device in order to configure analogue hardware.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

L'ensemble de circuits selon l'invention comprend : un trajet de surveillance de tension ; un trajet de surveillance de courant ; un élément de référence d'une impédance prédéfinie ; et un ensemble de circuits de traitement, lors du fonctionnement de l'ensemble de circuits dans un mode de fonctionnement d'étalonnage : le trajet de surveillance de tension est opérationnel pour délivrer un signal indiquant une tension à travers l'élément de référence en réponse à un signal de référence appliqué à l'élément de référence ; le trajet de surveillance de courant est opérationnel pour délivrer un signal indiquant un courant à travers l'élément de référence en réponse au signal de référence ; et l'ensemble de circuits de traitement est opérationnel pour : recevoir le signal indiquant la tension à travers l'élément de référence et le signal indiquant le courant à travers l'élément de référence ; générer une estimation d'une impédance de l'élément de référence ; et déterminer un paramètre de compensation pour un élément de l'ensemble de circuits pour compenser une différence entre l'estimation de l'impédance et l'impédance prédéfinie de l'élément de référence.
PCT/GB2022/052395 2021-11-09 2022-09-22 Ensemble de circuits pour compenser un décalage de gain et/ou de phase entre des chemins de surveillance de tension et de courant WO2023084180A1 (fr)

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US202163277339P 2021-11-09 2021-11-09
US63/277,339 2021-11-09
US17/690,327 2022-03-09
US17/690,327 US11644521B1 (en) 2021-11-09 2022-03-09 Circuitry for compensating for gain and/or phase mismatch between voltage and current monitoring paths

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2246639A (en) * 1990-08-02 1992-02-05 Farnell Instr Testing and calibrating LCR meters
US5886529A (en) * 1996-04-18 1999-03-23 Hewlett-Packard Company Impedance measuring device
US20020149424A1 (en) * 2001-03-21 2002-10-17 Jun Honda Power amplifying device
EP2270521A1 (fr) * 2004-02-27 2011-01-05 Ultra Electronics Limited Procédé et appareil de traitement et de mesure du signal
US20150168529A1 (en) * 2013-12-13 2015-06-18 National Instruments Corporation Self-Calibration of Source-Measure Unit via Capacitor
US20170254871A1 (en) * 2016-03-01 2017-09-07 Texas Instruments Incorporated Calibration of Inverting Amplifier Based Impedance Analyzers
US20170350923A1 (en) * 2016-06-02 2017-12-07 Nxp B.V. Load detector
US20180252748A1 (en) * 2011-09-12 2018-09-06 Analog Devices Global Current measurement
US20210083637A1 (en) * 2019-08-28 2021-03-18 Stmicroelectronics S.R.L. Method of monitoring electrical loads, corresponding circuit, amplifier and audio system
US20210344310A1 (en) * 2020-05-01 2021-11-04 Cirrus Logic International Semiconductor Ltd. Common-mode insensitive current-sensing topology in full-bridge driver

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2246639A (en) * 1990-08-02 1992-02-05 Farnell Instr Testing and calibrating LCR meters
US5886529A (en) * 1996-04-18 1999-03-23 Hewlett-Packard Company Impedance measuring device
US20020149424A1 (en) * 2001-03-21 2002-10-17 Jun Honda Power amplifying device
EP2270521A1 (fr) * 2004-02-27 2011-01-05 Ultra Electronics Limited Procédé et appareil de traitement et de mesure du signal
US20180252748A1 (en) * 2011-09-12 2018-09-06 Analog Devices Global Current measurement
US20150168529A1 (en) * 2013-12-13 2015-06-18 National Instruments Corporation Self-Calibration of Source-Measure Unit via Capacitor
US20170254871A1 (en) * 2016-03-01 2017-09-07 Texas Instruments Incorporated Calibration of Inverting Amplifier Based Impedance Analyzers
US20170350923A1 (en) * 2016-06-02 2017-12-07 Nxp B.V. Load detector
US20210083637A1 (en) * 2019-08-28 2021-03-18 Stmicroelectronics S.R.L. Method of monitoring electrical loads, corresponding circuit, amplifier and audio system
US20210344310A1 (en) * 2020-05-01 2021-11-04 Cirrus Logic International Semiconductor Ltd. Common-mode insensitive current-sensing topology in full-bridge driver

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