WO2023082723A1 - 处理器电路、供电控制方法及终端设备 - Google Patents

处理器电路、供电控制方法及终端设备 Download PDF

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Publication number
WO2023082723A1
WO2023082723A1 PCT/CN2022/109476 CN2022109476W WO2023082723A1 WO 2023082723 A1 WO2023082723 A1 WO 2023082723A1 CN 2022109476 W CN2022109476 W CN 2022109476W WO 2023082723 A1 WO2023082723 A1 WO 2023082723A1
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Prior art keywords
power supply
target core
core
module
cores
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PCT/CN2022/109476
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English (en)
French (fr)
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史岩松
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Oppo广东移动通信有限公司
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Publication of WO2023082723A1 publication Critical patent/WO2023082723A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of power supplies, and in particular to a processor circuit, a power supply control method, and a terminal device.
  • the statements herein merely provide background information related to the present application and may not necessarily constitute prior art.
  • Existing charging methods include contact charging and wireless charging.
  • the number of cores of a processor refers to the number of physical cores, that is, how many cores exist on the hardware.
  • a dual-core includes two relatively independent processor core unit groups
  • a quad-core includes four relatively independent processor core unit groups.
  • the large core when running a mobile game that needs performance, the large core will run at high frequency to achieve the highest performance, while the small core is idle; while only running social chat software, only the small core may be turned on during the Internet access process, and the large core is in an idle state. , so as to achieve the best energy efficiency ratio.
  • the power supply of each core in the current processor is affected by the core with the maximum power supply voltage, which will cause the same voltage to be provided to all cores when only some cores are working, so compared to other cores, more A higher supply voltage will result in an unnecessary increase in power consumption.
  • the purpose of the embodiments of the present application is to provide a processor circuit, a power supply control method, and a terminal device, including but not limited to solving the problem that each core of a current multi-core processor needs to be powered at the same time, which affects power consumption.
  • a processor circuit including:
  • a processor provided with a control logic module and a plurality of cores
  • the control logic module is respectively connected with the plurality of cores and the plurality of power supply modules, and is used to output a voltage adjustment signal according to the frequency of the target core, so that it is compatible with
  • the power supply module corresponding to the target core adjusts the power supply voltage, and the target core is at least one core among the multiple cores.
  • a power supply control method which is applied to a power supply module for supplying power to a processor, the processor is provided with a control logic module and multiple cores, and different cores in the multiple cores are powered by different power supply modules,
  • the power supply control method includes:
  • the power supply voltage provided to the target core is adjusted according to the trigger from the control logic module for adjusting the frequency of the target core, and the target core is at least one core among the plurality of cores.
  • a power supply control method is provided, which is applied to a processor provided with multiple cores, and different cores in the multiple cores are powered by different power supply modules.
  • the power supply control method includes:
  • the frequency of the target core is obtained, and the target core is at least one core among multiple cores;
  • control the power supply module that supplies power to the target core to adjust the power supply voltage provided to the target core.
  • a fourth aspect provides a terminal device, including the processor circuit provided in the first aspect above.
  • a fifth aspect provides a terminal device, which includes a processor and a computer program stored in the processor and operable on the processor, wherein when the processor executes the computer program The steps of the method in the second aspect or the third aspect are realized.
  • a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method in the second aspect or the third aspect above are implemented.
  • the beneficial effect of the embodiment of the present application is that an independent power supply module is provided for each core, and power supply can be performed according to the actual working conditions of each core, and it is not necessary to provide the maximum power supply voltage for each core to supply power to all cores at the same time.
  • the independent power supply enables cores that are idle or only need to run at a low load to stop power supply or run at low voltage, which can reduce power consumption.
  • each core is powered by a power supply module with a load detection function (the load detection function can also be set independently), and the The real-time monitoring of the load current can realize the power supply of each core that is closest to the actual operating conditions, and when implementing multi-threaded tasks, the cores can be more accurately assigned and allocated to achieve the maximum utilization of each core, thereby achieving maximum energy saving.
  • the beneficial effect of the power supply control method provided by the second aspect of the embodiment of the present application is that: the control logic module can schedule the tasks of more than one core to another core, and after the scheduling is completed, the core of the transferred task can reduce its work Therefore, based on inter-core task scheduling, the frequency of some target cores can be reduced to reduce power consumption.
  • each of the multiple cores in the processor is controlled to follow the change of its frequency, and supply power with the corresponding voltage, so that not only can the multiple Asymmetric workloads are performed on the cores to provide deterministic performance; cores with low loads can also be operated at lower frequencies, supplemented by lower voltages for power supply, and cores with no operating tasks are powered off, so as to Reduce unnecessary loss.
  • FIG. 1 is a schematic structural diagram of a processor circuit provided in the first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a processor of the processor circuit shown in FIG. 1;
  • Fig. 3 is a schematic diagram of a power supply module of the processor circuit shown in Fig. 1;
  • FIG. 4 is a schematic structural diagram of a processor circuit provided in a second embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a processor circuit provided in a third embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a power supply control method provided by one embodiment of the present application.
  • FIG. 7 is a schematic flowchart of voltage regulation in a power supply control method provided by one embodiment of the present application.
  • FIG. 8 is a schematic flowchart of voltage regulation in a power supply control method provided by one embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a power supply control method provided by one embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a power supply control method provided by one embodiment of the present application.
  • FIG. 11 is a schematic flowchart of frequency adjustment in a power supply control method provided by one embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
  • orientation or positional relationship indicated by the terms “upper”, “lower”, etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of description, rather than indicating or implying that the referred device or element must Having a specific orientation, constructing and operating in a specific orientation should not be construed as limiting the present application, and those skilled in the art can understand the specific meanings of the above terms according to specific situations.
  • the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of technical features. "Plurality” means two or more, unless otherwise clearly and specifically defined.
  • a processor circuit applicable to terminal devices such as mobile phones, tablet computers, smart watches, personal computers, etc.
  • terminal devices such as mobile phones, tablet computers, smart watches, personal computers, etc.
  • a control logic module 120 and a multi- A processor 100 with multiple cores 110a-110n wherein different cores 110a-110n of the multiple cores 110a-110n are powered by different power supply modules 200a-200n, and the control logic module 120 communicates with multiple cores 110a-110n and multiple
  • the power supply modules 200a-200n are connected to output a voltage adjustment signal according to the frequency of the target core, so that the power supply modules 200a-200n corresponding to the target core adjust the power supply voltage, and the target core is at least one core among the multiple cores 110a-110n .
  • the processor circuit includes multiple power supply modules 200a-200n, and the number of the multiple power supply modules 200a-200n is the same as the number of the multiple cores 110a-110n.
  • the multiple power supply modules 200a-200n 200n may be integrated in the processor 100, or may be set independently of the processor 100.
  • the multiple power supply modules 200 a - 200 n are in a matching relationship with the processor circuit; at this time, the multiple power supply modules 200 a - 200 n are set independently of the processor 100 .
  • each of the multiple cores 110a-110n in the processor 100 is controlled to follow the change of its frequency and supply power with a corresponding voltage, so that not only can the multiple cores 110a-110n execute Asymmetric workloads to provide definite performance; cores 110a-110n with low loads can also be operated at lower frequencies, supplemented by lower voltages for power supply, and even cores 110a-110n without operating tasks will be powered off closed to reduce unnecessary losses.
  • the control logic module 120 of the processor 100 includes non-core parts of the processor 100, such as a logic control module 122, a clock generation module 124 for providing frequency, and a frequency modulation control module for adjusting the operating frequency of the cores 110a-110n 126.
  • the control logic module 120 may specifically be constructed by a logic circuit.
  • the frequency adjustment of the target core may be a preset adjustment through an external command; it may also be that the logic control module 122 adjusts the frequency of the target core according to the load status of the target core.
  • control logic module 120 can compare the task at the next moment in the queue of the target core with the current or historical task, for example, compare the same task with the task at the next moment , if there is no identical task, it can also be compared with similar tasks to estimate the load status of the target core at the next moment that will run the task at the next moment.
  • the load state at the next moment can include idle, load reduction, and load increase, and the logic control module 122 can control the frequency modulation control module 126 to provide a
  • the preset frequency can also be an adjustment frequency, such as stopping the frequency (signal) to make the target core sleep (corresponding to idle), reducing the frequency (corresponding to reducing the load), and increasing the frequency (corresponding to increasing the load).
  • the load state of the target core can be reflected in its operating voltage or current, or operating frequency. It can also be reflected in the types of tasks currently performed by the target core, such as multi-image data calculation game tasks and shooting tasks are high loads, while instant messaging tasks and web browsing tasks are low loads.
  • the logic control module 122 while adjusting the frequency of the target core, the logic control module 122 also outputs a voltage adjustment signal corresponding to the frequency according to the current or next frequency of the target core, and controls the corresponding power supply modules 200a-200a that supply power to the target core. 200n adjusts the supply voltage. Specifically, the logic control module 122 outputs corresponding voltage adjustment signals to the power supply modules 200 a - 200 n according to the frequency change of the target core.
  • each power supply module 200 a - 200 n includes a power control module 210 and a voltage conversion module 220 respectively.
  • Each power control module 210 is connected to the control logic module 120 and each voltage conversion module 220 respectively, and is used to receive the voltage adjustment signal output by the control logic module 120, so as to control the voltage conversion module 220 to adjust the power supply voltage VOUT output to the target core;
  • each voltage The conversion module 220 is connected to each core 110a-110n, and is used for adjusting the supply voltage VOUT output to the target core.
  • the voltage adjustment signal carries a specific target voltage value, or the voltage adjustment signal carries the frequency of the target core, and the power control module 210 can determine the target voltage value according to the corresponding relationship between the pre-stored frequency and the target voltage value. 210 controls the voltage conversion of the voltage conversion module 220 according to the voltage adjustment signal to obtain the supply voltage VOUT of the target voltage value.
  • the power control module 210 may be a single-chip microcomputer based on an Advanced RISC Machine (ARM), a Microcontroller Unit (MCU) or the like.
  • the process includes four cores: core 1, core 2, core 3, core 4, core 1 is currently or will be tuned to work at 1.8G, and cores 2-4 are currently or will be tuned to work At a frequency of 1.2G, the power supply voltage required by core 1 is 1.2V, and the power supply voltage required by core 2-4 is 0.8V.
  • the power control module 210 of the power supply module that supplies power to core 1 controls and The connected voltage conversion module 220 outputs a 1.2V voltage to the core 1; the power control module 210 of the power supply module that supplies power to the core 2-4 receives the corresponding instruction, and controls the voltage conversion module 220 connected to it to output a 0.8V voltage to the core 2 -4.
  • the processor circuit also includes a power management module 150
  • the power management module 150 can be a power management integrated circuit (Power Management IC, PMIC)
  • the power management module 150 is connected with the control logic module 120 and each power supply module 200a ⁇ 200n respectively
  • the power management module 150 is connected to the power control module 210, and the power management module 150 is used to receive the voltage adjustment signal output by the control logic module 120, and control at least one power control module 210 to work according to the voltage adjustment signal.
  • the power management module 150 is used to manage and control multiple power control modules 210 to control the corresponding voltage conversion modules 220 to adjust the power supply voltage VOUT.
  • the power management module 150 can be omitted to save cost, and a connected serial port is provided for each power control module 210 to transmit voltage regulation signals, as shown in FIG. 1 . It can be understood that setting the power management module 150 can save the serial port of the processor 100 .
  • the voltage conversion module 220 may be a boost circuit, a buck circuit or a boost-buck circuit. Please continue to refer to FIG. 3.
  • the voltage conversion module 220 is a step-down circuit, including a half-bridge power part composed of MOS transistors M1 and M2, and an energy storage filter part composed of an inductor L1 and a capacitor C1.
  • This voltage conversion module 220 mainly realizes voltage conversion and power output, and provides power supply voltage VOUT to corresponding cores 110a-110n; specifically, power supply control module 210 outputs control signals H_Drive, L_Drive according to changes in voltage regulation signal, load and output (supply voltage VOUT)
  • the switching frequency and duty cycle of the MOS transistors M1 and M2 are respectively controlled to realize the adjustment of different power supply voltages VOUT.
  • the processor circuit further includes a current detection module 300 connected to each power supply module 200a-200n; the current detection module 300 is configured to: detect each power supply module 200a-200n output current; the current detection module 300 is specifically connected to the power control module 210, and the current detection module 300 can adopt methods such as current mirrors, coupled inductors, series connection of current detection resistors, or digital sampling and analysis. Applications are not limited to this.
  • the current detection module 300 may include a plurality of detection branches, which are connected to the plurality of power supply modules 200a-200n in one-to-one correspondence, and each detection branch is used to detect the power of the power supply modules 200a-200n connected to it. Output current.
  • the current detection module 300 is a single detection circuit provided with multiple detection ports, which can detect the output currents of each of the multiple power supply modules 200a-200n in a time-sharing manner.
  • the output current value of the power supply modules 200a-200n detected by the current detection module 300 is the current consumed by the cores 110a-110n associated with the power supply modules 200a-200n when working, which includes the cores 110a-110n running software As well as the consumption of hardware, it also reflects the operating conditions and loads of computing tasks and control tasks in the cores 110a-110n.
  • control logic module 120 adjusting the frequency of the target core according to the load state of the target core specifically includes: determining the average operating current of each core 110a-110n (which may also be the target core) within a period of time; according to each core 110a-110n Inter-core task scheduling is performed based on the average working current within a period of time; and the frequencies of the cores 110 a - 110 n are adjusted according to the results of the inter-core task scheduling.
  • the determination of the average working current can be performed in the power control module 210 or in the control logic module 120 .
  • the first way is that the power control module 210 obtains the output current of each power supply module 200a-200n from the current detection module 300, and the control logic module 120 calculates the output current of each core 110a-110n corresponding to each power supply module 200a-200n Average operating current over a period of time.
  • the second method is that the power control module 210 obtains the output current of each power supply module 200a-200n from the current detection module 300, and at the same time, the power control module 210 also calculates the current of each core 110a-110n corresponding to each power supply module 200a-200n.
  • the control logic module 120 obtains the average working current of each core 110 a - 110 n from the power control module 210 of each power supply module 200 a - 200 n for a period of time and transmits it to it.
  • the average working current of each core 110 a - 110 n in each clock cycle is calculated first, and the average working current in a period of time is the average working current in at least one clock cycle.
  • the cores 110 a - 110 n of the processor 100 can more accurately assign tasks to be processed, and realize the maximum utilization rate of each core 110 a - 110 n, thereby realizing maximum energy saving.
  • the control logic module 120 performs inter-core task scheduling specifically as follows: the inter-kernel task scheduling includes scheduling tasks of the first target core to the second target core for execution. At this time, the first target core can be disabled. The power supply of the target core, or make the first target core go into sleep mode, reduce the load of the first target core, and then reduce the power supply voltage/current, so as to reduce the power consumption of the processor 100 .
  • the first target core is at least one core among the plurality of cores 110a-110n, that is, tasks of more than one core can be scheduled to another core.
  • the average operating current of the second target core is less than or equal to the full load current of the second target core during the preset time period, so that the second target core can meet the multi- Simultaneous processing or control of multiple tasks.
  • the preset duration may be the same as or different from the above-mentioned period of time, but they are all at least one clock cycle.
  • Full load current is the current consumed by the core at full load at a certain frequency.
  • control logic module 120 performs inter-core task scheduling specifically as follows: within a preset period of time, if the average operating current of the first target core is ⁇ I1*80%, the average operating current of the second target core is If the current i2 ⁇ I2*20%, the task in the second target core is scheduled to the first target core, and the second target core is turned off, where I1 is the current consumed by the first target core during full load operation , I2 is the current consumed by the second target core at full load.
  • control logic module 120 performs inter-kernel task scheduling specifically as follows: scheduling tasks in the second target core to the first target core, and shutting down the second target core, where the first target core is multiple Among the cores, the cores whose average working current is ⁇ I1*80% within the preset time period, the second target core is the cores whose average working current i2 ⁇ I2*20% within the preset time period among the multiple cores.
  • I1 is the current consumed by the first target core during full load operation
  • I2 is the current consumed by the second target core during full load operation.
  • the frequency of the cores 110a-110n related to the task scheduling between the cores is adjusted according to the result of the task scheduling between the cores, and then the control logic module 120 will output according to the frequency of any core 110a-110n
  • the power supply control module 210 will adjust the supply voltage VOUT of the provided cores 110 a - 110 n according to the voltage adjustment signal related to the frequency adjustment.
  • the current consumed by the core when running at full load at this frequency is I1
  • core 2 works at a frequency of 1.2GHz.
  • the current consumed by the core at full load is The consumed current is I2
  • the current detection module 300 monitors the load currents of the cores 1 and 2 (ie, the output currents of the corresponding power supply modules 200a-200n) in real time, and transmits them to the power control module 210, which is controlled by the power control module 210 through communication.
  • the method is passed to the logic control module 122 in the processor 100, and the logic control module 122 calculates the average operating current of each clock cycle of the core 1 and 2, if the average operating current of the core 1 in multiple cycles is i1, and i1 ⁇ I1* 80%, the average operating current of core 2 in multiple cycles is i2, and i2 ⁇ I2*20%, then the logic control module 122 will schedule the tasks in core 2 to core 1 for execution, and then turn off core 2, thereby realizing The purpose of energy saving.
  • the current detection module 300 can be integrated into the power supply modules 200a-200n as a part of the power supply modules 200a-200n, so that the power supply modules 200a-200n have a load detection function.
  • the current detection module 300 can also be independent from the power supply modules 200a-200n.
  • the power supply modules 200a-200n can be implemented using discrete devices, or can be implemented using integrated circuits.
  • each core 110a-110n is powered by a power supply module 200a-200n with a load detection function (the load detection function can also be set independently), and the load current of each core 110a-110n is monitored in real time. Monitoring can realize the power supply of each core 110a-110n that is closest to the actual operating situation, and when implementing multi-threaded tasks, the cores 110a-110n can more accurately assign processing and allocation to achieve the maximum utilization of each core 110a-110n, thereby realizing Maximum energy saving.
  • the second aspect of the embodiment of the present application provides a power supply control method, which is applied to the power supply modules 200a-200n for supplying power to the processor 100.
  • the processor 100 is provided with a control logic module 120 and multiple cores 110a-110n.
  • the multiple cores Different cores 110a-110n in 110a-110n are powered by different power supply modules 200a-200n, please refer to Figure 1 to Figure 5, and Figure 6, the power supply control methods include:
  • Step S110 providing power supply voltage for each core 110 a - 110 n connected to the power supply modules 200 a - 200 n .
  • Step S120 adjusting the power supply voltage provided to the target core according to the trigger from the control logic module 120 for adjusting the frequency of the target core, where the target core is at least one core among the plurality of cores 110 a - 110 n .
  • each of the multiple cores 110a-110n in the processor 100 is controlled to follow the change of its frequency and supply power with a corresponding voltage, so that not only can the multiple cores 110a-110n execute Asymmetric workloads to provide definite performance; cores 110a-110n with low loads can also be operated at lower frequencies, supplemented by lower voltages for power supply, and even cores 110a-110n without operating tasks will be powered off closed to reduce unnecessary losses.
  • the frequency of the cores 110a-110n is adjusted according to the load status of the cores 110a-110n.
  • the logic control module 122 adjusts the frequency of the target core according to the load state of the target core, and the power supply modules 200 a - 200 n respond to the adjustment of the frequency of the target core.
  • each power supply module 200a-200n includes a power control module 210 and a voltage conversion module 220 connected to the power control module 210, each power control module 210 is connected to the control logic module 120 , multiple voltage conversion modules 220 are connected to multiple cores 110a-110n in one-to-one correspondence, please refer to FIG. 7, step S120 includes:
  • step S122 the receiving control logic module 120 outputs a corresponding voltage adjustment signal according to the frequency of the adjusted target core.
  • the control logic module 120 generates a corresponding voltage adjustment signal of the target core according to the frequency of the target core and outputs it to the power control module 210 .
  • the voltage adjustment signal is used by the power control module 210 to determine the adjusted supply voltage VOUT. It can be understood that the voltage adjustment signal carries a specific target voltage value, or the voltage adjustment signal carries the frequency of the target core, and the power control module 210 can determine the target voltage value according to the pre-stored correspondence between the frequency and the target voltage value.
  • Step S124 controlling the voltage conversion modules 220 of the power supply modules 200a-200n to perform voltage conversion according to the received voltage adjustment signal, so as to adjust the power supply voltage of the target core. It can be understood that steps S122 and S124 may be executed by the power control module 210 or by the power management module 150 .
  • the control logic module 120 can compare the task at the next moment in the queue of the target core with the current or historical task, such as comparing the same task with the task at the next moment. Yes, if there is no similar task, you can also compare similar tasks to estimate the load status of the target core at the next moment that will run the task at the next moment.
  • the power supply control method further includes:
  • Step S210 determining the average operating current of the target core within a period of time.
  • the current detection module 300 detects the output current of each power supply module 200a-200n, obtains the output current of each power supply module 200a-200n, and calculates the average Working current.
  • the average working current As mentioned above, for the calculation of the average operating current within a period of time, reference may be made to the foregoing embodiments, and details are not repeated here.
  • Step S220 according to the trigger from the control logic module 120 to adjust the frequency of the target core after performing inter-core task scheduling according to the average operating current of the target core within a period of time, adjust the supply voltage VOUT provided to the target core.
  • the adjustment of the power supply voltage VOUT of the target core is based on the change of the frequency of the target core.
  • the control logic module 120 can schedule tasks of more than one core to another In the kernel, after the scheduling is completed, the core of the transferred task can reduce its working frequency, so based on the task scheduling between the cores, the frequency of some target cores can be reduced, and as a trigger, the power supply modules 200a-200n will adjust the provided The supply voltage VOUT for this part of the target core.
  • the power control module 210 will adjust the frequency of the target core by the control logic module 120 based on the inter-core task scheduling and output a voltage adjustment signal related to frequency adjustment to adjust the supply voltage VOUT of the provided target core.
  • the third aspect of the embodiment of the present application also provides another power supply control method, which is applied to the processor 100 provided with multiple cores 110a-110n, and different cores 110a-110n of the multiple cores 110a-110n are powered by different power supply modules 200a ⁇ 200n power supply, please refer to Figure 1 to Figure 5, and Figure 9, power supply control methods include:
  • step S320 during the power supply module 200 a - 200 n of the target core is supplying power to the target core, the frequency of the target core is acquired, and the target core is at least one core among the plurality of cores 110 a - 110 n .
  • Step S340 according to the frequency of the target core, control the power supply modules 200a-200n supplying power to the target core to adjust the power supply voltage provided to the target core.
  • each of the multiple cores 110a-110n in the processor 100 is controlled to follow the change of its frequency and supply power with a corresponding voltage, so that not only can the multiple cores 110a-110n execute Asymmetric workloads to provide definite performance; cores 110a-110n with low loads can also be operated at lower frequencies, supplemented by lower voltages for power supply, and even cores 110a-110n without operating tasks will be powered off closed to reduce unnecessary losses.
  • the power supply control method further includes: step S310, adjusting the frequency of the target core according to the load state of the target core.
  • the load state can be divided into idle, reduce load, and increase load.
  • adjusting the frequency of the corresponding target core may be to stop the supply of the frequency (signal) to make the target core sleep (corresponding to idle), reduce the frequency (corresponding to reducing the load), or increase the frequency (corresponding to increasing the load).
  • the frequency adjustment of the cores 110 a - 110 n may be preset by an external command; it may also be that the logic control module 122 adjusts the frequency of the corresponding target core according to the load status of the target core.
  • the control logic module 120 can compare the task at the next moment in the queue of the target core with the current or historical task, for example, the task that is the same as the task at the next moment For comparison, if there is no similar task, similar tasks can also be compared to estimate the load status of the target core at the next moment of the task that is about to run at the next moment.
  • the load state at the next moment may include idle, load reduction, and load increase, and the logic control module 122 may control the frequency adjustment control module 126 to provide a predetermined load state for the target core according to the estimated current or next moment load state.
  • the set frequency can also be an adjustment frequency, such as stopping the frequency (signal) to make the target core sleep (corresponding to idle), reducing the frequency (corresponding to reducing the load), and increasing the frequency (corresponding to increasing the load).
  • the load of the target core can be reflected in its operating voltage or current or power, or its operating frequency.
  • step S320 includes outputting a corresponding voltage adjustment signal to the power control modules 210 of the power supply modules 200 a - 200 n that supply power to the target cores according to the frequency of the target cores.
  • the voltage adjustment signal is used to instruct the power control module 210 to control and adjust the voltage conversion performed by the voltage conversion module 220 of the power supply modules 200a-200n, so as to adjust the power supply voltage VOUT provided by the voltage conversion module 220 to the target core.
  • the power supply module refer to FIG. 3 and its description.
  • step S310 adjusting the frequency of the target core according to the load state of the target core includes:
  • Step S312 determining the average operating current of the target core within a period of time.
  • the current detection module 300 detects the output current of each power supply module 200a-200n, obtains the output current of each power supply module 200a-200n, and calculates the average operating current of the target core corresponding to each power supply module 200a-200n within a period of time .
  • the average operating current of the target core corresponding to each power supply module 200a-200n within a period of time.
  • Step S314 performing task scheduling between cores according to the average working current of the target core within a period of time.
  • the inter-core task scheduling includes scheduling tasks of the first target core to be executed by the second target core, and shutting down the first target core, so as to reduce power consumption of the processor 100 .
  • the first target core is at least one core among the plurality of cores 110a-110n, and after the tasks of the first target core are scheduled to be executed by the second target core, the average operating current of the second target core in a preset period of time is less than or equal to the full load current of the second target core.
  • the preset duration may be the same as or different from the above-mentioned period of time, but they are all at least one clock cycle.
  • Full load current is the current consumed by the core at full load at a certain frequency.
  • core 1 works at a frequency of 1.8GHz
  • the current consumed by the core when it runs at full load at this frequency is I1
  • core 2 works at a frequency of 1.2GHz
  • the current consumed by the core at this frequency is The consumed current is I2
  • the current detection module 300 monitors the load currents of the cores 1 and 2 (ie, the output currents of the corresponding power supply modules 200a-200n) in real time, and transmits them to the power control module 210, which is controlled by the power control module 210 through communication.
  • the method is passed to the logic control module 122 in the processor 100, and the logic control module 122 calculates the average operating current of each clock cycle of the core 1 and 2, if the average operating current of the core 1 in multiple cycles is i1, and i1 ⁇ I1* 80%, the average operating current of core 2 in multiple cycles is i2, and i2 ⁇ I2*20%, then the logic control module 122 will schedule the tasks in core 2 to core 1 for execution, and then turn off core 2, thereby realizing The purpose of energy saving.
  • Step S316 adjusting the frequency of the target core related to the task scheduling according to the result of the task scheduling between the cores. Furthermore, the control logic module 120 controls the power supply module that supplies power to the target core to adjust the power supply voltage VOUT provided by the target core according to the frequency of the target core.
  • determining the average operating current of the target core within a period of time includes: the control logic module 120 calculates the target core corresponding to each power supply module 200a-200n in a period of time according to the acquired output current of each power supply module 200a-200n. Or, the control logic module 120 obtains the average operating current of the target core calculated by the power management module 150 or the power control module 210 in a period of time from each power supply module 200a-200n, and the core is in The average working current within a period of time is calculated by the power management module 150 or the power control module 210 according to the output currents of the power supply modules 200 a - 200 n detected by the current detection module 300 .
  • the control logic module 120 can adjust the frequency of the cores 110a-110n based on the task scheduling between the cores and output the frequency related to the frequency adjustment.
  • Voltage adjustment signal the power control module 210 will adjust the supply voltage VOUT of the provided cores 110a-110n according to the voltage adjustment signal.
  • the power supply control method provided by the second aspect in the embodiments of the present application may be implemented when the power control module 210 of the power supply modules 200a-200n executes a computer program, or may be implemented when the power management module 150 executes a computer program.
  • the power supply control method provided by the third aspect in the embodiment of the present application can be realized when the control logic module 120 in the processor 100 executes a computer program, or it can be realized when other controllers in the processor 100 execute a computer program, such as power Control logic module. It may also be realized when other controllers other than the processor 100 execute computer programs.
  • an embodiment of the present application also provides an energy storage device data display device.
  • Fig. 12 is a schematic structural diagram of an energy storage device data display device provided in an embodiment of the present application.
  • the terminal device provided in this embodiment includes: a memory 400 and a processor 100, the memory 400 is used to store computer programs; processing The device 100 is configured to execute the methods described in the above method embodiments when calling a computer program.
  • the terminal device provided in this embodiment includes a processor 100, a computer program is stored in the processor 100, and the processor 100 is configured to execute the method described in the foregoing method embodiments when calling the computer program.
  • the terminal device provided in the embodiment of the present application can execute the above method embodiment, and its implementation principle and technical effect are similar, and will not be repeated here.
  • the embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the foregoing method embodiment is implemented.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein.
  • the processor can be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • Memory may include non-permanent memory in computer-readable media, in the form of random-access memory (Random Access Memory, RAM) and/or non-volatile memory, such as read-only memory (Read-Only Memory, ROM) or flash memory (Flash Memory).
  • RAM Random Access Memory
  • ROM read-only memory
  • Flash Memory flash memory
  • Computer-readable media includes both volatile and non-volatile, removable and non-removable storage media.
  • the storage medium may store information by any method or technology, and the information may be computer-readable instructions, data structures, program modules, or other data.
  • Examples of computer storage media include, but are not limited to, phase-change memory (Phase-Change Memory, PCM), static random-access memory (Static Random-Access Memory, SRAM), dynamic random-access memory (Dynamic Random-Access Memory, DRAM) ), other types of RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technologies, CD-ROM, ROM, Digital Versatile Disc (Digital Versatile Disc, DVD) or other optical storage, magnetic cassette tape, magnetic disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
  • computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

Abstract

本申请适用于电源技术领域，提供了一种处理器电路、供电控制方法及终端设备，处理器电路包括处理器，所述处理器设置有控制逻辑模块120和多个内核110a～110n；其中，多个内核110a～110n中的不同内核分别由不同供电模块200a～200n进行供电；所述控制逻辑模块120分别与多个内核110a～110n和多个供电模块200a～200n连接，用于根据目标内核的频率，输出电压调节信号，以使得与所述目标内核对应的供电模块200a～200n调整供电电压，所述目标内核为多个内核110a～110n中的至少一个内核。为每个内核设置独立的供电模块，并且可以根据每个内核的实际工况进行供电，不需要为每个内核提供最大的供电电压来为所有内核同时供电，独立供电使处于空闲或只需低负荷运行的内核可以停止供电或低电压运行，可以避免不必要的功耗。

Description

处理器电路、供电控制方法及终端设备
本申请要求于2021年11月11日在中国专利局提交的、申请号为202111333114.4、发明名称为“处理器电路、供电控制方法及终端设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电源技术领域，具体涉及一种处理器电路、供电控制方法及终端设备。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。现有的充电的方式包括接触式充电和无线式充电。处理器的核心数是指物理上，也就是硬件上存在着几个核心。比如，双核就是包括2个相对独立的处理器核心单元组，四核就包含4个相对独立的处理器核心单元组。以一个8核处理器举例，内中包含了4个大核和4个小核，其中，是为了平衡系统的功耗而引入小核的概念。比如在运行在需要发挥性能的手游时，大核会高频率运行达到最高性能，而小核心闲置；而只运行社交聊天软件时，上网过程中可能只会开启小核心，大核心处于闲置状态，从而达到最佳的能效配比。
但是，目前的处理器中各个内核的供电受供电电压最大值的内核的影响，这样会导致在只有部分核心工作时，还是要提供相同的电压给所有核心，那么相对其他核心来说，多出的供电电压就会造成不必要功耗的增加。
申请内容
本申请实施例的目的在于：提供一种处理器电路、供电控制方法及终端设备，包括但不限于解决目前多核心的处理器各个核心需同时供电而影响功耗的问题。
本申请实施例采用的技术方案是：
第一方面，提供了一种处理器电路，包括：
处理器，所述处理器设置有控制逻辑模块和多个内核；
其中，多个内核中的不同内核分别由不同供电模块进行供电；所述控制逻辑模块分别与多个内核和多个供电模块连接，用于根据目标内核的频率，输出电压调节信号，以使得与所述目标内核对应的供电模块调整供电电压，所述目标内核为多个内核中的至少一个内核。
第二方面，提供了一种供电控制方法，应用于为处理器供电的供电模块，所述处理器设置有控制逻辑模块和多个内核，多个内核中不同的内核由不同的供电模块供电，所述供电控制方法包括：
为与所述供电模块连接的各个内核提供供电电压；
根据来自所述控制逻辑模块为调整目标内核的频率引起的触发，调整所提供给所述目标内核的供电电压，所述目标内核为多个内核中的至少一个内核。
第三方面，提供一种供电控制方法，应用于设置有多个内核的处理器，多个内核中不同的内核由不同的供电模块供电，所述供电控制方法包括：
在目标内核的所述供电模块为所述目标内核供电过程中，获取所述目标内核的频率，所述目标内核为多个内核中的至少一个内核；
根据所述目标内核的频率，控制为所述目标内核供电的所述供电模块调整所提供给所述目标内核的供电电压。
第四方面，提供了一种终端设备，包括上述第一方面提供的处理器电路。
第五方面，提供了一种终端设备，所包括处理器以及存储在所述处理器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如上述第二方面或第三方面的方法的步骤。
第六方面，提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现上述第二方面或第三方面的方法的步骤。
本申请实施例的有益效果是：为每个内核设置独立的供电模块，并且可以根据每个内核的实际工况进行供电，不需要为每个内核提供最大的供电电压来为所有内核同时供电，独立供电使处于空闲或只需低负荷运行的内核可以停止供电或低电压运行，可以降低功耗。
本申请实施例的第一方面提供的处理器电路的有益效果在于：通过将每个内核单独使用具有负载检测功能的供电模块进行供电(负载检测功能也可以独立设置)，通过对每个内核的负载电流进行实时监控，可以实现每个内核最贴近实际运行情况的供电，并且实现多线程任务时，内核更加精准的指派处理分配，实现每个内核的最大利用率，从而实现最大限度的节能。
本申请实施例的第二方面提供的供电控制方法的有益效果在于：控制逻辑模块可以将一个以上的内核的任务调度到另一个内核中，调度完成后，被调走任务的内核可以降低其工作的频率，因此基于内核间的任务调度将可以降低部分目标内核的频率，以实现降低功耗。
本申请实施例的第三方面提供的供电控制方法的有益效果在于：处理器内的多个内核的每一个都被控制跟随其频率的变化，以相应的电压进行供电，这样不但可以在多个内核上执行不对称的工作负荷，以提供确定的性能；还可以让负荷低的内核将以较低频率工作，辅以较低的电压进行供电，并将没有操作任务的内核停止供电关闭，以降低不必要的损耗。
可以理解的是，上述第四方面的有益效果可以参见上述第一方面中的相关描述，上述第五方面的有益效果可以参见上述第二方面或第三方面中的相关描述，上述第六方面的有益效果可以参见上述第二方面或第三方面中的相关描述，在此不再赘述。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请第一实施例提供的处理器电路的结构示意图；
图2为图1所示的处理器电路的处理器的结构示意图；
图3为图1所示的处理器电路的供电模块的原理图；
图4为本申请第二实施例提供的处理器电路的结构示意图；
图5为本申请第三实施例提供的处理器电路的结构示意图；
图6为本申请其中一个实施例提供的供电控制方法流程示意图；
图7为本申请其中一个实施例提供的供电控制方法中电压调节的流程示意图；
图8为本申请其中一个实施例提供的供电控制方法中电压调节的流程示意图；
图9为本申请其中一个实施例提供的供电控制方法流程示意图；
图10为本申请其中一个实施例提供的供电控制方法流程示意图；
图11为本申请其中一个实施例提供的供电控制方法中频率调节的流程示意图；
图12为本申请实施例提供的终端设备的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所提供的技术方案，以下结合具体附图及实施例进行详细说明。
请参阅图1，本申请的第一方面实施例提供的一种可应用于终端设备(比如手机、平板电脑、智能手表、个人计算机等)的处理器电路，包括设置有控制逻辑模块120和多个内核110a～110n的处理器100，其中，多个内核110a～110n中的不同内核110a～110n由不同的供电模块200a～200n供电，控制逻辑模块120分别与多个内核110a～110n和多个供电模块200a～200n连接，用于根据目标内核的频率，输出电压调节信号，以使得与目标内核对应的供电模块200a～200n调整供电电压，目标内核为多个内核110a～110n中的至少一个内核。
在一些可选的实施例中，处理器电路包括多个供电模块200a～200n，多个供电模块200a～200n的数量与多个内核110a～110n的数量相同，此时，多个供电模块200a～200n可以集成在处理器100之内，也可以独立于处理器100设置。在另一些可选的实施例中，多个供电模块200a～200n与处理器电路是相互匹配连接的关系；此时，多个供电模块200a～200n是独立于处理器100设置的。
可以理解的是，内核110a～110n的频率代表工作负荷状态。因此，在各个实施例中，处理器100内的多个内核110a～110n的每一个都被控制跟随其频率的变化，以相应的电压进行供电，这样不但可以在多个内核110a～110n上执行不对称的工作负荷，以提供确定的性能；还可以让负荷低的内核110a～110n将以较低频率工作，辅以较低的电压进行供电，甚至将没有操作任务的内核110a～110n停止供电关闭，以降低不必要的损耗。
请参阅图2，处理器100的控制逻辑模块120包括处理器100的非内核部分，比如逻辑控制模块122，用于提供频率的时钟产生模块124，以及调节内核110a～110n工作频率的调频控制模块126，控制逻辑模块120具体可由逻辑电路搭建。在另外的一些实施例中，目标内核的频率调节，可以是通过外部指令进行预设调节；也可以是逻辑控制模块122根据目标内核的负荷状态调整目标内核的频率。而对于目标内核的负荷状态的确定，控制逻辑模块120可以根据目标内核的列队中的下一时刻的任务与当前或历史任务进行比对，比如是与下一时刻的任务相同的任务进行比对，如果没有相同的也可以与相近的任务进行比对，估算即将运行下一时刻的任务的目标内核的下一时刻的负荷状态。
而该下一时刻的负荷状态可以包括空闲、减轻负荷、增加负荷，逻辑控制模块122可以根据预估的即将执行的当前的或下一时刻的负荷状态控制调频控制模块126给该目标内核提供一个预设的频率，也可以是调节频率，比如停止频率(信号)的提供使得目标内核休眠(对应空闲)，降低频率(对应减轻负荷)，升高频率(对应增加负荷)。
其中，该目标内核的负荷状态可以体现在其工作电压或电流，或者工作频率上。也可以体现在该目标内核当前所执行的任务的类型上，比如多图像数据运算的游戏任务、拍摄任务为高负荷量，即时通讯任务、网页浏览任务等为低负荷量。
另外，在调整目标内核的频率的同时，逻辑控制模块122还根据目标内核当前的或下一时刻的频率，输出与该频率对应的电压调节信号，控制为该目标内核供电的相应供电模块200a～200n调整供电电压。具体地，逻辑控制模块122是根据目标内核的频率变化，向供电模块200a～200n输出相应的电压调节信号。
请参阅图3，在一些实施例中，各个供电模块200a～200n分别包括电源控制模块210以及电压变换模块220。各个电源控制模块210分别与控制逻辑模块120和各个电压变换模块220连接，用于接收控制逻辑模块120输出的电压调节信号，以控制电压变换模块220调整输出至目标内核的供电电压VOUT；各个电压变换模块220与各个内核110a～110n连接，用于调整输出至目标内核的供电电压VOUT。
可以理解的是，电压调节信号里面携带具体的目标电压值，或者电压调节信号携带目标内核的频率，电源控制模块210可以根据预存的频率和目标电压值的对应关系确定目标电压值，电源控制模块210将根据电压调节信号控制电压变换模块220的电压变换得到该目标电压值的供电电压VOUT。电源控制模块210可以是基于进阶精简指令集机器(Advanced  RISC Machine，ARM)的单片机、微控制单元(Microcontroller Unit，MCU)等。
在一个示例中，假设处理包括四个内核：内核1、内核2、内核3、内核4，内核1当前或将被调整至工作在1.8G频率下，内核2-4当前或将被调整至工作在1.2G频率下，内核1需要的供电电压为1.2V，内核2-4需要的供电电压为0.8V，则为内核1供电的供电模块的电源控制模块210接收到相应的指令后，控制与其连接的电压变换模块220输出1.2V电压给内核1；为内核2-4供电的供电模块的电源控制模块210接收到相应的指令后，控制与其连接的电压变换模块220输出0.8V电压给内核2-4。
请参阅图4，处理器电路还包括电源管理模块150，电源管理模块150可以是电源管理集成电路(Power Management IC，PMIC)，电源管理模块150分别与控制逻辑模块120和各个供电模块200a～200n中的电源控制模块210连接，电源管理模块150用于接收控制逻辑模块120输出的电压调节信号，并根据电压调节信号控制至少一个电源控制模块210工作。本实施例中，电源管理模块150用于管控多个电源控制模块210去控制相应的电压变换模块220进行供电电压VOUT的调整。在其他实施例中，若处理器100的串口足够，可以省略电源管理模块150以节约成本，而为每个电源控制模块210设置一个相连接的串口以传输电压调节信号，如图1所示。可以理解的是，设置电源管理模块150则可以节省处理器100的串口。
其中，电压变换模块220可以为升压(boost)电路、降压(buck)电路或升降压(boost-buck)电路。请继续参阅图3，在一些实施例中，电压变换模块220为降压电路，包括MOS管M1、M2组成的半桥功率部分以及电感L1、电容C1组成的储能滤波部分，此电压变换模块220主要实现电压转换和功率输出，给相应的内核110a～110n提供供电电压VOUT；具体的，电源控制模块210根据电压调节信号、负载以及输出(供电电压VOUT)的变化，输出控制信号H_Drive、L_Drive分别控制MOS管M1、M2的开关频率以及占空比来实现不同供电电压VOUT的调节。
另外，传统的处理器对线程任务进行内核指派时，具有一定随机性，不能达到每个内核的处理能力的充分利用，基于此，本申请的还对此作出以下改进。
请参阅图3和图5，在其中一些实施例中，处理器电路还包括与各个供电模块200a～200n连接的电流检测模块300；电流检测模块300被配置为：检测各个供电模块200a～200n的输出电流；电流检测模块300的具体是与电源控制模块210连接，电流检测模块300可以采用比如电流镜的方式，耦合电感的方式，串接检流电阻的方式，或者数字采样分析等方式，本申请对此不作限定。并且，电流检测模块300可以包括多个检测支路，多个检测支路和多个供电模块200a～200n一一对应连接，每一检测支路用于检测与其所连接的供电模块200a～200n的输出电流。而在一些情况下，电流检测模块300为设置有多个检测口的单个检测电路，其可以用分时轮流的方式检测各个多个供电模块200a～200n的输出电流。
其中，电流检测模块300所检测到的供电模块200a～200n的输出电流值即为该供电模块200a～200n相关联内核110a～110n工作时所消耗的电流，其包括内核110a～110n在运行时软件以及硬件所消耗，亦反映出了内核110a～110n中运算任务以及控制任务的工况和负荷。
可选地，控制逻辑模块120根据目标内核的负荷状态调整目标内核的频率具体包括：确定各个内核110a～110n(也可以是目标内核)在一段时间内的平均工作电流；根据各个内核110a～110n在一段时间内的平均工作电流进行内核间的任务调度；根据内核间的任务调度的结果调整内核110a～110n的频率。
对于平均工作电流的确定可以在电源控制模块210执行，也可以在控制逻辑模块120执行。具体地，第一种方式是，电源控制模块210从电流检测模块300处获取的各个供电模块200a～200n的输出电流，控制逻辑模块120计算各个供电模块200a～200n对应的每个内核110a～110n在一段时间内的平均工作电流。第二种方式是，电源控制模块210从电流检测模块300处获取的各个供电模块200a～200n的输出电流，同时电源控制模块210还计 算各个供电模块200a～200n对应的每个内核110a～110n在一段时间内的平均工作电流，控制逻辑模块120从各供电模块200a～200n的电源控制模块210处获取各内核110a～110n的一段时间内的平均工作电流传输给。
对于平均工作电流，先计算每个内核110a～110n每个时钟周期的平均工作电流，而所述的一段时间内的平均工作电流即为至少一个时钟周期内的平均工作电流。如此，实现多线程任务时，处理器100的内核110a～110n更加精准的指派任务的处理分配，实现每个内核110a～110n的最大利用率，从而实现最大限度的节能。
在一个可选的实施例中，控制逻辑模块120进行内核间的任务调度具体为：内核间的任务调度包括将第一目标内核的任务调度到第二目标内核执行，此时，可以关闭第一目标内核的供电，或者使第一目标内核进入休眠，以第一目标内核减轻负荷，进而降低供电电压/电流，以降低处理器100功耗。其中，第一目标内核为多个内核110a～110n中的至少一个内核，即可以将一个以上的内核的任务调度到另一个内核中。且在将第一目标内核的任务调度到第二目标内核执行后，第二目标内核在预设时长的平均工作电流小于或等于第二目标内核的满负荷电流，使得第二目标内核能够满足多个任务的同时处理或控制。其中，预设时长可以跟上述的一段时间相同，也可以不同，但也都是至少一个时钟周期。满负荷电流是内核在一定频率下的满负荷运行时所消耗的电流。
在一个可选的实施例中，控制逻辑模块120进行内核间的任务调度具体为：在预设时长内，如果第一目标内核的平均工作电流<I1*80％，第二目标内核的平均工作电流i2<I2*20％，则将第二目标内核中的任务调度到第一目标内核，并关闭所述第二目标内核，其中，I1是第一目标内核的满负荷运行时所消耗的电流，I2是第二目标内核的满负荷运行时所消耗的电流。
在一个可选的实施例中，控制逻辑模块120进行内核间的任务调度具体为：将第二目标内核中的任务调度到第一目标内核，并关闭第二目标内核，第一目标内核为多个内核中在预设时长内平均工作电流<I1*80％的内核，第二目标内核为多个内核中在预设时长内平均工作电流i2<I2*20％的内核。I1是第一目标内核的满负荷运行时所消耗的电流，I2是第二目标内核的满负荷运行时所消耗的电流。
在一个可选的实施例中，根据内核间的任务调度的结果调整与内核间的任务调度相关的内核110a～110n的频率，进而控制逻辑模块120将根据任一内核110a～110n的频率，输出与该频率调整相关的电压调节信号，电源控制模块210将根据电压调节信号调整所提供内核110a～110n的供电电压VOUT。
在一个示例中，比如内核1工作在1.8GHz频率下，此频率下该内核满负荷运行时所消耗的电流为I1，内核2工作在1.2GHz频率下，此频率下该内核满负荷运行时所消耗的电流为I2，电流检测模块300实时监控内核1、2的负载电流(即相应的供电模块200a～200n的输出电流)情况，并传递给电源控制模块210，由电源控制模块210通过通信的方式传递给处理器100中的逻辑控制模块122，逻辑控制模块122计算内核1、2每个时钟周期的平均工作电流，假如多个周期内内核1的平均工作电流为i1，且i1<I1*80％，多个周期内内核2的平均工作电流为i2，且i2<I2*20％，则逻辑控制模块122会将内核2中的任务调度到内核1来执行，进而关闭内核2，从而实现节能的目的。
在一些实施例中，电流检测模块300可以被整合到供电模块200a～200n之内，作为供电模块200a～200n的一部分，以使得供电模块200a～200n有负载检测功能。当然，电流检测模块300也可以独立于供电模块200a～200n。供电模块200a～200n可以使用分立器件实现，也可以采用集成电路实现。
本申请的实施例通过将每个内核110a～110n单独使用具有负载检测功能的供电模块200a～200n进行供电(负载检测功能也可以独立设置)，通过对每个内核110a～110n的负载电流进行实时监控，可以实现每个内核110a～110n最贴近实际运行情况的供电，并且实现多线程任务时，内核110a～110n更加精准的指派处理分配，实现每个内核110a～110n的 最大利用率，从而实现最大限度的节能。
本申请实施例的第二方面提供了一种供电控制方法，应用于为处理器100供电的供电模块200a～200n，处理器100设置有控制逻辑模块120和多个内核110a～110n，多个内核110a～110n中不同的内核110a～110n由不同的供电模块200a～200n供电，请参阅图1至图5，以及图6，供电控制方法包括：
步骤S110，为与供电模块200a～200n连接的各个内核110a～110n提供供电电压。
步骤S120，根据来自控制逻辑模块120为调整目标内核的频率引起的触发，调整所提供给目标内核的供电电压，目标内核为多个内核110a～110n中的至少一个内核。
可以理解的是，内核110a～110n的频率代表工作负荷状态。因此，在各个实施例中，处理器100内的多个内核110a～110n的每一个都被控制跟随其频率的变化，以相应的电压进行供电，这样不但可以在多个内核110a～110n上执行不对称的工作负荷，以提供确定的性能；还可以让负荷低的内核110a～110n将以较低频率工作，辅以较低的电压进行供电，甚至将没有操作任务的内核110a～110n停止供电关闭，以降低不必要的损耗。
内核110a～110n的频率根据内核110a～110n的负荷状态调整。逻辑控制模块122是根据目标内核的负荷状态调整目标内核的频率的，供电模块200a～200n将响应于该目标内核的频率的调整。
在一个可选的实施例中，请参阅图3，各个供电模块200a～200n分别包括电源控制模块210以及与电源控制模块210连接的电压变换模块220，各电源控制模块210与控制逻辑模块120相连，多个电压变换模块220与多个内核110a～110n一一对应连接，请参阅图7，步骤S120包括：
步骤S122，接收控制逻辑模块120根据调整目标内核的频率而输出相应的电压调节信号。
具体地，控制逻辑模块120根据目标内核的频率，生成对应的目标内核的电压调节信号被输出到电源控制模块210。电压调节信号被电源控制模块210用于确定调整后的供电电压VOUT。可以理解的是，电压调节信号里面携带具体的目标电压值，或者电压调节信号携带目标内核的频率，电源控制模块210可以根据预存的频率和目标电压值的对应关系确定目标电压值。
步骤S124，根据接收到的电压调节信号控制供电模块200a～200n的电压变换模块220进行电压变换，以调整目标内核的供电电压。可以理解的是步骤S122、S124可以是被电源控制模块210执行的，也可以是被电源管理模块150执行的。
而对于目标内核的负荷状态的确定，控制逻辑模块120可以根据目标内核的列队中的下一时刻的任务与当前或历史任务进行比对，比如是将与下一时刻的任务相同的任务进行比对，如果没有相同的也可以将相近的任务进行比对，估算即将运行下一时刻的任务的目标内核的下一时刻的负荷状态。
在一个可选的实施例中，请参阅图3、图5和图8，供电控制方法还包括：
步骤S210，确定目标内核在一段时间内的平均工作电流。
具体地，通过电流检测模块300检测各个供电模块200a～200n的输出电流，获取的各个供电模块200a～200n的输出电流，计算各个供电模块200a～200n对应的内核110a～110n在一段时间内的平均工作电流。如上所述，对于一段时间内的平均工作电流的计算，可以参照前述实施例，这里不在赘述。
步骤S220，根据来自控制逻辑模块120根据目标内核在一段时间内的平均工作电流进行内核间的任务调度后而调整目标内核的频率的触发，调整所提供给目标内核的供电电压VOUT。
根据前述实施例可知，目标内核的供电电压VOUT的调整是基于目标内核的频率的变化，本实施例中，基于为了降低功耗，控制逻辑模块120可以将一个以上的内核的任务调度到另一个内核中，调度完成后，被调走任务的内核可以降低其工作的频率，因此基于内 核间的任务调度将可以降低部分目标内核的频率，以此作为触发，供电模块200a～200n将调整所提供给该部分目标内核的供电电压VOUT。可以理解的是，电源控制模块210将根据控制逻辑模块120基于内核间的任务调度调整目标内核的频率而输出与频率的调节相关的电压调节信号，调整所提供目标内核的供电电压VOUT。
而关于内核间的任务调度的具体说明，可以参照前述的实施例，这里不再赘述。
本申请实施例第三方面还提供了另一种供电控制方法，应用于设置有多个内核110a～110n的处理器100，多个内核110a～110n中的不同内核110a～110n由不同的供电模块200a～200n供电，请参阅图1至图5，以及图9，供电控制方法包括：
步骤S320，在目标内核的供电模块200a～200n为目标内核供电过程中，获取目标内核的频率，目标内核为多个内核110a～110n中的至少一个内核。
步骤S340，根据目标内核的频率，控制为目标内核供电的供电模块200a～200n调整所提供给目标内核的供电电压。
可以理解的是，内核110a～110n的频率可以代表工作负荷状态。因此，在各个实施例中，处理器100内的多个内核110a～110n的每一个都被控制跟随其频率的变化，以相应的电压进行供电，这样不但可以在多个内核110a～110n上执行不对称的工作负荷，以提供确定的性能；还可以让负荷低的内核110a～110n将以较低频率工作，辅以较低的电压进行供电，甚至将没有操作任务的内核110a～110n停止供电关闭，以降低不必要的损耗。
请参阅图10，在一个可选的实施例中，供电控制方法在步骤S320之前还包括：步骤S310，根据目标内核的负荷状态调整目标内核的频率。一般地，负荷状态可以分为空闲、减轻负荷、增加负荷。相应的，调整相应目标内核的频率可以是停止频率(信号)的提供使得目标内核休眠(对应空闲)，降低频率(对应减轻负荷)，升高频率(对应增加负荷)。
在另外的一些实施例中，内核110a～110n的频率调节，可以是通过外部指令进行预设调节；也可以是逻辑控制模块122根据目标内核的负荷状态调整相应目标内核的频率。而对于内核110a～110n的负荷状态的确定，控制逻辑模块120可以根据目标内核的列队中的下一时刻的任务与当前或历史任务进行比对，比如是将与下一时刻的任务相同的任务进行比对，如果没有相同的也可以将相近的任务进行比对，估算即将运行下一时刻的任务的目标内核的下一时刻的负荷状态。
该下一时刻的负荷状态可以包括空闲、减轻负荷、增加负荷，逻辑控制模块122可以根据预估的即将执行的当前的或下一时刻的负荷状态控制调频控制模块126给该目标内核提供一个预设的频率，也可以是调节频率，比如停止频率(信号)的提供使得目标内核休眠(对应空闲)，降低频率(对应减轻负荷)，升高频率(对应增加负荷)。其中，该目标内核的负荷量可以体现在其工作电压或电流或功率，或者工作频率上。
在一个更详细的实施例中，步骤S320包括根据目标内核的频率，向为目标内核供电的供电模块200a～200n的电源控制模块210输出相应的电压调节信号。其中，电压调节信号用于指示电源控制模块210控制调整供电模块200a～200n的电压变换模块220所进行的电压变换，以调整述电压变换模块220向目标内核所提供的供电电压VOUT。供电模块的实施方式可以参阅图3及其说明。
另外，传统的处理器对线程任务进行内核指派时，具有一定随机性，不能达到每个内核的处理能力的充分利用，基于此，本申请的供电控制方法还对此作出以下改进。
请参阅图3、图5和图11，在一个可选的实施例中，步骤S310根据目标内核的负荷状态调整目标内核的频率包括：
步骤S312，确定目标内核在一段时间内的平均工作电流。具体地，通过电流检测模块300检测各个供电模块200a～200n的输出电流，获取的各个供电模块200a～200n的输出电流，计算各个供电模块200a～200n对应的目标内核在一段时间内的平均工作电流。如上所述，对于一段时间内的平均工作电流的计算，可以参照前述实施例，这里不在赘述。
步骤S314，根据目标内核在一段时间内的平均工作电流进行内核间的任务调度。
在一个可选的实施例中，内核间的任务调度包括将第一目标内核的任务调度到第二目标内核执行，并关闭第一目标内核，以降低处理器100功耗。其中，第一目标内核为多个内核110a～110n中的至少一个内核，且在将第一目标内核的任务调度到第二目标内核执行后，第二目标内核在预设时长的平均工作电流小于或等于第二目标内核的满负荷电流。使得第二目标内核能够满足多个任务的同时处理或控制。其中，预设时长可以跟上述的一段时间相同，也可以不同，但也都是至少一个时钟周期。满负荷电流是内核在一定频率下的满负荷运行时所消耗的电流。
比如在一个示例中，内核1工作在1.8GHz频率下，此频率下该内核满负荷运行时所消耗的电流为I1，内核2工作在1.2GHz频率下，此频率下该内核满负荷运行时所消耗的电流为I2，电流检测模块300实时监控内核1、2的负载电流(即相应的供电模块200a～200n的输出电流)情况，并传递给电源控制模块210，由电源控制模块210通过通信的方式传递给处理器100中的逻辑控制模块122，逻辑控制模块122计算内核1、2每个时钟周期的平均工作电流，假如多个周期内内核1的平均工作电流为i1，且i1<I1*80％，多个周期内内核2的平均工作电流为i2，且i2<I2*20％，则逻辑控制模块122会将内核2中的任务调度到内核1来执行，进而关闭内核2，从而实现节能的目的。
步骤S316，根据内核间的任务调度的结果调整与任务调度相关的目标内核的频率。进而控制逻辑模块120将根据目标内核的频率，控制为目标内核供电的供电模块调整为目标内核提供的供电电压VOUT。
对于步骤S312，确定目标内核在一段时间内的平均工作电流包括：控制逻辑模块120根据所获取的各个供电模块200a～200n的输出电流，并计算各个供电模块200a～200n对应的目标内核在一段时间内的平均工作电流；或者，包括控制逻辑模块120从各供电模块200a～200n处获取被电源管理模块150或电源控制模块210先计算好的目标内核在一段时间内的平均工作电流，而内核在一段时间内的平均工作电流由电源管理模块150或电源控制模块210根据电流检测模块300检测的供电模块200a～200n的输出电流计算得到。
可以理解的是，内核间的任务调度也是内核的负荷状态的改变的一种，即控制逻辑模块120可以基于内核间的任务调度，而调整内核110a～110n的频率并输出与该频率调整相关的电压调节信号，电源控制模块210将根据电压调节信号调整所提供内核110a～110n的供电电压VOUT。
本申请的实施例中第二方面提供的供电控制方法可以由供电模块200a～200n的电源控制模块210执行计算机程序时实现，也可以是电源管理模块150执行计算机程序时实现。本申请的实施例中第三方面提供的供电控制方法可以由处理器100内的控制逻辑模块120执行计算机程序时实现，也可以是处理器100内的其他控制器执行计算机程序时实现，比如功率控制逻辑模块。也可以是由处理器100之外的其他控制器执行计算机程序时实现。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述处理器电路的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
基于同一构思，本申请实施例还提供了一种储能设备数据显示设备。图12为本申请实施例提供的储能设备数据显示设备的结构示意图，如图12所示，本实施例提供的终端设备包括：存储器400和处理器100，存储器400用于存储计算机程序；处理器100用于在调用计算机程序时执行上述方法实施例所述的方法。在其他实施例中，本实施例提供的终端 设备包括处理器100，计算机程序存储于处理器100，处理器100用于在调用计算机程序时执行上述方法实施例所述的方法。
本申请实施例提供的终端设备可以执行上述方法实施例，其实现原理与技术效果类似，此处不再赘述。
本申请实施例还提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现上述方法实施例所述的方法。
本领域技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质上实施的计算机程序产品的形式。
处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
存储器可能包括计算机可读介质中的非永久性存储器，随机存取存储器(Random Access Memory，RAM)和/或非易失性内存等形式，如只读存储器(Read-Only Memory，ROM)或闪存(Flash Memory)。存储器是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动存储介质。存储介质可以由任何方法或技术来实现信息存储，信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(Phase-Change Memory，PCM)、静态随机存取存储器(Static Random-Access Memory，SRAM)、动态随机存取存储器(Dynamic Random Access Memory，DRAM)、其他类型的RAM、ROM、电可擦除可编程只读存储器(Electrically-Erasable Programmable Read-Only Memory，EEPROM)、快闪记忆体或其他内存技术、只读光盘、ROM、数字多功能光盘(Digital Versatile Disc，DVD)或其他光学存储、磁盒式磁带，磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体，如调制的数据信号和载波。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (23)

  1. 一种处理器电路，其特征在于，包括：
    处理器，所述处理器设置有控制逻辑模块和多个内核；
    其中，多个内核中的不同内核分别由不同供电模块进行供电；所述控制逻辑模块分别与多个内核和多个供电模块连接，用于根据目标内核的频率，输出电压调节信号，以使得与所述目标内核对应的供电模块调整供电电压，所述目标内核为多个内核中的至少一个内核。
  2. 根据权利要求1所述的处理器电路，其特征在于，所述供电模块包括电源控制模块和电压变换模块；
    所述电源控制模块分别与所述控制逻辑模块和所述电压变换模块连接，用于接收所述控制逻辑模块输出的所述电压调节信号，以控制所述电压变换模块调整输出至所述目标内核的供电电压；
    所述电压变换模块与所述目标内核连接，用于调整输出至所述目标内核的供电电压。
  3. 根据权利要求2所述的处理器电路，其特征在于，还包括电源管理模块；
    所述电源管理模块分别与所述控制逻辑模块和各个所述电源控制模块连接，用于接收所述控制逻辑模块输出的所述电压调节信号，并根据所述电压调节信号，控制至少一个所述电源控制模块工作。
  4. 根据权利要求1至3任一项所述的处理器电路，其特征在于，所述控制逻辑模块还配置有如下功能：根据所述目标内核的负荷状态调整所述目标内核的频率。
  5. 根据权利要求4所述的处理器电路，其特征在于，所述根据所述目标内核的负荷状态调整所述目标内核的频率，包括：
    确定所述目标内核在一段时间内的平均工作电流；
    根据所述目标内核在所述一段时间内的平均工作电流进行内核间的任务调度；
    根据所述内核间的任务调度的结果调整所述目标内核的频率。
  6. 根据权利要求5所述的处理器电路，其特征在于，还包括电流检测模块，所述电流检测模块与各个所述供电模块连接，用于检测各个所述供电模块的输出电流；
    相应的，所述确定所述目标内核在一段时间内的平均工作电流，包括：
    所述控制逻辑模块从所述电流检测模块获取各个所述供电模块的输出电流，并根据各个所述供电模块的输出电流计算每个所述供电模块对应连接的所述目标内核在一段时间内的平均工作电流；或者，所述供电模块的电源控制模块从所述电流检测模块处获取所述供电模块的输出电流，并根据所述供电模块的输出电流计算所述供电模块对应连接的所述目标内核在一段时间内的平均工作电流，并传输至所述控制逻辑模块。
  7. 根据权利要求6所述的处理器电路，其特征在于，所述电流检测模块包括多个检测支路，各个所述检测支路和各个所述供电模块一一对应连接，每一所述检测支路用于检测与其对应连接的所述供电模块的输出电流。
  8. 根据权利要求5所述的处理器电路，其特征在于，所述内核间的任务调度包括将第一目标内核的任务调度到第二目标内核执行；
    其中，所述第一目标内核为多个内核中的至少一个内核，且在将所述第一目标内核的任务调度到所述第二目标内核执行后，所述第二目标内核在预设时长的平均工作电流小于或等于所述第二目标内核的满负荷电流。
  9. 一种供电控制方法，其特征在于，应用于为处理器供电的供电模块，所述处理器设置有控制逻辑模块和多个内核，多个内核中不同的内核由不同的供电模块供电，所述供电控制方法包括：
    为与所述供电模块连接的各个所述内核提供供电电压；
    根据来自所述控制逻辑模块为调整目标内核的频率引起的触发，调整所提供给所述目标内核的供电电压，所述目标内核为多个内核中的至少一个内核。
  10. 根据权利要求9所述的供电控制方法，其特征在于，所述触发由所述控制逻辑模块根据所述目标内核的负荷状态调整所述目标内核的频率引起。
  11. 根据权利要求9或10所述的供电控制方法，其特征在于，所述供电控制方法还包括：
    确定所述目标内核在一段时间内的平均工作电流；
    根据来自所述控制逻辑模块根据所述目标内核在所述一段时间内的平均工作电流进行内核间的任务调度后而调整所述目标内核的频率的触发，调整所提供给所述目标内核的供电电压。
  12. 根据权利要求11所述的供电控制方法，其特征在于，所述确定所述目标内核在一段时间内的平均工作电流，包括：
    获取的所述供电模块的输出电流，计算所述供电模块对应的所述目标内核在一段时间内的平均工作电流。
  13. 根据权利要求11所述的供电控制方法，其特征在于，所述内核间的任务调度包括将第一目标内核的任务调度到第二目标内核执行；
    其中，所述第一目标内核为多个内核中的至少一个内核，且在将第一目标内核的任务调度到所述第二目标内核执行后，所述第二目标内核在预设时长的平均工作电流小于或等于所述第二目标内核的满负荷电流。
  14. 根据权利要求9或10所述的供电控制方法，其特征在于，所述根据来自所述控制逻辑模块为调整目标内核的频率引起的触发，调整为所述目标内核所提供给所述目标内核的供电电压，包括：
    接收所述控制逻辑模块根据调整所述目标内核的频率而输出相应的电压调节信号；
    根据接收到的电压调节信号控制所述供电模块的电压变换模块进行电压变换，以调整所述目标内核的供电电压。
  15. 一种供电控制方法，其特征在于，应用于设置有多个内核的处理器，多个内核中不同的内核由不同的供电模块供电，所述供电控制方法包括：
    在目标内核的所述供电模块为所述目标内核供电过程中，获取所述目标内核的频率，所述目标内核为多个内核中的至少一个内核；
    根据所述目标内核的频率，控制为所述目标内核供电的所述供电模块调整所提供给所述目标内核的供电电压。
  16. 根据权利要求15所述的供电控制方法，其特征在于，在所述在目标内核的所述供电模块为所述目标内核供电过程中，获取所述目标内核的频率之前，还包括：
    根据所述目标内核的负荷状态调整所述目标内核的频率。
  17. 根据权利要求16所述的供电控制方法，其特征在于，所述根据所述目标内核的负荷状态调整所述目标内核的频率，包括：
    确定所述目标内核在一段时间内的平均工作电流；
    根据所述目标内核在所述一段时间内的平均工作电流进行内核间的任务调度；
    根据所述内核间的任务调度的结果调整与所述内核间的任务调度相关的所述目标内核的频率。
  18. 根据权利要求17所述的供电控制方法，其特征在于，所述确定所述目标内核在一段时间内的平均工作电流，包括：
    根据所获取的各个所述供电模块的输出电流，计算各个所述供电模块对应的所述目标内核在一段时间内的平均工作电流；或者，
    从各所述供电模块处获取各所述目标内核在一段时间内的平均工作电流，其中，所述目标内核在一段时间内的平均工作电流由对应的所述供电模块根据电流检测模块检测的所 述供电模块的输出电流计算得到。
  19. 根据权利要求17所述的供电控制方法，其特征在于，所述内核间的任务调度包括将第一目标内核的任务调度到第二目标内核执行；
    其中，所述第一目标内核为多个内核中的至少一个内核，且在将第一目标内核的任务调度到所述第二目标内核执行后，所述第二目标内核在预设时长的平均工作电流小于或等于所述第二目标内核的满负荷电流。
  20. 根据权利要求15或16所述的供电控制方法，其特征在于，所述根据所述目标内核的频率，控制为所述目标内核供电的所述供电模块调整所提供给所述目标内核的供电电压，包括：
    根据所述目标内核的频率，向为所述目标内核供电的所述供电模块的电源控制模块输出相应的电压调节信号；
    其中，所述电压调节信号用于指示所述电源控制模块控制调整所述供电模块的电压变换模块所进行的电压变换，以调整所述电压变换模块向所述目标内核所提供的供电电压。
  21. 一种终端设备，其特征在于，包括如权利要求1至8任一项所述的处理器电路。
  22. 一种终端设备，包括处理器以及存储在所述处理器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求9至14任一项所述方法的步骤，或实现如权利要求15至20任一项所述方法的步骤。
  23. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求9至14任一项所述方法的步骤，或实现如权利要求15至20任一项所述方法的步骤。
PCT/CN2022/109476 2021-11-11 2022-08-01 处理器电路、供电控制方法及终端设备 WO2023082723A1 (zh)

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CN105022469A (zh) * 2014-04-24 2015-11-04 宏达国际电子股份有限公司 便携式电子装置及其内核交换方法
CN110245109A (zh) * 2019-04-26 2019-09-17 深圳市致宸信息科技有限公司 实现系统级芯片soc低功耗控制的方法及soc
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CN105022469A (zh) * 2014-04-24 2015-11-04 宏达国际电子股份有限公司 便携式电子装置及其内核交换方法
CN110245109A (zh) * 2019-04-26 2019-09-17 深圳市致宸信息科技有限公司 实现系统级芯片soc低功耗控制的方法及soc
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