WO2023080084A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2023080084A1
WO2023080084A1 PCT/JP2022/040496 JP2022040496W WO2023080084A1 WO 2023080084 A1 WO2023080084 A1 WO 2023080084A1 JP 2022040496 W JP2022040496 W JP 2022040496W WO 2023080084 A1 WO2023080084 A1 WO 2023080084A1
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Prior art keywords
electrode
semiconductor device
gate
insulating film
source
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PCT/JP2022/040496
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English (en)
Japanese (ja)
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佑紀 中野
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ローム株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • Patent Document 1 discloses a semiconductor device including a semiconductor substrate, electrodes and a protective layer.
  • the electrode is arranged on the semiconductor substrate.
  • the protective layer has a laminate structure including an inorganic protective layer and an organic protective layer, and covers the electrodes.
  • One embodiment provides a semiconductor device capable of improving reliability.
  • One embodiment includes a chip having a main surface, a main surface electrode arranged on the main surface, and a terminal electrode arranged on the main surface electrode so as to expose a part of the main surface electrode. and a sealing insulator covering the periphery of the terminal electrode so as to partially expose the terminal electrode and having a portion directly covering the main surface electrode.
  • One embodiment has a chip having a main surface, a main surface electrode disposed on the main surface, and a single layer structure composed of an inorganic film or an organic film, and a part of the main surface electrode is exposed.
  • a terminal electrode disposed on the principal surface electrode; a periphery of the terminal electrode so as to expose the terminal electrode; and an encapsulating insulator having a portion directly covering the insulating film thereon.
  • FIG. 1 is a plan view showing the semiconductor device according to the first embodiment.
  • FIG. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a cross-sectional view taken along line III-III shown in FIG.
  • FIG. 4 is an enlarged plan view showing the main part of the inner part of the chip.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG.
  • FIG. 6 is an enlarged cross-sectional view showing the main part of the periphery of the chip.
  • FIG. 7 is a plan view showing a layout example of gate electrodes and source electrodes.
  • 8 is a cross-sectional view showing a main part of the gate terminal electrode shown in FIG. 3.
  • FIG. 9 is a cross-sectional view showing a main part of the source terminal electrode shown in FIG. 3.
  • FIG. FIG. 10 is a plan view showing the wafer structure used during fabrication.
  • 11 is a cross-sectional view showing the device region shown in FIG. 10.
  • FIG. 12A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 12B is a cross-sectional view showing a step after FIG. 12A.
  • FIG. 12C is a cross-sectional view showing a step after FIG. 12B.
  • FIG. 12D is a cross-sectional view showing a step after FIG. 12C.
  • FIG. 12E is a cross-sectional view showing a step after FIG. 12D.
  • FIG. 12F is a cross-sectional view showing a step after FIG. 12E.
  • FIG. 12G is a cross-sectional view showing a step after FIG. 12F.
  • FIG. 12H is a cross-sectional view showing a step after FIG. 12G.
  • FIG. 12I is a cross-sectional view showing a step after FIG. 12H.
  • FIG. 13 is a cross-sectional view showing the semiconductor device according to the second embodiment.
  • 14 is a cross-sectional view showing a main part of the gate terminal electrode shown in FIG. 13.
  • FIG. 15 is a cross-sectional view showing a main part of the source terminal electrode shown in FIG. 13.
  • FIG. 16 is a plan view showing a layout example of the upper insulating film shown in FIG. 13.
  • FIG. 17A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 13.
  • FIG. FIG. 17B is a cross-sectional view showing a step after FIG. 17A.
  • FIG. 18 is a cross-sectional view showing the semiconductor device according to the third embodiment.
  • 19A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 18.
  • FIG. 19B is a cross-sectional view showing a step after FIG. 19A.
  • FIG. 20 is a cross-sectional view showing a semiconductor device according to the fourth embodiment.
  • 21 is a cross-sectional view showing a main part of the gate terminal electrode shown in FIG. 20.
  • FIG. 22 is a cross-sectional view showing a main part of the source terminal electrode shown in FIG. 20.
  • FIG. 23 is a plan view showing a layout example of the upper insulating film shown in FIG. 20.
  • FIG. FIG. 24 is a plan view showing the semiconductor device according to the fifth embodiment.
  • FIG. 25 is a plan view showing the semiconductor device according to the sixth embodiment.
  • 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25.
  • FIG. FIG. 27 is a circuit diagram showing an electrical configuration of the semiconductor device shown in FIG. 25.
  • Referring to FIG. FIG. 28 is a plan view showing the semiconductor device according to the seventh embodiment. 29 is a cross-sectional view taken along line XXIX-XXIX shown in FIG. 28.
  • FIG. 30 is a plan view showing the semiconductor device according to the eighth embodiment.
  • FIG. 31 is a plan view showing the semiconductor device according to the ninth embodiment.
  • FIG. 32 is a plan view showing the semiconductor device according to the tenth embodiment.
  • FIG. 33 is a plan view showing the semiconductor device according to the eleventh embodiment.
  • 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 33.
  • FIG. FIG. 35 is a plan view showing the semiconductor device according to the twelfth embodiment.
  • FIG. 36 is a plan view showing a semiconductor device according to the thirteenth embodiment.
  • FIG. 37 is a plan view showing the semiconductor device according to the fourteenth embodiment.
  • FIG. 38 is a cross-sectional view showing a modification of the chip applied to each embodiment.
  • FIG. 39 is a cross-sectional view showing a modification of the sealing insulator applied to each embodiment having an upper insulating film.
  • FIG. 40 is a plan view showing a package in which the semiconductor devices according to the first to tenth embodiments are mounted.
  • FIG. 41 is a plan view showing a package on which semiconductor devices according to eleventh to fourteenth embodiments are mounted.
  • FIG. 42 is a perspective view showing a package in which the semiconductor devices according to the first to tenth embodiments and the semiconductor devices according to the eleventh to fourteenth embodiments are mounted.
  • 43 is an exploded perspective view of the package shown in FIG. 42.
  • FIG. 44 is a cross-sectional view taken along line XLIV-XLIV shown in FIG. 42.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a cross-sectional view taken along line III-III shown in FIG.
  • FIG. 4 is an enlarged plan view showing the main part of the inner part of the chip 2.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG.
  • FIG. 6 is an enlarged cross-sectional view showing the essential parts of the periphery of the chip 2.
  • FIG. 7 is a plan view showing a layout example of the gate electrode 30 and the source electrode 32.
  • FIG. FIG. 8 is a cross-sectional view showing a main part of the gate terminal electrode 50 shown in FIG.
  • FIG. 9 is a cross-sectional view showing a main part of the source terminal electrode 60 shown in FIG. 3.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • a semiconductor device 1A in this embodiment includes a chip 2 which includes a wide bandgap semiconductor single crystal and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). include. That is, the semiconductor device 1A is a "wide bandgap semiconductor device". Chip 2 may also be referred to as a "semiconductor chip” or a "wide bandgap semiconductor chip”.
  • a wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). GaN (gallium nitride), SiC (silicon carbide) and C (diamond) are exemplified as wide bandgap semiconductors.
  • the chip 2 is, in this embodiment, a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. That is, the semiconductor device 1A is a "SiC semiconductor device". Hexagonal SiC single crystals have a plurality of polytypes including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals and the like. In this form an example is shown in which the chip 2 comprises a 4H—SiC single crystal, but this does not exclude the choice of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. ing.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2 .
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of SiC single crystal.
  • the first main surface 3 is formed by the silicon surface of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface of the SiC single crystal.
  • the first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane.
  • the off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may exceed 0° and be 10° or less.
  • the off angle is preferably 5° or less.
  • the second main surface 4 may be a ground surface having grinding marks, or may be a smooth surface having no grinding marks.
  • the first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y intersecting (specifically, perpendicular to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks, or may be smooth surfaces having no grinding marks.
  • the chip 2 may have a thickness of 5 ⁇ m or more and 250 ⁇ m or less with respect to the normal direction Z.
  • the thickness of the chip 2 may be 100 ⁇ m or less.
  • the thickness of the chip 2 is preferably 50 ⁇ m or less. It is particularly preferable that the thickness of the chip 2 is 40 ⁇ m or less.
  • the first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 10 mm or less in plan view.
  • the length of the first to fourth side surfaces 5A to 5D is preferably 1 mm or more. It is particularly preferable that the lengths of the first to fourth side surfaces 5A to 5D are 2 mm or more. That is, it is preferable that the chip 2 has a plane area of 1 mm square or more (preferably 2 mm square or more) and a thickness of 100 ⁇ m or less (preferably 50 ⁇ m or less) in a cross-sectional view. The lengths of the first to fourth side surfaces 5A to 5D are set in the range of 4 mm or more and 6 mm or less in this embodiment.
  • the semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side within the chip 2 .
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 consists of an epitaxial layer (specifically, a SiC epitaxial layer) in this embodiment.
  • the first semiconductor region 6 may have a thickness in the normal direction Z of 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the first semiconductor region 6 is preferably 3 ⁇ m or more and 30 ⁇ m or less. It is particularly preferable that the thickness of the first semiconductor region 6 is 5 ⁇ m or more and 25 ⁇ m or less.
  • the semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer portion) on the second main surface 4 side within the chip 2 .
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 .
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate) in this embodiment. That is, the chip 2 has a laminated structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 may have a thickness of 1 ⁇ m or more and 200 ⁇ m or less with respect to the normal direction Z.
  • the thickness of the second semiconductor region 7 is preferably 5 ⁇ m or more and 50 ⁇ m or less. It is particularly preferable that the thickness of the second semiconductor region 7 is 5 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the second semiconductor region 7 is preferably 10 ⁇ m or more. Most preferably, the thickness of the second semiconductor region 7 is less than the thickness of the first semiconductor region 6 .
  • the resistance value for example, on-resistance
  • the thickness of the second semiconductor region 7 may exceed the thickness of the first semiconductor region 6 .
  • the semiconductor device 1A includes an active surface 8 formed on the first main surface 3, an outer surface 9, and first to fourth connection surfaces 10A to 10D (connecting surfaces).
  • the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D define a mesa portion 11 (plateau) on the first main surface 3.
  • the active surface 8 may be called "first surface”
  • the outer surface 9 may be called “second surface”
  • the first to fourth connection surfaces 10A to 10D may be called “connection surfaces”.
  • the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A-10D (that is, the mesa portion 11) may be regarded as components of the chip 2 (first main surface 3).
  • the active surface 8 is formed spaced inwardly from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).
  • the active surface 8 has a flat surface extending in the first direction X and the second direction Y. As shown in FIG. In this form, the active surface 8 is formed in a square shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.
  • the outer surface 9 is located outside the active surface 8 and recessed from the active surface 8 in the thickness direction of the chip 2 (the second main surface 4 side). Specifically, the outer surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6 .
  • the outer side surface 9 extends in a belt shape along the active surface 8 in a plan view and is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active surface 8 .
  • the outer side surface 9 has flat surfaces extending in the first direction X and the second direction Y and formed substantially parallel to the active surface 8 .
  • the outer side surface 9 is continuous with the first to fourth side surfaces 5A to 5D.
  • the first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer surface 9.
  • the first connection surface 10A is positioned on the first side surface 5A side
  • the second connection surface 10B is positioned on the second side surface 5B side
  • the third connection surface 10C is positioned on the third side surface 5C side
  • the fourth connection surface 10D. is located on the side of the fourth side surface 5D.
  • the first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y.
  • the third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 10A to 10D may extend substantially vertically between the active surface 8 and the outer surface 9 so as to define a quadrangular prism-shaped mesa portion 11.
  • the first to fourth connection surfaces 10A to 10D may be inclined downward from the active surface 8 toward the outer surface 9 so that the mesa portion 11 in the shape of a truncated square pyramid is defined.
  • semiconductor device 1A includes mesa portion 11 formed in first semiconductor region 6 on first main surface 3 .
  • the mesa portion 11 is formed only in the first semiconductor region 6 and not formed in the second semiconductor region 7 .
  • a semiconductor device 1A includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure 12 formed on an active surface 8 (first main surface 3). 2 and 3, the MISFET structure 12 is shown simplified by dashed lines. A specific structure of the MISFET structure 12 will be described below with reference to FIGS. 4 and 5. FIG.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the MISFET structure 12 includes a p-type (second conductivity type) body region 13 formed on the surface layer of the active surface 8 .
  • the body region 13 is formed spaced from the bottom of the first semiconductor region 6 toward the active surface 8 side.
  • Body region 13 is formed in a layered shape extending along active surface 8 .
  • the body region 13 may be partially exposed from the first to fourth connection surfaces 10A to 10D.
  • the MISFET structure 12 includes an n-type source region 14 formed on the surface layer of the body region 13 .
  • the source region 14 has an n-type impurity concentration higher than that of the first semiconductor region 6 .
  • the source region 14 is formed spaced from the bottom of the body region 13 toward the active surface 8 side.
  • the source region 14 is formed in layers extending along the active surface 8 .
  • Source region 14 may be exposed from the entire active surface 8 .
  • the source region 14 may be exposed from part of the first to fourth connection surfaces 10A to 10D.
  • Source region 14 forms a channel in body region 13 with first semiconductor region 6 .
  • the MISFET structure 12 includes multiple gate structures 15 formed on the active surface 8 .
  • the plurality of gate structures 15 are arranged in the first direction X at intervals in plan view, and are formed in strips extending in the second direction Y, respectively.
  • a plurality of gate structures 15 extend through the body region 13 and the source region 14 to reach the first semiconductor region 6 .
  • a plurality of gate structures 15 control channel inversion and non-inversion within the body region 13 .
  • Each gate structure 15, in this form, includes a gate trench 15a, a gate insulating film 15b and a gate buried electrode 15c.
  • a gate trench 15 a is formed in the active surface 8 and defines the walls of the gate structure 15 .
  • the gate insulating film 15b covers the walls of the gate trench 15a.
  • the gate buried electrode 15c is buried in the gate trench 15a with the gate insulating film 15b interposed therebetween and faces the channel with the gate insulating film 15b interposed therebetween.
  • the MISFET structure 12 includes multiple source structures 16 formed on the active surface 8 .
  • a plurality of source structures 16 are arranged in regions between a pair of adjacent gate structures 15 on the active surface 8 .
  • the plurality of source structures 16 are each formed in a strip shape extending in the second direction Y in plan view.
  • a plurality of source structures 16 extend through the body region 13 and the source region 14 to reach the first semiconductor region 6 .
  • a plurality of source structures 16 have a depth that exceeds the depth of gate structures 15 .
  • the plurality of source structures 16 specifically has a depth approximately equal to the depth of the outer surface 9 .
  • Each source structure 16 includes a source trench 16a, a source insulating film 16b and a source buried electrode 16c.
  • a source trench 16 a is formed in the active surface 8 and defines the walls of the source structure 16 .
  • the source insulating film 16b covers the walls of the source trench 16a.
  • the source buried electrode 16c is buried in the source trench 16a with the source insulating film 16b interposed therebetween.
  • the MISFET structure 12 includes a plurality of p-type contact regions 17 respectively formed in regions along the plurality of source structures 16 within the chip 2 .
  • a plurality of contact regions 17 have a higher p-type impurity concentration than body region 13 .
  • Each contact region 17 covers the sidewalls and bottom walls of each source structure 16 and is electrically connected to body region 13 .
  • the MISFET structure 12 includes a plurality of p-type well regions 18 respectively formed in regions along the plurality of source structures 16 within the chip 2 .
  • Each well region 18 may have a p-type impurity concentration higher than body region 13 and lower than contact region 17 .
  • Each well region 18 covers the corresponding source structure 16 with the corresponding contact region 17 interposed therebetween.
  • Each well region 18 covers the sidewalls and bottom walls of corresponding source structure 16 and is electrically connected to body region 13 and contact region 17 .
  • semiconductor device 1A includes p-type outer contact region 19 formed in the surface layer portion of outer side surface 9 .
  • Outer contact region 19 has a p-type impurity concentration higher than that of body region 13 .
  • the outer contact region 19 is formed in a band-like shape extending along the active surface 8 and spaced apart from the peripheral edge of the active surface 8 and the peripheral edge of the outer side surface 9 in plan view.
  • the outer contact region 19 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.
  • the outer contact region 19 is formed spaced apart from the bottom of the first semiconductor region 6 to the outer side surface 9 .
  • the outer contact region 19 is located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16).
  • the semiconductor device 1A includes a p-type outer well region 20 formed in the surface layer portion of the outer side surface 9 .
  • the outer well region 20 has a p-type impurity concentration lower than that of the outer contact region 19 .
  • the p-type impurity concentration of the outer well region 20 is preferably approximately equal to the p-type impurity concentration of the well region 18 .
  • the outer well region 20 is formed in a region between the peripheral edge of the active surface 8 and the outer contact region 19 in plan view, and is formed in a strip shape extending along the active surface 8 .
  • the outer well region 20 is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active surface 8 in plan view.
  • the outer well region 20 is formed spaced apart from the bottom of the first semiconductor region 6 to the outer side surface 9 .
  • the outer well region 20 may be formed deeper than the outer contact region 19 .
  • the outer well region 20 is located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16).
  • the outer well region 20 is electrically connected to the outer contact region 19.
  • the outer well region 20 extends from the outer contact region 19 side toward the first to fourth connection surfaces 10A to 10D and covers the first to fourth connection surfaces 10A to 10D.
  • Outer well region 20 is electrically connected to body region 13 at the surface layer of active surface 8 .
  • the semiconductor device 1A has at least one (preferably two or more and twenty or less) p-type field regions 21 formed in a region between the peripheral edge of the outer side surface 9 and the outer contact region 19 in the surface layer portion of the outer side surface 9. including.
  • the semiconductor device 1A includes five field regions 21 in this form.
  • a plurality of field regions 21 relax the electric field within the chip 2 at the outer surface 9 .
  • the number, width, depth, p-type impurity concentration, etc. of the field regions 21 are arbitrary and can take various values according to the electric field to be relaxed.
  • the plurality of field regions 21 are arranged at intervals from the outer contact region 19 side to the peripheral edge side of the outer surface 9 .
  • the plurality of field regions 21 are formed in strips extending along the active surface 8 in plan view.
  • the plurality of field regions 21 are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.
  • the plurality of field regions 21 are each formed as an FLR (Field Limiting Ring) region.
  • a plurality of field regions 21 are formed at intervals from the bottom of the first semiconductor region 6 to the outer surface 9 .
  • the plurality of field regions 21 are located on the bottom side of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (source structures 16).
  • a plurality of field regions 21 may be formed deeper than the outer contact region 19 .
  • the innermost field region 21 may be connected to the outer contact region 19 .
  • the semiconductor device 1A includes a main surface insulating film 25 covering the first main surface 3.
  • Main surface insulating film 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 25 has a single layer structure made of a silicon oxide film in this embodiment.
  • Main surface insulating film 25 particularly preferably includes a silicon oxide film made of oxide of chip 2 .
  • the main surface insulating film 25 covers the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D.
  • the main surface insulating film 25 continues to the gate insulating film 15b and the source insulating film 16b, and covers the active surface 8 so as to expose the gate buried electrode 15c and the source buried electrode 16c.
  • the main surface insulating film 25 covers the outer surface 9 and the first to fourth connection surfaces 10A to 10D so as to cover the outer contact region 19, the outer well region 20 and the plurality of field regions 21. As shown in FIG.
  • the main surface insulating film 25 may be continuous with the first to fourth side surfaces 5A to 5D.
  • the outer wall of the main surface insulating film 25 may be a ground surface having grinding marks.
  • the outer wall of the main surface insulating film 25 may form one ground surface together with the first to fourth side surfaces 5A to 5D.
  • the outer wall of the main surface insulating film 25 may be formed with a space inwardly from the peripheral edge of the outer surface 9 to expose the first semiconductor region 6 from the peripheral edge of the outer surface 9 .
  • the semiconductor device 1A includes a sidewall structure 26 formed on the main surface insulating film 25 so as to cover at least one of the first to fourth connection surfaces 10A to 10D on the outer surface 9.
  • the sidewall structure 26 is formed in an annular shape (square annular shape) surrounding the active surface 8 in plan view.
  • the sidewall structure 26 may have a portion overlying the active surface 8 .
  • Sidewall structure 26 may comprise an inorganic insulator or polysilicon.
  • Sidewall structure 26 may be a sidewall interconnect electrically connected to source structure 16 .
  • the semiconductor device 1A includes an interlayer insulating film 27 formed on the main surface insulating film 25 .
  • Interlayer insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 27 has a single-layer structure made of a silicon oxide film in this embodiment.
  • the interlayer insulating film 27 covers the active surface 8, the outer side surface 9 and the first to fourth connection surfaces 10A to 10D with the main surface insulating film 25 interposed therebetween. Specifically, the interlayer insulating film 27 covers the active surface 8, the outer side surface 9 and the first to fourth connection surfaces 10A to 10D with the sidewall structure 26 interposed therebetween. The interlayer insulating film 27 covers the MISFET structure 12 on the active surface 8 side, and covers the outer contact region 19, the outer well region 20 and the plurality of field regions 21 on the outer side surface 9 side.
  • the interlayer insulating film 27 continues to the first to fourth side surfaces 5A to 5D in this form.
  • the outer wall of the interlayer insulating film 27 may be a ground surface having grinding marks.
  • the outer wall of the interlayer insulating film 27 may form one ground surface together with the first to fourth side surfaces 5A to 5D.
  • the outer wall of the interlayer insulating film 27 may be formed spaced inwardly from the peripheral edge of the outer side surface 9 to expose the first semiconductor region 6 from the peripheral edge portion of the outer side surface 9 .
  • the semiconductor device 1A includes a gate electrode 30 arranged on the first main surface 3 (interlayer insulating film 27).
  • Gate electrode 30 may be referred to as a “gate main surface electrode”.
  • the gate electrode 30 is arranged in the inner part of the first main surface 3 with a space from the peripheral edge of the first main surface 3 .
  • a gate electrode 30 is arranged above the active surface 8 in this embodiment.
  • the gate electrode 30 is arranged in a region on the periphery of the active surface 8 and close to the central portion of the third connection surface 10C (third side surface 5C).
  • the gate electrode 30 is formed in a square shape in plan view.
  • the gate electrode 30 may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view.
  • gate electrode 30 has gate electrode surface 30a and gate electrode sidewalls 30b.
  • Gate electrode surface 30 a extends flat along interlayer insulating film 27 .
  • Gate electrode sidewall 30 b is located on interlayer insulating film 27 .
  • the gate electrode sidewall 30 b may extend obliquely with respect to the interlayer insulating film 27 or may extend substantially vertically with respect to the interlayer insulating film 27 .
  • gate electrode side wall 30b may extend in a curved recess toward interlayer insulating film 27 from gate electrode surface 30a.
  • the gate electrode 30 preferably has a plane area of 25% or less of the first main surface 3.
  • the planar area of gate electrode 30 may be 10% or less of first main surface 3 .
  • the gate electrode 30 may have a thickness of 0.5 ⁇ m or more and 15 ⁇ m or less.
  • the gate electrode 30 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.
  • the gate electrode 30 is made of at least one of a pure Cu film (a Cu film with a purity of 99% or higher), a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. may contain one.
  • the gate electrode 30 has a laminated structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) laminated in this order from the chip 2 side.
  • the semiconductor device 1A includes a source electrode 32 spaced from the gate electrode 30 and arranged on the first main surface 3 (interlayer insulating film 27).
  • the source electrode 32 may be referred to as a "source main surface electrode”.
  • the source electrode 32 is arranged in the inner part of the first main surface 3 with a space from the periphery of the first main surface 3 .
  • a source electrode 32 is arranged on the active surface 8 in this embodiment.
  • the source electrode 32 has a body electrode portion 33 and at least one (in this embodiment, a plurality of) extraction electrode portions 34A and 34B.
  • the body electrode portion 33 is arranged in a region on the side of the fourth side surface 5D (fourth connection surface 10D) with a gap from the gate electrode 30 in plan view, and faces the gate electrode 30 in the first direction X.
  • the body electrode portion 33 is formed in a polygonal shape (specifically, a rectangular shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.
  • the multiple lead electrode portions 34A and 34B include a first lead electrode portion 34A on one side (first side surface 5A side) and a second lead electrode portion 34B on the other side (second side surface 5B side).
  • the first extraction electrode portion 34A is extracted from the body electrode portion 33 to a region located on one side (first side surface 5A side) in the second direction Y with respect to the gate electrode 30 in plan view, and extends in the second direction Y to the gate electrode portion 34A. It faces the electrode 30 .
  • the second extraction electrode portion 34B is extracted from the body electrode portion 33 to a region located on the other side (the second side surface 5B side) in the second direction Y with respect to the gate electrode 30 in plan view, and extends in the second direction Y to the gate electrode portion 34B. It faces the electrode 30 . That is, the plurality of extraction electrode portions 34A and 34B sandwich the gate electrode 30 from both sides in the second direction Y in plan view.
  • the source electrode 32 (body electrode portion 33 and lead-out electrode portions 34A and 34B) penetrates the interlayer insulating film 27 and the main surface insulating film 25 and electrically connects the plurality of source structures 16, the source regions 14 and the plurality of well regions 18. It is connected to the.
  • the source electrode 32 may be composed of only the body electrode portion 33 without the lead electrode portions 34A and 34B.
  • the source electrode 32 has a source electrode surface 32a and source electrode sidewalls 32b.
  • Source electrode surface 32 a extends flat along interlayer insulating film 27 .
  • Source electrode sidewall 32 b is located on interlayer insulating film 27 .
  • the source electrode sidewall 32 b may extend obliquely with respect to the interlayer insulating film 27 or may extend substantially vertically with respect to the interlayer insulating film 27 .
  • source electrode side wall 32b may extend from source electrode surface 32a toward interlayer insulating film 27 so as to be recessed in a curved shape.
  • the source electrode 32 has a planar area exceeding that of the gate electrode 30 .
  • the plane area of the source electrode 32 is preferably 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the source electrode 32 is 75% or more of the first main surface 3 .
  • the source electrode 32 may have a thickness of 0.5 ⁇ m or more and 15 ⁇ m or less.
  • the source electrode 32 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.
  • the source electrode 32 is composed of at least one of a pure Cu film (a Cu film with a purity of 99% or higher), a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. It is preferred to include one.
  • the source electrode 32 has a laminated structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) laminated in this order from the chip 2 side.
  • Source electrode 32 preferably comprises the same conductive material as gate electrode 30 .
  • the semiconductor device 1A includes at least one (a plurality in this embodiment) gate wirings 36A and 36B drawn from the gate electrode 30 onto the first main surface 3 (interlayer insulating film 27).
  • the plurality of gate wirings 36A, 36B preferably contain the same conductive material as the gate electrode 30 .
  • a plurality of gate lines 36A, 36B cover the active surface 8 and do not cover the outer surface 9 in this configuration.
  • a plurality of gate wirings 36A and 36B are led out to a region between the peripheral edge of the active surface 8 and the source electrode 32 in a plan view, and extend along the source electrode 32 in a strip shape.
  • the plurality of gate wirings 36A, 36B specifically includes a first gate wiring 36A and a second gate wiring 36B.
  • the first gate wiring 36A is drawn from the gate electrode 30 to a region on the first side surface 5A side in plan view.
  • the first gate line 36A has a strip-like portion extending in the second direction Y along the third side surface 5C and a strip-like portion extending in the first direction X along the first side surface 5A.
  • the second gate wiring 36B is drawn from the gate electrode 30 to a region on the second side surface 5B side in plan view.
  • the second gate line 36B has a strip-like portion extending in the second direction Y along the third side surface 5C and a strip-like portion extending in the first direction X along the second side surface 5B.
  • the plurality of gate wirings 36A and 36B intersect (specifically, perpendicularly) both ends of the plurality of gate structures 15 at the periphery of the active surface 8 (first main surface 3).
  • the multiple gate wirings 36A and 36B are electrically connected to the multiple gate structures 15 through the interlayer insulating film 27 .
  • the plurality of gate wirings 36A and 36B may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.
  • the semiconductor device 1A includes a source wiring 37 drawn from the source electrode 32 onto the first main surface 3 (interlayer insulating film 27).
  • Source line 37 preferably contains the same conductive material as source electrode 32 .
  • the source wiring 37 is formed in a strip shape extending along the periphery of the active surface 8 in a region closer to the outer surface 9 than the plurality of gate wirings 36A and 36B.
  • the source wiring 37 is formed in a ring shape (specifically, a square ring shape) surrounding the gate electrode 30, the source electrode 32 and the plurality of gate wirings 36A and 36B in plan view.
  • the source wiring 37 covers the sidewall structure 26 with the interlayer insulating film 27 interposed therebetween, and is drawn out from the active surface 8 side to the outer surface 9 side.
  • the source wiring 37 preferably covers the entire sidewall structure 26 over the entire circumference.
  • Source line 37 has a portion that penetrates interlayer insulating film 27 and main surface insulating film 25 on the side of outer surface 9 and is connected to outer surface 9 (specifically, outer contact region 19).
  • the source wiring 37 may be electrically connected to the sidewall structure 26 through the interlayer insulating film 27 .
  • the semiconductor device 1A includes a dicing street 41 provided in a region between the peripheral edge of the first main surface 3 and the source wiring 37 .
  • Dicing streets 41 are specifically provided in a region between the peripheral edge of first main surface 3 and outermost field region 21 .
  • the dicing street 41 is formed in a band-like shape extending along the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) in plan view.
  • the dicing street 41 is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the inner portion (active surface 8) of the first main surface 3 in plan view.
  • the dicing street 41 exposes the interlayer insulating film 27 in this form.
  • dicing street 41 may expose outer surface 9 .
  • the dicing street 41 may have a width of 1 ⁇ m or more and 200 ⁇ m or less.
  • the width of the dicing street 41 is the width in the direction perpendicular to the extending direction of the dicing street 41 .
  • the width of the dicing street 41 is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • semiconductor device 1A includes a gate terminal electrode 50 arranged on gate electrode 30 .
  • the gate terminal electrode 50 is erected on the gate electrode 30 in a columnar shape.
  • the gate terminal electrode 50 has an area smaller than that of the gate electrode 30 in a plan view, and is arranged above the inner portion of the gate electrode 30 with a gap from the periphery of the gate electrode 30 . That is, the gate terminal electrode 50 exposes at least part of the corner (periphery) of the gate electrode 30 .
  • the gate terminal electrode 50 exposes the corners of the gate electrode 30 over the entire circumference. Specifically, the gate terminal electrode 50 exposes the gate electrode surface 30a and the gate electrode sidewalls 30b at the corners of the gate electrode 30 . Gate terminal electrode 50 has a lower end connected only to gate electrode surface 30 a above gate electrode 30 .
  • the gate terminal electrode 50 has a gate terminal surface 51 and gate terminal sidewalls 52 .
  • Gate terminal surface 51 extends flat along first main surface 3 .
  • the gate terminal surface 51 may be a ground surface having grinding marks.
  • the gate terminal sidewall 52 is positioned above the gate electrode 30 and extends substantially vertically in the normal direction Z. As shown in FIG. "Substantially vertical" also includes a form extending in the stacking direction while curving (meandering).
  • the gate terminal side walls 52 are preferably smooth surfaces without grinding marks.
  • the gate terminal electrode 50 has a first projecting portion 53 projecting outward from the lower end portion of the gate terminal side wall 52 .
  • the first protruding portion 53 is formed in a region closer to the gate electrode 30 than the intermediate portion of the gate terminal side wall 52 .
  • the first projecting portion 53 extends along the gate electrode surface 30a of the gate electrode 30 in a cross-sectional view, and is formed in a tapered shape in which the thickness gradually decreases from the gate terminal side wall 52 toward the tip portion.
  • the first projecting portion 53 has a sharp tip that forms an acute angle.
  • the gate terminal electrode 50 without the first projecting portion 53 may be formed.
  • the gate terminal electrode 50 preferably has a thickness exceeding the thickness of the gate electrode 30 .
  • the thickness of gate terminal electrode 50 is defined by the distance between gate electrode surface 30 a and gate terminal surface 51 .
  • the thickness of the gate terminal electrode 50 exceeds the thickness of the chip 2 in this embodiment.
  • the thickness of the gate terminal electrode 50 may be less than the thickness of the chip 2 .
  • the thickness of the gate terminal electrode 50 may be 10 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the gate terminal electrode 50 is preferably 30 ⁇ m or more. It is particularly preferable that the thickness of the gate terminal electrode 50 is 80 ⁇ m or more and 200 ⁇ m or less.
  • the planar area of the gate terminal electrode 50 is adjusted according to the planar area of the first main surface 3 .
  • the planar area of the gate terminal electrode 50 is defined by the planar area of the gate terminal surface 51 .
  • the planar area of gate terminal electrode 50 is preferably 25% or less of first main surface 3 .
  • the planar area of the gate terminal electrode 50 may be 10% or less of the first main surface 3 .
  • the plane area of the gate terminal electrode 50 may be 0.4 mm square or more.
  • Gate terminal electrode 50 may be formed in a polygonal shape (for example, rectangular shape) having a plane area of 0.4 mm ⁇ 0.7 mm or more.
  • the gate terminal electrode 50 is formed in a polygonal shape (quadrangular shape with four rectangular notched corners) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.
  • the gate terminal electrode 50 may be formed in a rectangular shape, a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape in plan view.
  • the gate terminal electrode 50 has a laminated structure including a first gate conductor film 55 and a second gate conductor film 56 laminated in this order from the gate electrode 30 side.
  • the first gate conductor film 55 may contain a Ti-based metal film.
  • the first gate conductor film 55 may have a single layer structure made of a Ti film or a TiN film.
  • the first gate conductor film 55 may have a laminated structure including a Ti film and a TiN film laminated in any order.
  • the first gate conductor film 55 has a thickness less than the thickness of the gate electrode 30 .
  • the first gate conductor film 55 covers the gate electrode 30 like a film.
  • the first gate conductor film 55 forms part of the first projecting portion 53 .
  • the first gate conductor film 55 is not necessarily formed and may be removed.
  • the second gate conductor film 56 forms the main body of the gate terminal electrode 50 .
  • the second gate conductor film 56 may contain a Cu-based metal film.
  • the Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film.
  • the second gate conductor film 56 includes a pure Cu plating film in this embodiment.
  • the second gate conductor film 56 preferably has a thickness exceeding the thickness of the gate electrode 30 . The thickness of the second gate conductor film 56 exceeds the thickness of the chip 2 in this embodiment.
  • the second gate conductor film 56 covers the gate electrode 30 with the first gate conductor film 55 interposed therebetween.
  • the second gate conductor film 56 forms part of the first projecting portion 53 . That is, the first projecting portion 53 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56 .
  • the second gate conductor film 56 preferably has a thickness exceeding the thickness of the first gate conductor film 55 within the first projecting portion 53 .
  • the semiconductor device 1A includes a source terminal electrode 60 arranged on the source electrode 32 .
  • the source terminal electrode 60 is erected in a columnar shape on the source electrode 32 .
  • the source terminal electrode 60 has an area smaller than the area of the source electrode 32 in a plan view, and is arranged above the inner portion of the source electrode 32 with a gap from the periphery of the source electrode 32 . That is, the source terminal electrode 60 exposes at least a portion of the corner (periphery) of the source electrode 32 .
  • the source terminal electrode 60 exposes the corners of the source electrode 32 over the entire circumference in plan view. Specifically, the source terminal electrode 60 exposes the source electrode surface 32a and the source electrode side walls 32b at the corners of the source electrode 32 .
  • the source terminal electrode 60 has a lower end connected only to the source electrode surface 32 a above the source electrode 32 .
  • the source terminal electrode 60 is arranged on the body electrode portion 33 of the source electrode 32 and is not arranged on the extraction electrode portions 34A and 34B of the source electrode 32. Thereby, the facing area between the gate terminal electrode 50 and the source terminal electrode 60 is reduced.
  • Such a structure reduces the risk of a short circuit between the gate terminal electrode 50 and the source terminal electrode 60 when a conductive adhesive such as solder or metal paste is attached to the gate terminal electrode 50 and the source terminal electrode 60. is valid.
  • a conductive joining member such as a conductive plate or a conductive wire (eg, bonding wire) may be connected to the gate terminal electrode 50 and the source terminal electrode 60 . In this case, the risk of a short circuit between the conductive joint member on the gate terminal electrode 50 side and the conductive joint member on the source terminal electrode 60 side can be reduced.
  • the source terminal electrode 60 has a source terminal surface 61 and source terminal sidewalls 62 .
  • the source terminal surface 61 extends flat along the first main surface 3 .
  • the source terminal surface 61 may be a ground surface having grinding marks.
  • the source terminal sidewall 62 is positioned above the source electrode 32 and extends substantially vertically in the normal direction Z in this embodiment. "Substantially vertical” also includes a form extending in the stacking direction while curving (meandering).
  • the source terminal sidewall 62 preferably has a smooth surface without grinding marks.
  • the source terminal electrode 60 has a second projecting portion 63 projecting outward from the lower end portion of the source terminal side wall 62 in this embodiment.
  • the second protruding portion 63 is formed in a region closer to the source electrode 32 than the intermediate portion of the source terminal side wall 62 .
  • the second protruding portion 63 extends along the source electrode surface 32a of the source electrode 32 in a cross-sectional view, and is formed in a tapered shape in which the thickness gradually decreases from the source terminal side wall 62 toward the tip portion.
  • the second projecting portion 63 has a sharp tip that forms an acute angle.
  • the source terminal electrode 60 without the second projecting portion 63 may be formed.
  • the source terminal electrode 60 preferably has a thickness exceeding the thickness of the source electrode 32 .
  • the thickness of source terminal electrode 60 is defined by the distance between source electrode surface 32 a and source terminal surface 61 .
  • the thickness of the source terminal electrode 60 exceeds the thickness of the chip 2 in this embodiment.
  • the thickness of the source terminal electrode 60 may be less than the thickness of the chip 2 .
  • the thickness of the source terminal electrode 60 may be 10 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the source terminal electrode 60 is preferably 30 ⁇ m or more. It is particularly preferable that the thickness of the source terminal electrode 60 is 80 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the source terminal electrode 60 is approximately equal to the thickness of the gate terminal electrode 50 .
  • the planar area of the source terminal electrode 60 is adjusted according to the planar area of the first main surface 3 .
  • the planar area of the source terminal electrode 60 is defined by the planar area of the source terminal surface 61 .
  • the planar area of the source terminal electrode 60 preferably exceeds the planar area of the gate terminal electrode 50 .
  • the plane area of the source terminal electrode 60 is preferably 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the source terminal electrode 60 is 75% or more of the first main surface 3 .
  • the plane area of the source terminal electrode 60 is preferably 0.8 mm square or more. In this case, it is particularly preferable that the plane area of the source terminal electrode 60 is 1 mm square or more.
  • the source terminal electrode 60 may be formed in a polygonal shape having a plane area of 1 mm ⁇ 1.4 mm or more. In this form, the source terminal electrode 60 is formed in a square shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. Of course, the source terminal electrode 60 may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view.
  • the source terminal electrode 60 has a laminated structure including a first source conductor film 67 and a second source conductor film 68 laminated in this order from the source electrode 32 side.
  • the first source conductor film 67 may contain a Ti-based metal film.
  • the first source conductor film 67 may have a single layer structure made of a Ti film or a TiN film.
  • the first source conductor film 67 may have a laminated structure including a Ti film and a TiN film laminated in any order.
  • the first source conductor film 67 is preferably made of the same conductive material as the first gate conductor film 55 .
  • the first source conductor film 67 has a thickness less than the thickness of the source electrode 32 .
  • the first source conductor film 67 covers the source electrode 32 like a film.
  • the first source conductor film 67 forms part of the second projecting portion 63 .
  • the thickness of the first source conductor film 67 is approximately equal to the thickness of the first gate conductor film 55 .
  • the first source conductor film 67 does not necessarily have to be formed and may be removed.
  • the second source conductor film 68 forms the main body of the source terminal electrode 60 .
  • the second source conductor film 68 may contain a Cu-based metal film.
  • the Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film.
  • the second source conductor film 68 includes a pure Cu plating film in this embodiment.
  • the second source conductor film 68 is preferably made of the same conductive material as the second gate conductor film 56 .
  • the second source conductor film 68 preferably has a thickness exceeding the thickness of the source electrode 32 .
  • the thickness of the second source conductor film 68 exceeds the thickness of the chip 2 in this form.
  • the thickness of the second source conductor film 68 is approximately equal to the thickness of the second gate conductor film 56 .
  • the second source conductor film 68 covers the source electrode 32 with the first source conductor film 67 interposed therebetween.
  • the second source conductor film 68 forms part of the second projecting portion 63 . That is, the second projecting portion 63 has a laminated structure including the first source conductor film 67 and the second source conductor film 68 .
  • the second source conductor film 68 preferably has a thickness exceeding the thickness of the first source conductor film 67 within the second protruding portion 63 .
  • the semiconductor device 1A includes a sealing insulator 71 that covers the first main surface 3.
  • the sealing insulator 71 covers the periphery of the gate terminal electrode 50 and the periphery of the source terminal electrode 60 so as to expose a portion of the gate terminal electrode 50 and a portion of the source terminal electrode 60 on the first main surface 3 . are doing.
  • the encapsulating insulator 71 covers the active surface 8, the outer surface 9 and the first to fourth connection surfaces 10A to 10D so as to expose the gate terminal electrode 50 and the source terminal electrode 60. As shown in FIG.
  • the encapsulation insulator 71 exposes the gate terminal surface 51 and the source terminal surface 61 and covers the gate terminal sidewalls 52 and the source terminal sidewalls 62 .
  • the sealing insulator 71 covers the first projecting portion 53 of the gate terminal electrode 50 and faces the gate electrode 30 with the first projecting portion 53 interposed therebetween.
  • the sealing insulator 71 prevents the gate terminal electrode 50 from coming off.
  • the sealing insulator 71 covers the second projecting portion 63 of the source terminal electrode 60 and faces the source electrode 32 with the second projecting portion 63 interposed therebetween.
  • the sealing insulator 71 prevents the source terminal electrode 60 from coming off.
  • the sealing insulator 71 has a portion that directly covers the gate electrode 30 on the lower end side of the gate terminal electrode 50 .
  • the encapsulating insulator 71 specifically has a portion that directly covers at least part of the corner of the gate electrode 30 .
  • the encapsulating insulator 71 directly covers the entire corner of the gate electrode 30 in this form.
  • the sealing insulator 71 directly covers the gate electrode surface 30a and the gate electrode sidewalls 30b at the corners of the gate electrode 30. As shown in FIG. In other words, the encapsulating insulator 71 has a portion directly above the gate electrode 30 that contacts only the gate electrode 30 (gate electrode surface 30a) and the gate terminal electrode 50 (gate terminal side wall 52). A portion of the sealing insulator 71 that directly covers the gate electrode side wall 30 b is in contact with the interlayer insulating film 27 .
  • the sealing insulator 71 has a portion that directly covers the source electrode 32 on the lower end side of the source terminal electrode 60 .
  • the sealing insulator 71 specifically has a portion that directly covers at least part of the corner of the source electrode 32 .
  • the encapsulating insulator 71 directly covers the entire corner of the source electrode 32 in this form.
  • the sealing insulator 71 directly covers the source electrode surface 32a and the source electrode side walls 32b at the corners of the source electrode 32. As shown in FIG. That is, the encapsulating insulator 71 has a portion directly above the source electrode 32 that is in contact only with the source electrode 32 (source electrode surface 32a) and the source terminal electrode 60 (source terminal side wall 62). A portion of the sealing insulator 71 that directly covers the source electrode side wall 32 b is in contact with the interlayer insulating film 27 .
  • the sealing insulator 71 directly covers the entire area of the plurality of gate wirings 36A, 36B and the entire area of the source wiring 37. Thereby, the sealing insulator 71 electrically insulates the gate terminal electrode 50 and the source terminal electrode 60 and electrically insulates the gate electrode 30 and the source electrode 32 .
  • the sealing insulator 71 covers the dicing street 41 at the periphery of the outer surface 9 .
  • the sealing insulator 71 directly covers the interlayer insulating film 27 at the dicing street 41 in this embodiment.
  • the sealing insulator 71 directly covers the chip 2 and the main surface insulating film 25 on the dicing street 41.
  • the sealing insulator 71 has an insulating main surface 72 and insulating side walls 73 .
  • the insulating main surface 72 extends flat along the first main surface 3 .
  • Insulating main surface 72 forms one flat surface with gate terminal surface 51 and source terminal surface 61 .
  • the insulating main surface 72 may be a ground surface having grinding marks. In this case, the insulating main surface 72 preferably forms one ground surface together with the gate terminal surface 51 and the source terminal surface 61 .
  • the insulating side wall 73 extends from the periphery of the insulating main surface 72 toward the chip 2 and forms one flat surface together with the first to fourth side surfaces 5A to 5D.
  • the insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72 .
  • the angle formed between insulating side wall 73 and insulating main surface 72 may be 88° or more and 92° or less.
  • the insulating side wall 73 may consist of a ground surface with grinding marks.
  • the insulating sidewall 73 may form one grinding surface with the first to fourth side surfaces 5A to 5D.
  • the encapsulating insulator 71 preferably has a thickness exceeding the thickness of the gate electrode 30 and the thickness of the source electrode 32 .
  • the thickness of the encapsulation insulator 71 exceeds the thickness of the chip 2 in this embodiment.
  • the thickness of the encapsulating insulator 71 may be less than the thickness of the chip 2 .
  • the thickness of the sealing insulator 71 may be 10 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the sealing insulator 71 is preferably 30 ⁇ m or more. It is particularly preferable that the thickness of the sealing insulator 71 is 80 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of encapsulating insulator 71 is approximately equal to the thickness of gate terminal electrode 50 and the thickness of source terminal electrode 60 .
  • the sealing insulator 71 contains a matrix resin, multiple fillers, and multiple flexible particles (flexible agents).
  • the sealing insulator 71 is configured such that its mechanical strength is adjusted by the matrix resin, multiple fillers, and multiple flexible particles.
  • the sealing insulator 71 only needs to contain a matrix resin, and the presence or absence of fillers and flexible particles is optional.
  • the sealing insulator 71 may contain a coloring material such as carbon black for coloring the matrix resin.
  • the matrix resin is preferably made of a thermosetting resin.
  • the matrix resin may contain at least one of epoxy resin, phenolic resin, and polyimide resin, which are examples of thermosetting resins.
  • the matrix resin, in this form, contains an epoxy resin.
  • the plurality of fillers are composed of one or both of spherical objects made of insulators and amorphous objects made of insulators, and are added to the matrix resin.
  • Amorphous objects have random shapes other than spheres, such as grains, fragments, and crushed pieces.
  • the amorphous object may have corners.
  • the plurality of fillers are each composed of a spherical object from the viewpoint of suppressing damage due to filler attack.
  • the plurality of fillers may contain at least one of ceramics, oxides and nitrides.
  • the plurality of fillers in this form, are each composed of silicon oxide particles (silica particles).
  • a plurality of fillers may each have a particle size of 1 nm or more and 100 ⁇ m or less.
  • the particle size of the plurality of fillers is preferably 50 ⁇ m or less.
  • the sealing insulator 71 preferably contains a plurality of fillers with different particle sizes.
  • the plurality of fillers may include a plurality of small-diameter fillers, a plurality of medium-diameter fillers, and a plurality of large-diameter fillers.
  • the plurality of fillers are preferably added to the matrix resin at a content rate (density) in the order of small-diameter filler, medium-diameter filler, and large-diameter filler.
  • the small-diameter filler may have a thickness less than the thickness of the source electrode 32 (the thickness of the gate electrode 30).
  • the particle size of the small-diameter filler may be 1 nm or more and 1 ⁇ m or less.
  • the medium-diameter filler may have a thickness exceeding the thickness of the source electrode 32 .
  • the particle diameter of the medium-diameter filler may be 1 ⁇ m or more and 20 ⁇ m or less.
  • the large-diameter filler may have a thickness exceeding any one of the thickness of the first semiconductor region 6 (epitaxial layer), the thickness of the second semiconductor region 7 (substrate), and the thickness of the chip 2 .
  • the particle size of the large-diameter filler may be 20 ⁇ m or more and 100 ⁇ m or less.
  • the particle size of the large-diameter filler is preferably 50 ⁇ m or less.
  • the average particle size of the plurality of fillers may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the average particle size of the plurality of fillers is preferably 4 ⁇ m or more and 8 ⁇ m or less.
  • the plurality of fillers need not contain all of the small-diameter fillers, medium-diameter fillers and large-diameter fillers at the same time, and may be composed of either one or both of the small-diameter fillers and the medium-diameter fillers.
  • the maximum particle size of the plurality of fillers (medium-sized fillers) may be 10 ⁇ m or less.
  • the encapsulation insulator 71 may include a plurality of filler fragments having broken particle shapes at the surface of the insulating main surface 72 and the surface of the insulating sidewalls 73 .
  • the plurality of filler pieces may each be formed of a portion of the small-diameter filler, a portion of the medium-diameter filler, and a portion of the large-diameter filler.
  • the plurality of filler pieces located on the insulating main surface 72 side have broken portions formed along the insulating main surface 72 so as to face the insulating main surface 72 .
  • a plurality of filler pieces located on the side of the insulating sidewall 73 have broken portions formed along the insulating sidewall 73 so as to face the insulating sidewall 73 .
  • the broken portions of the plurality of filler pieces may be exposed from the insulating main surface 72 and the insulating sidewalls 73, or may be partially or wholly covered with the matrix resin. Since the plurality of filler pieces are located on the surface layers of the insulating main surface 72 and the insulating side walls 73, they do not affect the structures on the chip 2 side.
  • a plurality of flexible particles are added to the matrix resin.
  • the plurality of flexible particles may include at least one of silicon-based flexible particles, acrylic-based flexible particles, and butadiene-based flexible particles.
  • the encapsulating insulator 71 preferably contains silicon-based flexing particles.
  • the plurality of flexing particles have an average particle size less than the average particle size of the plurality of fillers.
  • the average particle size of the plurality of flexible particles is preferably 1 nm or more and 1 ⁇ m or less.
  • the maximum particle size of the plurality of flexible particles is preferably 1 ⁇ m or less.
  • the plurality of flexible particles are added to the matrix resin so that the ratio of the total cross-sectional area per unit cross-sectional area is 0.1% or more and 10% or less.
  • the plurality of flexible particles are added to the matrix resin at a content in the range of 0.1% by weight to 10% by weight.
  • the average particle size and content of the plurality of flexible particles are appropriately adjusted according to the elastic modulus to be imparted to the sealing insulator 71 during and/or after manufacturing.
  • the semiconductor device 1A includes a drain electrode 77 (second main surface electrode) that covers the second main surface 4 .
  • Drain electrode 77 is electrically connected to second main surface 4 .
  • Drain electrode 77 forms ohmic contact with second semiconductor region 7 exposed from second main surface 4 .
  • the drain electrode 77 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).
  • the drain electrode 77 may cover the second main surface 4 with a space inward from the periphery of the chip 2 .
  • the drain electrode 77 is configured such that a drain-source voltage of 500 V or more and 3000 V or less is applied between the drain electrode 77 and the source terminal electrode 60 . That is, the chip 2 is formed so that a voltage of 500 V or more and 3000 V or less is applied between the first principal surface 3 and the second principal surface 4 .
  • the semiconductor device 1A includes the chip 2, the gate electrode 30 (main surface electrode), the gate terminal electrode 50, and the sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • Gate electrode 30 is arranged on first main surface 3 .
  • the gate terminal electrode 50 is arranged on the gate electrode 30 so as to partially expose the gate electrode 30 .
  • the encapsulating insulator 71 covers the periphery of the gate terminal electrode 50 so as to partially expose the gate terminal electrode 50 and has a portion that directly covers the gate electrode 30 .
  • the sealing object (the gate electrode 30 and the like) can be appropriately protected by the sealing insulator 71 .
  • the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1A with improved reliability.
  • the semiconductor device 1A includes a chip 2, a source electrode 32 (main surface electrode), a source terminal electrode 60 and a sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • the source electrode 32 is arranged on the first main surface 3 .
  • the source terminal electrode 60 is arranged on the source electrode 32 so as to partially expose the source electrode 32 .
  • the encapsulating insulator 71 covers the periphery of the source terminal electrode 60 so as to partially expose the source electrode 32 and has a portion that directly covers the source electrode 32 .
  • the sealing object (source electrode 32 etc.) can be appropriately protected by the sealing insulator 71 .
  • the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1A with improved reliability.
  • the gate terminal electrode 50 (source terminal electrode 60) exposes the corner of the gate electrode 30 (source electrode 32), and the sealing insulator 71 directly covers at least part of the corner of the gate electrode 30 (source electrode 32). preferably. That is, the gate terminal electrode 50 (source terminal electrode 60) exposes the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewall 30b (source electrode sidewall 32b), and the sealing insulator 71 exposes the gate electrode surface 30a (source electrode sidewall 32b). It preferably directly covers the source electrode surface 32a) and the gate electrode sidewalls 30b (source electrode sidewalls 32b).
  • the encapsulating insulator 71 preferably has a portion in contact only with the gate electrode 30 (source electrode 32) and the gate terminal electrode 50 (source terminal electrode 60).
  • the encapsulating insulator 71 is preferably thicker than the gate electrode 30 (source electrode 32). It is particularly preferred that the encapsulating insulator 71 is thicker than the chip 2 .
  • the above configuration provides a gate terminal electrode 50 (source terminal electrode 60) having a relatively large plane area and/or a relatively large thickness for a chip 2 having a relatively large plane area and/or a relatively small thickness. is effective when applying The gate terminal electrode 50 (source terminal electrode 60) having a relatively large plane area and/or a relatively large thickness is also effective in absorbing heat generated on the chip 2 side and dissipating it to the outside.
  • the gate terminal electrode 50 (source terminal electrode 60) is preferably thicker than the gate electrode 30 (source electrode 32). It is particularly preferable that the gate terminal electrode 50 (source terminal electrode 60 ) be thicker than the chip 2 .
  • the gate terminal electrode 50 may cover 25% or less of the first main surface 3 in plan view.
  • the source terminal electrode 60 may cover 50% or more of the first main surface 3 in plan view.
  • the chip 2 may have a first main surface 3 having an area of 1 mm square or more in plan view.
  • the chip 2 may have a thickness of 100 ⁇ m or less when viewed in cross section.
  • the chip 2 preferably has a thickness of 50 ⁇ m or less when viewed in cross section.
  • Chip 2 may have a laminated structure including a semiconductor substrate and an epitaxial layer. In this case, the epitaxial layer is preferably thicker than the semiconductor substrate.
  • the chip 2 preferably contains a wide bandgap semiconductor single crystal.
  • Single crystals of wide bandgap semiconductors are effective in improving electrical characteristics.
  • the structure having the sealing insulator 71 is also effective in the structure including the drain electrode 77 covering the second main surface 4 of the chip 2 .
  • Drain electrode 77 forms a potential difference (for example, 500 V or more and 3000 V or less) across chip 2 with source electrode 32 .
  • the distance between the source electrode 32 and the drain electrode 77 is reduced, increasing the risk of discharge phenomena between the rim of the first main surface 3 and the source electrode 32.
  • FIG. in the structure having the sealing insulator 71, the insulation between the peripheral edge of the first main surface 3 and the source electrode 32 can be ensured, so that the discharge phenomenon can be suppressed.
  • FIG. 10 is a plan view showing a wafer structure 80 used when manufacturing the semiconductor device 1A shown in FIG.
  • FIG. 11 is a cross-sectional view showing device region 86 shown in FIG. 10 and 11, wafer structure 80 includes wafer 81 formed in a disc shape.
  • Wafer 81 serves as the base of chip 2 .
  • the wafer 81 has a first wafer main surface 82 on one side, a second wafer main surface 83 on the other side, and a wafer side surface 84 connecting the first wafer main surface 82 and the second wafer main surface 83 . .
  • the wafer 81 has marks 85 indicating the crystal orientation of the SiC single crystal on the wafer side surface 84 .
  • the mark 85 includes an orientation flat cut linearly in plan view.
  • the orientation flat extends in the second direction Y in this configuration.
  • the orientation flat does not necessarily have to extend in the second direction Y and may extend in the first direction X as well.
  • the mark 85 may include a first orientation flat extending in the first direction X and a first orientation flat extending in the second direction Y.
  • the mark 85 may have an orientation notch cut toward the central portion of the wafer 81 instead of the orientation flat.
  • the orientation notch may be a cut-out portion cut in a polygonal shape such as a triangular shape or a square shape in a plan view.
  • the wafer 81 may have a diameter of 50 mm or more and 300 mm or less (that is, 2 inches or more and 12 inches or less) in plan view.
  • the diameter of wafer structure 80 is defined by the length of a chord passing through the center of wafer structure 80 outside of mark 85 .
  • Wafer structure 80 may have a thickness between 100 ⁇ m and 1100 ⁇ m.
  • the wafer structure 80 includes a first semiconductor region 6 formed in a region on the first wafer main surface 82 side inside a wafer 81 and a second semiconductor region 7 formed in a region on the second wafer main surface 83 side.
  • the first semiconductor region 6 is formed by an epitaxial layer and the second semiconductor region 7 is formed by a semiconductor substrate. That is, the first semiconductor region 6 is formed by epitaxially growing a semiconductor single crystal from the second semiconductor region 7 by an epitaxial growth method.
  • the second semiconductor region 7 preferably has a thickness exceeding the thickness of the first semiconductor region 6 .
  • the wafer structure 80 includes a plurality of device regions 86 and a plurality of scheduled cutting lines 87 provided on the first wafer main surface 82 .
  • a plurality of device regions 86 are regions respectively corresponding to the semiconductor devices 1A.
  • the plurality of device regions 86 are each set to have a rectangular shape in plan view. In this form, the plurality of device regions 86 are arranged in a matrix along the first direction X and the second direction Y in plan view.
  • the plurality of planned cutting lines 87 are lines (regions extending in a belt shape) that define locations to be the first to fourth side surfaces 5A to 5D of the chip 2 .
  • the plurality of planned cutting lines 87 are set in a grid pattern extending along the first direction X and the second direction Y so as to partition the plurality of device regions 86 .
  • the plurality of planned cutting lines 87 may be defined by, for example, alignment marks or the like provided inside and/or outside the wafer 81 .
  • the wafer structure 80 includes a mesa portion 11 formed in a plurality of device regions 86, a MISFET structure 12, an outer contact region 19, an outer well region 20, a field region 21, a main surface insulating film 25, and sidewall structures. 26, an interlayer insulating film 27, a gate electrode 30, a source electrode 32, a plurality of gate wirings 36A, 36B and a source wiring 37.
  • the wafer structure 80 includes dicing streets 41 defined in regions between the source wirings 37 (specifically, the plurality of outermost field regions 21).
  • the dicing street 41 extends across a plurality of device regions 86 across the planned cutting line 87 so as to expose the planned cutting line 87 .
  • the dicing streets 41 are formed in a lattice shape extending along a plurality of planned cutting lines 87 .
  • the dicing street 41 exposes the interlayer insulating film 27 in this form.
  • FIGS. 12A to 12I are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1A shown in FIG. Descriptions of specific features of each structure formed in each process shown in FIGS. 12A to 12I are omitted or simplified because they are as described above.
  • a wafer structure 80 is prepared (see FIGS. 10 and 11).
  • a first base conductor film 88 serving as a base for the first gate conductor film 55 and the first source conductor film 67 is formed over the wafer structure 80 .
  • the first base conductor film 88 is formed in a film shape along the interlayer insulating film 27 , the gate electrode 30 , the source electrode 32 , the plurality of gate wirings 36A and 36B and the source wiring 37 .
  • the first base conductor film 88 includes a Ti-based metal film.
  • the first base conductor film 88 may be formed by sputtering and/or vapor deposition.
  • a second base conductor film 89 serving as the base of the second gate conductor film 56 and the second source conductor film 68 is formed on the first base conductor film 88 .
  • the second base conductor film 89 covers the interlayer insulating film 27, the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A and 36B and the source wiring 37 with the first base conductor film 88 interposed therebetween.
  • the second base conductor film 89 contains a Cu-based metal film.
  • the second base conductor film 89 may be formed by sputtering and/or vapor deposition.
  • Resist mask 90 includes a first opening 91 exposing only gate electrode 30 and a second opening 92 exposing only source electrode 32 .
  • the first opening 91 exposes only the portion of the second base conductor film 89 that covers the gate electrode 30 .
  • the second opening 92 exposes only the portion of the second base conductor film 89 that covers the source electrode 32 .
  • the first opening 91 exposes the region where the gate terminal electrode 50 is to be formed in the region above the gate electrode 30 .
  • the second opening 92 exposes the region where the source terminal electrode 60 is to be formed in the region above the source electrode 32 .
  • This step includes a step of reducing the adhesion of the resist mask 90 to the second base conductor film 89 .
  • the adhesion of the resist mask 90 is adjusted by adjusting exposure conditions for the resist mask 90 and post-exposure baking conditions (baking temperature, time, etc.). As a result, the growth starting point of the first protrusion 53 is formed at the lower end of the first opening 91 , and the growth starting point of the second protrusion 63 is formed at the lower end of the second opening 92 .
  • a third base conductor film 95 serving as the base of the second gate conductor film 56 and the second source conductor film 68 is formed on the second base conductor film 89 .
  • the third base conductor film 95 is formed by depositing a conductor (Cu-based metal in this embodiment) in the first opening 91 and the second opening 92 by plating (eg, electroplating). .
  • the third base conductor film 95 is integrated with the second base conductor film 89 inside the first opening 91 and the second opening 92 .
  • the gate terminal electrode 50 covering the gate electrode 30 is formed.
  • a source terminal electrode 60 covering the source electrode 32 is also formed.
  • This step includes a step of allowing the plating solution to enter between the second base conductor film 89 and the resist mask 90 at the lower end of the first opening 91 .
  • This step also includes a step of allowing the plating solution to enter between the second base conductor film 89 and the resist mask 90 at the lower end of the second opening 92 .
  • a portion of the third base conductor film 95 grows like a protrusion at the lower end of the first opening 91 to form the first protrusion 53 .
  • a portion of the third base conductor film 95 (the source terminal electrode 60 ) is grown in a projection shape at the lower end of the second opening 92 to form a second projection 63 .
  • resist mask 90 is removed. Thereby, the gate terminal electrode 50 and the source terminal electrode 60 are exposed to the outside.
  • portions of the second base conductor film 89 exposed from the gate terminal electrode 50 and the source terminal electrode 60 are removed.
  • An unnecessary portion of the second base conductor film 89 may be removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • portions of the first base conductor film 88 exposed from the gate terminal electrode 50 and the source terminal electrode 60 are removed.
  • An unnecessary portion of the first base conductor film 88 may be removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • a sealant 93 is supplied onto the first wafer main surface 82 so as to cover the gate terminal electrode 50 and the source terminal electrode 60 .
  • the encapsulant 93 forms the base of the encapsulation insulator 71 .
  • the sealant 93 fills the periphery of the gate terminal electrode 50 and the periphery of the source terminal electrode 60 to cover the entire area of the gate terminal electrode 50 and the entire area of the source terminal electrode 60 .
  • the sealant 93 directly covers the entire portion of the gate electrode 30 exposed from the gate terminal electrode 50 .
  • the sealant 93 directly covers the entire portion of the source electrode 32 exposed from the source terminal electrode 60 .
  • the encapsulant 93 in this form, contains a thermosetting resin, a plurality of fillers and a plurality of flexible particles (flexifying agents), and is cured by heating. Thereby, a sealing insulator 71 is formed.
  • the encapsulating insulator 71 has an insulating main surface 72 that covers the entire gate terminal electrode 50 and the source terminal electrode 60 .
  • the sealing insulator 71 is partially removed.
  • the sealing insulator 71 is ground from the insulating main surface 72 side by a grinding method.
  • the grinding method may be a mechanical polishing method or a chemical mechanical polishing method.
  • the insulating main surface 72 is ground until the gate terminal electrode 50 and the source terminal electrode 60 are exposed.
  • This step includes grinding the gate terminal electrode 50 and the source terminal electrode 60 .
  • insulating main surface 72 forming one ground surface between gate terminal electrode 50 (gate terminal surface 51) and source terminal electrode 60 (source terminal surface 61) is formed.
  • the sealing insulator 71 may be formed in a semi-cured state (incompletely cured state) by adjusting the heating conditions in the process of FIG. 12F described above. In this case, the sealing insulator 71 is ground again in the step of FIG. 12G and then heated again to be fully cured (completely cured). In this case, the sealing insulator 71 can be easily removed.
  • the wafer 81 is partially removed from the second wafer main surface 83 side and thinned to a desired thickness.
  • the thinning process of the wafer 81 may be performed by an etching method or a grinding method.
  • the etching method may be a wet etching method or a dry etching method.
  • the grinding method may be a mechanical polishing method or a chemical mechanical polishing method.
  • This process includes thinning the wafer 81 using the sealing insulator 71 as a support member for supporting the wafer 81 .
  • the wafer 81 can be handled appropriately.
  • the deformation of the wafer 81 warping due to thinning
  • the sealing insulator 71 can suppress the deformation of the wafer 81 (warping due to thinning) to be suppressed by the sealing insulator 71, the wafer 81 can be thinned appropriately.
  • wafer 81 is further thinned. As another example, if the thickness of wafer 81 is greater than or equal to the thickness of encapsulation insulator 71 , wafer 81 is thinned to a thickness less than the thickness of encapsulation insulator 71 . In these cases, the wafer 81 is preferably thinned until the thickness of the second semiconductor region 7 (semiconductor substrate) is less than the thickness of the first semiconductor region 6 (epitaxial layer).
  • the thickness of the second semiconductor region 7 may be greater than or equal to the thickness of the first semiconductor region 6 (epitaxial layer).
  • the wafer 81 may be thinned until the first semiconductor region 6 is exposed from the second wafer main surface 83 . That is, the entire second semiconductor region 7 may be removed.
  • a drain electrode 77 covering the second wafer main surface 83 is formed.
  • the drain electrode 77 may be formed by sputtering and/or vapor deposition.
  • the wafer structure 80 and encapsulation insulator 71 are cut along planned cutting lines 87 .
  • Wafer structure 80 and encapsulation insulator 71 may be cut by a dicing blade (not shown).
  • a plurality of semiconductor devices 1A are manufactured from one wafer structure 80 through the steps including the above.
  • the manufacturing method of the semiconductor device 1A includes the preparation process of the wafer structure 80, the formation process of the gate terminal electrode 50, and the formation process of the sealing insulator 71.
  • the wafer structure 80 including the wafer 81 and the gate electrode 30 (main surface electrode) is prepared.
  • Wafer 81 has a first wafer main surface 82 .
  • the gate electrode 30 is arranged on the first wafer main surface 82 .
  • the gate terminal electrode 50 is formed on the gate electrode 30 so that the gate electrode 30 is partially exposed.
  • the sealing insulator 71 is formed to cover the periphery of the gate terminal electrode 50 so as to partially expose the gate terminal electrode 50 and to have a portion directly covering the gate electrode 30 . be.
  • the sealing object (the gate electrode 30 and the like) can be appropriately protected by the sealing insulator 71 .
  • the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, the semiconductor device 1A with improved reliability can be manufactured.
  • the method of manufacturing the semiconductor device 1A includes a step of preparing the wafer structure 80, a step of forming the source terminal electrode 60, and a step of forming the sealing insulator 71.
  • the wafer structure 80 including the wafer 81 and the source electrode 32 (main surface electrode) is prepared.
  • Wafer 81 has a first wafer main surface 82 .
  • the source electrode 32 is arranged on the first wafer major surface 82 .
  • the source terminal electrode 60 is formed on the source electrode 32 so that the source electrode 32 is partially exposed.
  • the sealing insulator 71 is formed which covers the periphery of the source terminal electrode 60 so as to partially expose the source terminal electrode 60 and has a portion directly covering the source electrode 32 . be.
  • the sealing object (source electrode 32 etc.) can be appropriately protected by the sealing insulator 71 .
  • the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, the semiconductor device 1A with improved reliability can be manufactured.
  • the gate terminal electrode 50 (source terminal electrode 60) exposing at least part of the corner of the gate electrode 30 (source electrode 32) is formed.
  • the sealing insulator 71 that directly covers at least part of the corners of the gate electrode 30 (source electrode 32) be formed in the step of forming the sealing insulator 71 .
  • the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewall 30b (source electrode sidewall 32b) are exposed.
  • the encapsulating insulator 71 it is preferable to form the encapsulating insulator 71 that directly covers the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewalls 30b (source electrode sidewalls 32b).
  • the corners of the gate electrode 30 (source electrode 32 ) can be protected by the sealing insulator 71 .
  • entry of moisture or the like starting from the corners of the gate electrode 30 (source electrode 32) can be suppressed. Therefore, the deterioration of the gate electrode 30 (source electrode 32), the gate terminal electrode 50 (source terminal electrode 60), etc. due to humidity or the like can be suppressed, and the reliability can be improved.
  • FIG. 13 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment.
  • 14 is a cross-sectional view showing a main part of the gate terminal electrode 50 shown in FIG. 13.
  • FIG. 15 is a cross-sectional view showing a main part of the source terminal electrode 60 shown in FIG. 13.
  • FIG. 16 is a plan view showing a layout example of the upper insulating film 38 shown in FIG. 13.
  • semiconductor device 1B has a modified form of semiconductor device 1A.
  • Semiconductor device 1B specifically includes an upper insulating film 38 that directly covers gate electrode 30, source electrode 32, a plurality of gate wirings 36A and 36B, and source wiring 37.
  • the upper insulating film 38 has a gate opening 39 that exposes the inner part of the gate electrode 30 and has a portion that directly covers at least part of the corner (periphery) of the gate electrode 30 .
  • the upper insulating film 38 directly covers the entire corner of the gate electrode 30 in this embodiment.
  • Upper insulating film 38 directly covers gate electrode surface 30 a and gate electrode sidewalls 30 b at the corners of gate electrode 30 .
  • a portion of the upper insulating film 38 that directly covers the gate electrode sidewall 30 b is in contact with the interlayer insulating film 27 .
  • the gate opening 39 is formed in a square shape along the periphery of the gate electrode 30 in plan view.
  • the upper insulating film 38 has a source opening 40 that exposes the inner portion of the source electrode 32 and has a portion that directly covers at least a portion of the corner (periphery) of the source electrode 32 .
  • the upper insulating film 38 directly covers the entire corner of the source electrode 32 in this form.
  • the upper insulating film 38 directly covers the source electrode surface 32a and the source electrode sidewalls 32b at the corners of the source electrode 32 .
  • a portion of the upper insulating film 38 that directly covers the source electrode sidewall 32 b is in contact with the interlayer insulating film 27 .
  • the source opening 40 is formed in a polygonal shape along the periphery of the source electrode 32 in plan view.
  • the upper insulating film 38 directly covers the entire area of the plurality of gate wirings 36A and 36B and the entire area of the source wiring 37 in this embodiment.
  • the upper insulating film 38 covers the sidewall structure 26 with the interlayer insulating film 27 interposed therebetween, and extends from the active surface 8 side to the outer surface 9 side.
  • the upper insulating film 38 is formed spaced inwardly from the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) and covers the outer contact region 19, the outer well region 20 and the plurality of field regions 21. are doing.
  • the upper insulating film 38 partitions the dicing streets 41 with the periphery of the outer side surface 9 .
  • the dicing street 41 is formed in a strip shape extending along the peripheral edges (first to fourth side surfaces 5A to 5D) of the outer side surface 9 in plan view.
  • the dicing street 41 is formed in an annular shape (specifically, a quadrangular annular shape) surrounding the inner portion (active surface 8) of the first main surface 3 in plan view.
  • the dicing street 41 exposes the interlayer insulating film 27 in this form.
  • the dicing streets 41 may expose the outer surface 9 .
  • an upper insulating film 38 may be formed extending to the periphery of the first main surface 3 so as to be continuous with the first to fourth side surfaces 5A to 5D.
  • the dicing street 41 is set in a region between the peripheral edge of the first main surface 3 and the source wiring 37 (specifically, the outermost field region 21), as in the first embodiment.
  • the dicing street 41 may have a width of 1 ⁇ m or more and 200 ⁇ m or less.
  • the width of the dicing street 41 is the width in the direction perpendicular to the extending direction of the dicing street 41 .
  • the width of the dicing street 41 is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • the upper insulating film 38 may have a thickness less than the thickness of the gate electrode 30 (source electrode 32).
  • the upper insulating film 38 may have a thickness exceeding the thickness of the gate electrode 30 (source electrode 32).
  • the thickness of the upper insulating film 38 is preferably less than the thickness of the chip 2 .
  • the upper insulating film 38 has a single-layer structure composed of an inorganic insulating film 42 (inorganic film) in this form.
  • the inorganic insulating film 42 is preferably made of a silicon oxide film (oxide film), a silicon nitride film (nitride film), or a silicon oxynitride film (oxynitride film).
  • Inorganic insulating film 42 preferably contains an insulator different from one or both of main surface insulating film 25 and interlayer insulating film 27 .
  • the inorganic insulating film 42 is made of a silicon nitride film in this embodiment.
  • the inorganic insulating film 42 has a thickness less than the thickness of the gate electrode 30 and the thickness of the source electrode 32 .
  • the inorganic insulating film 42 preferably has a thickness less than the thickness of the interlayer insulating film 27 .
  • the inorganic insulating film 42 may have a thickness of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the gate terminal electrode 50 has an area smaller than the area of the gate electrode 30 in plan view, and is spaced apart from the periphery of the gate electrode 30 and above the inner portion of the gate electrode 30 . are placed.
  • the gate terminal electrode 50 has a thickness exceeding the thickness of the upper insulating film 38 in this form.
  • the gate terminal electrode 50 extends from above the gate electrode 30 to above the upper insulating film 38 and directly covers the gate electrode 30 and the upper insulating film 38 .
  • the gate terminal electrode 50 exposes portions of the upper insulating film 38 that cover the corners of the gate electrode 30 (that is, the gate electrode surface 30a and the gate electrode sidewalls 30b).
  • a gate terminal side wall 52 of the gate terminal electrode 50 is located on the upper insulating film 38 and extends substantially vertically in the normal direction Z.
  • the gate terminal sidewall 52 faces the gate electrode 30 with the upper insulating film 38 interposed therebetween.
  • the first protruding portion 53 of the gate terminal electrode 50 extends along the outer surface of the upper insulating film 38 in a cross-sectional view, and has a tapered shape in which the thickness gradually decreases from the gate terminal side wall 52 toward the tip. formed.
  • the gate terminal electrode 50 has a laminated structure including a first gate conductor film 55 and a second gate conductor film 56, as in the case of the first embodiment.
  • the first gate conductor film 55 covers the gate electrode 30 in the gate opening 39 in a film shape and is pulled out on the upper insulating film 38 in a film shape.
  • the second gate conductor film 56 covers the gate electrode 30 in the gate opening 39 with the first gate conductor film 55 interposed therebetween, and is a film on the upper insulating film 38 with the first gate conductor film 55 interposed therebetween. drawn out in the shape of
  • the source terminal electrode 60 has an area smaller than the area of the source electrode 32 in plan view, and is spaced apart from the periphery of the source electrode 32 and above the inner portion of the source electrode 32 . are placed.
  • the source terminal electrode 60 has a thickness exceeding the thickness of the upper insulating film 38 in this form.
  • the source terminal electrode 60 extends from above the source electrode 32 to above the upper insulating film 38 and directly covers the source electrode 32 and the upper insulating film 38 .
  • the source terminal electrode 60 exposes a portion of the upper insulating film 38 that covers the corners of the source electrode 32 (that is, the source electrode surface 32a and the source electrode sidewalls 32b).
  • a source terminal side wall 62 of the source terminal electrode 60 is located on the upper insulating film 38 and extends substantially vertically in the normal direction Z in this embodiment.
  • the source terminal sidewall 62 faces the source electrode 32 with the upper insulating film 38 interposed therebetween.
  • the second protruding portion 63 of the source terminal electrode 60 extends along the outer surface of the upper insulating film 38 in a cross-sectional view, and has a tapered shape in which the thickness gradually decreases from the source terminal side wall 62 toward the tip. formed.
  • the source terminal electrode 60 has a laminated structure including a first source conductor film 67 and a second source conductor film 68, as in the first embodiment.
  • the first source conductor film 67 covers the source electrode 32 in the source opening 40 in a film form and is pulled out on the upper insulating film 38 in a film form.
  • the second source conductor film 68 covers the source electrode 32 in the source opening 40 with the first source conductor film 67 interposed therebetween, and overlies the upper insulating film 38 with the first source conductor film 67 interposed therebetween. drawn out in the shape of
  • the sealing insulator 71 has a portion that directly covers the upper insulating film 38 in this form. Referring to FIG. 14, sealing insulator 71 has a portion directly covering upper insulating film 38 on gate electrode 30 . That is, the sealing insulator 71 has a portion covering the gate electrode 30 with the upper insulating film 38 interposed therebetween. Specifically, the sealing insulator 71 has a portion that covers at least a portion of the corner of the gate electrode 30 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the entire corner of the gate electrode 30 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the gate electrode surface 30a and the gate electrode sidewalls 30b at the corners of the gate electrode 30 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 is formed on the upper insulating film 38 with a gap from the gate opening 39 to the corner side of the gate electrode 30 .
  • the sealing insulator 71 has a portion that is in contact with only the upper insulating film 38 and the gate terminal electrode 50 (gate terminal side wall 52) immediately above the gate electrode 30, and a portion that directly covers the gate electrode 30. does not have In this embodiment, the sealing insulator 71 covers the first projecting portion 53 on the lower end side of the gate terminal electrode 50 and has a portion facing the upper insulating film 38 with the first projecting portion 53 interposed therebetween. .
  • the sealing insulator 71 has a portion directly covering the upper insulating film 38 on the source electrode 32 . That is, the sealing insulator 71 has a portion covering the source electrode 32 with the upper insulating film 38 interposed therebetween. Specifically, the sealing insulator 71 has a portion that covers at least a portion of the corner of the source electrode 32 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the entire corner of the source electrode 32 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the source electrode surface 32a and the source electrode side walls 32b at the corners of the source electrode 32 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 is formed on the upper insulating film 38 with a space from the source opening 40 to the corner side of the source electrode 32 .
  • the sealing insulator 71 has a portion that contacts only the upper insulating film 38 and the source terminal electrode 60 (source terminal side wall 62) immediately above the source electrode 32, and a portion that directly covers the source electrode 32. does not have In this embodiment, the sealing insulator 71 covers the second projecting portion 63 on the lower end side of the source terminal electrode 60 and has a portion facing the upper insulating film 38 with the second projecting portion 63 interposed therebetween. .
  • the sealing insulator 71 covers the entire area of the plurality of gate wirings 36A and 36B and the entire area of the source wiring 37 with the upper insulating film 38 interposed therebetween.
  • the encapsulating insulator 71 may contain a plurality of fillers having a thickness exceeding the thickness of the upper insulating film 38 .
  • the semiconductor device 1B includes the chip 2, the gate electrode 30 (main surface electrode), the gate terminal electrode 50, the upper insulating film 38 (insulating film), and the sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • Gate electrode 30 is arranged on first main surface 3 .
  • the upper insulating film 38 has a single-layer structure composed of an inorganic insulating film 42 (inorganic film), and directly covers the gate electrode 30 so as to partially expose the gate electrode 30 .
  • the gate terminal electrode 50 is arranged on the gate electrode 30 .
  • the sealing insulator 71 covers the periphery of the gate terminal electrode 50 so as to partially expose the gate terminal electrode 50 and has a portion directly covering the upper insulating film 38 .
  • the upper insulating film 38 can protect the gate electrode 30 from external force and moisture.
  • peeling starting points between the gate electrode 30 and the sealing insulator 71 can be reduced.
  • both the upper insulating film 38 and the sealing insulator 71 can properly protect the object to be sealed (gate electrode 30, etc.). That is, it is possible to protect the objects to be sealed (gate electrode 30, etc.) from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1B with improved reliability.
  • the semiconductor device 1B includes a chip 2, a source electrode 32 (main surface electrode), a source terminal electrode 60, an upper insulating film 38 (insulating film), and a sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • the source electrode 32 is arranged on the first main surface 3 .
  • the upper insulating film 38 has a single-layer structure composed of an inorganic insulating film 42 (inorganic film), and directly covers the source electrode 32 so as to partially expose the source electrode 32 .
  • the source terminal electrode 60 is arranged on the source electrode 32 .
  • the sealing insulator 71 covers the periphery of the source terminal electrode 60 so as to partially expose the source terminal electrode 60 and has a portion directly covering the upper insulating film 38 on the source electrode 32 .
  • the upper insulating film 38 can protect the source electrode 32 from external forces and moisture.
  • peeling starting points between the source electrode 32 and the sealing insulator 71 can be reduced.
  • both the upper insulating film 38 and the sealing insulator 71 can properly protect the object to be sealed (the source electrode 32, etc.).
  • the object to be sealed (source electrode 32, etc.) can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1B with improved reliability.
  • the upper insulating film 38 preferably directly covers at least part of the corners of the gate electrode 30 (source electrode 32). That is, the upper insulating film 38 preferably directly covers the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewalls 30b (source electrode sidewalls 32b). According to this structure, peeling starting points at the corners of the gate electrode 30 (source electrode 32) can be reduced, and entry of moisture or the like starting from the corners of the gate electrode 30 (source electrode 32) can be appropriately suppressed.
  • the sealing insulator 71 preferably covers at least part of the corners of the gate electrode 30 (source electrode 32) with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 preferably has a portion covering the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewall 30b (source electrode sidewall 32b) with the upper insulating film 38 interposed therebetween.
  • both the upper insulating film 38 and the sealing insulator 71 can appropriately protect the corners of the gate electrode 30 (source electrode 32).
  • Gate terminal electrode 50 (source terminal electrode 60 ) preferably has a portion located on gate electrode 30 (source electrode 32 ) and a portion located on upper insulating film 38 .
  • FIGS. 17A and 17B are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1B shown in FIG. 17A and 17B show the steps of forming the upper insulating film 38 (inorganic insulating film 42).
  • the process of forming the upper insulating film 38 is performed prior to the process of forming the gate terminal electrode 50 and the source terminal electrode 60 (see FIGS. 12A to 12I).
  • a wafer structure 80 is prepared (see FIGS. 10 and 11).
  • An upper insulating film 38 is then formed on the first wafer main surface 82 .
  • the upper insulating film 38 directly covers the interlayer insulating film 27 , the gate electrode 30 , the source electrode 32 , the plurality of gate wirings 36A and 36B and the source wiring 37 .
  • the upper insulating film 38 has a single-layer structure composed of the inorganic insulating film 42 in this embodiment.
  • the upper insulating film 38 may be formed by a CVD (Chemical Vapor Deposition) method.
  • a resist mask 96 having a predetermined pattern is formed on the upper insulating film 38. Then, referring to FIG. The resist mask 96 exposes the regions where the gate opening 39, the source opening 40 and the dicing street 41 are to be formed in the upper insulating film 38 and covers the other regions.
  • the etching method may be a wet etching method and/or a dry etching method. Thereby, the upper insulating film 38 that partitions the gate opening 39, the source opening 40 and the dicing street 41 is formed. After that, the resist mask 96 is removed. 12A to 12I are sequentially performed to manufacture the semiconductor device 1B.
  • the method of manufacturing the semiconductor device 1B includes the steps of preparing the wafer structure 80, forming the upper insulating film 38, forming the gate terminal electrode 50, and forming the sealing insulator 71.
  • the wafer structure 80 including the wafer 81 and the gate electrode 30 (main surface electrode) is prepared.
  • Wafer 81 has a first wafer main surface 82 .
  • the gate electrode 30 is arranged on the first wafer main surface 82 .
  • the upper insulating film 38 In the process of forming the upper insulating film 38, the upper insulating film 38 that directly covers the gate electrode 30 is formed so that part of the gate electrode 30 is exposed. In the step of forming the gate terminal electrode 50 , the gate terminal electrode 50 is formed on the gate electrode 30 . In the step of forming the sealing insulator 71 , the sealing insulator 71 is formed which covers the periphery of the gate terminal electrode 50 so as to partially expose the gate terminal electrode 50 and has a portion directly covering the upper insulating film 38 . be done.
  • the upper insulating film 38 can protect the gate electrode 30 from external force and moisture.
  • peeling starting points between the gate electrode 30 and the sealing insulator 71 can be reduced.
  • both the upper insulating film 38 and the sealing insulator 71 can properly protect the object to be sealed (gate electrode 30, etc.). That is, it is possible to protect the objects to be sealed (gate electrode 30, etc.) from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, the semiconductor device 1B with improved reliability can be manufactured.
  • the manufacturing method of the semiconductor device 1B includes a wafer structure 80 preparation process, an upper insulating film 38 forming process, a source terminal electrode 60 forming process, and a sealing insulator 71 forming process.
  • the wafer structure 80 including the wafer 81 and the source electrode 32 (main surface electrode) is prepared.
  • Wafer 81 has a first wafer main surface 82 .
  • the source electrode 32 is arranged on the first wafer major surface 82 .
  • the upper insulating film 38 that directly covers the source electrode 32 is formed so that the source electrode 32 is partially exposed.
  • the source terminal electrode 60 is formed on the source electrode 32 .
  • the sealing insulator 71 covers the periphery of the source terminal electrode 60 so as to partially expose the source terminal electrode 60 and has a portion directly covering the upper insulating film 38 on the source electrode 32 .
  • a stop insulator 71 is formed.
  • the upper insulating film 38 can protect the source electrode 32 from external force and moisture.
  • peeling starting points between the source electrode 32 and the sealing insulator 71 can be reduced.
  • both the upper insulating film 38 and the sealing insulator 71 can properly protect the object to be sealed (the source electrode 32, etc.).
  • the object to be sealed (source electrode 32, etc.) can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, the semiconductor device 1B with improved reliability can be manufactured.
  • the upper insulating film 38 it is preferable to form the upper insulating film 38 that directly covers at least part of the corners of the gate electrode 30 (source electrode 32). In this case, in the step of forming the sealing insulator 71, it is preferable to form the sealing insulator 71 that covers at least part of the corners of the gate electrode 30 (source electrode 32) with the upper insulating film 38 interposed therebetween. .
  • the sealing insulator 71 covering the gate electrode surface 30a (source electrode surface 32a) and the gate electrode sidewall 30b (source electrode sidewall 32b) with the upper insulating film 38 interposed therebetween is formed. preferably formed. According to these manufacturing methods, the corners of the gate electrode 30 (source electrode 32 ) can be protected by the upper insulating film 38 and the sealing insulator 71 .
  • FIG. 18 is a cross-sectional view showing a semiconductor device 1C according to the third embodiment.
  • a semiconductor device 1C has a configuration obtained by modifying the aforementioned semiconductor device 1B (see FIG. 13).
  • the semiconductor device 1C has a single-layer structure composed of an organic insulating film 43 (organic film) instead of the inorganic insulating film 42, and includes a gate electrode 30, a source electrode 32, a plurality of gate wirings 36A, 36B and An upper insulating film 38 directly covering the source line 37 is included.
  • the organic insulating film 43 is preferably made of a resin film other than thermosetting resin.
  • the organic insulating film 43 may be made of translucent resin or transparent resin.
  • the organic insulating film 43 may be made of a negative type or positive type photosensitive resin film.
  • the organic insulating film 43 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film.
  • the organic insulating film 43 includes a polybenzoxazole film in this form.
  • the thickness of the organic insulating film 43 preferably exceeds the thickness of the interlayer insulating film 27 . It is particularly preferable that the thickness of the organic insulating film 43 exceeds the thickness of the gate electrode 30 and the thickness of the source electrode 32 .
  • the thickness of the organic insulating film 43 may be 3 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the organic insulating film 43 is preferably 20 ⁇ m or less.
  • the semiconductor device 1C has the same effect as the semiconductor device 1B.
  • FIGS. 19A and 19B are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1C shown in FIG. 19A and 19B show the steps of forming the upper insulating film 38 (organic insulating film 43).
  • the process of forming the upper insulating film 38 is performed prior to the process of forming the gate terminal electrode 50 and the source terminal electrode 60 (see FIGS. 12A to 12I).
  • a fluid resin that forms the base of the organic insulating film 43 is applied onto the main surface 82 of the first wafer.
  • the resin in this form, consists of a photosensitive resin.
  • the photosensitive resin is applied, for example, to the central portion of the first wafer main surface 82 and spread to the periphery of the first wafer main surface 82 in the form of a liquid film by spin coating.
  • the liquid film-like photosensitive resin is exposed in a pattern corresponding to the gate openings 39, the source openings 40 and the dicing streets 41, and then developed. Thereby, the upper insulating film 38 that partitions the gate opening 39, the source opening 40 and the dicing street 41 is formed.
  • the steps of FIGS. 12A to 12I are sequentially performed to manufacture the semiconductor device 1C. As described above, the method for manufacturing the semiconductor device 1C also produces the same effect as the method for manufacturing the semiconductor device 1B.
  • FIG. 20 is a cross-sectional view showing a semiconductor device 1D according to the fourth embodiment.
  • FIG. 21 is a cross-sectional view showing a main part of gate terminal electrode 50 shown in FIG. 22 is a cross-sectional view showing a main part of the source terminal electrode 60 shown in FIG. 20.
  • FIG. FIG. 23 is a plan view showing a layout example of the upper insulating film 38 shown in FIG. 20 to 23, a semiconductor device 1D has a modified form of the above-described semiconductor device 1B (see FIG. 13).
  • the semiconductor device 1D includes an upper insulating film 38 having a single-layer structure composed of an inorganic insulating film 42.
  • an organic insulating film 42 is used instead of the inorganic insulating film 42. It may have a single layer structure consisting of the film 43 .
  • the upper insulating film 38 has a gate removal portion 38a exposing at least part of the corner of the gate electrode 30 in this embodiment.
  • the gate removal portion 38a exposes the entire corner of the gate electrode 30 in this embodiment.
  • Gate removal portion 38 a exposes gate electrode surface 30 a and gate electrode sidewalls 30 b at the corners of gate electrode 30 .
  • the upper insulating film 38 has a source removal portion 38b that exposes at least part of the corner of the source electrode 32. As shown in FIG. The source removal portion 38b exposes the entire corner of the source electrode 32 in this form. The source removal portion 38b exposes the source electrode surface 32a and the source electrode side walls 32b at the corners of the source electrode 32 . The source removal portion 38b communicates with the gate removal portion 38a in the region between the gate electrode 30 and the source electrode 32 in this embodiment.
  • the upper insulating film 38 includes a wiring removal portion 38c exposing the plurality of gate wirings 36A and 36B and the source wiring 37.
  • the wiring removed portion 38c exposes the entire area of the plurality of gate wirings 36A and 36B and the entire area of the source wiring 37.
  • the wiring removed portion 38c surrounds the gate electrode 30 and the source electrode 32 in plan view, and communicates with the gate removed portion 38a and the source removed portion 38b.
  • the upper insulating film 38 has a gate covering portion 38d defined above the gate electrode 30 by a gate removal portion 38a.
  • the gate covering portion 38 d covers the peripheral edge portion of the gate electrode 30 so as to expose the corner portion of the gate electrode 30 in plan view, and defines a gate opening 39 exposing the inner portion of the gate electrode 30 .
  • the gate covering portion 38d is formed in an annular shape surrounding the inner portion of the gate electrode 30 in plan view.
  • the upper insulating film 38 has a source covering portion 38e partitioned over the source electrode 32 by a source removal portion 38b.
  • the source covering portion 38e covers the peripheral portion of the source electrode 32 so as to expose the corner portion of the source electrode 32 in plan view, and defines a source opening 40 exposing the inner portion of the source electrode 32.
  • the source covering portion 38e is formed in an annular shape surrounding the inner portion of the source electrode 32 in plan view.
  • the upper insulating film 38 has an outer covering portion 38f defined on the outer surface 9 (interlayer insulating film 27) by a wire removal portion 38c.
  • the outer covering portion 38f covers a region outside the source wiring 37 in plan view.
  • the outer covering portion 38f is formed in a ring shape surrounding the active surface 8 (source wiring 37) in plan view.
  • the aforementioned dicing street 41 is defined in the region between the peripheral edge of the first main surface 3 and the outer covering portion 38f in this embodiment.
  • the sealing insulator 71 directly covers the upper insulating film 38 from above the upper insulating film 38 so as to enter the gate removal portion 38a.
  • the encapsulating insulator 71 directly covers at least a portion of the corners of the gate electrode 30 within the gate removal portion 38a.
  • the encapsulating insulator 71 directly covers the entire corner of the gate electrode 30 in this form.
  • the sealing insulator 71 directly covers the gate electrode surface 30a and the gate electrode sidewalls 30b of the gate electrode 30 in the gate removal portion 38a.
  • the sealing insulator 71 has a portion that directly covers the gate covering portion 38 d of the upper insulating film 38 directly above the gate electrode 30 .
  • the sealing insulator 71 may have a portion facing the gate covering portion 38d with the first projecting portion 53 of the gate terminal electrode 50 interposed therebetween.
  • the sealing insulator 71 directly covers the upper insulating film 38 from above the upper insulating film 38 so as to enter the source removal portion 38b.
  • the encapsulating insulator 71 directly covers at least part of the corners of the source electrode 32 in the source removal portion 38b.
  • the encapsulating insulator 71 directly covers the entire corner of the source electrode 32 in this form.
  • the sealing insulator 71 directly covers the source electrode surface 32a and the source electrode sidewalls 32b of the source electrode 32 in the source removal portion 38b.
  • the sealing insulator 71 has a portion that directly covers the source covering portion 38 e of the upper insulating film 38 directly above the source electrode 32 .
  • the sealing insulator 71 may have a portion facing the source covering portion 38e with the second projecting portion 63 of the source terminal electrode 60 interposed therebetween.
  • the sealing insulator 71 directly covers the upper insulating film 38 from above the upper insulating film 38 so as to enter the wiring removal portion 38c.
  • the sealing insulator 71 directly covers the entire area of the plurality of gate lines 36A and 36B and the entire area of the source line 37 in the line removed portion 38c.
  • the sealing insulator 71 covers the outer covering portion 38f in a region outside the source wiring 37. As shown in FIG.
  • the sealing insulator 71 directly covers the interlayer insulating film 27 exposed to the outside in the gate removal portion 38a, the source removal portion 38b, and the wiring removal portion 38c.
  • the semiconductor device 1D has the same effect as the semiconductor device 1B.
  • the semiconductor device 1D is manufactured by changing the layout of the upper insulating film 38 in the manufacturing method of the semiconductor device 1B (semiconductor device 1C). Therefore, the method for manufacturing the semiconductor device 1D also has the same effect as the method for manufacturing the semiconductor device 1B.
  • FIG. 24 is a plan view showing a semiconductor device 1E according to the fifth embodiment.
  • semiconductor device 1E has a modified form of semiconductor device 1A.
  • the semiconductor device 1E specifically includes a source terminal electrode 60 having at least one (in this embodiment, a plurality of) lead terminal portions 100 .
  • the plurality of lead terminal portions 100 are led out above the plurality of lead electrode portions 34A and 34B of the source electrode 32 so as to face the gate terminal electrode 50 in the second direction Y, respectively. That is, the plurality of lead terminal portions 100 sandwich the gate terminal electrode 50 from both sides in the second direction Y in plan view.
  • the semiconductor device 1E has the same effect as the semiconductor device 1A. Also, the semiconductor device 1E is manufactured through a manufacturing method similar to the manufacturing method of the semiconductor device 1A. Therefore, the method for manufacturing the semiconductor device 1E also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • This form shows an example in which the lead terminal portion 100 is applied to the semiconductor device 1A. Of course, the lead terminal portion 100 may be applied to the second to fourth embodiments.
  • FIG. 25 is a plan view showing a semiconductor device 1F according to the sixth embodiment. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25.
  • FIG. FIG. 27 is a circuit diagram showing an electrical configuration of semiconductor device 1F shown in FIG. 25 to 27, semiconductor device 1F has a modified form of semiconductor device 1A.
  • the semiconductor device 1F specifically includes a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 .
  • the semiconductor device 1F includes at least one (one in this embodiment) source terminal electrode 60 arranged on the body electrode portion 33 of the source electrode 32, a lead-out electrode portion 34A of the source electrode 32, It includes at least one (in this form a plurality) source terminal electrode 60 disposed over 34B.
  • the source terminal electrode 60 on the body electrode portion 33 side is formed as a main terminal electrode 102 that conducts the drain-source current IDS in this embodiment.
  • the plurality of source terminal electrodes 60 on the side of the plurality of lead-out electrode portions 34A and 34B are formed as sense terminal electrodes 103 in this embodiment for conducting a monitor current IM for monitoring the drain-source current IDS.
  • Each sense terminal electrode 103 has an area smaller than that of the main terminal electrode 102 in plan view.
  • One sense terminal electrode 103 is arranged on the first extraction electrode portion 34A and faces the gate terminal electrode 50 in the second direction Y in plan view.
  • the other sense terminal electrode 103 is arranged on the second extraction electrode portion 34B and faces the gate terminal electrode 50 in the second direction Y in plan view.
  • the plurality of sense terminal electrodes 103 sandwich the gate terminal electrode 50 from both sides in the second direction Y in plan view.
  • gate drive circuit 106 is electrically connected to gate terminal electrode 50, at least one first resistor R1 is electrically connected to main terminal electrode 102, and a plurality of sense resistors are connected. At least one second resistor R2 is connected to the terminal electrode 103 .
  • the first resistor R1 is configured to conduct the drain-source current IDS generated in the semiconductor device 1F.
  • the second resistor R2 is configured to conduct a monitor current IM having a value less than the drain-source current IDS.
  • the first resistor R1 may be a resistor or a conductive joint member having a first resistance value.
  • the second resistor R2 may be a resistor or a conductive joint member having a second resistance value greater than the first resistance value.
  • the conductive joining member may be a conductive plate or a conductive wire (eg, bonding wire). That is, at least one first bonding wire having a first resistance value may be connected to the main terminal electrode 102 .
  • At least one second bonding wire having a second resistance value exceeding the first resistance value may be connected to at least one sense terminal electrode 103 .
  • the second bonding wire may have a line thickness less than the line thickness of the first bonding wire.
  • the bonding area of the second bonding wire to the sense terminal electrode 103 may be less than the bonding area of the first bonding wire to the main terminal electrode 102 .
  • the semiconductor device 1F has the same effect as the semiconductor device 1A.
  • a resist mask 90 having a plurality of second openings 92 exposing regions where the source terminal electrode 60 and the sense terminal electrode 103 are to be formed is formed in the method for manufacturing the semiconductor device 1A.
  • the same steps as in the manufacturing method of 1A are carried out. Therefore, the method for manufacturing the semiconductor device 1F also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • the sense terminal electrodes 103 are arranged on the lead electrode portions 34A and 34B, but the arrangement location of the sense terminal electrodes 103 is arbitrary. Therefore, the sense terminal electrode 103 may be arranged on the body electrode portion 33 .
  • This form shows an example in which the sense terminal electrode 103 is applied to the semiconductor device 1A.
  • the sense terminal electrode 103 may be applied to the second to fifth embodiments.
  • FIG. 28 is a plan view showing a semiconductor device 1G according to the seventh embodiment. 29 is a cross-sectional view taken along line XXIX-XXIX shown in FIG. 28.
  • the semiconductor device 1 ⁇ /b>G specifically includes a gap 107 formed in the source electrode 32 .
  • the gap portion 107 is formed in the body electrode portion 33 of the source electrode 32 .
  • the gap 107 penetrates the source electrode 32 and exposes a portion of the interlayer insulating film 27 in a cross-sectional view.
  • the gap portion 107 extends in a strip shape from a portion of the wall portion of the source electrode 32 facing the gate electrode 30 in the first direction X toward the inner portion of the source electrode 32 .
  • the gap part 107 is formed in a strip shape extending in the first direction X in this embodiment.
  • the gap portion 107 crosses the central portion of the source electrode 32 in the first direction X in plan view.
  • the gap portion 107 has an end portion at a position spaced inward (gate electrode 30 side) from the wall portion of the source electrode 32 on the fourth side surface 5D side in plan view.
  • the gap 107 may divide the source electrode 32 in the second direction Y.
  • the semiconductor device 1G includes a gate intermediate wiring 109 pulled out from the gate electrode 30 into the gap portion 107 .
  • the gate intermediate wiring 109 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56, like the gate electrode 30 (the plurality of gate wirings 36A and 36B).
  • the gate intermediate wiring 109 is formed spaced apart from the source electrode 32 in a plan view and extends along the gap 107 in a strip shape.
  • the gate intermediate wiring 109 is electrically connected to the plurality of gate structures 15 through the interlayer insulating film 27 in the inner portion of the active surface 8 (first main surface 3).
  • the gate intermediate wiring 109 may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.
  • the semiconductor device 1G in this embodiment includes a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 .
  • the plurality of source terminal electrodes 60 are arranged on the source electrode 32 with a gap from the gap 107 in plan view, and are opposed to each other in the second direction Y. As shown in FIG.
  • each of the plurality of source terminal electrodes 60 is formed in a quadrangular shape (specifically, a rectangular shape extending in the first direction X) in plan view.
  • the planar shape of the plurality of source terminal electrodes 60 is arbitrary, and may be formed in a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape.
  • the aforementioned sealing insulator 71 covers the gap 107 in the region between the plurality of source terminal electrodes 60 in this embodiment.
  • the encapsulating insulator 71 directly covers the gate intermediate wiring 109 in the region between the plurality of source terminal electrodes 60 .
  • the encapsulating insulator 71 directly covers at least a portion (in this embodiment, the entire area) of the corners of the source electrode 32 in the region between the plurality of source terminal electrodes 60 . That is, the encapsulating insulator 71 directly covers the source electrode surface 32 a and the source electrode side walls 32 b of the source electrode 32 in the regions between the plurality of source terminal electrodes 60 .
  • the semiconductor device 1G has the same effect as the semiconductor device 1A.
  • a wafer structure 80 in which structures corresponding to the semiconductor device 1G are formed in the device regions 86 is prepared, and the same steps as in the method for manufacturing the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1G also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • the gap 107, the gate intermediate wiring 109, and the like are applied to the semiconductor device 1A.
  • the gap 107, the gate intermediate wiring 109, etc. may be applied to the second to sixth embodiments.
  • the semiconductor device 1G may include the upper insulating film 38 according to the second to fourth embodiments.
  • upper insulating film 38 may include a portion covering gap 107 .
  • the upper insulating film 38 directly cover the entire area of the gate intermediate wiring 109 within the gap 107 . Moreover, it is preferable that the upper insulating film 38 directly cover at least a portion (in this embodiment, the entire area) of the corners of the source electrode 32 in the gap 107 . In other words, upper insulating film 38 preferably directly covers source electrode surface 32 a and source electrode side wall 32 b in gap 107 .
  • the plurality of source terminal electrodes 60 are preferably arranged so as to expose portions of the upper insulating film 38 that cover the gaps 107 .
  • the plurality of source terminal electrodes 60 may include second protrusions 63 formed on portions of the upper insulating film 38 covering the gaps 107 .
  • the sealing insulator 71 may directly cover the upper insulating film 38 in regions between the plurality of source terminal electrodes 60 . That is, the sealing insulator 71 may cover the gate intermediate wiring 109 with the upper insulating film 38 interposed therebetween. The sealing insulator 71 may cover the corners of the source electrodes 32 with the upper insulating film 38 interposed therebetween in the regions between the plurality of source terminal electrodes 60 .
  • FIG. 30 is a plan view showing a semiconductor device 1H according to the eighth embodiment.
  • semiconductor device 1H has the feature (structure having gate intermediate wiring 109) of semiconductor device 1G according to the seventh embodiment, and the feature (sense terminal electrode 103) of semiconductor device 1F according to the sixth embodiment. It has a form combined with a structure having The semiconductor device 1H having such a form also provides the same effects as those of the semiconductor device 1A.
  • FIG. 31 is a plan view showing a semiconductor device 1I according to the ninth embodiment.
  • a semiconductor device 1I has a modified form of semiconductor device 1A.
  • the semiconductor device 1I specifically has gate electrodes 30 arranged in regions along arbitrary corners of the chip 2 .
  • the gate electrode 30 has a first straight line L1 (see two-dot chain line) that crosses the central portion of the first main surface 3 in the first direction X, and a straight line L1 that crosses the central portion of the first main surface 3 in the second direction Y.
  • the crossing second straight line L2 (see the two-dot chain line portion) is set, it is arranged at a position shifted from both the first straight line L1 and the second straight line L2.
  • gate electrode 30 is arranged in a region along a corner connecting second side surface 5B and third side surface 5C in plan view.
  • the plurality of extraction electrode portions 34A and 34B related to the source electrode 32 described above sandwich the gate electrode 30 from both sides in the second direction Y in plan view, as in the first embodiment.
  • the first extraction electrode portion 34A is extracted from the body electrode portion 33 with a first plane area.
  • the second extraction electrode portion 34B is extracted from the body electrode portion 33 with a second plane area smaller than the first plane area.
  • the source electrode 32 may include only the body electrode portion 33 and the first lead electrode portion 34A without the second lead electrode portion 34B.
  • the gate terminal electrode 50 described above is arranged on the gate electrode 30 as in the case of the first embodiment.
  • the gate terminal electrode 50 is arranged in a region along an arbitrary corner of the chip 2 in this embodiment. That is, the gate terminal electrode 50 is arranged at a position shifted from both the first straight line L1 and the second straight line L2 in plan view. In this embodiment, the gate terminal electrode 50 is arranged in a region along the corner connecting the second side surface 5B and the third side surface 5C in plan view.
  • the aforementioned source terminal electrode 60 in this form, has a lead terminal portion 100 that is led out above the first lead electrode portion 34A.
  • the source terminal electrode 60 does not have the extraction terminal portion 100 extracted above the second extraction electrode portion 34B. Therefore, the lead terminal portion 100 faces the gate terminal electrode 50 from one side in the second direction Y.
  • the source terminal electrode 60 has a portion facing the gate terminal electrode 50 from two directions, the first direction X and the second direction Y, by having the lead terminal portion 100 .
  • the semiconductor device 1I has the same effect as the semiconductor device 1A.
  • a wafer structure 80 in which structures corresponding to the semiconductor device 1I are formed in the device regions 86 is prepared, and steps similar to those of the method of manufacturing the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1I also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • the structure in which the gate electrode 30 and the gate terminal electrode 50 are arranged along the corners of the chip 2 may be applied to the second to eighth embodiments.
  • FIG. 32 is a plan view showing a semiconductor device 1J according to the tenth embodiment.
  • semiconductor device 1J has a configuration obtained by modifying semiconductor device 1A.
  • the semiconductor device 1J has a gate electrode 30 arranged in the central portion of the first main surface 3 (active surface 8) in plan view.
  • the gate electrode 30 has a first straight line L1 (see two-dot chain line) that crosses the central portion of the first main surface 3 in the first direction X, and a straight line L1 that crosses the central portion of the first main surface 3 in the second direction Y.
  • the crossing second straight line L2 (see two-dot chain line) is set, it is arranged so as to cover the intersection Cr of the first straight line L1 and the second straight line L2.
  • the source electrode 32 described above is formed in a ring shape (specifically, a square ring shape) surrounding the gate electrode 30 in plan view.
  • the semiconductor device 1J includes a plurality of gaps 107A and 107B formed in the source electrode 32.
  • the plurality of gaps 107A, 107B includes a first gap 107A and a second gap 107B.
  • the first gap portion 107A crosses in the second direction Y a portion extending in the first direction X in the region on one side (first side surface 5A side) of the source electrode 32 .
  • the first gap portion 107A faces the gate electrode 30 in the second direction Y in plan view.
  • the second gap portion 107B crosses in the second direction Y the portion extending in the first direction X in the region on the other side (second side surface 5B side) of the source electrode 32 .
  • the second gap portion 107B faces the gate electrode 30 in the second direction Y in plan view.
  • the second gap 107B faces the first gap 107A across the gate electrode 30 in plan view.
  • the aforementioned first gate wiring 36A is drawn from the gate electrode 30 into the first gap 107A.
  • the first gate line 36A has a portion extending in the second direction Y in a band shape in the first gap portion 107A, and a portion extending in the first direction X along the first side surface 5A (first connection surface 10A). It has a strip-like portion.
  • the aforementioned second gate wiring 36B is led out from the gate electrode 30 into the second gap portion 107B.
  • the second gate wiring 36B has a portion extending in the second direction Y in a strip shape in the second gap 107B and a portion extending in the first direction X along the second side surface 5B (second connection surface 10B). It has a strip-like portion.
  • the plurality of gate wirings 36A and 36B intersect (specifically, orthogonally) the both ends of the plurality of gate structures 15, as in the first embodiment.
  • the multiple gate wirings 36A and 36B are electrically connected to the multiple gate structures 15 through the interlayer insulating film 27 .
  • the plurality of gate wirings 36A and 36B may be directly connected to the plurality of gate structures 15, or may be electrically connected to the plurality of gate structures 15 via a conductor film.
  • the source wiring 37 described above, in this embodiment, is drawn out from the source electrode 32 at multiple locations and surrounds the gate electrode 30, the source electrode 32, and the gate wirings 36A and 36B.
  • the source wiring 37 may be led out from a single portion of the source electrode 32 as in the first embodiment.
  • the gate terminal electrode 50 described above is arranged on the gate electrode 30 as in the case of the first embodiment.
  • the gate terminal electrode 50 is arranged in the central portion of the first main surface 3 (active surface 8) in this embodiment. That is, the gate terminal electrode 50 has a first straight line L1 (see two-dot chain line) crossing the central portion of the first main surface 3 in the first direction X, and a central portion of the first main surface 3 extending in the second direction Y.
  • a second straight line L2 (see the two-dot chain line) is set to cross the two straight lines L1 and L2, it is arranged so as to cover the intersection Cr of the first straight line L1 and the second straight line L2.
  • the semiconductor device 1J in this embodiment includes a plurality of source terminal electrodes 60 spaced apart from each other on the source electrode 32 .
  • the plurality of source terminal electrodes 60 are arranged on the source electrode 32 at intervals from the plurality of gaps 107A and 107B in plan view, and face each other in the first direction X. As shown in FIG.
  • the plurality of source terminal electrodes 60 are arranged in this form so as to expose the plurality of gaps 107A and 107B.
  • each of the plurality of source terminal electrodes 60 is formed in a strip shape extending along the source electrode 32 in plan view (specifically, in a C shape curved along the gate terminal electrode 50).
  • the planar shape of the plurality of source terminal electrodes 60 is arbitrary, and may be rectangular, polygonal other than rectangular, circular, or elliptical.
  • the aforementioned sealing insulator 71 covers the plurality of gaps 107A and 107B in the region between the plurality of source terminal electrodes 60 in this embodiment.
  • the encapsulating insulator 71 directly covers the plurality of gate wirings 36A, 36B in the regions between the plurality of source terminal electrodes 60. As shown in FIG.
  • the encapsulating insulator 71 directly covers at least a portion (in this embodiment, the entire area) of the corners of the source electrode 32 in the region between the plurality of source terminal electrodes 60 . That is, the encapsulating insulator 71 directly covers the source electrode surface 32 a and the source electrode side walls 32 b of the source electrode 32 in the regions between the plurality of source terminal electrodes 60 .
  • the semiconductor device 1J has the same effect as the semiconductor device 1A.
  • a wafer structure 80 in which a structure corresponding to the semiconductor device 1J is formed in each device region 86 is prepared, and the same steps as in the manufacturing method of the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1J also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • the semiconductor device 1J may include the upper insulating film 38 according to the second to fourth embodiments.
  • the upper insulating film 38 may include portions covering the plurality of gaps 107A and 107B.
  • the upper insulating film 38 preferably directly covers the entire area of the plurality of gate wirings 36A, 36B within the plurality of gaps 107A, 107B. Moreover, it is preferable that the upper insulating film 38 directly cover at least a portion (preferably the entire area) of the corners of the source electrode 32 in the plurality of gaps 107A and 107B. That is, the upper insulating film 38 preferably directly covers the source electrode surface 32a and the source electrode sidewalls 32b in the plurality of gaps 107A and 107B.
  • the plurality of source terminal electrodes 60 are preferably arranged so as to expose portions of the upper insulating film 38 that cover the gaps 107 .
  • the plurality of source terminal electrodes 60 may include second protrusions 63 formed on portions of the upper insulating film 38 covering the gaps 107 .
  • the sealing insulator 71 may directly cover the upper insulating film 38 in regions between the plurality of source terminal electrodes 60 . That is, the sealing insulator 71 may cover the plurality of gate wirings 36A and 36B with the upper insulating film 38 interposed therebetween. The sealing insulator 71 preferably covers the corners of the source electrodes 32 in the regions between the plurality of source terminal electrodes 60 with the upper insulating film 38 interposed therebetween.
  • FIG. 33 is a plan view showing a semiconductor device 1K according to the eleventh embodiment.
  • 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 33.
  • FIG. The semiconductor device 1K includes the chip 2 described above.
  • the chip 2 does not have a mesa portion 11 in this form and includes a flat first principal surface 3 .
  • the semiconductor device 1K includes an SBD (Schottky Barrier Diode) structure 120 as an example of a diode formed on the chip 2 .
  • SBD Schottky Barrier Diode
  • the semiconductor device 1K includes an n-type diode region 121 formed in the inner part of the first main surface 3.
  • the diode region 121 is formed using part of the first semiconductor region 6 in this embodiment.
  • the semiconductor device 1K includes a p-type guard region 122 that partitions the diode region 121 from other regions on the first main surface 3 .
  • the guard region 122 is formed in the surface layer portion of the first semiconductor region 6 with an inward space from the peripheral edge of the first main surface 3 .
  • the guard region 122 is formed in a ring shape (in this form, a square ring shape) surrounding the diode region 121 in plan view.
  • Guard region 122 has an inner edge portion on the diode region 121 side and an outer edge portion on the peripheral edge side of first main surface 3 .
  • the semiconductor device 1K includes the main surface insulating film 25 that selectively covers the first main surface 3 .
  • Main surface insulating film 25 has diode opening 123 exposing the inner edge of diode region 121 and guard region 122 .
  • the main surface insulating film 25 is formed spaced inward from the peripheral edge of the first main surface 3 , exposing the first main surface 3 (first semiconductor region 6 ) from the peripheral edge of the first main surface 3 .
  • the main surface insulating film 25 may cover the peripheral portion of the first main surface 3 . In this case, the peripheral portion of the main surface insulating film 25 may continue to the first to fourth side surfaces 5A to 5D.
  • the semiconductor device 1K includes a first polar electrode 124 (main surface electrode) arranged on the first main surface 3 .
  • the first polarity electrode 124 is the "anode electrode” in this form.
  • the first polar electrode 124 is spaced inwardly from the periphery of the first major surface 3 .
  • the first polar electrode 124 is formed in a square shape along the periphery of the first main surface 3 in plan view.
  • the first polar electrode 124 enters the diode opening 123 from above the main surface insulating film 25 and is electrically connected to the first main surface 3 and the inner edge of the guard region 122 .
  • the first polar electrode 124 forms a Schottky junction with the diode region 121 (first semiconductor region 6). Thus, an SBD structure 120 is formed.
  • the plane area of the first polar electrode 124 is preferably 50% or more of the first major surface 3 . It is particularly preferable that the plane area of the first polar electrode 124 is 75% or more of the first major surface 3 .
  • the first polar electrode 124 may have a thickness of 0.5 ⁇ m to 15 ⁇ m.
  • the first polarity electrode 124 has an electrode surface 124a and electrode sidewalls 124b. Electrode surface 124 a extends along first main surface 3 and main surface insulating film 25 . Electrode sidewall 124 b is located on main surface insulating film 25 . The electrode sidewalls 124 b may extend obliquely with respect to the main surface insulating film 25 or may extend substantially vertically with respect to the main surface insulating film 25 .
  • the first polar electrode 124 may have a laminated structure including a Ti-based metal film and an Al-based metal film.
  • the Ti-based metal film may have a single layer structure consisting of a Ti film or a TiN film.
  • the Ti-based metal film may have a laminated structure including a Ti film and a TiN film in any order.
  • the Al-based metal film is preferably thicker than the Ti-based metal film.
  • the Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the semiconductor device 1K includes a terminal electrode 126 arranged on the first polarity electrode 124 .
  • the terminal electrode 126 is erected in a columnar shape on the first polarity electrode 124 .
  • the terminal electrode 126 has an area less than the area of the first polar electrode 124 in a plan view, and is spaced apart from the periphery of the first polar electrode 124 and disposed above the inner portion of the first polar electrode 124 . . That is, the terminal electrode 126 exposes at least a portion of the corner (periphery) of the first polarity electrode 124 .
  • the terminal electrode 126 exposes the corners of the first polarity electrode 124 over the entire circumference. Specifically, the terminal electrode 126 exposes the electrode surface 124a and the electrode sidewall 124b at the corners of the first polarity electrode 124 . The terminal electrode 126 has a lower end connected only to the electrode surface 124 a on the first polarity electrode 124 . In this form, the terminal electrode 126 is formed in a polygonal shape (quadrangular shape in this form) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view.
  • the terminal electrode 126 has a terminal surface 127 and terminal sidewalls 128 .
  • Terminal surface 127 extends flat along first main surface 3 .
  • the terminal surface 127 may consist of a ground surface with grinding marks.
  • the terminal side wall 128 is positioned above the terminal electrode 126 and extends substantially vertically in the normal direction Z in this embodiment. "Substantially vertical” also includes a form extending in the stacking direction while curving (meandering).
  • the terminal side wall 128 preferably has a smooth surface without grinding marks.
  • the terminal electrode 126 has a projecting portion 129 projecting outward from the lower end portion of the terminal side wall 128 in this embodiment.
  • the projecting portion 129 is formed in a region closer to the first polarity electrode 124 than the intermediate portion of the terminal side wall 128 .
  • the protruding portion 129 extends along the electrode surface 124a of the first polarity electrode 124, and is formed in a tapered shape in which the thickness gradually decreases from the terminal side wall 128 toward the tip portion in a cross-sectional view. As a result, the protruding portion 129 has a sharp tip that forms an acute angle.
  • the terminal electrode 126 without the projecting portion 129 may be formed.
  • the terminal electrode 126 preferably has a thickness exceeding the thickness of the first polarity electrode 124 .
  • the thickness of the terminal electrode 126 exceeds the thickness of the chip 2 in this embodiment.
  • the thickness of the terminal electrode 126 may be less than the thickness of the chip 2 .
  • the thickness of the terminal electrode 126 may be 10 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the terminal electrode 126 is preferably 30 ⁇ m or more. It is particularly preferable that the thickness of the terminal electrode 126 is 80 ⁇ m or more and 200 ⁇ m or less.
  • the terminal electrode 126 preferably has a planar area of 50% or more of the first main surface 3 . It is particularly preferable that the plane area of the terminal electrode 126 is 75% or more of the first main surface 3 .
  • the terminal electrode 126 has a laminated structure including a first conductor film 133 and a second conductor film 134 laminated in this order from the first polarity electrode 124 side.
  • the first conductor film 133 may contain a Ti-based metal film.
  • the first conductor film 133 may have a single layer structure made of a Ti film or a TiN film.
  • the first conductor film 133 may have a laminated structure including a Ti film and a TiN film laminated in any order.
  • the first conductor film 133 has a thickness less than the thickness of the first polarity electrode 124 .
  • the first conductor film 133 covers the first polarity electrode 124 in a film shape.
  • the first conductor film 133 forms part of the projecting portion 129 .
  • the first conductor film 133 does not necessarily have to be formed, and may be removed.
  • the second conductor film 134 forms the main body of the terminal electrode 126 .
  • the second conductor film 134 may contain a Cu-based metal film.
  • the Cu-based metal film may be a pure Cu film (a Cu film with a purity of 99% or more) or a Cu alloy film.
  • the second conductor film 134 includes a pure Cu plating film in this embodiment.
  • the second conductor film 134 preferably has a thickness exceeding the thickness of the first polar electrode 124 . The thickness of the second conductor film 134 exceeds the thickness of the chip 2 in this embodiment.
  • the second conductor film 134 covers the first polarity electrode 124 with the first conductor film 133 interposed therebetween.
  • the second conductor film 134 forms part of the projecting portion 129 . That is, the projecting portion 129 has a laminated structure including the first conductor film 133 and the second conductor film 134 .
  • the second conductor film 134 has a thickness exceeding the thickness of the first conductor film 133 within the projecting portion 129 .
  • the semiconductor device 1K includes a dicing street 41 provided in a region between the peripheral edge of the first main surface 3 and the first polar electrode 124 in this embodiment.
  • the dicing street 41 is provided in a region between the peripheral edge of the first main surface 3 and the main surface insulating film 25 in this embodiment.
  • the dicing street 41 exposes the first main surface 3 in a plan view and is formed in a belt shape extending along the periphery of the first main surface 3 .
  • the dicing street 41 is formed in a ring shape (specifically, a square ring shape) surrounding the inner portion of the first main surface 3 in plan view.
  • the dicing street 41 exposes the main surface insulating film 25 in the region between the peripheral edge of the first main surface 3 and the first polarity electrode 124 .
  • the semiconductor device 1K includes the aforementioned sealing insulator 71 covering the first main surface 3 .
  • the sealing insulator 71 covers the periphery of the terminal electrode 126 so as to partially expose the terminal electrode 126 on the first main surface 3 .
  • the sealing insulator 71 exposes the terminal surface 127 and covers the terminal side walls 128 .
  • the sealing insulator 71 covers the projecting portion 129 and faces the terminal electrode 126 with the projecting portion 129 interposed therebetween. The sealing insulator 71 prevents the terminal electrode 126 from coming off.
  • the sealing insulator 71 has a portion that directly covers the first polarity electrode 124 on the lower end side of the terminal electrode 126 .
  • the sealing insulator 71 specifically has a portion that directly covers at least part of the corner of the first polarity electrode 124 .
  • the encapsulating insulator 71 directly covers the entire corner of the first polarity electrode 124 in this configuration.
  • the sealing insulator 71 directly covers the electrode surface 124a and the electrode side walls 124b at the corners of the first polarity electrode 124. As shown in FIG. In other words, the encapsulating insulator 71 has a portion directly above the first polarity electrode 124 that contacts only the first polarity electrode 124 (electrode surface 124a) and the gate terminal electrode 50 (electrode side wall 124b). A portion of the sealing insulator 71 that directly covers the electrode side wall 124 b is in contact with the main surface insulating film 25 .
  • the sealing insulator 71 covers the dicing streets 41 partitioned by the main-surface insulating film 25 on the periphery of the first main surface 3 .
  • the encapsulating insulator 71 directly covers the first major surface 3 (first semiconductor region 6 ) at the dicing street 41 in this embodiment.
  • the sealing insulator 71 may directly cover the main surface insulating film 25 at the dicing streets 41 .
  • the sealing insulator 71 preferably has a thickness exceeding the thickness of the first polar electrode 124 .
  • the thickness of the encapsulation insulator 71 exceeds the thickness of the chip 2 in this embodiment.
  • the thickness of the encapsulating insulator 71 may be less than the thickness of the chip 2 .
  • the thickness of the sealing insulator 71 may be 10 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the sealing insulator 71 is preferably 30 ⁇ m or more. It is particularly preferable that the thickness of the sealing insulator 71 is 80 ⁇ m or more and 200 ⁇ m or less.
  • the sealing insulator 71 has an insulating main surface 72 and insulating side walls 73 .
  • the insulating main surface 72 extends flat along the first main surface 3 .
  • the insulating main surface 72 forms one flat surface with the terminal surface 127 .
  • the insulating main surface 72 may be a ground surface having grinding marks. In this case, the insulating main surface 72 preferably forms one ground surface with the terminal surface 127 .
  • the insulating side wall 73 extends from the peripheral edge of the insulating main surface 72 toward the chip 2 and continues to the first to fourth side surfaces 5A to 5D.
  • the insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72 .
  • the angle formed between insulating side wall 73 and insulating main surface 72 may be 88° or more and 92° or less.
  • the insulating side wall 73 may consist of a ground surface with grinding marks.
  • the insulating sidewall 73 may form one grinding surface with the first to fourth side surfaces 5A to 5D.
  • the semiconductor device 1K includes a second polarity electrode 136 (second main surface electrode) covering the second main surface 4.
  • the second polar electrode 136 is the "cathode electrode” in this form.
  • the second polar electrode 136 is electrically connected to the second major surface 4 .
  • the second polar electrode 136 forms an ohmic contact with the second semiconductor region 7 exposed from the second major surface 4 .
  • the second polar electrode 136 may cover the entire second main surface 4 so as to be connected to the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).
  • the second polar electrode 136 may cover the second main surface 4 with a space inward from the periphery of the chip 2 .
  • the second polarity electrode 136 is configured such that a voltage of 500 V or more and 3000 V or less is applied between the terminal electrode 126 and the terminal electrode 126 . That is, the chip 2 is formed so that a voltage of 500 V or more and 3000 V or less is applied between the first principal surface 3 and the second principal surface 4 .
  • the semiconductor device 1K includes the chip 2, the first polarity electrode 124 (main surface electrode), the terminal electrode 126, and the sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • the first polar electrode 124 is arranged on the first major surface 3 .
  • a terminal electrode 126 is disposed on the first polarity electrode 124 so as to expose a portion of the first polarity electrode 124 .
  • the sealing insulator 71 covers the periphery of the terminal electrode 126 so as to partially expose the terminal electrode 126 and has a portion that directly covers the first polarity electrode 124 .
  • the sealing object (first polar electrode 124 and the like) can be appropriately protected by the sealing insulator 71 .
  • the object to be sealed can be protected from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1K with improved reliability.
  • the terminal electrode 126 exposes the corner of the first polarity electrode 124 and the sealing insulator 71 directly covers at least part of the corner of the first polarity electrode 124 . That is, it is preferable that the terminal electrode 126 exposes the electrode surface 124a and the electrode sidewalls 124b, and the sealing insulator 71 directly covers the electrode surface 124a and the electrode sidewalls 124b. According to these structures, it is possible to reduce the number of exfoliation starting points at the corners of the first polarity electrode 124 and suppress the entry of moisture or the like originating from the corners of the first polarity electrode 124 . Sealing insulator 71 preferably has a portion that contacts only first polarity electrode 124 and terminal electrode 126 .
  • the same effects as those of the semiconductor device 1A can be obtained.
  • a wafer structure 80 in which structures corresponding to the semiconductor device 1K are formed in the device regions 86 is prepared, and the same steps as in the method for manufacturing the semiconductor device 1A are performed. Therefore, the method for manufacturing the semiconductor device 1K also produces the same effect as the method for manufacturing the semiconductor device 1A.
  • FIG. 35 is a plan view showing a semiconductor device 1L according to the twelfth embodiment.
  • the semiconductor device 1L has a configuration in which the technical concept of the semiconductor device 1B (see FIG. 13) according to the second embodiment is applied to the above-described semiconductor device 1K (see FIGS. 33 and 34).
  • the semiconductor device 1L has a single-layer structure composed of the inorganic insulating film 42 (inorganic film) and includes the upper insulating film 38 that directly covers the first polarity electrode 124 . It is particularly preferable that the inorganic insulating film 42 has a thickness less than the thickness of the first polar electrode 124 .
  • the upper insulating film 38 has a contact opening 125 that exposes the inner portion of the first polarity electrode 124 and has a portion that directly covers at least a portion of the corner (periphery) of the first polarity electrode 124 . there is The upper insulating film 38 directly covers the entire corner of the first polarity electrode 124 in this form.
  • the upper insulating film 38 directly covers the electrode surface 124a and the electrode sidewalls 124b at the corners of the first polarity electrode 124.
  • a portion of the upper insulating film 38 that directly covers the electrode side wall 124 b is in contact with the main surface insulating film 25 .
  • the contact opening 125 is formed in a square shape in plan view.
  • the upper insulating film 38 is formed spaced inwardly from the peripheral edge of the first main surface 3 (first to fourth side surfaces 5A to 5D), and forms a dicing street 41 between the peripheral edge of the first main surface 3 and the upper insulating film 38 . are partitioned.
  • the dicing street 41 is formed in a strip shape extending along the periphery of the first main surface 3 in plan view.
  • the dicing street 41 exposes the first main surface 3 (first semiconductor region 6) in this form.
  • the dicing streets 41 may expose the main surface insulating film 25 .
  • the terminal electrode 126 has an area smaller than the area of the first polarity electrode 124 in plan view, and is spaced apart from the periphery of the first polarity electrode 124 . placed on the square.
  • the terminal electrode 126 has a thickness exceeding the thickness of the upper insulating film 38 in this form.
  • the terminal electrode 126 extends from above the first polarity electrode 124 to above the upper insulating film 38 and directly covers the first polarity electrode 124 and the upper insulating film 38 . Specifically, the terminal electrode 126 exposes a portion of the upper insulating film 38 that covers the corners of the first polarity electrode 124 (that is, the electrode surface 124a and the electrode side walls 124b).
  • the terminal side wall 128 of the terminal electrode 126 is positioned above the upper insulating film 38 and extends substantially vertically in the normal direction Z in this embodiment.
  • the terminal sidewall 128 faces the first polarity electrode 124 with the upper insulating film 38 interposed therebetween.
  • the projecting portion 129 of the terminal electrode 126 extends along the outer surface of the upper insulating film 38 in a cross-sectional view, and is tapered so that the thickness gradually decreases from the terminal side wall 128 toward the tip. .
  • the terminal electrode 126 has a laminated structure including a first conductor film 133 and a second conductor film 134, as in the eleventh embodiment.
  • the first conductor film 133 covers the first polarity electrode 124 in the contact opening 125 in a film form and is drawn out on the upper insulating film 38 in a film form.
  • the second conductor film 134 covers the first polarity electrode 124 in the contact opening 125 with the first conductor film 133 interposed therebetween, and forms a film on the upper insulating film 38 with the first conductor film 133 interposed therebetween. is drawn out to
  • the sealing insulator 71 has a portion that directly covers the upper insulating film 38 in this form.
  • the sealing insulator 71 has a portion directly covering the upper insulating film 38 on the terminal electrode 126 . That is, the sealing insulator 71 has a portion covering the terminal electrode 126 with the upper insulating film 38 interposed therebetween. Specifically, the sealing insulator 71 has a portion that covers at least a portion of the corner of the terminal electrode 126 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the entire corner of the first polarity electrode 124 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 covers the electrode surface 124a and the electrode side walls 124b at the corners of the first polarity electrode 124 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 is formed on the upper insulating film 38 at a distance from the contact opening 125 to the corner side of the first polarity electrode 124 .
  • the sealing insulator 71 has a portion that contacts only the upper insulating film 38 and the terminal electrode 126 (terminal side wall 128) immediately above the first polarity electrode 124, and directly covers the first polarity electrode 124. does not have the part to In this embodiment, the sealing insulator 71 has a portion that covers the projecting portion 129 of the terminal electrode 126 and faces the upper insulating film 38 with the projecting portion 129 interposed therebetween.
  • the semiconductor device 1L includes the chip 2, the first polarity electrode 124 (main surface electrode), the terminal electrode 126, the upper insulating film 38 (insulating film), and the sealing insulator 71.
  • Chip 2 has a first main surface 3 .
  • the first polar electrode 124 is arranged on the first major surface 3 .
  • the upper insulating film 38 has a single-layer structure composed of an inorganic insulating film 42 (inorganic film), and directly covers the first polar electrode 124 so as to partially expose the first polar electrode 124 .
  • a terminal electrode 126 is disposed on the first polarity electrode 124 .
  • the sealing insulator 71 covers the periphery of the terminal electrode 126 so as to partially expose the terminal electrode 126 and has a portion that directly covers the upper insulating film 38 .
  • the upper insulating film 38 can protect the first polarity electrode 124 from external force and moisture.
  • the laminated film is not interposed between the first polarity electrode 124 and the sealing insulator 71, it is possible to reduce the separation starting points between the first polarity electrode 124 and the sealing insulator 71. .
  • both the upper insulating film 38 and the sealing insulator 71 can appropriately protect the sealing object (first polar electrode 124, etc.). That is, it is possible to protect the object to be sealed (the first polar electrode 124, etc.) from damage caused by external force and deterioration caused by moisture. This can suppress shape defects and variations in electrical characteristics. Therefore, it is possible to provide the semiconductor device 1L with improved reliability.
  • the upper insulating film 38 preferably directly covers at least part of the corners of the first polarity electrode 124 .
  • the upper insulating film 38 directly covers the electrode surface 124a and the electrode sidewalls 124b of the first polarity electrode 124 . According to this structure, it is possible to reduce the number of exfoliation starting points at the corners of the first polar electrode 124 and appropriately suppress the entry of moisture or the like originating from the corners of the first polar electrode 124 .
  • the sealing insulator 71 preferably covers at least part of the corner of the first polarity electrode 124 with the upper insulating film 38 interposed therebetween.
  • the sealing insulator 71 preferably covers the electrode surface 124a and the electrode sidewalls 124b with the upper insulating film 38 interposed therebetween.
  • both the upper insulating film 38 and the sealing insulator 71 can appropriately protect the corners of the first polarity electrode 124 .
  • Terminal electrode 126 preferably has a portion located on first polarity electrode 124 and a portion located on upper insulating film 38 .
  • FIG. 36 is a plan view showing a semiconductor device 1M according to the thirteenth embodiment.
  • the semiconductor device 1M has a configuration in which the technical concept of the semiconductor device 1C (see FIG. 18) according to the third embodiment is applied to the above-described semiconductor device 1K (see FIGS. 33 and 34). That is, the semiconductor device 1M has a single-layer structure composed of the organic insulating film 43 (organic film) and includes the upper insulating film 38 that directly covers the first polarity electrode 124 .
  • the upper insulating film 38, the terminal electrode 126, and the sealing insulator 71 are formed in the same manner as in the semiconductor device 1C and the semiconductor device 1L described above, so description thereof will be omitted.
  • the semiconductor device 1M has the same effect as the semiconductor device 1L.
  • FIG. 37 is a plan view showing a semiconductor device 1N according to the fourteenth embodiment.
  • the semiconductor device 1N is obtained by applying the technical idea of the semiconductor device 1D (see FIGS. 20 to 23) according to the fourth embodiment to the semiconductor device 1L (see FIG. 35) or the semiconductor device 1M (see FIG. 36). It has the form adopted. That is, the semiconductor device 1N has a single-layer structure composed of the inorganic insulating film 42 (inorganic film) or the organic insulating film 43 (organic film), and includes the upper insulating film 38 directly covering the first polarity electrode 124 .
  • the upper insulating film 38 has a removed portion 38g that exposes at least a portion of the corner of the first polarity electrode 124 in this embodiment.
  • the removed portion 38g exposes the entire corner of the first polarity electrode 124 in this form.
  • the removed portion 38g exposes the electrode surface 124a and the electrode sidewall 124b at the corner of the first polarity electrode 124. As shown in FIG.
  • the upper insulating film 38 has an inner covering portion 38h partitioned over the first polarity electrode 124 by a removed portion 38g.
  • the inner covering portion 38h covers the peripheral edge portion of the first polarity electrode 124 so as to expose the corner portion of the first polarity electrode 124, and defines the diode opening 123 that exposes the inner portion of the first polarity electrode 124.
  • the inner covering portion 38h is formed in an annular shape surrounding the inner portion of the first polar electrode 124 in plan view.
  • the upper insulating film 38 has an outer covering portion 38i that is defined in a region outside the first polarity electrode 124 (specifically, above the main surface insulating film 25) by a removed portion 38g.
  • the outer covering portion 38i is formed in an annular shape surrounding the first polar electrode 124 in plan view.
  • the aforementioned dicing street 41 is defined in the region between the peripheral edge of the first main surface 3 and the outer covering portion 38i in this embodiment.
  • the sealing insulator 71 directly covers the upper insulating film 38 from above the upper insulating film 38 so as to enter the removed portion 38g.
  • the sealing insulator 71 directly covers at least part of the corner of the first polarity electrode 124 in the removed portion 38g.
  • the encapsulating insulator 71 directly covers the entire corner of the first polarity electrode 124 in this configuration.
  • the sealing insulator 71 directly covers the electrode surface 124a and the electrode sidewalls 124b within the removed portion 38g.
  • the sealing insulator 71 directly covers the inner covering portion 38 h of the upper insulating film 38 directly above the first polarity electrode 124 .
  • the sealing insulator 71 may have a portion facing the inner covering portion 38h with the projecting portion 129 of the terminal electrode 126 interposed therebetween.
  • a sealing insulator 71 covers the outer covering portion 38i in the region outside the first polarity electrode 124 .
  • the semiconductor device 1N has the same effects as those of the semiconductor device 1K.
  • FIG. 38 is a cross-sectional view showing a modification of the tip 2 applied to each embodiment.
  • FIG. 38 shows, as an example, a mode in which a chip 2 according to a modification is applied to a semiconductor device 1A.
  • the chip 2 according to the modification may be applied to the second to fourteenth embodiments.
  • semiconductor device 1A may include only first semiconductor region 6 without second semiconductor region 7 inside chip 2 .
  • the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • FIG. in other words, the chip 2 in this form does not have a semiconductor substrate and has a single-layer structure consisting of an epitaxial layer.
  • Such a chip 2 is formed by completely removing the second semiconductor region 7 (semiconductor substrate) in the process of FIG. 12H.
  • FIG. 39 is a cross-sectional view showing a modification of the sealing insulator 71 applied to each embodiment having the upper insulating film 38.
  • FIG. FIG. 39 shows, as an example, a mode in which a sealing insulator 71 according to a modification is applied to a semiconductor device 1B.
  • the sealing insulator 71 according to the modification may be applied to any embodiment having the upper insulating film 38 among the second to fourteenth embodiments.
  • semiconductor device 1B may include a sealing insulator 71 covering the entire upper insulating film 38 .
  • the gate terminal electrode 50 not in contact with the upper insulating film 38 and the source terminal electrode 60 not in contact with the upper insulating film 38 are formed. .
  • the sealing insulator 71 may have a portion that directly covers the gate electrode 30 and the source electrode 32 .
  • the terminal electrode 126 that does not contact the upper insulating film 38 is formed.
  • the encapsulating insulator 71 may have a portion that directly covers the first polarity electrode 124 .
  • FIG. 40 is a plan view showing a package 201A on which semiconductor devices 1A to 1J according to the first to tenth embodiments are mounted.
  • Package 201A may also be referred to as a "semiconductor package” or “semiconductor module.”
  • package 201A includes a rectangular parallelepiped package main body 202 .
  • the package body 202 is made of mold resin, and contains a matrix resin (for example, epoxy resin), a plurality of fillers, and a plurality of flexible particles (flexifying agent), similar to the sealing insulator 71 .
  • the package body 202 has a first surface 203 on one side, a second surface 204 on the other side, and first to fourth side walls 205A to 205D connecting the first surface 203 and the second surface 204. As shown in FIG.
  • the first surface 203 and the second surface 204 are formed in a quadrangular shape when viewed from the normal direction Z thereof.
  • the first side wall 205A and the second side wall 205B extend in the first direction X and face the second direction Y orthogonal to the first direction X.
  • the third sidewall 205C and the fourth sidewall 205D extend in the second direction Y and face the first direction X. As shown in FIG.
  • the package 201A includes a metal plate 206 (conductor plate) arranged inside the package body 202 .
  • Metal plate 206 may be referred to as a "die pad.”
  • the metal plate 206 is formed in a square shape (specifically, a rectangular shape) in plan view.
  • the metal plate 206 includes a drawer plate portion 207 drawn out of the package body 202 from the first side wall 205A.
  • the drawer plate portion 207 has a circular through hole 208 .
  • Metal plate 206 may be exposed from second surface 204 .
  • the package 201A includes a plurality of (three in this embodiment) lead terminals 209 drawn out from the inside of the package body 202 to the outside.
  • a plurality of lead terminals 209 are arranged on the second side wall 205B side.
  • the plurality of lead terminals 209 are each formed in a strip shape extending in the direction perpendicular to the second side wall 205B (that is, the second direction Y).
  • the lead terminals 209 on both sides of the plurality of lead terminals 209 are spaced apart from the metal plate 206 , and the central lead terminal 209 is integrally formed with the metal plate 206 .
  • Arrangement of the lead terminal 209 connected to the metal plate 206 is arbitrary.
  • the package 201A includes a semiconductor device 210 arranged on a metal plate 206 within the package body 202 .
  • the semiconductor device 210 is composed of any one of the semiconductor devices 1A to 1J according to the first to tenth embodiments.
  • the semiconductor device 210 is arranged on the metal plate 206 with the drain electrode 77 facing the metal plate 206 and is electrically connected to the metal plate 206 .
  • the package 201A includes a conductive adhesive 211 interposed between the drain electrode 77 and the metal plate 206 to bond the semiconductor device 210 to the metal plate 206.
  • Conductive adhesive 211 may include solder or metal paste.
  • the solder may be lead-free solder.
  • the metal paste may contain at least one of Au, Ag and Cu.
  • the Ag paste may consist of Ag sintered paste.
  • the Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.
  • the package 201A includes at least one (a plurality of in this embodiment) conducting wires 212 (conductive connection members) electrically connected to the lead terminals 209 and the semiconductor device 210 within the package body 202 .
  • Conductor 212 consists of a metal wire (that is, a bonding wire) in this form.
  • Conductors 212 may include at least one of gold wire, copper wire and aluminum wire.
  • the conducting wire 212 may be made of a metal plate such as a metal clip instead of the metal wire.
  • At least one (one in this embodiment) conducting wire 212 is electrically connected to the gate terminal electrode 50 and the lead terminal 209 . At least one (four in this embodiment) conducting wire 212 is electrically connected to the source terminal electrode 60 and the lead terminal 209 .
  • source terminal electrode 60 includes sense terminal electrode 103 (see FIG. 25)
  • lead terminal 209 corresponding to sense terminal electrode 103 and conducting wire 212 connected to sense terminal electrode 103 and lead terminal 209 are further provided.
  • FIG. 41 is a plan view showing a package 201B on which semiconductor devices 1K to 1N according to 11th to 14th embodiments are mounted.
  • Package 201B may also be referred to as a "semiconductor package” or “semiconductor module.”
  • package 201B includes package body 202, metal plate 206, a plurality (two in this embodiment) of lead terminals 209, semiconductor device 213, conductive adhesive 211 and a plurality of conductors 212. As shown in FIG. Differences from the package 201A will be described below.
  • One lead terminal 209 of the plurality of lead terminals 209 is spaced apart from the metal plate 206 , and the other lead terminal 209 is integrally formed with the metal plate 206 .
  • the semiconductor device 213 is arranged on the metal plate 206 inside the package body 202 .
  • the semiconductor device 213 is composed of any one of the semiconductor devices 1K to 1N according to the 11th to 14th embodiments.
  • the semiconductor device 213 is placed on the metal plate 206 with the second polarity electrode 136 facing the metal plate 206 and electrically connected to the metal plate 206 .
  • a conductive adhesive 211 is interposed between the second polar electrode 136 and the metal plate 206 to bond the semiconductor device 213 to the metal plate 206 .
  • At least one (four in this embodiment) conducting wire 212 is electrically connected to the terminal electrode 126 and the lead terminal 209 .
  • FIG. 42 is a perspective view showing a package 201C on which the semiconductor devices 1A to 1J according to the first to tenth embodiments and the semiconductor devices 1K to 1N according to the eleventh to fourteenth embodiments are mounted.
  • 43 is an exploded perspective view of the package 201C shown in FIG. 42.
  • FIG. 44 is a cross-sectional view taken along line XLIV-XLIV shown in FIG. 42.
  • FIG. Package 201C may also be referred to as a "semiconductor package” or “semiconductor module.”
  • the package 201C includes a rectangular parallelepiped package main body 222.
  • the package body 222 is made of mold resin, and contains a matrix resin (for example, epoxy resin), a plurality of fillers, and a plurality of flexible particles (flexifying agent), similar to the sealing insulator 71 .
  • the package body 222 has a first surface 223 on one side, a second surface 224 on the other side, and first to fourth side walls 225A to 225D connecting the first surface 223 and the second surface 224. As shown in FIG.
  • the first surface 223 and the second surface 224 are formed in a quadrangular shape (rectangular shape in this embodiment) when viewed from the normal direction Z thereof.
  • the first side wall 225A and the second side wall 225B extend in the first direction X along the first surface 223 and face the second direction Y. As shown in FIG.
  • the first side wall 225A and the second side wall 225B form the long sides of the package body 222 .
  • the third sidewall 225C and the fourth sidewall 225D extend in the second direction Y and face the first direction X. As shown in FIG.
  • the third side wall 225C and the fourth side wall 225D form short sides of the package body 222 .
  • the package 201C includes first metal plates 226 arranged inside and outside the package body 222 .
  • the first metal plate 226 is arranged on the side of the first surface 223 of the package body 222 and includes first pad portions 227 and first lead terminals 228 .
  • the first pad portion 227 is formed in a rectangular shape extending in the first direction X inside the package body 222 and exposed from the first surface 223 .
  • the first lead terminal 228 is pulled out from the first pad portion 227 toward the first side wall 225A in a strip shape extending in the second direction Y, penetrates the first side wall 225A and is exposed from the package body 222 .
  • the first lead terminal 228 is arranged on the side of the fourth side wall 225D in plan view.
  • the first lead terminal 228 is spaced apart from the first surface 223 and the second surface 224 and exposed from the first side wall 225A.
  • the package 201C includes second metal plates 230 arranged inside and outside the package body 222 .
  • the second metal plate 230 is arranged on the second surface 224 side of the package body 222 with a gap in the normal direction Z from the first metal plate 226 , and includes a second pad section 231 and a second lead terminal 232 .
  • the second pad portion 231 is formed in a rectangular shape extending in the first direction X inside the package body 222 and is exposed from the second surface 224 .
  • the second lead terminal 232 is pulled out from the second pad portion 231 toward the first side wall 225A in a strip shape extending in the second direction Y, penetrates the first side wall 225A and is exposed from the package main body 222 .
  • the second lead terminal 232 is arranged on the side of the third side wall 225C in plan view.
  • the second lead terminal 232 is spaced apart from the first surface 223 and the second surface 224 and exposed from the first side wall 225A.
  • the second lead terminal 232 is pulled out from a thickness position different from that of the first lead terminal 228 with respect to the normal direction Z.
  • the second lead terminal 232 is spaced from the first lead terminal 228 toward the second surface 224 and does not face the first lead terminal 228 in the first direction X.
  • the second lead terminal 232 has a different length in the second direction Y than the first lead terminal 228 .
  • the package 201C includes a plurality of (five in this embodiment) third lead terminals 234 drawn out from the inside of the package body 222 to the outside.
  • the plurality of third lead terminals 234 are arranged in a thickness range between the first pad portion 227 and the second pad portion 231 in this embodiment.
  • the plurality of third lead terminals 234 are pulled out from inside the package main body 222 toward the second side wall 225B in a strip shape extending in the second direction Y, and are exposed from the package main body 222 through the second side wall 225B.
  • the arrangement of the plurality of third lead terminals 234 is arbitrary.
  • the plurality of third lead terminals 234 are arranged on the side of the third side wall 225C so as to be positioned on the same straight line as the second lead terminals 232 in plan view.
  • the plurality of third lead terminals 234 may have curved portions recessed toward the first surface 223 and/or the second surface 224 at portions located outside the package body 222 .
  • the package 201C includes a first semiconductor device 235 arranged within the package body 222 .
  • the first semiconductor device 235 is composed of any one of the semiconductor devices 1A to 1J according to the first to tenth embodiments.
  • the first semiconductor device 235 is arranged between the first pad portion 227 and the second pad portion 231 .
  • the first semiconductor device 235 is arranged on the side of the third side wall 225C in plan view.
  • the first semiconductor device 235 is arranged on the second metal plate 230 with the drain electrode 77 facing the second metal plate 230 (the second pad portion 231 ), and is electrically connected to the second metal plate 230 . It is
  • the package 201C includes a second semiconductor device 236 spaced from the first semiconductor device 235 and arranged within the package body 222 .
  • the second semiconductor device 236 is composed of any one of the semiconductor devices 1K to 1N according to the 11th to 14th embodiments.
  • the second semiconductor device 236 is arranged between the first pad portion 227 and the second pad portion 231 .
  • the second semiconductor device 236 is arranged on the side of the fourth side wall 225D in plan view.
  • the second semiconductor device 236 is arranged on the second metal plate 230 with the second polar electrode 136 facing the second metal plate 230 (the second pad portion 231). It is connected to the.
  • the package 201C includes a first conductor spacer 237 (first conductive connection member) and a second conductor spacer 238 (second conductive connection member) respectively arranged within the package body 222 .
  • the first conductor spacer 237 is interposed between the first semiconductor device 235 and the first pad portion 227 and electrically connected to the first semiconductor device 235 and the first pad portion 227 .
  • the second conductor spacer 238 is interposed between the second semiconductor device 236 and the first pad section 227 and electrically connected to the second semiconductor device 236 and the first pad section 227 .
  • the first conductor spacer 237 and the second conductor spacer 238 may each contain a metal plate (for example, a Cu-based metal plate).
  • the second conductor spacer 238 is separate from the first conductor spacer 237 in this embodiment, but may be formed integrally with the first conductor spacer 237 .
  • the package 201C includes first to sixth conductive adhesives 239A-239F.
  • the first through sixth conductive adhesives 239A-239F may include solder or metal paste.
  • the solder may be lead-free solder.
  • the metal paste may contain at least one of Au, Ag and Cu.
  • the Ag paste may consist of Ag sintered paste.
  • the Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.
  • the first conductive adhesive 239 A is interposed between the drain electrode 77 and the second pad portion 231 to connect the first semiconductor device 235 to the second pad portion 231 .
  • a second conductive adhesive 239 B is interposed between the second polarity electrode 136 and the second pad portion 231 to connect the second semiconductor device 236 to the second pad portion 231 .
  • a third conductive adhesive 239 ⁇ /b>C is interposed between the source terminal electrode 60 and the first conductor spacer 237 to connect the first conductor spacer 237 to the source terminal electrode 60 .
  • a fourth conductive adhesive 239 D is interposed between the terminal electrode 126 and the second conductor spacer 238 to connect the second conductor spacer 238 to the terminal electrode 126 .
  • the fifth conductive adhesive 239E is interposed between the first pad portion 227 and the first conductor spacer 237 to connect the first conductor spacer 237 to the first pad portion 227.
  • a sixth conductive adhesive 239 ⁇ /b>F is interposed between the first pad portion 227 and the second conductor spacer 238 to connect the second conductor spacer 238 to the first pad portion 227 .
  • the package 201C includes at least one (in this embodiment, a plurality of) electrically connected to the gate terminal electrode 50 of the first semiconductor device 235 and at least one (in this embodiment, a plurality of) third lead terminals 234 in the package body 222. ) conductors 240 (conductive connecting members). Conductor 240 consists of a metal wire (that is, a bonding wire) in this form.
  • the conductor 240 may include at least one of gold wire, copper wire and aluminum wire.
  • the conducting wire 240 may be made of a metal plate such as a metal clip instead of the metal wire.
  • the source terminal electrode 60 is connected to the first pad portion 227 via the first conductor spacer 237 .
  • the source terminal electrode 60 may be connected to the first pad portion 227 by the third conductive adhesive 239C without the first conductor spacer 237 interposed therebetween.
  • the terminal electrode 126 is connected to the first pad portion 227 via the second conductor spacer 238 .
  • the terminal electrode 126 may be connected to the first pad portion 227 by the fourth conductive adhesive 239D without the second conductor spacer 238 interposed.
  • the chip 2 having the mesa portion 11 was shown. However, a chip 2 that does not have the mesa portion 11 and has the flatly extending first main surface 3 may be employed. In this case the sidewall structure 26 is removed.
  • the form having the source wiring 37 was shown. However, a form without the source wiring 37 may be adopted.
  • the trench gate type gate structure 15 controlling the channel inside the chip 2 was shown. However, a planar gate type gate structure 15 that controls the channel from above the first main surface 3 may be employed.
  • the MISFET structure 12 and the SBD structure 120 were formed on different chips 2 .
  • the MISFET structure 12 and the SBD structure 120 may be formed in different regions of the first main surface 3 in the same chip 2 .
  • SBD structure 120 may be formed as a freewheeling diode of MISFET structure 12 .
  • the "first conductivity type” is “n-type” and the “second conductivity type” is “p-type”.
  • a form in which the "first conductivity type” is the “p-type” and the “second conductivity type” is the “n-type” may be adopted.
  • a specific configuration in this case can be obtained by replacing “n-type” with “p-type” and "p-type” with “n-type” in the above description and accompanying drawings.
  • the "n-type” second semiconductor region 7 was shown.
  • the second semiconductor region 7 may be "p-type".
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure 12.
  • the "source” of the MISFET structure 12 is replaced with the “emitter” of the IGBT structure and the "drain” of the MISFET structure 12 is replaced with the "collector" of the IGBT structure in the preceding description.
  • the "p-type" second semiconductor region 7 is formed on the surface layer of the second main surface 4 of the chip 2 (epitaxial layer) by ion implantation. It may have p-type impurities introduced.
  • the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D.
  • the first direction X and the second direction Y may be arbitrary directions as long as they maintain a relationship of crossing each other (specifically, orthogonally).
  • the first direction X may be a direction intersecting the first to fourth side surfaces 5A-5D
  • the second direction Y may be a direction intersecting the first to fourth side surfaces 5A-5D.
  • semiconductor device in the following items may be replaced with "wide bandgap semiconductor device”, “SiC semiconductor device”, “semiconductor switching device”, or “semiconductor rectifier” as necessary.
  • A4 Any one of A1 to A3, wherein the terminal electrodes (50, 60, 126) are thicker than the chip (2), and the sealing insulator (71) is thicker than the chip (2) 1.
  • the terminal electrodes (50, 60, 126) expose the corners of the main surface electrodes (30, 32, 124), and the sealing insulator (71) covers the main surface electrodes (30, 30, 124). 32, 124), the semiconductor device (1A-1N) according to any one of A1-A4.
  • the main-surface electrodes (30, 32, 124) have electrode surfaces (30a, 32a, 124a) and electrode sidewalls (30b, 32b, 124b), and the terminal electrodes (50, 60, 126) , the electrode surfaces (30a, 32a, 124a) and the electrode sidewalls (30b, 32b, 124b) are exposed, and the sealing insulator (71) covers the electrode surfaces (30a, 32a, 124a) and the electrode sidewalls.
  • the semiconductor device (1A-1N) according to any one of A1-A5, directly coating (30b, 32b, 124b).
  • the sealing insulator (71) is formed only on the main surface electrodes (30, 32, 124) and the terminal electrodes (50, 60, 126) on the main surface electrodes (30, 32, 124).
  • the semiconductor device (1A-1N) according to any one of A1-A6, having a portion in contact with the .
  • the terminal electrodes (50, 60, 126) have terminal surfaces (51, 61, 127), and the sealing insulator (71) is flush with the terminal surfaces (51, 61, 127).
  • the chip (2) has side surfaces (5A-5D), and the encapsulation insulator (71) has an insulating side wall (73) forming one flat surface with the side surfaces (5A-5D).
  • the semiconductor device (1A-1N) according to any one of A1-A8, comprising:
  • a chip (2) having a principal surface (3), principal surface electrodes (30, 32, 124) disposed on the principal surface (3), and an inorganic film (42) or an organic film (43) and an insulating film (38) that directly covers the main surface electrodes (30, 32, 124) so as to expose a portion of the main surface electrodes (30, 32, 124). , terminal electrodes (50, 60, 126) disposed on the main surface electrodes (30, 32, 124), and the terminal electrodes (50, 60, 126) so as to partially expose the terminal electrodes (50, 60, 126). and a sealing insulator (71) covering the periphery of (50, 60, 126) and having a portion directly covering the insulating film (38).
  • A14 Any one of A11 to A13, wherein the terminal electrodes (50, 60, 126) are thicker than the chip (2), and the sealing insulator (71) is thicker than the chip (2) 1.
  • the insulating film (38) directly covers at least part of the corners of the main surface electrodes (30, 32, 124), and the sealing insulator (71) is the insulating film (38).
  • the semiconductor device (1A to 1N) according to any one of A11 to A14, covering at least a part of the corners of the main surface electrodes (30, 32, 124) with the .
  • the main-surface electrodes (30, 32, 124) have electrode surfaces (30a, 32a, 124a) and electrode sidewalls (30b, 32b, 124b), and the insulating film (38) (30a, 32a, 124a) and the electrode side walls (30b, 32b, 124b) are directly covered, and the sealing insulator (71) sandwiches the insulating film (38) and the electrode surfaces (30a, 32a, 124a) and covering the electrode sidewalls (30b, 32b, 124b).
  • the terminal electrodes (50, 60, 126) have portions located on the main surface electrodes (30, 32, 124) and portions located on the insulating film (38). , A11 to A16.
  • the terminal electrodes (50, 60, 126) have terminal surfaces (51, 61, 127), and the sealing insulator (71) is flush with the terminal surfaces (51, 61, 127).
  • a semiconductor device (1A-1N) according to any one of A11-A17, having an insulating main surface (72) forming two planar surfaces.
  • the chip (2) has side surfaces (5A-5D), and the encapsulating insulator (71) has an insulating side wall (73) forming one flat surface with the side surfaces (5A-5D).
  • the semiconductor device (1A-1N) according to any one of A11-A18, comprising:
  • [B1] providing a wafer structure (80) comprising a wafer (81) having a major surface (82) and major surface electrodes (30, 32, 124) disposed on said major surface (82); forming terminal electrodes (50, 60, 126) on the main surface electrodes (30, 32, 124) so as to partially expose the main surface electrodes (30, 32, 124); A portion covering the periphery of the terminal electrode (50, 60, 126) so as to partially expose the terminal electrode (50, 60, 126) and directly covering the main surface electrode (30, 32, 124) and forming an encapsulation insulator (71) having a.
  • the process according to B1, wherein the step of forming the sealing insulator (71) includes a step of supplying a sealing agent (93) containing a resin onto the main surface electrodes (30, 32, 124).
  • the step of forming the terminal electrodes (50, 60, 126) includes forming the terminal electrodes (50, 60, 126) exposing at least part of corners of the principal surface electrodes (30, 32, 124).
  • the step of forming the sealing insulator (71) includes the sealing insulator (71) that directly covers at least part of the corners of the main surface electrodes (30, 32, 124).
  • the step of forming the terminal electrodes (50, 60, 126) comprises: The step of forming the terminal electrodes (50, 60, 126) to be exposed is included, and the step of forming the sealing insulator (71) is performed by the step of The semiconductor device (1A to 1N) manufacturing method.
  • the insulating main surface (72) forming one flat surface with the terminal surfaces (51, 61, 127) of the terminal electrodes (50, 60, 126)
  • [C1] preparing a wafer structure (80) comprising a wafer (81) having a major surface (82) and major surface electrodes (30, 32, 124) disposed on said major surface (82); and a single-layer structure composed of an inorganic film (42) or an organic film (43), and the main surface electrodes (30, 32, 124) are partially exposed.
  • 124) forming terminal electrodes (50, 60, 126) on the main surface electrodes (30, 32, 124); forming terminal electrodes (50, 60, 126);
  • the step of forming the insulating film (38) includes the step of forming the insulating film (38) having a single-layer structure made of an oxide film, a nitride film, an oxynitride film, or a photosensitive resin film.
  • the step of forming the insulating film (38) includes the step of forming the insulating film (38) directly covering at least part of the corners of the main surface electrodes (30, 32, 124),
  • the step of forming a sealing insulator (71) includes forming the sealing insulator (71) covering at least a portion of the corners of the main surface electrodes (30, 32, 124) with the insulating film (38) interposed therebetween. ), a method for manufacturing a semiconductor device (1A to 1N) according to any one of C1 to C5.
  • the step of forming the sealing insulator (71) includes the step of forming an insulating film (38), and the step of forming the sealing insulator (71) includes the step of forming the electrode surface ( The semiconductor device (1A ⁇ 1N) manufacturing method.
  • the step of forming the terminal electrodes (50, 60, 126) has a portion located on the main surface electrodes (30, 32, 124) and a portion located on the insulating film (38).
  • the step of forming the sealing insulator (71) directly covers the insulating film (38) and the terminal electrodes (50, 60, 126) on the main surface electrodes (30, 32, 124).
  • the insulating main surface (72) forming one flat surface with the terminal surfaces (51, 61, 127) of the terminal electrodes (50, 60, 126)
  • [C11] C1 to C10 including thinning the wafer (81) to a thickness less than the thickness of the encapsulation insulator (71) after the step of forming the encapsulation insulator (71); A method for manufacturing a semiconductor device (1A to 1N) according to any one of

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur (1A) qui comprend : une puce (2) qui présente une surface principale (3) ; des électrodes de surface principale (30, 32) disposées sur la surface principale ; des électrodes terminales (50, 60) disposées sur les électrodes de surface principale de manière à laisser apparente une partie des électrodes de surface principale ; et un corps isolant de scellement (71) qui recouvre la périphérie des électrodes terminales de façon à laisser apparente une partie des électrodes terminales et présente une section qui recouvre directement les électrodes de surface principale.
PCT/JP2022/040496 2021-11-05 2022-10-28 Dispositif à semi-conducteur WO2023080084A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013239607A (ja) * 2012-05-16 2013-11-28 Mitsubishi Electric Corp 半導体装置
WO2020100947A1 (fr) * 2018-11-15 2020-05-22 ローム株式会社 Dispositif à semi-conducteur
WO2022196158A1 (fr) * 2021-03-18 2022-09-22 ローム株式会社 Dispositif semi-conducteur à large bande interdite

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013239607A (ja) * 2012-05-16 2013-11-28 Mitsubishi Electric Corp 半導体装置
WO2020100947A1 (fr) * 2018-11-15 2020-05-22 ローム株式会社 Dispositif à semi-conducteur
WO2022196158A1 (fr) * 2021-03-18 2022-09-22 ローム株式会社 Dispositif semi-conducteur à large bande interdite

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