WO2023075773A1

WO2023075773A1 - Power tracking at a radio frequency chip based on a two-dimensional digital pre-distortion circuit

Info

Publication number: WO2023075773A1
Application number: PCT/US2021/057001
Authority: WO
Inventors: Jifeng Geng
Original assignee: Zeku, Inc.
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2023-05-04

Abstract

According to one aspect of the present disclosure, a digital pre-distortion (DPD) engine of a radio frequency (RF) chip is disclosed. The DPD engine may include a control function circuit configured to estimate a controllable parameter associated with a PA based on a set of samples. The DPD engine may include a memoryless DPD circuit. The memoryless DPD circuit may include a first multiplier configured to apply a first scaling function to the set of samples to generate a first set of scaled samples. The memoryless DPD engine may include a DPD circuit configured to generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The first memoryless DPD circuit may include a second multiplier configured to apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples that are output.

Description

POWER TRACKING AT A RADIO FREQUENCY CHIP BASED ON A TWO-DIMENSIONAL DIGITAL PRE-DISTORTION CIRCUIT BACKGROUND [0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication. [0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modern terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various mechanisms for performing power tracking of a power amplifier (PA) at a radio frequency (RF) chip. SUMMARY [0003] According to one aspect of the present disclosure, a digital pre-distortion (DPD) engine of an RF chip is disclosed. The DPD engine may include a control function circuit configured to estimate a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The DPD engine may include a first memoryless DPD circuit. The first memoryless DPD circuit may include a first multiplier configured to apply a first scaling function to the set of samples to generate a first set of scaled samples. The first memoryless DPD engine may include a first DPD circuit configured to generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The first memoryless DPD engine may include a second multiplier configured to apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0004] According to another aspect of the present disclosure, an RF chip is provided. The RF chip may include an envelope tracking (ET) path and an in-phase/in-quadrature (IQ) path. The IQ path may include a DPD engine. The DPD engine may include a control function circuit configured to estimate a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The DPD engine may include a first memoryless DPD circuit. The first memoryless DPD circuit may include a first multiplier configured to apply a first scaling function to the set of samples to generate a first set of scaled samples. The first memoryless DPD engine may include a first DPD circuit configured to generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The first memoryless DPD engine may include a second multiplier configured to apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0005] According to yet another aspect of the present disclosure, a method is provided. The method may include estimating, by a control function circuit, a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The method may include applying, by a first multiplier of a first memoryless DPD circuit, a first scaling function to the set of samples to generate a first set of scaled samples. The method may include generating, by a first DPD circuit of the first memoryless DPD circuit, a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The method may include applying, by a second multiplier of the first memoryless DPD circuit, a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0008] FIG.1A illustrates a conventional RF chip that implements envelope tracking (ET). [0009] FIG.1B illustrates a conventional RF chip that implements fast ET. [0010] FIG.1C is a graphical representation of a control voltage (Vcc) associated with fast ET, slow ET, and multi-level ET. [0011] FIG. 1D illustrates a conventional RF chip that implements constant-level power tracking. [0012] FIG.1E illustrates a graphical representation of constant-level power tracking. [0013] FIG. 2 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure. [0014] FIG.3 illustrates an exemplary wireless network, according to some embodiments of the present disclosure. [0015] FIG.4 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure. [0016] FIG.5A illustrates an exemplary RF chip that implements slow ET using a 2D DPD engine, according to some embodiments of the present disclosure. [0017] FIG. 5B illustrates an exemplary RF chip that implements multi-level ET using a 2D DPD engine, according to some embodiments of the present disclosure. [0018] FIG.5C illustrates a detailed block diagram of a first exemplary 2D DPD engine of the RF chip of FIG.4, according to some embodiments of the present disclosure. [0019] FIG.5D illustrates a graphical representation of DPD input and DPD output scaling curves, according to some embodiments of the present disclosure. [0020] FIG.5E illustrates a detailed block diagram of a second exemplary 2D DPD engine of the RF chip of FIG.4, according to some embodiments of the present disclosure. [0021] FIG.6 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure. [0022] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION [0023] Although some configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. [0024] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0025] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0026] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the application and design constraints imposed on the overall system. [0027] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as global system for mobile communications (GSM). An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. [0028] As used herein, the term “controllable memory” does not refer to a type of physical storage device; instead, controllable memory is a term used in reference to a type of signal memory that is intentionally introduced at the RF to slow down the tracking signal associated with the PA. For example, controllable memory may refer to inter-sample dependency (e.g., inter-in-phase/in- quadrature (inter-IQ) sample dependency) introduced in a known fashion, e.g., by a low pass filter. The controllable memory may be associated with the Vcc, for example. Controllable memory may cause performance degradation at a wireless device by causing the PA to operate at least than peak efficiency. Using the exemplary 2D DPD engine described herein, controllable memory may be canceled or reduced to improve system performance. [0029] As used herein, the term “uncontrollable memory” does not refer to a type of physical storage device. On the other hand, uncontrollable memory refers to a signal memory that is associated with PA matching. For example, uncontrollable memory refers to inter-sample dependency introduced by the physical system, such as by the PA). Uncontrollable memory may occur due to poor PA design, poor post-PA matching, analog low-pass filter, etc. Using the exemplary 2D DPD engine described herein, uncontrollable memory may be decoupled from the controllable memory in both calibration and compensation using the techniques described herein [0030] In the marketplace today, there are a wide variety of electronic devices available for a wide variety of purposes. Such devices include cellular telephones, tablet computers, laptop computers, personal computers, internet-of-things (IoT) devices, smart vehicles, smart devices, televisions, BluetoothTM enabled devices, printers, and cameras, just to name a few. It is often desirable for one electronic device to communicate with one or more other electronic devices. To facilitate these communications, various wireless technologies have become popular. Regardless of the particular type of wireless communication technology, these technologies are all similar in the sense that they use radio waves, often referred to as radiofrequency (RF) signals, to communicate information from one device to another. [0031] Information to be transmitted is typically modulated onto the RF signal prior to transmission to a receiving device. In other words, the information is typically embedded in an envelope of a carrier signal that has a frequency in the RF range. The envelope is typically referred to as the baseband signal or IQ signal, and there are various techniques for using IQ signals to modulate the carrier signal. The receiving device demodulates a received signal by removing the carrier signal to recover the information embedded in the envelope. ET describes an approach to RF amplifier design in which the power supply voltage applied to the RF chip’s PA is continuously adjusted to ensure that the PA is operating at peak power efficiency at each instant during a transmission. In another known approach, constant-level power tracking may be implemented. Various examples of conventional RF chips that perform ET and/or constant-level power tracking are depicted in FIGs. 1A, 1B, and 1D. A graphical representation 135 of fast ET, slow ET, and multi-level ET is depicted in FIG.1C; and a graphical representation 155 of constant-level power tracking is depicted in FIG.1E. [0032] Referring to FIG. 1A, a conventional RF chip 100 (referred to hereinafter as “RF chip 100”) that performs ET is shown. As depicted in FIG.1A, RF chip 100 includes an ET path 101 and an IQ path 103. ET path 101 includes an ET detrough 102, an envelope (ENV) digital-to- analog converter (DAC) 104, and an ENV tracker 106. IQ path 103 includes a digital pre-distortion (DPD) circuit 108, an IQ DAC 110, an analog baseline filter 112, and a PA 114 coupled to antenna 118. [0033] As shown in FIG.1A, an IQ signal generated by a baseband chip (not shown) may be input into ET path 101 and IQ path 103. ET tracking along ET path 101 may include identifying, at ET detrough 102, an envelope shaping detrough function from a shaping table, digital-to-analog conversion by ENV DAC 104, and amplification of the output of the ENV DAC 104 by ENV tracker 106. The amplification by ENV tracker 106 may be used to modulate the supply voltage applied to PA 114 to provide peak power efficiency. ENV tracker 106 may include a continuous ENV tracker (as shown in FIGs.1B and 1C) or a multi-level ENV tracker (as shown in FIG.1D). [0034] Since the IQ signal is split into ET path 101 and IQ path 103, and then combined at PA 114, the delay matching between these two paths is critical to achieve a high level of performance. In other words, PA 114 must align the modulated supply voltage and the RF input signal in the time domain with a high degree of accuracy. Even small time deviations in the nanosecond (ns) range may substantially degrade the quality of the RF output signal. This is especially detrimental to wideband RF signals, which are particularly sensitive to this type of deviation. [0035] ET path 101 and IQ path 103 may have different delays for various reasons. For example, the digital circuits of these two paths may not be the same. In other words, ET path 101 and IQ path 103 may have a different number of processing circuits. Moreover, ENV DAC 104 and IQ DAC 110 may have different delays. Still further, analog baseline filter 112 of IQ path 103 is absent from ET path 101, thereby introducing a delay in IQ path 103 that is absent from ET path 101. Thus, to avoid a misalignment of the modulated supply voltage and the RF input signal at PA 114, ET path 101 and IQ path 103 should be calibrated. [0036] Conventional techniques for calibrating ET path 101 and IQ path 103 include, e.g., slow ET delay calibration, fast ET delay calibration, and/or multi-level ET delay calibration. Using slow ET delay calibration, the delays between ET path 101 and IQ path 103 are swept, and performance metric(s) such as power added efficiency (PAE), error vector magnitude (EVM), and/or adjacent channel leakage ratio (ACLR) measured. Then, an optimal delay is found when the best performance is achieved based on an evaluation of the performance metric(s). However, identifying a delay between ET path 101 based on a sweep and performance metric evaluation is a time-consuming process, which degrades system performance. Conventional examples of fast ET, slow ET, and multi-level ET are described below in connection with FIGs. 1B, 1C, and 1D, respectively. [0037] For example, FIG.1B illustrates a conventional RF chip 105 (referred to hereinafter as “RF chip 105”) that implements fast ET delay calibration. As shown in FIG.1B, RF chip 105 may include one or more circuits described above in connection with FIG.1A. Additionally and/or alternatively, RF chip 105 may include a crest-factor reduction (CFR) circuit 116 configured to reduce the peak-to-average power-ratio (PAPR) associated with the input IQ samples. Moreover, a pre-DPD gain 120 may be located between CFR circuit 116 and DPD circuit 108; and a pre-DCA gain 130 may be located between DPD circuit 108 and IQ DAC 110. Here, ENV tracker 106 may include a continuous ENV tracker, which supplies the PA bias voltage (Vcc) to PA 114. The Vcc may track the signal amplitude instantaneously, which is why the ET technique performed by RF chip 105 is referred to as “fast ET.” For each incoming set of IQ samples, the envelope may be extracted by continuous ENV tracker 106, which generates a tracking signal, so there is a point- by-point correspondence. Here, DPD circuit 108 may be used to cancel any non-linearity in the signals of RF chip 105. The Vcc level at PA 114 is usually controlled by ENV DAC 104. The Vcc is typically modulated by continuous ENV tracker 106. [0038] FIG.1D illustrates a conventional RF chip 145 (referred to hereinafter as “RF chip 145”) that implements continuous-level power tracking. As shown in FIG.1D, RF chip 145 may include one or more circuits described above in connection with FIG.1A. However, RF chip 145 may include a Vcc-level controller 122 and a switching-mode power supply (SMPS) 124. Here, PA bias voltage Vcc is supplied by SMPS 124. SMPS 124 provides a constant Vcc voltage level to PA 114 for up to an entire slot, which may be 1 millisecond (ms) in duration. The Vcc level may be controlled by Vcc-level controller 122 via RF front-end (RFFE) commands, for example. The Vcc level at RF chip 145 may remain constant within the symbol. In some examples, the Vcc level may be changed from symbol-to-symbol to track the power level, which is referred to as “average power tracking” (APT). If Vcc is further lowered to improve PA efficiency, and DPD circuit 108 is used to compensate for the nonlinearity of PA 114, this type of power tracking is referred to as “enhanced power tracking” (EPT). [0039] Conventional RF chips that implement slow ET and multi-level ET suffer from various problems. For example, Vcc can introduce “controllable memory” in slow ET or multi- level ET. Other parameters, such as PA internal bias circuit, matching circuit, thermal, etc., may introduce uncontrollable memory at PA 114. To compensate for controllable and/or uncontrollable memory introduced in such RF chips, conventional approaches have employed generic memory kernels to model and compensate memories in PA. However, these generic approaches cannot distinguish between controllable memory and uncontrollable memory. Thus, the performance of conventional RF chips that implement slow ET and/or multi-level ET is negatively impacted by controllable memory and uncontrollable memory introduced at the PA. [0040] Thus, there exists an unmet need for a technique that compensates for controllable memory and uncontrollable memory introduced at the PA. [0041] To overcome these and other challenges, the present disclosure provides an exemplary 2D DPD engine that models and compensates for controllable memory and uncontrollable memory, separately. For example, the 2D DPD engine of the present disclosure assumes that controllable memory is introduced to the RF chip in a controllable or known fashion via function where x0

is an IQ sample at etc. Once

is known, the rest of the system becomes memoryless. The memoryless

system’s dependency on controllable parameter can be learned by characterization or calibration.

In its simplest form, the dependency on can be linear scaling functions on input/output by

The separation of controllable and uncontrollable memories allows more effective memory compensation within the RF chip. Additional details of the 2D DPD engine are provided below in connection with FIGs.2-6. [0042] FIG.2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation. [0043] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation. [0044] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., S1 interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless. [0045] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation. [0046] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0047] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack. [0048] Each element in FIG.2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG.3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG.2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible. [0049] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well. [0050] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0051] As shown in FIG.3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro- electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read- only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0052] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0053] Referring back to FIG. 2, in some embodiments, user equipment 202 may be implemented with an RF chip that includes the exemplary 2D DPD engine mentioned above. The 2D DPD engine of user equipment 202 may model and compensate for controllable memory introduced by the Vcc at the PA. For example, the controllable memory may be introduced to the RF chip in a controllable or known fashion via function where v0

is the supply voltage at the PA at t=0, x0 is an IQ sample at t=0, etc. Once is

known, the rest of the system becomes memoryless. The memoryless system’s dependency on controllable parameter ^^^^ can be learned by characterization or calibration. In its simplest form, the dependency on ^^^^0 can be linear scaling functions on input/output by

The separation of controllable and uncontrollable memories allows more effective memory compensation within the RF chip. [0054] For example, the memoryless DPDs used by the 2D DPD engine are learned at different Vcc levels,

, and input into a memoryless DPD circuit as a LUT. For incoming

IQ samples x, a control function unit of the 2D DPD engine may estimate a controllable parameter, which is the instantaneous supply voltage v0 at the PA at instant t=0. Then, v0 may be fed into a memoryless DPD circuit, which cancels the controllable memory based on a complex LUT that maintains information associated with one or more of the functions f’ mentioned above. On the input side of the memoryless DPD circuit, a first multiplier may apply a first scaling function α to the incoming IQ samples. Then, after the memoryless DPD circuit cancels the controllable memory based on the complex scaled samples received from the first multiplier and the controllable parameter received from the control function circuit, a second multiplier may apply a second scaling function β to achieve a DPD output that cancels the controllable memory. In some embodiments, the 2D DPD engine of user equipment 202 may include multiple memoryless DPD circuits each including a set of scaling multipliers and complex LUTs. Depending on the instantaneous v0, the closest memoryless DPD circuit may be used for linear scaling to minimize the scaling errors. For example, DPD output

may be output depending on whether

is closer to

Additional details of the 2D DPD engine of user equipment 202 are provided below in connection with FIGs.4, 5A, 5B, 5C, 5D, 5E, and 6. [0055] FIG. 4 illustrates a block diagram of an apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. Apparatus 400 may be implemented as user equipment 202 of wireless network 200 in FIG.2. As shown in FIG.4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by processor 302 and memory 304, and RF chip 404 is implemented by processor 302, memory 304, and transceiver 306, as described above with respect to FIG.3. Besides the on-chip memory 418 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG.4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC, as described above. [0056] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 414 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface 414. RF chip 404, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404. [0057] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402. [0058] As shown in FIG. 4, RF chip 404 may include a 2D DPD engine 420. 2D DPD engine 420 may model and compensate for controllable memory introduced by the Vcc at the PA. For example, the controllable memory may be introduced in RF chip 404 in a controllable or known fashion via function

where v0 is the supply voltage at the PA at t=0, x0 is an IQ sample at is known, the rest of the system

becomes memoryless. The memoryless system’s dependency on controllable parameter can be

learned by characterization or calibration. In its simplest form, the dependency on

can be linear scaling functions on input/output by

[0059] The separation of controllable and uncontrollable memories allows more effective memory compensation within the RF chip. For example, the memoryless DPDs are learned at different Vcc levels, e.g.,

, and input into a memoryless DPD circuit as a LUT. For incoming

IQ samples x, a control function unit of 2D DPD engine 420 may estimate a controllable parameter, which is the instantaneous supply voltage v0 at the PA at instant t=0. Then, v0 may be fed into a memoryless DPD circuit of 2D DPD engine 420, which cancels the controllable memory based on a complex LUT. On the input side of the memoryless DPD circuit, a first multiplier may apply a first scaling function α to the incoming IQ samples. Then, after the memoryless DPD circuit cancels the controllable memory based on the complex scaled samples and the controllable parameter received from the control function circuit, a second multiplier may apply a second scaling function β to achieve a DPD output that cancels the controllable memory. [0060] In some embodiments, 2D DPD engine 420 may include multiple memoryless DPD circuits each including a set of scaling multipliers and complex LUTs, as shown in FIG. 3C. Depending on the instantaneous v0, the closest memoryless DPD circuit may be used for linear scaling to minimize the scaling errors. For example, DPD output

may be output depending on whether is closer to Additional

details of 2D DPD engine 420 are provided below in connection with FIGs.5A, 5B, 5C, and 6. [0061] FIG.5A illustrates an exemplary RF chip 500 that implements slow ET and includes 2D DPD engine 420, according to some embodiments of the disclosure. RF chip 500 may include an ET path and an IQ path. The ET path may include, among others, an ENV DAC 504, a continuous ENV tracker 506a, an optional multi-level generator 526, and a slow ENV generator 528. In some embodiments, optional multi-level generator 526 may be included in exemplary RF chip 500, while in other embodiments multi-level generator 526 may not be present. The IQ path may include, among others, CFR 516, pre-DPD gain 520, 2D DPD engine 420, pre-DAC gain 530, IQ DAC 510, and a PA 514 coupled to antenna 518. Moreover, RF chip 500 may include an RF transceiver (RF-TRX) and one or more digital front-end circuits (DFEC). [0062] Referring to FIG. 5A, the Vcc may be supplied by continuous ENV tracker 506a. The Vcc can be generated from a multi-level generator 526, or other ways. Here, the Vcc follows signal amplitude slowly, and hence, is referred to as “slow ET.” This introduces “controllable memory.” Continuous ENV tracker 506a may be a dedicated chip may source up to or greater than amps of current, instantaneously. Moreover, continuous ENV tracker 506a tracks an underlying waveform that changes very fast (e.g., the 5G changes rapidly). To overcome this issue, RF chip 500 may slow down the tracking. However, this introduces “memory” to the overall system in the sense that there is no longer a point-by-point tracking on the underlying waveform; instead, continuous ENV tracker 506a relies on knowledge or an estimation of the previous tracking of the waveform. To compensate for this memory, 2D DPD engine 420 may cancel it using the techniques described below in connection with FIGs.5C-5E. [0063] FIG.5B illustrates an exemplary RF chip 525 that implements multi-level ET and includes 2D DPD engine 420, according to some embodiments of the disclosure. RF chip 525 may include an ET path and an IQ path. The ET path may include, among others, a multi-level ENV tracker 506b, a multi-level generator 526, and a slow ENV generator 528. The IQ path may include, among others, CFR 516, pre-DPD gain 520, 2D DPD engine 420, pre-DAC gain 530, IQ DAC 510, and a PA 514 coupled to antenna 518. [0064] In FIG. 5B, the PA bias control does not use a continuous signal; instead, it uses discrete multi-level signals. The PA bias voltage Vcc may be selected from one of several predetermined constant power levels, which are generated by multi-level ENV tracker 506b. Multi-level generator 526 may select which level should be used for Vcc based on signal amplitude. The multi-level Vcc should be smoothed (e.g., by low pass filtered) before being applied to PA 514. The smoothed Vcc tracks signal amplitude slowly. This introduces “controllable memory.” Multi-level ENV tracker 506b may be a dedicated chip that sources up to or greater than amps of current, instantaneously. Moreover, multi-level ENV tracker 506b tracks the underlying waveform that changes very fast (e.g., the 5G changes rapidly). To overcome this issue, RF chip 525 may slow down the tracking. However, this introduces “memory” to the overall system in the sense that there is no longer a point-by-point tracking on the underlying waveform; instead, multi-level ENV tracker 506b relies on knowledge or an estimation of the previous tracking of the waveform. To compensate for this memory, 2D DPD engine 420 may cancel it using the techniques described below in connection with FIGs.5C-5E. [0065] FIG. 5C illustrates a detailed block diagram of a memoryless DPD circuit 550 included in 2D DPD engine 420 of FIGs.4, 5A, and 5B, according to some embodiments of the present disclosure. FIG.5B illustrates a graphical representation 555 of an DPD input and DPD output, according to some embodiments of the present disclosure. FIG. 5E illustrates a detailed block diagram 575 of 2D DPD engine 420 shown in FIG.4, according to some embodiments of the present disclosure. FIGs.5A-5C will be described together. [0066] Referring to FIG. 5A, memoryless DPD circuit 550 may include a first multiplier 552, a DPD circuit 554, and a second multiplier 556. First multiplier 552 may apply a first scaling function to an incoming complex IQ sample x. Scaling factor α may be a real number, and

hence, the output of first multiplier 552 may include a complex scaled IQ sample. DPD circuit 554 implemented as a complex LUT (x0LUT0(x0,v0)), where x0 is the current IQ sample and v0 is the PA control voltage where the complex LUT is calibrated. For example, although not shown in FIG.5A, DPD circuit 554 may receive a controllable parameter from a

control function circuit, as shown in FIG.5E. DPD circuit 554 may use the controllable parameter and/or the complex scaled IQ sample received from first multiplier 552 to determine which function f’ to use to cancel the controllable memory. Thus, DPD circuit 554 may output a pre- distorted complex IQ sample Second multiplier may apply a second scaling function

In other words, DPD output y0

at can be calculated from calibrated DPD output at

by linearly scaling the input and output using α and β, respectively. The linear scaling is illustrated in the graphical representation 555 depicted in FIG.5B. [0067] Referring to FIG.5D, the inverse of a PA’s input and output is shown. Because the PA is an analog amplifier, it’s input and output can be scaled based on various Vcc. Thus, by scaling one curve, the other curve can be identified based on the Vcc applied to the PA. Based on this knowledge, the 2D DPD engine 420 can be implemented using first multiplier 552 and second multiplier 556. Both can be pre-computed and implemented as separate LUTs in

first multiplier 552 and second multiplier 556, respectively. [0068] Referring to FIG.5E, a detailed illustration of 2D DPD engine 420 is depicted. As shown, 2D DPD engine 420 may include a first memoryless DPD circuit (e.g., first multiplier 552a, first DPD circuit 554a, and second multiplier 556a) and a second memoryless DPD circuit (e.g., third multiplier 552b, second DPD circuit 554b, and fourth multiplier 556b). The memoryless DPDs may be associated with different Vcc levels, e.g.,

etc. The first and/or second memoryless DPD

circuits in FIG. 5E may be configured to perform the operations described above in connection with FIG.5A. [0069] Still referring to FIG.5E, 2D DPD engine 420 may include a control function circuit 558 and a selection unit 560. Control function circuit 558 may estimate a controllable parameter v based on an input sample x. The controllable parameter v0 may be input to first DPD circuit 554a and second DPD circuit 554b. [0070] Depending on the instantaneous

the closest memoryless DPD circuit may be used for linear scaling to minimize the scaling errors. For example, selection unit 560 may select DPD output depending on whether

is closer to [0071] Thus, using 2D DPD engine 420, effective DPD compensation of controllable memory may be achieved using a controllable parameter

and control parameter scaling of memoryless DPD LUTs by and without memory. By treating the

controllable memory and uncontrollable memory separately, a highly accurate model of the controllable memory may be used to cancel out the controllable memory introduced at the RF chip by Vcc. [0072] FIG. 6 illustrates a flowchart of an exemplary method 600 of wireless communication, according to embodiments of the disclosure. Exemplary method 600 may be performed by an apparatus for wireless communication, e.g., such as user equipment 202, apparatus 400, RF chip 404, 2D DPD engine 420, first multiplier 552a, first DPD circuit 554a, second multiplier 556a, third multiplier 552b, second DPD circuit 554b, fourth multiplier 556b, control function circuit 558, selection unit 560, and/or node 300. Method 600 may include steps 602-608 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG.6. [0073] Referring to FIG.6, at 602, the apparatus may estimate, by a control function circuit, a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. For example, referring to FIG.5E, control function circuit 558 may estimate a controllable parameter based on an IQ sample x0.

[0074] At 604, the apparatus may apply, by a first multiplier of a first memoryless DPD circuit, a first scaling function to the set of samples to generate a first set of scaled samples. For example, referring to FIG. 5E, first multiplier 552 may apply a first scaling function to an

incoming complex IQ sample x0. Scaling factor α may be a real number, and hence, the output of first multiplier 552 may include a complex scaled IQ sample. [0075] At 606, the apparatus may generate, by a first DPD circuit of the first memoryless DPD circuit, a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. For example, referring to FIG. 5E, DPD circuit 554 implemented as a complex LUT (x0LUT0(x0,v0)), where x0 is the current IQ sample and v0 is the PA control voltage where the complex LUT is calibrated. For example, DPD circuit 554 may receive a controllable parameter from a control function circuit 558. DPD circuit 554a may

use the controllable parameter and/or the complex scaled IQ sample received from first multiplier 552a to determine which function f’ to use to cancel the controllable memory. Thus, DPD circuit 554a may output a pre-distorted complex IQ sample

[0076] At 608, the apparatus may apply, by a second multiplier of the first memoryless DPD circuit, a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. For example, referring to FIG. 5E, second multiplier may apply a second scaling function to to generate a DPD output In other words,

DPD output y0 at ^^^^0 can be calculated from calibrated DPD output at

by linearly scale the input and output using α and β, respectively. [0077] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0078] According to one aspect of the present disclosure, a DPD engine of an RF chip is disclosed. The DPD engine may include a control function circuit configured to estimate a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The DPD engine may include a first memoryless DPD circuit. The first memoryless DPD circuit may include a first multiplier configured to apply a first scaling function to the set of samples to generate a first set of scaled samples. The first memoryless DPD circuit may include a first DPD circuit configured to generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The first memoryless DPD circuit may include a second multiplier configured to apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0079] In some embodiments, the controllable parameter may be associated with a control voltage applied at the PA. [0080] In some embodiments, the first multiplier may include a first scaling function LUT. [0081] In some embodiments, the second multiplier may include a second scaling function LUT. [0082] In some embodiments, the first DPD circuit may include a pre-distortion LUT. [0083] In some embodiments, the DPD engine may include a second memoryless DPD circuit. The second memoryless DPD circuit may include a third multiplier configured to apply a third scaling function to the set of samples to generate a third set of scaled samples. In some embodiments, the second memoryless DPD circuit may include a second DPD circuit configured to generate a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples. In some embodiments, the second memoryless DPD circuit may include a fourth multiplier configured to apply a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples. The fourth set of scaled samples may be associated with a second DPD output. [0084] In some embodiments, the DPD engine may further include a selection unit configured to in response to the first DPD output being nearest to the controllable parameter, output the first DPD output. In some embodiments, the DPD engine may further include a selection unit configured to in response to the second DPD output being nearest to the controllable parameter, output the second DPD output. [0085] In some embodiments, the set of samples may include a set of IQ samples. [0086] According to another aspect of the present disclosure, an RF chip is provided. The RF chip may include an ET path and an IQ path. The IQ path may include a DPD engine. The DPD engine may include a control function circuit configured to estimate a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The DPD engine may include a first memoryless DPD circuit. The first memoryless DPD circuit may include a first multiplier configured to apply a first scaling function to the set of samples to generate a first set of scaled samples. The first memoryless DPD circuit may include a first DPD circuit configured to generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The first memoryless DPD circuit may include a second multiplier configured to apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0087] In some embodiments, the controllable parameter may be associated with a control voltage applied at the PA. [0088] In some embodiments, the first multiplier may include a first scaling function LUT. [0089] In some embodiments, the second multiplier may include a second scaling function LUT. [0090] In some embodiments, the first DPD circuit may include a pre-distortion LUT. [0091] In some embodiments, the DPD engine may include a second memoryless DPD circuit. The second memoryless DPD circuit may include a third multiplier configured to apply a third scaling function to the set of samples to generate a third set of scaled samples. In some embodiments, the second memoryless DPD circuit may include a second DPD circuit configured to generate a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples. In some embodiments, the second memoryless DPD circuit may include a fourth multiplier configured to apply a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples. The fourth set of scaled samples may be associated with a second DPD output. [0092] In some embodiments, the DPD engine may further include a selection unit configured to in response to the first DPD output being nearest to the controllable parameter, output the first DPD output. In some embodiments, the DPD engine may further include a selection unit configured to in response to the second DPD output being nearest to the controllable parameter, output the second DPD output. [0093] According to yet another aspect of the present disclosure, a method of an RF chip is provided. The method may include estimating, by a control function circuit, a controllable parameter associated with a PA based on a set of samples associated with a transmit signal. The method may include applying, by a first multiplier of a first memoryless DPD circuit, a first scaling function to the set of samples to generate a first set of scaled samples. The method may include generating, by a first DPD circuit of the first memoryless DPD circuit, a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples. The method may include applying, by a second multiplier of the first memoryless DPD circuit, a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples. The second set of scaled samples may be associated with a first DPD output. [0094] In some embodiments, the controllable parameter may be associated with a control voltage applied to the PA. [0095] In some embodiments, the first multiplier includes a first scaling function LUT. In some embodiments, the second multiplier includes a second scaling function LUT. In some embodiments, the first DPD circuit includes a pre-distortion LUT. [0096] In some embodiments, the method may include applying, by a third multiplier of a second memoryless DPD circuit, a third scaling function to the set of samples to generate a third set of scaled samples. In some embodiments, the method may include generating, by a second DPD circuit of the second memoryless DPD circuit, a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples. In some embodiments, the method may include applying, by a fourth multiplier of the second memoryless DPD circuit, a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples. In some embodiments, the fourth set of scaled samples may be associated with a second DPD output. [0097] The foregoing description of the embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0098] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0099] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0100] Various functional blocks, modules, and steps are disclosed above. The arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. [0101] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS: 1. A digital pre-distortion (DPD) engine of a radio frequency (RF) chip, comprising: a control function circuit configured to: estimate a controllable parameter associated with a power amplifier (PA) based on a set of samples associated with a transmit signal; a first memoryless DPD circuit, comprising: a first multiplier configured to: apply a first scaling function to the set of samples to generate a first set of scaled samples; a first DPD circuit configured to: generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples; and a second multiplier configured to: apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples, wherein the second set of scaled samples is associated with a first DPD output.

2. The DPD engine of claim 1, wherein the controllable parameter is associated with a control voltage applied at the PA.

3. The DPD engine of claim 1, wherein the first multiplier includes a first scaling function lookup table (LUT).

4. The DPD engine of claim 3, wherein the second multiplier includes a second scaling function LUT.

5. The DPD engine of claim 1, wherein the first DPD circuit includes a pre-distortion lookup table (LUT).

6. The DPD engine of claim 1, further comprising: a second memoryless DPD circuit, comprising: a third multiplier configured to: apply a third scaling function to the set of samples to generate a third set of scaled samples; a second DPD circuit configured to: generate a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples; and a fourth multiplier configured to: apply a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples, wherein the fourth set of scaled samples is associated with a second DPD output.

7. The DPD engine of claim 6, further comprising: a selection unit configured to: in response to the first DPD output being nearest to the controllable parameter, output the first DPD output; or in response to the second DPD output being nearest to the controllable parameter, output the second DPD output.

8. The DPD engine of claim 1, wherein the set of samples includes a set of in-phase/in- quadrature (IQ) samples.

9. A radio frequency (RF) chip, comprising: an envelope tracking (ET) path; and an in-phase/in-quadrature (IQ) path, the IQ path including a digital pre-distortion (DPD) engine, comprising: a control function circuit configured to: estimate a controllable parameter associated with a power amplifier (PA) based on a set of samples associated with a transmit signal; a first memoryless DPD circuit, comprising: a first multiplier configured to: apply a first scaling function to the set of samples to generate a first set of scaled samples; a first DPD circuit configured to: generate a first set of pre-distorted samples based on the controllable parameter and the first set of scaled samples; and a second multiplier configured to: apply a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples, wherein the second set of scaled samples is associated with a first DPD output.

10. The RF chip of claim 9, wherein the controllable parameter is associated with a control voltage applied at the PA.

11. The RF chip of claim 9, wherein the first multiplier includes a first scaling function lookup table (LUT).

12. The RF chip of claim 11, wherein the second multiplier includes a second scaling function LUT.

13. The RF chip of claim 9, wherein the first DPD circuit includes a pre-distortion lookup- table (LUT).

14. The RF chip of claim 9, further comprising: a second memoryless DPD circuit, comprising: a third multiplier configured to: apply a third scaling function to the set of samples to generate a third set of scaled samples; a second DPD circuit configured to: generate a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples; and a fourth multiplier configured to: apply a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples, wherein the fourth set of scaled samples is associated with a second DPD output.

15. The RF chip of claim 14, further comprising: a selection unit configured to: in response to the first DPD output being nearest to the controllable parameter, output the first DPD output; or in response to the second DPD output being nearest to the controllable parameter, output the second DPD output.

16. The RF chip of claim 9, wherein the set of samples includes a set of in-phase/in- quadrature (IQ) samples.

17. A method, comprising: estimating, by a control function circuit, a controllable parameter associated with a power amplifier (PA) based on a set of samples associated with a transmit signal; applying, by a first multiplier of a first memoryless DPD circuit, a first scaling function to the set of samples to generate a first set of scaled samples; generating, by a first DPD circuit of the first memoryless DPD circuit, a first set of pre- distorted samples based on the controllable parameter and the first set of scaled samples; and applying, by a second multiplier of the first memoryless DPD circuit, a second scaling function to the first set of pre-distorted samples to generate a second set of scaled samples, wherein the second set of scaled samples is associated with a first DPD output.

18. The method of claim 17, wherein the controllable parameter is associated with a control voltage applied to the PA.

19. The method of claim 17, wherein: the first multiplier includes a first scaling function lookup table (LUT), the second multiplier includes a second scaling function LUT, and the first DPD circuit includes a pre-distortion LUT.

20. The method of claim 17, further comprising: applying, by a third multiplier of a second memoryless DPD circuit, a third scaling function to the set of samples to generate a third set of scaled samples; generating, by a second DPD circuit of the second memoryless DPD circuit, a second set of pre-distorted samples based on the controllable parameter and the third set of scaled samples; and applying, by a fourth multiplier of the second memoryless DPD circuit, a fourth scaling function to the second set of pre-distorted samples to generate a fourth set of scaled samples, wherein the fourth set of scaled samples is associated with a second DPD output.