WO2023070476A1 - 一种存储器及其制作方法 - Google Patents

一种存储器及其制作方法 Download PDF

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Publication number
WO2023070476A1
WO2023070476A1 PCT/CN2021/127194 CN2021127194W WO2023070476A1 WO 2023070476 A1 WO2023070476 A1 WO 2023070476A1 CN 2021127194 W CN2021127194 W CN 2021127194W WO 2023070476 A1 WO2023070476 A1 WO 2023070476A1
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block
semiconductor
memory
semiconductor block
bit line
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PCT/CN2021/127194
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English (en)
French (fr)
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范鲁明
焦慧芳
李檀
应成伟
王敬元璋
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华为技术有限公司
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Priority to PCT/CN2021/127194 priority Critical patent/WO2023070476A1/zh
Priority to CN202180099328.1A priority patent/CN117501822A/zh
Publication of WO2023070476A1 publication Critical patent/WO2023070476A1/zh

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  • the present application relates to the technical field of semiconductors, and in particular to a memory and a manufacturing method thereof.
  • dynamic random access memory In a computing system, dynamic random access memory (dynamic random access memory, DRAM) is used to temporarily store the calculation data of the central processing unit (CPU), and the data exchanged between the CPU and external memory such as hard disk.
  • the DRAM is A very important component of a computing system.
  • the basic unit constituting a DRAM is called a dynamic random access memory cell (DRAM Cell), which can also be called a storage unit.
  • DRAM Cell dynamic random access memory cell
  • the existing mainstream storage unit is a 6F 2 architecture, that is, the area of the storage unit is 6F 2 , where , F represents the feature size.
  • the feature size F With the development of photolithography technology, the feature size F is gradually reduced, so that the area of the memory cell is gradually reduced.
  • the reduction of the area of memory cells has encountered a bottleneck. Therefore, there is a need for a memory cell with a smaller area.
  • FIG. 1 is a schematic structural diagram of a DRAM.
  • the DRAM usually includes a plurality of storage units arranged in a matrix, and the storage units in the plurality of storage units are The area of each storage unit is 4F 2 , and FIG. 1 illustrates that the DRAM includes 12 storage units as an example. As shown in FIG.
  • the DRAM includes: a single crystal silicon substrate, a plurality of bit lines (bit lines, BL), a plurality of word lines (word lines, WL) and a plurality of vertical For vertical pillar transistors (vertical pillar transistors, VPTs), the plurality of WLs are perpendicular to the plurality of BLs, and each of the plurality of VPTs is provided with a capacitor C on a side away from the single crystal silicon substrate.
  • the plurality of BLs are heavily doped single crystal silicon, and each BL can be used to receive an external voltage to charge and discharge the capacitor C connected to the BL, and each VPT in the plurality of VPTs can be used to control
  • the connected capacitor C is connected or disconnected from the BL, the capacitor C can be used to store charges, and each WL can be used to control the on or off of the VPT connected to the WL.
  • the DRAM implements reading and writing of data by charging and discharging the capacitor C.
  • the above storage unit has an area of 4F 2 . Compared with the storage unit of 6F 2 structure, the area of the storage unit is reduced.
  • the present application provides a memory and a manufacturing method thereof, which are used to ensure the reliability and consistency of bit lines in the memory and further ensure the performance of the memory.
  • a memory which includes at least one storage unit, each of which includes: a first semiconductor block, a second semiconductor block, and a bit line block stacked in sequence, and the bit line block is made of a metal material
  • a medium and a metal block are stacked on at least a part of the side of the first semiconductor block, the medium is located between the first semiconductor block and the metal block, and a word line block is provided on at least a part of the side of the second semiconductor block.
  • each of the memory cells includes: a first semiconductor block, a second semiconductor block and a bit line block stacked in sequence, and the bit line block is made of a metal material; at least a part of the side of the first semiconductor block is stacked There is a medium and a metal block, the medium is between the first semiconductor block and the metal block, at least part of the side of the second semiconductor block is provided with a word line block, and the storage unit under this structure is a storage unit of 4F 2 structure, That is, the area of the storage unit is 4F 2 .
  • the bit line block of the storage unit provided by this application is made of metal material, compared with the storage unit of 4F2 structure using heavily doped single crystal silicon as the bit line, the bit line has higher stability in high temperature process Reliability, thereby ensuring the reliability and consistency of the bit line, and further ensuring the performance of the DRAM.
  • the storage unit further includes a ground terminal, and the metal block is electrically connected to the ground terminal.
  • the metal block is used as the upper plate of the capacitor in the storage unit, and the metal block is electrically connected to the ground terminal, so that the capacitor can be charged and discharged normally.
  • the medium is disposed around a side surface of the first semiconductor block.
  • the medium is used as an intermediate medium layer of the capacitor in the storage unit, which ensures the capacity and efficiency of the capacitor.
  • the memory cell further includes a third semiconductor block, the third semiconductor block is disposed between the second semiconductor block and the bit line block, and the third semiconductor block is a metal Silicide, for example, the third semiconductor block is titanium silicide, and the second semiconductor block includes vertical transistors.
  • the third semiconductor block reduces the contact resistance between the vertical transistor and the bit line block.
  • the memory further includes an isolation block disposed on the substrate, and the isolation block is used to isolate two adjacent storage units.
  • the isolation block ensures that two adjacent storage units can work normally, further ensuring the performance of the storage.
  • the metal blocks in the at least one storage unit are connected. In the above possible implementation manner, it is not necessary to wire each storage unit separately in the process, which simplifies the process flow.
  • the second semiconductor block includes vertical transistors.
  • the vertical transistor is used to control the on and off of the storage unit, so as to realize reading and writing of data.
  • the at least one storage unit includes M ⁇ N storage units, and among the M ⁇ N storage units, the bit lines of multiple storage units located in the same row are connected in blocks, Word lines of multiple memory cells in the same column among the M ⁇ N memory cells are connected in blocks, and M and N are positive integers.
  • a plurality of the memory cells in the same row among the M ⁇ N memory units share one bit line, and a plurality of the memory cells in the same column among the M ⁇ N memory units share one of the bit lines.
  • the word line can implement parallel data writing of multiple memory cells included in the same row in the memory cell array, thereby greatly improving the read-write efficiency of the memory.
  • the semiconductor type of the substrate is different from that of the first semiconductor block, the semiconductor type of the second semiconductor block is the same as that of the substrate, and the substrate is doped with second ions , when the substrate is a P-type semiconductor, the second ions are boron ions, the first semiconductor block is doped with first ions, and when the first semiconductor block is an N-type semiconductor, the first ions can be Phosphorus ions.
  • the first semiconductor block when the substrate is a P-type semiconductor, the first semiconductor block is an N-type semiconductor, and the second semiconductor block is a P-type semiconductor; or when the substrate is an N-type semiconductor, the first semiconductor block is a P-type semiconductor.
  • One semiconductor block is a P-type semiconductor
  • the second semiconductor block is an N-type semiconductor, which improves the diversity and flexibility of selection.
  • the memory includes a dynamic random access memory.
  • the dynamic random access memory is used to realize fast storage of data, thereby improving the efficiency of reading and writing data.
  • a method for fabricating a memory comprising: forming a first semiconductor layer and a second semiconductor layer that are stacked in sequence, and forming at least one stacked semiconductor layer based on the first semiconductor layer and the second semiconductor layer A first semiconductor block and a second semiconductor block; a medium is formed on at least a part of the side of the first semiconductor block, and a metal block is formed on the side of the medium; a word line block is formed on at least a part of the side of the second semiconductor block; A side of the second semiconductor block away from the first semiconductor block forms a bit line block to obtain a memory including at least one memory cell, and the bit line block is made of metal material.
  • the medium is disposed around a side surface of the first semiconductor block.
  • the method before forming a bit line block on a side of the second semiconductor block far away from the first semiconductor block, the method further includes: One side of the block forms a third semiconductor block.
  • the third semiconductor block is a metal silicide.
  • the method before forming a dielectric on at least a part of the side surfaces of the first semiconductor block, the method further includes: forming a first isolation block; forming a word on at least a part of the side surfaces of the second semiconductor block After the line block, the method further includes: forming a second isolation block on the surface of the metal block and the side surface of the second semiconductor block.
  • the method before forming the word line on at least a part of side surfaces of the second semiconductor block, the method further includes: forming a vertical transistor in the second semiconductor block.
  • the storage includes at least one storage unit, the at least one storage unit includes M ⁇ N storage units, and among the M ⁇ N storage units, multiple The bit line blocks of the storage unit are connected, and the word line blocks of a plurality of the storage units in the same column among the M ⁇ N storage units are connected.
  • the semiconductor types of the first semiconductor layer and the second semiconductor layer are different.
  • the memory includes a dynamic random access memory.
  • a storage device in a third aspect, includes: a circuit board, and a memory connected to the circuit board, where the memory is the memory provided in the first aspect or any possible implementation manner of the first aspect.
  • a storage device in a fourth aspect, includes a controller and a memory, the controller is used to control reading and writing of the memory, and the memory is provided by the first aspect or any possible implementation manner of the first aspect of memory.
  • a non-transitory computer-readable storage medium for use with a computer has software for designing an integrated circuit, one or more computer-readable data structures are stored on the computer-readable storage medium, a One or more computer-readable data structures include photomask data used to manufacture the memory provided by the above-mentioned first aspect or any possible implementation manner of the first aspect.
  • any storage device provided above and a non-transitory computer-readable storage medium used with a computer include the same or corresponding features of the memory provided above, so it can achieve For the beneficial effects, reference may be made to the beneficial effects in the corresponding integrated circuits provided above, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a DRAM provided by the prior art
  • FIG. 2 is a schematic diagram of a circuit structure of a storage unit provided in an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional view of a capacitor provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a comparison of storage units with different architectures provided by the embodiment of the present application.
  • FIG. 5 is a process flow diagram of a DRAM provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a storage system provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another storage unit provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a method for manufacturing a memory provided in an embodiment of the present application.
  • FIG. 11 is a schematic cross-sectional view of a memory structure provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • At least one means one or more, and “multiple” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • “At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • the embodiments of the present application use words such as "first” and "second” to distinguish the same or similar items with basically the same function and effect.
  • the first threshold and the second threshold are only used to distinguish different thresholds, and their sequence is not limited. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order.
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory cell
  • Fig. 2 is a schematic diagram of a circuit structure of a memory cell, as shown in Fig. 2, the memory cell includes: a transistor (Transistor, T), a capacitor (Capacity, C), a bit line (bit line, BL) and a word line (word line, WL).
  • the transistor T is connected to the word line WL
  • the bit line BL is connected to one end of the capacitor C through the transistor T
  • the other end of the capacitor C is connected to the ground
  • the bit line BL and the word line WL are perpendicular to each other.
  • the transistor T can be used to control the connection or disconnection between the capacitor C and the bit line BL, the capacitor C can be used to store charges, the bit line BL can be used to receive an external voltage, and the capacitor C can be charged through the transistor T or When discharging, the word line WL can be used to control the transistor T to be turned on or off.
  • the storage unit implements data reading (Read) or writing (Write) by charging or discharging the capacitor C.
  • the Read stage the bit line BL receives an external voltage, so that the voltage on the bit line BL is equal to half of the operating voltage, which is the voltage required for writing 1 in the capacitor C, and the word line WL controls the transistor T to turn on, so that the bit line BL and the capacitor C are connected and a phenomenon of charge sharing occurs. If the value stored in the capacitor C is 1, the voltage of the bit line BL will be higher than half of the operating voltage; if If the value stored in the capacitor C is 0, the voltage of the bit line BL will be lower than half of the operating voltage, and the data can be read according to the voltage of the bit line BL.
  • WL controls the transistor T to turn on.
  • the capacitor C is connected to the bit line BL.
  • the voltage on the bit line BL is raised, so that the voltage on the bit line BL and the capacitor C are equal to the operating voltage , that is, charge the capacitor C; when writing 0, reduce the voltage on the bit line BL, so that the voltage on the bit line BL and the capacitor C are both equal to 0, that is, discharge the capacitor C, so as to realize the data Write, that is, to realize the storage of data.
  • Fig. 3 is a cross-sectional schematic diagram of a capacitor C, as shown in Fig. The intermediate dielectric layer 303 and the plurality of lower plates 302 are separated from each other.
  • the intermediate dielectric layer 303 is a high dielectric constant insulating layer, and the high dielectric constant insulating layer is used as a charge storage layer.
  • the upper pole plate 301 and each lower pole plate 302 in the plurality of lower pole plates 302 are For metal materials. It should be noted that for the working principle of the capacitor C, reference may be made to the prior art, which will not be repeated here.
  • the existing mainstream memory cell has a 6F 2 structure, that is, the area of the memory cell is 6F 2 , wherein the characteristic size of the bit line BL is 2F, the characteristic size of the word line WL is 3F, and F represents the characteristic size.
  • the area S of satisfies formula (1):
  • the feature size F is gradually reduced, so that the area of the storage unit is gradually reduced, and the area of the memory is further reduced gradually.
  • the reduction of the area of memory cells has encountered a bottleneck. Therefore, there is a need for a memory cell with a smaller area.
  • a memory cell with a 4F 2 structure is provided in the prior art.
  • the characteristic size of the bit line BL and the word line WL of the memory cell with the 4F 2 structure are both 2F, that is, the area of the memory cell is 4F 2 .
  • a schematic diagram of the structure of the DRAM formed by the memory cells of the 4F 2 architecture is shown in FIG. 1 . For details, please refer to the relevant description in FIG. 1 , which will not be repeated here.
  • FIG. 4 is a schematic diagram of a comparison of memory cells of different architectures, wherein the abscissa represents memory cells of different architectures, and the first ordinate (left side) represents the percentage (%) of the number of memory cells that can be cut from a single wafer, The second ordinate (right side) represents the percentage (%) of the area of the storage unit.
  • the storage unit of the 8F2 structure is used as the benchmark, that is, it is assumed that the number of storage units of the 8F2 structure that can be cut into a single wafer is 1 , the area of the storage unit of the 8F 2 architecture is 1.
  • memory cells with 4F 2 , 6F 2 and 8F 2 structures are taken as examples for illustration. As shown in FIG.
  • the curve S401 represents the percentage (%) of the area of the memory cells of different architectures, wherein the area of the memory cells of the 4F2 architecture is about 60%, the area of the memory cells of the 6F2 architecture is about 80%, The area of the memory cell of the 8F 2 architecture is 100%.
  • Curve S402 represents the percentage (%) of the number of storage units of different structures that can be cut by a single wafer. In practical applications, the area of a single wafer is fixed. For example, the area of a single wafer can be 12, as can be seen from the curve S402. A single wafer can cut about 160% memory cells of 4F 2 architecture, 125% memory cells of 6F 2 architecture or 100% memory cells of 8F 2 architecture.
  • the memory cells of the 4F2 structure have a smaller area and the number of memory cells that can be cut from a single wafer More, that is, the memory unit of the 4F 2 architecture has significantly improved the area and the number of single wafers that can be cut.
  • FIG. 5 is a process flow chart of the DRAM described in FIG. 1 .
  • the process flow of the DRAM described in FIG. 1 can be divided into four stages, and each stage will be described below.
  • the first semiconductor 502 is the bit line BL
  • the vertical columnar single crystal silicon 503 is formed by photolithography and dry etching process
  • An insulating layer 504 is provided on the side and top of the vertical columnar silicon single crystal 503
  • ions are implanted at the bottom of the vertical columnar single crystal silicon 503 to form a PN junction and further form a drain (D).
  • D drain
  • photolithography is a processing technology that copies the temporary circuit structure on the mask to the silicon wafer that will be etched and ion-implanted later
  • dry etching is a technology that uses plasma to etch thin films.
  • bit lines BL of each row of storage cells are separated from each other by using a dry etching process. As shown in (b) in Figure 5.
  • the insulating layer 504 is used to fill the gap between adjacent bit lines BL, and the insulating layer 504 around the vertical columnar single crystal silicon 503 is removed. As shown in (c) in Figure 5.
  • ions are implanted on the top of the vertical columnar single crystal silicon 503 to form a PN junction, further forming a source (source, S), and setting a gate oxide layer and metal material on the side to form a gate (gate, G) , to obtain a vertical pillar transistor (vertical pillar transistor, VPT) 505, and a word line 506 is provided on the side of the gate G, as shown in (d) in FIG. 5 .
  • Capacitors are fabricated on top of the VPT 505 to form the DRAM shown in Figure 1.
  • the area of the memory cell in FIG. 1 is 4F 2 .
  • the area of the memory cell is reduced.
  • many BLs are heavily doped single crystal silicon. In the high temperature process, the heavily doped ions will be redistributed under the influence of high temperature, thereby affecting the reliability and consistency of the BL, and further affecting the performance of the DRAM.
  • an embodiment of the present application provides a DRAM and a manufacturing method based on the DRAM.
  • the DRAM can be applied to various storage systems.
  • the DRAM usually includes a plurality of storage units, and each of the plurality of storage units stores
  • the cell is a memory cell of 4F 2 structure, and the DRAM includes a bit line BL of a metal material, which has high heat resistance and stability, thereby ensuring the reliability and consistency of the bit line BL in a high-temperature process. Further guarantee the performance of DRAM.
  • the technical solutions of the present application can be applied to various storage systems including memories.
  • the technical solutions of the present application can be applied to computers, and can also be applied to storage systems including only memories, or storage systems including processors and memories.
  • the processor may be a central processing unit (central processing unit, CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (digital signal processor), a neural network processor, and the like.
  • FIG. 6 is a schematic structural diagram of a storage system provided by an embodiment of the present application.
  • the storage system may include a memory; optionally, the storage system may further include a CPU, a cache (cache), and a controller.
  • the CPU, cache, controller and memory can be integrated together, and the memory can be coupled to the cache through the controller, and coupled to the CPU through the cache.
  • FIG. 7 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • the memory may include a substrate 01 and at least one storage unit 02 .
  • the at least one storage unit 02 includes a plurality of storage units 02 , the metal blocks in the plurality of storage units 02 are connected.
  • the at least one storage unit 02 may include M ⁇ N storage units 02, the bit lines (BL) of the multiple storage units 02 in the same row are connected in the M ⁇ N storage units, and the M ⁇ N storage units
  • the word lines (WL) of multiple memory cells 02 in the same column in the memory cell 02 are connected in blocks, and M and N are positive integers.
  • the memory may include dynamic random access memory.
  • the structure of the storage unit 02 will be described in detail below by taking one storage unit 02 of the at least one storage unit 02 of the memory as an example.
  • Fig. 8 is a schematic structural diagram of a storage unit 02 provided by the embodiment of the present application, (a) in Fig. 8 is a perspective view of the storage unit 02, and (b) in Fig. 8 is shown in (a) in Fig. 8 The perspective view of is cut vertically downward along the straight line HH'. Referring to FIG.
  • each memory cell 02 includes: a first semiconductor block 03, a second semiconductor block 04, and a bit line block 05 stacked on the substrate 01 in sequence, and the bit line block 05 is made of a metal material; the first A dielectric 07 and a metal block 06 are stacked on at least a part of the side of the semiconductor block 03, the dielectric 07 is located between the first semiconductor block 03 and the metal block 06, at least a part of the side of the second semiconductor block 04 is covered with a word line block 08.
  • the material of the bit line block 05 can be tungsten or copper, etc.
  • the material of the medium 07 can be aluminum oxide or hafnium oxide, etc.
  • the material of the metal block 06 can be tungsten
  • the material of the word line block 06 can be is a metal material, for example, the metal material may be tungsten.
  • the first semiconductor block 03 , the medium 07 and the metal block 06 together constitute the capacitance of the storage unit 02 .
  • the first semiconductor block 03 is the lower plate of the capacitor
  • the medium 07 is the intermediate medium of the capacitor for storing charges
  • the metal block 06 is the upper plate of the capacitor.
  • the storage unit 02 also includes a ground terminal, and the metal block 06 is electrically connected to the ground terminal.
  • the semiconductor type of the substrate 01 is different from that of the first semiconductor block 03
  • the semiconductor type of the second semiconductor block 04 is the same as that of the substrate 01 .
  • the first semiconductor block 03 and the second semiconductor block 04 are taken as examples for description.
  • one of the first semiconductor block 03 and the second semiconductor block 04 is an N-type semiconductor, and the other is a P-type semiconductor.
  • the first semiconductor block 03 is an N-type semiconductor
  • the second semiconductor block 04 is a P-type semiconductor
  • the first semiconductor block 03 is a P-type semiconductor
  • the second semiconductor block 04 is an N-type semiconductor.
  • the semiconductor material in the substrate 01 , the first semiconductor block 03 and the second semiconductor block 04 may be silicon (Si) or silicon germanium (SiGe) or the like.
  • the first semiconductor block 03 is an N-type semiconductor
  • the second semiconductor block 04 is a P-type semiconductor
  • the substrate is a P-type semiconductor as an example for illustration.
  • FIG. 9 is a schematic structural diagram of another storage unit 02 provided in the embodiment of the present application.
  • (a) in FIG. 9 is a perspective view of the storage unit 02
  • (b) in FIG. 9 is a perspective view after the perspective view shown in (a) in FIG. 9 is cut vertically downward along the straight line HH' direction. As shown in FIG.
  • the memory cell 02 also includes a third semiconductor block 09, which is disposed between the second semiconductor block 04 and the bit line block 05, and the third semiconductor block 09 can react with heat generation
  • the third semiconductor block 09 is generally metal silicide, for example, the third semiconductor block 09 is titanium silicide, by setting the third semiconductor block 09 between the second semiconductor 04 and the bit line block 05, it can The contact resistance between the second semiconductor block 04 and the bit line block 05 is reduced.
  • the first semiconductor block 03 is doped with first ions
  • the substrate 01 is doped with second ions.
  • the first ion may include pentavalent ions, such as phosphorus ions (P 5+ ), and the second ion may be trivalent ions, such as boron ions (B 3+ ).
  • the second semiconductor block 04 includes a transistor, for example, the transistor may include a VPT.
  • the ions are pentavalent phosphorus ions (P 5+ ), that is, pentavalent phosphorus ions are implanted at the bottom and top of the P-type semiconductor (P 5+ ), so that the bottom and top of the second semiconductor block 04 respectively form a PN junction, and further form a drain and a source, and deposit a gate oxide material (such as silicon dioxide) on the side of the second semiconductor block 04 to form A gate oxide layer, depositing a metal material on the side of the gate oxide layer to obtain a gate (G), thereby forming the VPT.
  • a gate oxide material such as silicon dioxide
  • the memory also includes an isolation block disposed on the substrate 01 , and the isolation block is used to isolate two adjacent memory cells 02 .
  • the material of the isolation block may be silicon oxide, silicon nitride, and the like. The isolated blocks of this memory are not shown in Figures 7-9.
  • the DRAM provided by the embodiment of the present application includes a substrate and at least one storage unit, and each storage unit in the at least one storage unit includes: a first semiconductor block, a second semiconductor block, and a bit line that are sequentially stacked on the substrate block, the bit line block is made of metal material, at least a part of the side of the first semiconductor block is superimposed with a medium and a metal block, the medium is between the first semiconductor block and the metal block, and the second semiconductor block Word line blocks are provided on at least a part of the sides, and the storage unit under this structure is a storage unit with a 4F 2 structure, that is, the area of the storage unit is 4F 2 .
  • the bit line block of the storage unit provided by the application is made of metal material, compared with the storage unit of 4F 2 structure using heavily doped single crystal silicon as the bit line, the bit line block has a higher Stability, thereby ensuring the reliability and consistency of the bit line, and further ensuring the performance of the DRAM.
  • FIG. 10 is a schematic flowchart of a manufacturing method of a memory provided by an embodiment of the present application.
  • the memory may be the memory provided above.
  • the method may include the following steps.
  • FIG. 11 is a cross-sectional schematic view of the memory structure in the process of manufacturing the memory.
  • the first semiconductor layer 02 and the second semiconductor layer 03 are sequentially stacked, and based on the first semiconductor layer 02 and the second semiconductor layer 03, at least one stacked first semiconductor block 02 and the second semiconductor layer 03 are formed.
  • Two semiconductor blocks 03. The section structure of the memory is shown in (a) of FIG. 11 and (b) of FIG. 11 .
  • the semiconductor type of the substrate 01 and the first semiconductor layer 02 are different, and the semiconductor type of the second semiconductor layer 03 is the same as that of the substrate 01 .
  • first semiconductor layer 02 and the second semiconductor layer 03 are taken as examples for description.
  • one of the first semiconductor layer 02 and the second semiconductor layer 03 is an N-type semiconductor, and the other is a P-type semiconductor.
  • the first semiconductor layer 02 is an N-type semiconductor
  • the second semiconductor layer 03 is a P-type semiconductor
  • the first semiconductor layer 02 is a P-type semiconductor
  • the second semiconductor layer 03 is an N-type semiconductor.
  • the first semiconductor layer 02 is an N-type semiconductor
  • the substrate 01 and the second semiconductor layer 03 are P-type semiconductors as an example for illustration.
  • the first semiconductor layer 02 is an N-type semiconductor
  • the second semiconductor layer 03 and the substrate 01 are P-type semiconductors as an example for illustration.
  • the substrate 01 is doped with second ions
  • the first semiconductor layer 02 is doped with first ions.
  • the second ion is doped at the bottom of the P-type silicon substrate, for example, trivalent boron ions (B 3+ ) are doped at the bottom of the P-type silicon substrate to form a P-type silicon with ions.
  • substrate ((a) in FIG. 11 is represented by P + ), that is, the substrate 01 is formed;
  • the first ion is doped in the middle of the P-type silicon substrate, for example, doped in the middle of the P-type silicon substrate Heteropentavalent phosphorus ions (P 5+ ) form the first semiconductor layer 02 (indicated by N + in (a) in FIG. 11 ).
  • the second semiconductor layer 03 is an intrinsic P-type silicon semiconductor (indicated by P in (a) in FIG. 11 ).
  • forming at least one stacked first semiconductor block 02 and second semiconductor block 03 based on the first semiconductor layer 02 and the second semiconductor layer 03 specifically includes: based on the first semiconductor layer 02 and the second semiconductor layer 03
  • the doped ions are different, and at least one superimposed first semiconductor block 02 and second semiconductor block 03 are etched on the substrate 01 by photolithography and etching techniques.
  • the superimposed first semiconductor block 02 and the second semiconductor block 03 The second semiconductor block 03 is a vertical column shape.
  • S02 Form a medium 04 on at least a part of the side of the first semiconductor block 02, and form a metal block 05 on the side of the medium 04.
  • the section structure of the memory is shown in (c) of FIG. 11 .
  • the medium 04 is arranged around the side of the first semiconductor block 02, and the metal block 05 is connected to the ground terminal.
  • the medium 04 may be aluminum oxide or hafnium oxide, etc.
  • the material of the metal block 05 may be a metal material, for example, the metal material may be tungsten.
  • the first semiconductor block 02, the medium 04 and the metal block 05 together constitute the capacitance of the storage.
  • the first semiconductor block 02 is the lower plate of the capacitor
  • the medium 04 is the intermediate medium of the capacitor for storing charges
  • the metal block 05 is the upper plate of the capacitor.
  • the specific process of forming the dielectric 04 and the metal block 05 is: depositing a high dielectric constant material on the side of the first semiconductor block 02 by thin film deposition technology, such as atomic layer deposition technology, for example, the high dielectric constant material may include Aluminum oxide or hafnium oxide, etc., to form a dielectric film, which can be a single-layer film or a multi-layer composite film; deposit a metal material on the side of the medium 04 by metal deposition, for example, the metal material can be tungsten , to form a metal film, and finally, etch away the excess material of the dielectric film and the metal film to obtain the medium 04 and the metal block 05 .
  • atomic layer deposition technology for example, the high dielectric constant material may include Aluminum oxide or hafnium oxide, etc.
  • a first isolation block 06 is formed on the substrate 01 .
  • S03 Form a word line block 07 on at least a part of side surfaces of the second semiconductor block 03 .
  • the section structure of the memory is shown in (d) of FIG. 11 .
  • a metal material is deposited on at least a part of the side surface of the second semiconductor block 03 by a metal deposition method, and the metal material may be tungsten, so as to obtain the word line block 07 .
  • a VPT is formed in the second semiconductor block 03, specifically, ions of the same type are respectively implanted on the top and bottom of the second semiconductor block 03, and the ions are pentavalent Phosphorus ions (P 5+ ), respectively form PN junctions at the bottom and top of the second semiconductor block 03, further form source (S) and drain (D), and deposit gate oxide material on the surface of the semiconductor block 03 ( For example, silicon dioxide) forms a gate oxide layer, and metal materials are deposited on the surface of the gate oxide layer to obtain a gate (G), thereby forming the VPT.
  • gate oxide material For example, silicon dioxide
  • G gate
  • a second isolation is formed on the surface of the metal block 05 away from the substrate 01 and the side surface of the second semiconductor block 03. Block 08.
  • first isolation block 06 and the second isolation block 08 are insulating layers, and the materials of the first isolation block 06 and the second isolation block 08 can be silicon oxide, silicon nitride, etc., the first isolation block 06 and the The second isolation blocks 08 are collectively referred to as isolation blocks.
  • S04 Form a bit line block 09 on a side of the second semiconductor block 03 away from the first semiconductor block 02 to obtain the memory, and the bit line block 09 is made of a metal material.
  • the section structure of the memory is shown in (e) in FIG. 11 .
  • a metal material is provided on a side of the second semiconductor block 03 away from the first semiconductor block 02 to obtain a bit line block 09, thereby obtaining the memory.
  • the metal material may include tungsten or copper.
  • the memory may include a dynamic random access memory.
  • the storage may include at least one storage unit, and the metal blocks 05 in the at least one storage unit are in communication.
  • the at least one storage unit may include M ⁇ N storage units, the M ⁇ N storage units are connected to the bit line block 09 of a plurality of storage units in the same row, and the M ⁇ N storage units are located in Word line blocks 07 of multiple memory cells in the same column are connected, and M and N are positive integers.
  • FIG. 12 is a schematic structural diagram of another memory provided by the embodiment of the present application.
  • a third semiconductor block 10 is formed on the side of the second semiconductor block 03 away from the first semiconductor block 02.
  • the third semiconductor block 10 is formed by thermal reaction.
  • the third semiconductor block 10 is generally a metal silicide, for example,
  • the third semiconductor block 10 is titanium silicide.
  • the manufacturing method provided by the embodiment of the present application can be applied to the manufacturing of memory, forming a first semiconductor layer and a second semiconductor layer stacked in sequence on a substrate, and forming at least one semiconductor layer based on the first semiconductor layer and the second semiconductor layer
  • the first semiconductor block and the second semiconductor block are superimposed, a medium is formed on at least a part of the side of the first semiconductor block, a metal block is formed on the side of the medium, and a word line block is formed on at least a part of the side of the second semiconductor block,
  • a bit line block is formed on the side of the second semiconductor block away from the first semiconductor block, the bit line block is made of metal material, the structure of the storage unit under this structure is 4F 2 , that is, the area of the storage unit is 4F 2 .
  • the bit line block of the storage unit provided by the application is made of metal material, compared with the storage unit of 4F 2 structure using heavily doped single crystal silicon as the bit line, the bit line block has a higher Stability, thereby ensuring the reliability and consistency of the bit line, and further ensuring the performance of the DRAM.
  • an embodiment of the present application further provides a storage device.
  • the storage device includes a circuit board and a memory connected to the circuit board.
  • the memory may be any memory provided above.
  • the circuit board may be a printed circuit board (printed circuit board, PCB), and of course the circuit board may also be a flexible circuit board (FPC), etc., and this embodiment does not limit the circuit board.
  • the storage device is different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the storage device may also be network devices such as base stations.
  • the storage device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the memory is fixed on the packaging substrate through solder balls.
  • an embodiment of the present application further provides a storage device, the storage device includes a controller and a memory, the controller is used to control reading and writing in the memory, and the memory may be any memory provided above.
  • a non-transitory computer-readable storage medium for use with a computer having software for designing an integrated circuit, the computer-readable storage medium storing one or more Computer-readable data structures, one or more computer-readable data structures comprising photomask data used to fabricate any of the memories provided above.

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Abstract

本申请实施例提供一种存储器及其制作方法，用于保证储存器中位线的可靠性和一致性，进一步保证储存器的性能。该储存器包括至少一个存储单元，每个存储单元包括：依次叠加的第一半导体块、第二半导体块和位线块，该位线块由金属材料制成；该第一半导体块的至少一部分侧面上叠加设置有介质和金属块，该介质处于该第一半导体块和该金属块之间，该第二半导体块的至少一部分侧面覆盖有字线块。

Description

一种存储器及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器及其制作方法。
背景技术
在计算系统中，动态随机存取存储器(dynamic random access memory，DRAM)用于暂存中央处理器(central processing unit，CPU)的运算数据，以及CPU与硬盘等外部存储器交换的数据，该DRAM是计算系统非常重要的组成部分。构成DRAM的基本单元称为动态随机存储器单元(dynamic random access memory cell，DRAM Cell)，也可以称为存储单元，现有主流的存储单元为6F 2架构，即存储单元的面积为6F 2，其中，F表示特征尺寸。随着光刻技术的发展，使得特征尺寸F逐渐减小，从而使得存储单元的面积逐渐减少。但是，由于光刻技术和成本的限制，存储单元的面积减小遇到了瓶颈。因此，需要一种面积更小的存储单元。
现有技术提供了一种4F 2架构的存储单元，图1为一种DRAM的结构示意图，该DRAM通常包括多个存储单元，该多个存储单元呈矩阵式排列，该多个存储单元中的每一个存储单元的面积为4F 2，图1以该DRAM包括12个存储单元为例进行说明。如图1所示，该DRAM包括：单晶硅衬底，设置于单晶硅衬底上的多个位线(bit line，BL)、多个字线(word line，WL)和多个垂直柱状晶体管(vertical pillar transistor，VPT)，该多个WL与该多个BL垂直，该多个VPT中的每一个VPT上远离单晶硅衬底的一侧设置有一个电容C。其中，该多个BL为重掺杂的单晶硅，每个BL可用于接收外部电压对该BL所连接的电容C进行充放电，该多个VPT中的每个VPT可用于控制与该VPT连接的该电容C与该BL的连通或断开，电容C可用于存储电荷，每个WL可用于控制与该WL连接的VPT的导通或关断。该DRAM通过对电容C充放电的形式，实现数据的读写。上述存储单元的面积为4F 2，该4F 2架构的存储单元与6F 2架构的存储单元相比，减小了存储单元的面积。
但是，上述方案中的由于工艺限制多个BL为重掺杂的单晶硅，在高温工艺中重掺杂的离子受到高温影响会重新分布，从而影响BL的可靠性和一致性，进一步影响DRAM的性能。
发明内容
本申请提供一种存储器及其制作方法，用于保证储存器中位线的可靠性和一致性，进一步保证储存器的性能。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供了一种存储器，该存储器包括至少一个存储单元，每个该存储单元包括：依次叠加的第一半导体块、第二半导体块和位线块，该位线块由金属材料制成；第一半导体块的至少一部分侧面上叠加设置有介质和金属块，该介质处于该第一半导体块和该金属块之间，该第二半导体块的至少一部分侧面设置有字线块。
上述技术方案中，每个该存储单元包括：依次叠加的第一半导体块、第二半导体块和位线块，该位线块由金属材料制成；第一半导体块的至少一部分侧面上叠加设置有介质 和金属块，该介质处于该第一半导体块和该金属块之间，该第二半导体块的至少一部分侧面设置有字线块，该结构下的储存单元为4F 2架构的储存单元，即该储存单元的面积为4F 2。本申请提供的储存单元的位线块由金属材料制成，与采用重掺杂的单晶硅作为位线的4F 2架构的储存单元相比，该位线在高温工艺中具有较高的稳定性，从而保证了该位线的可靠性和一致性，进一步保证了DRAM的性能。
在第一方面的一种可能的实现方式中，该存储单元还包括接地端，该金属块被电性连接至该接地端。上述可能的实现方式中，该金属块作为该存储单元中电容的上极板，该金属块被电性连接至该接地端，以使得电容能够正常充电和放电。
在第一方面的一种可能的实现方式中，该介质围绕该第一半导体块的侧面一周设置。上述可能的实现方式中，该介质作为该存储单元中电容的中间介质层，保证了电容的容量和效率。
在第一方面的一种可能的实现方式中，该存储单元还包括第三半导体块，该第三半导体块设置于该第二半导体块与该位线块之间，该第三半导体块是金属硅化物，例如，该第三半导体块是钛硅化物，该第二半导体块包括垂直晶体管。上述可能的实现方式中，该第三半导体块减少了垂直晶体管与位线块的接触电阻。
在第一方面的一种可能的实现方式中，该存储器还包括设置在该衬底上的隔离块，该隔离块用于隔离相邻的两个存储单元。上述可能的实现方式中，该隔离块保证了相邻的两个储存单元可以正常工作，进一步保证了该储存器的性能。
在第一方面的一种可能的实现方式中，该至少一个存储单元中的所述金属块连通。上述可能的实现方式中，在工艺中不需要为每个储存单元单独布线，简化了工艺流程。
在第一方面的一种可能的实现方式中，第二半导体块包括垂直晶体管。上述可能的实现方式中，该垂直晶体管用于控制该储存单元的导通与关断，从而实现数据的读写。
在第一方面的一种可能的实现方式中，该至少一个存储单元包括M×N个该存储单元，M×N个该存储单元中位于同一行的多个该存储单元的位线块连通，M×N个该存储单元中位于同一列的多个该存储单元的字线块连通，M和N为正整数。上述可能的实现方式中，M×N个该存储单元中位于同一行的多个该存储单元共用一个该位线，M×N个该存储单元中位于同一列的多个该存储单元共用一个该字线，可以实现该存储单元阵列中同一行包括的多个存储单元的并行写数据，从而大大提高该存储器的读写效率。
在第一方面的一种可能的实现方式中，衬底和该第一半导体块的半导体类型不同，该第二半导体块和该衬底的半导体类型相同，该衬底中掺杂有第二离子，当该衬底为P型半导体时，该第二离子为硼离子，该第一半导体块中掺杂有第一离子，该第一半导体块为N型半导体时，该第一离子可以为为磷离子。上述可能的实现方式中，当该衬底为P型半导体时，该第一半导体块为N型半导体，该第二半导体块为P型半导体；或者当该衬底为N型半导体时，该第一半导体块为P型半导体，该第二半导体块为N型半导体，提高了选择的多样性和灵活性。
在第一方面的一种可能的实现方式中，该存储器包括动态随机存取存储器。上述可能的实现方式中，利用该动态随机存取存储器实现数据的快速储存，从而提高了数据的读写效率。
第二方面，提供一种存储器的制作方法，该方法包括：形成依次叠加设置的第一半导体层和第二半导体层，并基于该第一半导体层和该第二半导体层形成至少一个叠加设置的第一半导体块和第二半导体块；在该第一半导体块的至少一部分侧面形成介质，在该介质的侧面形成金属块；在该第二半导体块的至少一部分侧面形成字线块；在该第二半导体块远离该第一半导体块的一侧形成位线块以得到包括至少一个存储单元的存储器，该位线块由金属材料制成。
在第二方面的一种可能的实现方式中，该介质围绕该第一半导体块的侧面一周设置。
在第二方面的一种可能的实现方式中，在该第二半导体块远离该第一半导体块的一侧形成位线块之前，该方法还包括：在该第二半导体块远离该第一半导体块的一侧形成第三半导体块。
在第二方面的一种可能的实现方式中，该第三半导体块是金属硅化物。
在第二方面的一种可能的实现方式中，在该第一半导体块的至少一部分侧面形成介质之前，该方法还包括：形成第一隔离块；在该第二半导体块的至少一部分侧面形成字线块之后，该方法还包括：在该金属块的表面、以及该第二半导体块的侧面形成第二隔离块。
在第二方面的一种可能的实现方式中，在该第二半导体块的至少一部分侧面形成字线之前，该方法还包括：在该第二半导体块中形成垂直晶体管。
在第二方面的一种可能的实现方式中，该储存器包括至少一个存储单元，该至少一个存储单元包括M×N个该存储单元，M×N个该存储单元中位于同一行的多个该存储单元的位线块连通，M×N个该存储单元中位于同一列的多个该存储单元的字线块连通。
在第二方面的一种可能的实现方式中，该第一半导体层与该第二半导体层的半导体类型不同。
在第二方面的一种可能的实现方式中，该存储器包括动态随机存取存储器。
第三方面，提供一种存储设备，该存储设备包括：电路板、以及与电路板连接的存储器，该存储器为第一方面或者第一方面的任一项可能的实现方式所提供的存储器。
第四方面，提供一种存储设备，该存储设备包括控制器和存储器，该控制器用于控制该存储器的读写，该存储器为第一方面或者第一方面的任一项可能的实现方式所提供的存储器。
第五方面，提供一种与计算机一起使用的非瞬时性计算机可读存储介质，计算机具有用于设计集成电路的软件，计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构包括用于制造上述第一方面或者第一方面的任一种可能的实现方式所提供的存储器的光掩膜数据。
可以理解地是，上述提供的任一种存储设备和与计算机一起使用的非瞬时性计算机可读存储介质等包含了上文所提供的存储器的相同或相对应的特征，因此，其所能达到的有益效果可参考上文所提供的对应的集成电路中的有益效果，此处不再赘述。
附图说明
图1为现有技术提供的一种DRAM的结构示意图；
图2为本申请实施例提供的一种存储单元的电路结构示意图；
图3为本申请实施例提供的一种电容的切面示意图；
图4为本申请实施例提供的一种不同架构的存储单元的对比示意图；
图5为本申请实施例提供的一种DRAM的工艺流程图；
图6为本申请实施例提供的一种存储系统的结构示意图；
图7为本申请实施例提供的一种存储器的结构示意图；
图8为本申请实施例提供的一种存储单元的结构示意图；
图9为本申请实施例提供的另一种存储单元的结构示意图；
图10为本申请实施例提供的一种存储器的制作方法的流程示意图；
图11为本申请实施例提供的一种存储器结构的切面示意图；
图12为本申请实施例提供的另一种存储器的结构示意图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a、b、c、a-b、a-c、b-c、或a-b-c，其中a，b，c可以是单个，也可以是多个。另外，本申请实施例采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。例如，第一阈值和第二阈值仅仅是为了区分不同的阈值，并不对其先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在介绍本申请实施例之前，首先对动态随机存取存储器(dynamic random access memory，DRAM)相关的背景技术进行介绍说明。
在计算系统中，DRAM用于暂存中央处理器(central processing unit，CPU)的运算数据，以及CPU与硬盘等外部存储器交换的数据，是计算系统非常重要的组成部分。构成DRAM的基本单元称为动态随机存储器单元(dynamic random access memory cell，DRAM Cell)，也可以称为存储单元。
图2为一种存储单元的电路结构示意图，如图2所示，该存储单元包括：晶体管(Transistor、T)、电容(Capacity、C)、位线(bit line，BL)和字线(word line，WL)。其中，该晶体管T与该字线WL连接，该位线BL通过该晶体管T与该电容C的一端连接，电容C的另一端与接地端连接，该位线BL与该字线WL相互垂直。
下面对上述各器件的功能进行描述：
该晶体管T可用于控制该电容C与该位线BL的连通或断开，该电容C可用于存储电荷，该位线BL可用于接收外部电压，并通过该晶体管T对该电容C进行充电或者放电，该字线WL可用于控制该晶体管T的导通或关断。
下面对该存储单元的工作原理进行描述：
该存储单元通过对电容C进行充电或者放电的方式，实现数据的读(Read)或者写(Write)。
具体的，Read阶段：该位线BL接收外部电压，使得该位线BL上的电压等于操作电压的一半，该操作电压为该电容C中写入1时所需要的电压，此时该字线WL控制晶体管T导通，使得该位线BL和该电容C连通并产生电荷共享的现象，若电容C内部存储的值为1，则该位线BL的电压会高于操作电压的一半；若电容C内部存储的值为0，则该位线BL的电压会低于操作电压的一半，根据该位线BL的电压的大小，实现数据的读取。
Write阶段：WL控制晶体管T导通，此时该电容C与该位线BL连通，写1时，升高位线BL上的电压，使得该位线BL和该电容C上的电压均等于操作电压，即对该电容C进行充电；写0时、降低该位线BL上的电压，使得该位线BL和该电容C上的电压均等于0，即对该电容C进行放电，从而实现数据的写入，即实现数据的储存。
可选的，该电容C的结构可以为圆筒状的。图3为一种电容C的切面示意图，如图3所示，该电容C包括上极板301、多个下极板302以及位于该上极板301和该多个下极板302之间的中间介质层303，该多个下极板302相互分离。
其中，该中间介质层303为高介电常数绝缘层，该高介电常数绝缘层作为电荷的储存层，该上极板301和该多个下极板302中的每个下极板302均为金属材料。需要说明的是关于电容C的工作原理可参考现有技术，在此不再赘述。
现有主流的存储单元为6F 2架构，即存储单元的面积为6F 2，其中，该位线BL的特征尺寸为2F，该字线WL的特征尺寸为3F，F表示特征尺寸，该存储单元的面积S满足公式(1)：
S＝WL的特征尺寸×BL的特征尺寸        (1)
随着光刻技术的发展，使得特征尺寸F逐渐减小，从而使得存储单元的面积逐渐减少，进一步使得存储器的面积逐渐减小。但是，由于光刻技术和成本的限制，存储单元的面积减小遇到了瓶颈。因此，需要一种面积更小的存储单元。
现有技术中提供了一种4F 2架构的存储单元，该4F 2架构的存储单元的位线BL的特征尺寸和该字线WL的特征尺寸均为2F，即存储单元的面积为4F 2，该4F 2架构的存储单元构成的DRAM的结构示意图如图1所示，具体请参考图1的相关描述，此处不再赘述。
图4为一种不同架构的存储单元的对比示意图，其中，横坐标表示不同架构的存储单元，第一纵坐标(左侧)表示单个晶圆能够切割的储存单元的数量的百分比(％)，第二纵坐标(右侧)表示储存单元的面积的百分比(％)，图4中以8F 2架构的存储单元为基准，即假设单个晶圆能够切割的8F 2架构的存储单元的数量为1，8F 2架构的存储单元的面积为1。图4中以4F 2、6F 2和8F 2架构的存储单元为例进行说明。如图4所示，曲线S401表示不同架构的存储单元的面积的百分比(％)，其中，4F 2架构的存储单元的面积大约为60％，6F 2架构的存储单元的面积大约为80％，8F 2架构的存储单元的面积为100％。曲线S402表示单个晶圆能够切割的不同构架的储存单元的数量的百分比(％)，在实际应用中单个晶圆的面积是固定的，例如单个晶圆的面积可以为12，由曲线S402可知，单个晶圆能够切割大约160％个4F 2架构的存储单元、125％个6F 2架构的存储单元或者100％个8F 2架构的存储单元。
由图4可知，该4F 2架构的存储单元与6F 2架构的存储单元和8F 2架构的存储单元相比， 该4F 2架构的存储单元的面积小、单个晶圆能够切割的存储单元的数量多，即该4F 2架构的存储单元在面积和单个晶圆能够切割的数量上有显著的提升。
下面结合图5对图1所描述的DRAM的工艺流程进行介绍说明。图5为图1所描述的DRAM的工艺流程图，图1所描述的DRAM的工艺流程可以分为四个阶段，下面分别对每个阶段进行描述。
第一阶段、在单晶硅衬底501上进行重掺杂形成第一半导体502，该第一半导体502为位线BL，利用光刻和干法刻蚀工艺形成垂直柱状的单晶硅503，在该垂直柱状的单晶硅503的侧面和顶部设置绝缘层504，在该垂直柱状的单晶硅503的底部注入离子形成PN结，进一步形成漏极(drain，D)。如图5中的(a)所示。
其中，光刻是把掩膜版上临时的电路结构复制到后续要进行刻蚀和离子注入的硅片上的一种加工技术，干法刻蚀是用等离子体进行薄膜刻蚀的一种技术。详细描述请参考现有技术，此处不再赘述。
第二阶段、利用干法刻蚀工艺将每一行储存单元的位线BL相互分离。如图5中的(b)所示。
第三阶段、利用绝缘层504填充相邻的位线BL之间的间隙，去除该垂直柱状的单晶硅503四周的绝缘层504。如图5中的(c)所示。
第四阶段、在该垂直柱状的单晶硅503的顶部注入离子形成PN结，进一步形成源极(source，S)，并在侧面设置栅氧层和金属材料，形成栅极(gate，G)，以得到垂直柱状晶体管(vertical pillar transistor，VPT)505，在栅极G的侧面设置字线506，如图5中的(d)所示。在VPT 505的顶部制作电容，形成图1所示的DRAM。
图1中的存储单元的面积为4F 2，该4F 2架构的存储单元与6F 2架构的存储单元相比，减小了存储单元的面积。但是，由于工艺的限制多个BL为重掺杂的单晶硅，在高温工艺中重掺杂的离子受到高温影响会重新分布，从而影响BL的可靠性和一致性，进一步影响DRAM的性能。
基于此，本申请实施例提供了一种DRAM以及基于该DRAM的制作方法，该DRAM可应用于各种存储系统中，该DRAM通常包括多个存储单元，该多个存储单元中的每个储存单元为4F 2架构的存储单元，该DRAM包括金属材料的位线BL，该金属材料具有较高的耐热性和稳定性，从而能够保证位线BL在高温工艺中的可靠性和一致性，进一步保证了DRAM的性能。
下面首先对该存储系统进行介绍说明。
本申请的技术方案可以应用于包括存储器的各种存储系统中，比如，本申请的技术方案可以应用于计算机中，还可以应用于仅包括存储器的存储系统中、或者包括处理器和存储器的存储系统中，该处理器可以为中央处理器(central processing unit，CPU)、人工智能(artificial intelligence，AI)处理器、数字信号处理器(digital signal processor)和神经网络处理器等。
示例性的，图6为本申请实施例提供的一种存储系统的结构示意图，该存储系统可以包括存储器；可选的，该存储系统还可以包括CPU、缓存器(cache)和控制器等。其中，该CPU、缓存器、控制器和存储器可以集成在一起，存储器可以通过控制器与该缓存器耦合，以及通过该缓存器和该CPU相耦合。
下面结合图7和图8对该DRAM的结构进行详细的描述。
图7为本申请实施例提供的一种存储器的结构示意图，该存储器可以包括衬底01和至少一个存储单元02。在该至少一个存储单元02包括多个存储单元02的情况下，所述多个存储单元02中的金属块连通。此外，该至少一个存储单元02可以包括M×N个存储单元02，该M×N个存储单元该中位于同一行的多个存储单元02的位线(BL)块连通，该M×N个存储单元02中位于同一列的多个存储单元02的字线(WL)块连通，M和N为正整数。该存储器可以包括动态随机存取存储器。
下面以该存储器的至少一个存储单元02中的一个存储单元02为例，对该存储单元02的结构进行详细说明。
图8为本申请实施例提供的一种存储单元02的结构示意图，图8中的(a)为该存储单元02的立体图，图8中的(b)为图8中的(a)所示的立体图沿着直线HH’方向垂直向下剖开之后的立体图。参见图8，每个存储单元02包括：依次叠加设置在衬底01上的第一半导体块03、第二半导体块04和位线块05，该位线块05由金属材料制成；第一半导体块03的至少一部分侧面上叠加设置有介质07和金属块06，介质07处于该第一半导体块03和该金属块06之间，该第二半导体块04的至少一部分侧面覆盖有字线块08。
其中，该位线块05的材料可以是钨或者铜等，该介质07的材料可以是三氧化二铝或氧化铪等，该金属块06的材料可以是钨，该字线块06的材料可以是金属材料，例如，该金属材料可以是钨。
另外，该第一半导体块03、介质07和金属块06一起构成了该存储单元02的电容。其中，该第一半导体块03为该电容的下极板，该介质07为该电容的中间介质，该中间介质用于储存电荷，该金属块06为该电容的上极板。
进一步的，该存储单元02还包括接地端，该金属块06被电性连接至该接地端。
进一步的，该衬底01和该第一半导体块03的半导体类型不同，该第二半导体块04和该衬底01的半导体类型相同。下面以第一半导体块03和第二半导体块04为例进行说明。
其中，该第一半导体块03和该第二半导体块04中的一个为N型半导体、另一个为P型半导体。比如，该第一半导体块03为N型半导体，该第二半导体块04为P型半导体；或者，该第一半导体块03为P型半导体，该第二半导体块04为N型半导体。该衬底01、该第一半导体块03和该第二半导体块04中的半导体材料可以是硅(Si)或者硅锗(SiGe)等。
以下实施例中以该第一半导体块03为N型半导体，该第二半导体块04为P型半导体，该衬底为P型半导体为例进行说明。
进一步的，图9为本申请实施例提供的另一种存储单元02的结构示意图。图9中的(a)为该存储单元02的立体图，图9中的(b)为图9中的(a)所示的立体图沿着直线HH’方向垂直向下剖开之后的立体图。如图9所示，该存储单元02还包括第三半导体块09，该第三半导体09设置于该第二半导体块04与该位线块05之间，该第三半导体块09可以通过热反应生成，该第三半导体块09一般是金属硅化物，例如，该第三半导体块09为钛硅化物，通过在该第二半导体04与该位线块05之间设置第三半导体块 09，可以减小该第二半导体块04与该位线块05的接触电阻。
可选的，该第一半导体块03中掺杂有第一离子，该衬底01中掺杂有第二离子。其中，该第一离子可以包括五价离子，比如，磷离子(P 5+)，该第二离子可以为三价离子，例如，硼离子(B 3+)。
进一步的，该第二半导体块04包括晶体管，例如，该晶体管可以包括VPT。具体的，分别在该第二半导体块04的底部和顶部注入类型相同的离子，该离子为五价的磷离子(P 5+)，即在P型半导体的底部和顶部注入五价的磷离子(P 5+)，使得该第二半导体块04的底部和顶部分别形成PN结，进一步形成漏极和源极，在该第二半导体块04的侧面沉积栅氧材料(比如二氧化硅)形成栅氧层，在栅氧层的侧面沉积金属材料以得到栅极(G)，从而形成该VPT。该VPT详细的工艺流程可以参考现有技术，此处不再赘述。图8-图9中未示出该VPT的具体结构。
进一步的，该存储器还包括设置在该衬底01上的隔离块，该隔离块用于隔离相邻的两个存储单元02。其中，该隔离块的材料可以为氧化硅和氮化硅等。图7-图9中未示出该存储器的隔离块。
本申请实施例提供的DRAM包括衬底和至少一个存储单元，该至少一个存储单元中的每个存储单元包括：依次叠加设置在该衬底上的第一半导体块、第二半导体块和位线块，该位线块由金属材料制成，第一半导体块的至少一部分侧面上叠加设置有介质和金属块，该介质处于该第一半导体块和该金属块之间，该第二半导体块的至少一部分侧面设置有字线块，该结构下的储存单元为4F 2架构的储存单元，即该储存单元的面积为4F 2。本申请提供的储存单元的位线块由金属材料制成，与采用重掺杂的单晶硅作为位线的4F 2架构的储存单元相比，该位线块在高温工艺中具有较高的稳定性，从而保证了位线的可靠性和一致性，进一步保证了DRAM的性能。
下面结合图10和图11对存储器的制作方法进行描述。
图10为本申请实施例提供的一种存储器的制作方法的流程示意图，该存储器可以为上文提供的存储器，该方法可以包括以下步骤。图11为制作该存储器过程中该存储器结构的切面示意图。
S01：在衬底01上依次叠加设置第一半导体层02和第二半导体层03，并基于该第一半导体层02和该第二半导体层03形成至少一个叠加设置的第一半导体块02和第二半导体块03。该存储器的切面结构如图11中的(a)和图11中的(b)所示。
进一步的，该衬底01和该第一半导体层02的半导体类型不同，该第二半导体层03和该衬底01的半导体类型相同。
下面以第一半导体层02和第二半导体层03为例来进行说明。
其中，该第一半导体层02和该第二半导体层03一个为N型半导体、另一个为P型半导体。比如，该第一半导体层02为N型半导体，该第二半导体层03为P型半导体；或者，该第一半导体层02为P型半导体，该第二半导体层03为N型半导体。图10中以该第一半导体层02为N型半导体，该衬底01和第二半导体层03为P型半导体为例进行说明。需要说明的是图11中以该第一半导体层02为N型半导体，该第二半导体层03和该衬底01为P型半导体为例进行说明。
进一步的，该衬底01中掺杂有第二离子，该第一半导体层02中掺杂有第一离子，。 具体的，在P型硅衬底的底部掺杂该第二离子，比如，在该P型硅衬底的底部掺杂三价的硼离子(B 3+)，形成带有离子的P型硅衬底(图11中的(a)用P +表示)，即形成该衬底01；在P型硅衬底的中部掺杂该第一离子，例如，在该P型硅衬底的中部掺杂五价的磷离子(P 5+)形成该第一半导体层02(图11中的(a)用N +表示)。其中，第二半导体层03为本征P型硅半导体(图11中的(a)用P表示)。
另外，基于该第一半导体层02和该第二半导体层03形成至少一个叠加设置的第一半导体块02和第二半导体块03具体包括：基于该第一半导体层02和该第二半导体层03中掺杂的离子不同，通过光刻和刻蚀技术在衬底01上刻蚀出至少一个叠加设置的第一半导体块02和第二半导体块03，该叠加设置的第一半导体块02和第二半导体块03为垂直柱状的图形。
S02：在该第一半导体块02的至少一部分侧面形成介质04，在该介质04的侧面形成金属块05。该存储器的切面结构如图11中的(c)所示。
进一步的，该介质04围绕该第一半导体块02的侧面一周设置，该金属块05与接地端连接。
其中，该介质04可以是三氧化二铝或氧化铪等，该金属块05的材料可以金属材料，例如，该金属材料可以是钨。
再者，该第一半导体块02、介质04和金属块05一起构成了该储存器的电容。其中，该第一半导体块02为该电容的下极板，该介质04为该电容的中间介质，该中间介质用于储存电荷，该金属块05为该电容的上极板。
形成该介质04和金属块05的具体过程为：通过薄膜沉积的技术，例如原子层沉积技术，在第一半导体块02的侧面沉积高介电常数材料，例如，该高介电常数材料可以包括三氧化二铝或氧化铪等等，以形成介质薄膜，该介质薄膜可以是单层膜或多层复合膜；在介质04的侧面通过金属沉积的方法沉积金属材料，例如该金属材料可以是钨，形成金属薄膜，最后，刻蚀掉多余的介质薄膜和金属薄膜的材料，得到介质04和金属块05。
进一步的，在该第一半导体块02的侧面形成介质04之前，在该衬底01上形成第一隔离块06。
S03：在该第二半导体块03的至少一部分侧面形成字线块07。该存储器的切面结构如图11中的(d)所示。
具体的，在第二半导体块03的至少一部分侧面通过金属沉积的方法沉积金属材料，该金属材料可以是钨，以得到字线块07。
可选的，在得到字线块07之前，在该第二半导体块03中形成VPT，具体的，在该第二半导体块03的顶部和底部分别注入类型相同的离子，该离子为五价的磷离子(P 5+)，在该第二半导体块03的底部和顶部分别形成PN结，进一步形成源极(S)和漏极(D)，在该半导体块03的表面沉积栅氧材料(比如二氧化硅)形成栅氧层，在栅氧层的表面沉积金属材料得到栅极(G)，从而形成该VPT。该VPT详细的工艺流程可以参考现有技术，此处不再赘述。图11中的(d)和(e)中未示出该VPT的PN结、栅氧层和栅氧层侧面的金属材料。
进一步的，在该第二半导体块03的至少一部分侧面形成字线块07之后，在该金属块05远离该衬底01的一侧的表面、以及该第二半导体块03的侧面形成第二隔离块08。
其中，该第一隔离块06和第二隔离块08为绝缘层，该第一隔离块06和第二隔离块08的材料可以为氧化硅和氮化硅等，该第一隔离块06和该第二隔离块08统称为隔离块。
S04：在该第二半导体块03远离该第一半导体块02的一侧形成位线块09以得到该存储器，该位线块09为由金属材料制成。该存储器的切面结构如图11中的(e)所示。
具体的，在该第二半导体块03远离该第一半导体块02的一侧设置金属材料，得到位线块09，从而得到该存储器。其中，该金属材料可以包括钨或铜等。
其中，该存储器可以包括动态随机存取存储器。该储存器可以包括至少一个储存单元，该至少一个储存单元中的金属块05连通。
进一步的，该至少一个存储单元可以包括M×N个存储单元，该M×N个存储单元该中位于同一行的多个存储单元的位线块09连通，该M×N个存储单元中位于同一列的多个存储单元的字线块07连通，M和N为正整数。
图12为本申请实施例提供的另一种存储器的结构示意图，结合图11，如图12所示，在该第二半导体块03远离该第一半导体块02的一侧形成位线块09之前，在该第二半导体块03远离该第一半导体块02的一侧形成第三半导体块10，该第三半导体块10通过热反应生成，该第三半导体块10一般是金属硅化物，例如，该第三半导体块10为钛硅化物。
本申请实施例提供的制作方法可以应用于存储器的制作，在衬底上形成依次叠加设置的第一半导体层和第二半导体层，并基于该第一半导体层和该第二半导体层形成至少一个叠加设置的第一半导体块和第二半导体块，在该第一半导体块的至少一部分侧面形成介质，在该介质的侧面形成金属块，在该第二半导体块的至少一部分侧面形成字线块，在该第二半导体块远离该第一半导体块的一侧形成位线块，该位线块由金属材料制成，该结构下的储存单元的架构为4F 2，即该储存单元的面积为4F 2。本申请提供的储存单元的位线块由金属材料制成，与采用重掺杂的单晶硅作为位线的4F 2架构的储存单元相比，该位线块在高温工艺中具有较高的稳定性，从而保证了位线的可靠性和一致性，进一步保证了DRAM的性能。
基于此，本申请实施例还提供一种存储设备，该存储设备包括电路板、以及与电路板连接的存储器，该存储器可以为上文所提供的任一种存储器。其中，该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。可选的，该存储设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该存储设备还可以为基站等网络设备。
可选的，该存储设备还包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上，该存储器通过焊球固定于封装基板上。
基于此，本申请实施例还提供一种存储设备，该存储设备包括控制器和存储器，该控制器用于控制该存储器中的读写，该存储器可以为上文所提供的任一种存储器。
需要说明的是，关于该存储器的相关描述，具体可以参见上述图6-图7中关于存储器的描述，本申请实施例在此不再赘述。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构包括用于制造上文所提 供的任意一个存储器的光掩膜数据。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种存储器，其特征在于，所述存储器包括至少一个存储单元，每个所述存储单元包括依次叠加的第一半导体块、第二半导体块和位线块，所述位线块由金属材料制成；所述第一半导体块的至少一部分侧面上叠加设置有介质和金属块，所述介质处于所述第一半导体块和所述金属块之间，所述第二半导体块的至少一部分侧面设置有字线块。
  2. 根据权利要求1所述的存储器，其特征在于，所述存储单元还包括接地端，所述金属块被电性连接至所述接地端。
  3. 根据权利要求1或2所述的存储器，其特征在于，所述介质围绕所述第一半导体块的侧面一周设置。
  4. 根据权利要求1-3任一项所述的存储器，其特征在于，所述存储单元还包括第三半导体块，所述第三半导体块设置于所述第二半导体块与所述位线块之间。
  5. 根据权利要求4所述的存储器，其特征在于，所述第三半导体块是金属硅化物。
  6. 根据权利要求1-5任一项所述的存储器，其特征在于，所述存储器还包括隔离块，所述隔离块用于隔离相邻的两个所述存储单元。
  7. 根据权利要求1所述的存储器，其特征在于，所述至少一个存储单元中的所述金属块连通。
  8. 根据权利要求1-7任一项所述的存储器，其特征在于，所述第二半导体块包括垂直晶体管。
  9. 根据权利要求1-8任一项所述的存储器，其特征在于，所述至少一个存储单元包括M×N个所述存储单元，M×N个所述存储单元中位于同一行的多个所述存储单元的所述位线块连通，M×N个所述存储单元中位于同一列的多个所述存储单元的所述字线块连通，M和N为正整数。
  10. 根据权利要求1-9任一项所述的存储器，其特征在于，所述第一半导体块与所述第二半导体块的半导体类型不同。
  11. 根据权利要求1-10任一项所述的存储器，其特征在于，所述存储器包括动态随机存取存储器。
  12. 一种存储器的制作方法，其特征在于，所述方法包括：
    形成依次叠加设置的第一半导体层和第二半导体层，并基于所述第一半导体层和所述第二半导体层形成至少一个叠加设置的第一半导体块和第二半导体块；
    在所述第一半导体块的至少一部分侧面形成介质，在所述介质的侧面形成金属块；
    在所述第二半导体块的至少一部分侧面形成字线块；
    在所述第二半导体块远离所述第一半导体块的一侧形成位线块以得到包括至少一个存储单元的所述存储器，所述位线块由金属材料制成。
  13. 根据权利要求12所述的方法，其特征在于，所述介质围绕所述第一半导体块的侧面一周设置。
  14. 根据权利要求12或13所述的方法，其特征在于，在所述第二半导体块远离所述第一半导体块的一侧形成位线块之前，所述方法还包括：
    在所述第二半导体块远离所述第一半导体块的一侧形成第三半导体块。
  15. 根据权利要求14所述的方法，其特征在于，所述第三半导体块为金属硅化物。
  16. 根据权利要求12-15任一项所述的方法，其特征在于，所述在所述第一半导体块的至少一部分侧面形成介质之前，所述方法还包括：形成第一隔离块；
    所述在所述第二半导体块的至少一部分侧面形成字线块之后，所述方法还包括：在所述金属块的表面、以及所述第二半导体块的侧面形成第二隔离块。
  17. 根据权利要求12-16任一项所述的方法，其特征在于，所述在所述第二半导体块的至少一部分侧面形成字线块之前，所述方法还包括：
    在所述第二半导体块中形成垂直晶体管。
  18. 根据权利要求12-17任一项所述的方法，其特征在于，所述至少一个存储单元包括M×N个所述存储单元，M×N个所述存储单元中位于同一行的多个所述存储单元的所述位线块连通，M×N个所述存储单元中位于同一列的多个所述存储单元的所述字线块连通。
  19. 根据权利要求12-18任一项所述的方法，其特征在于，所述第一半导体层与所述第二半导体层的半导体类型不同。
  20. 根据权利要求12-19任一项所述的方法，其特征在于，所述存储器包括动态随机存取存储器。
  21. 根据权利要求12-20任一项所述的方法，其特征在于，所述存储单元包括接地端，所述金属块被电性连接至所述接地端。
  22. 一种存储设备，其特征在于，所述存储设备包括：电路板、以及与所述电路板连接的存储器，所述存储器为权利要求1-11任一项所述的存储器。
  23. 一种存储设备，其特征在于，所述存储设备包括控制器和存储器，所述控制器用于控制所述存储器的读写，所述存储器为权利要求1-11任一项所述的存储器。
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CN101933134A (zh) * 2008-01-29 2010-12-29 日本优尼山帝斯电子株式会社 半导体存储器件
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