WO2023065576A1 - 一种组网接入装置及系统 - Google Patents

一种组网接入装置及系统 Download PDF

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Publication number
WO2023065576A1
WO2023065576A1 PCT/CN2022/076747 CN2022076747W WO2023065576A1 WO 2023065576 A1 WO2023065576 A1 WO 2023065576A1 CN 2022076747 W CN2022076747 W CN 2022076747W WO 2023065576 A1 WO2023065576 A1 WO 2023065576A1
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WIPO (PCT)
Prior art keywords
signal
uplink
radio frequency
downlink
combiner
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PCT/CN2022/076747
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English (en)
French (fr)
Inventor
张德平
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普罗斯通信技术（苏州）有限公司
普罗斯技术（新泽西）有限公司
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Publication of WO2023065576A1 publication Critical patent/WO2023065576A1/zh
Priority to US18/349,575 priority Critical patent/US20230362849A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/401—Circuits for selecting or indicating operating mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1469—Two-way operation using the same type of signal, i.e. duplex using time-sharing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/18—Network planning tools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/18—Network planning tools
    • H04W16/20—Network planning tools for indoor coverage or short range network deployment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/02—Hybrid access

Definitions

  • the utility model relates to the field of mobile communication, in particular to a networking access device and system.
  • MIMO Multiple Input Multiple Output
  • LTE Long Term Evolution
  • 3G or 4G communication its indoor coverage system
  • ISISO single-input and single-output
  • a networking access device and system capable of realizing a MIMO networking access mode at the near end of a DAS system, and processing TDD switch signals.
  • a networking access device includes: a first signal transceiving port, used to transmit and receive a first radio frequency signal through multiple input and multiple output; a second signal transceiving port, used to transmit and receive a second radio frequency signal through a single input and single output mode; a signal processing unit for filtering and combining and/or splitting the first radio frequency signal and the second radio frequency signal, the signal processing unit is respectively connected to the first signal transceiving port and the second signal transceiving port; the synchronization unit is used for demodulation, analysis and modulation of the first
  • the radio frequency signal and the TDD switching signal in the second radio frequency signal are respectively connected to the synchronization unit with the first signal transceiving port, the second signal transceiving port, and the signal processing unit.
  • the signal processing unit includes: a first filter circuit connected to the first signal transceiving port; a second filter circuit connected to the second signal transceiving port; an uplink signal processing circuit; and a downlink signal processing circuit connected to the first filter circuit and the second filter circuit respectively.
  • the downlink signal processing circuit includes: a first downlink combiner connected to the second filter circuit, the first downlink combiner is used to combine the downlink radio frequency signal output by the second filter circuit and will pass through The downlink combiner signal generated by combining is output to the second downlink combiner; the second downlink combiner is connected to the first downlink combiner and the PLL element respectively, and the second downlink combiner is used for splitting the downlink combiner signal and the TDD switch signal of the synchronous unit input through the PLL element, and output the downlink split signal generated through the split to the third downlink combiner; and the third downlink combiner, combined with the second downlink
  • the filters are respectively connected to the first filter circuit, and the third downlink combiner is used to combine the downlink radio frequency signal output by the first filter circuit and the downlink split signal output by the second downlink splitter to generate a downlink output signal.
  • the uplink signal processing circuit includes: a first uplink power divider connected to the second filter circuit, the first uplink power divider is used for splitting the uplink combined signal output by the first uplink combiner and passing through The second uplink split signal generated by splitting is output to the second filter circuit; the first uplink combiner is connected to the first uplink power divider, and the first uplink combiner is used to combine the output of the second uplink combiner The first uplink split signal and output the generated uplink combiner signal to the first uplink power splitter; the second uplink combiner is connected to the first uplink combiner and the first filter circuit respectively, and the second uplink combiner The splitter is used to split the uplink radio frequency signal of the first radio frequency signal and the uplink radio frequency signal of the second radio frequency signal, and output the first uplink split signal generated by splitting to the first filter circuit and the first uplink combiner .
  • the first filtering circuit is a filter and the second filtering circuit is a filter or a duplexer.
  • the first signal transceiving port includes a 5G network port
  • the second signal transceiving port includes a 4G network port.
  • the second signal transceiving port further includes at least one of a 2G network port and a 3G network port.
  • the synchronization unit includes: a modulation and demodulation circuit, used to demodulate the TDD switch signal to output a pulse signal, and generate a modulated TDD switch signal; and a signal analysis circuit, connected to the modulation and demodulation circuit, to use It is used to analyze the pulse signal output by the modulation and demodulation circuit.
  • the modem circuit includes: a first modem connected to the first signal transceiving port for modulating and demodulating the TDD switch signal in the first radio frequency signal; a second modem connected to the second signal transceiving port connected for modulation and demodulation of the TDD switch signal in the second radio frequency signal.
  • the modulated TDD switching signal is output through the signal processing unit.
  • the signal analysis circuit includes: an MCU circuit for analysis and control of the pulse signal; and a CPLD circuit for analysis and calculation of the pulse signal.
  • a networking access system includes any network access device of the first aspect of the present disclosure.
  • the beneficial effects of the present disclosure include: by including the first signal transceiving port of multiple input and multiple output in the networking access device, the support for the radio frequency signal of MIMO is realized; by including the single input and single output in the networking access device
  • the second signal transmitting and receiving port realizes the support for the SISO radio frequency signal in the existing DAS system; by including the above two different transmitting and receiving ports in the networking access device, flexible networking can be realized.
  • a synchronization unit in the networking access device it is possible to demodulate and analyze the TDD switch signal in the radio frequency signal, and modulate and analyze the TDD switch signal to send it to the DAS system through the signal processing circuit.
  • the far end realizes the processing of the TDD switch signal at the near end of the DAS system. Further, the present disclosure saves the cost of the remote module in the DAS system.
  • FIG. 1 shows a schematic diagram of a network access device architecture 100 according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of a signal processing unit 200 according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of a downlink signal processing circuit 300 according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of an uplink signal processing circuit 400 according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a synchronization unit 500 according to an embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of a networking access device 600 according to an embodiment of the present disclosure
  • Fig. 7 shows a block diagram of a networking access system 700 according to an embodiment of the present disclosure.
  • the term “comprise” and its variants mean open inclusion, ie “including but not limited to”.
  • the term “or” means “and/or” unless otherwise stated.
  • the term “based on” means “based at least in part on”.
  • the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
  • the term “another embodiment” means “at least one further embodiment”.
  • the terms “first”, “second”, etc. may refer to a different or the same sample. Other definitions, both express and implied, may also be included below.
  • the indoor coverage system is only a single-line wiring design, which cannot provide network coverage for multiple standard network systems.
  • the key is to realize the MIMO technology of 5G communication, that is, at least two indoor signal coverage must be achieved in DAS. If the traditional design method is followed, or the existing DAS that only supports SISO is abandoned, and a new line is re-arranged, there will be problems of high renovation costs, and it will easily affect the existing properties, making the renovation difficult.
  • the existing DAS system puts the demodulation of the TDD switch signal at the remote end, and the cost is relatively high.
  • the networking access device includes multiple transceiver ports with different input and output modes.
  • the first transceiver port transmits and receives radio frequency signals in the way of multiple input and multiple output, realizing the support of MIMO radio frequency signals
  • the second transceiver port transmits and receives radio frequency signals in the mode of single input and single output, realizing the support of SISO radio frequency signals .
  • the networking access device also includes a synchronization unit, which can demodulate and analyze the TDD switching signal in the radio frequency signal, and modulate the analyzed TDD switching signal, so that the modulated TDD switching signal passes through the networking connection.
  • the signal processing circuit in the input device is sent to the remote end of the DAS system.
  • Fig. 1 shows a schematic diagram of a network access device architecture 100 according to an embodiment of the present disclosure.
  • the device includes a first signal transceiving port 102 , a second signal transceiving port 104 , a signal processing unit 108 and a synchronization unit 106 .
  • the first signal transceiving port 102 and the second signal transceiving port 104 are connected to the RRU 110 .
  • the signal processing unit 108 is connected to the first signal transceiving port 102 , the second signal transceiving port 104 and the DAS transmission medium 112 .
  • the synchronization unit 106 is connected to the first signal transceiving port 102 , the second signal transceiving port 104 and the signal processing unit 108 .
  • the first signal transceiving port 102 is used for transmitting and receiving the first radio frequency signal through multiple input and multiple output
  • the second signal transceiving port 104 is used for transmitting and receiving the second radio frequency signal through single input and single output.
  • the signal processing unit 108 is used for filtering and combining and/or splitting the first radio frequency signal and the second radio frequency signal, and the signal processing unit 108 is connected to the first signal transceiving port 102 and the second signal transceiving port 104 respectively.
  • depicted signal processing unit 108 may include additional functionality not shown and/or the functionality shown may be omitted, and that the scope of the present disclosure is not limited in this regard.
  • the synchronization unit 106 is connected to the first signal transceiving port 102 , the second signal transceiving port 104 and the signal processing unit 108 respectively.
  • the synchronization unit 106 respectively receives radio frequency signals from the first signal transceiving port 102 and the second signal transceiving port 104 to demodulate the TDD switching signals therein.
  • the synchronization unit 106 modulates the TDD switching signal and sends the TDD switching signal to the remote end of the DAS system through the connected signal processing unit 108 .
  • depicted synchronization unit 106 may include additional functionality not shown and/or may omit the functionality shown, and that the scope of the present disclosure is not limited in this respect.
  • the first signal transceiving port 102 includes a 5G network port
  • the second signal transceiving port 104 includes a 4G network port
  • the second signal transceiving port 104 further includes at least one of a 2G network port and a 3G network port.
  • FIG. 2 shows a schematic diagram of a signal processing unit 200 according to an embodiment of the present disclosure.
  • the signal processing unit 200 is connected to the first signal transceiving port 210 and the second signal transceiving port 212, respectively, for combining uplink radio frequency signals and splitting downlink radio frequency signals, and for The uplink radio frequency signal and the downlink radio frequency signal are filtered.
  • the signal processing unit 200 includes a first filter circuit 202 , a second filter circuit 206 , an uplink signal processing circuit 208 and a downlink signal processing circuit 204 .
  • depicted signal processing unit 200 may include additional functionality not shown and/or the functionality shown may be omitted, and that the scope of the present disclosure is not limited in this regard.
  • the first filtering circuit 202 is a filter and the second filtering circuit is a filter or a duplexer.
  • FIG. 3 shows a schematic diagram of a downlink signal processing circuit 300 according to an embodiment of the present disclosure.
  • the downlink signal processing circuit 300 is connected to the first filter circuit 312 , the first filter circuit 316 and the second filter circuit 314 , and the DAS transmission medium 318 respectively.
  • the downlink signal processing circuit 300 includes a first downlink combiner 302 connected to the second filter circuit 314, a second downlink combiner 306 connected to the first downlink combiner 302 and the PPL element 304, respectively, and a second downlink combiner 306 connected to the second filter circuit 314.
  • the downlink combiner 306 is connected to the third downlink combiner 308 respectively connected to the first filter circuit 312
  • the third downlink combiner 310 is connected to the second downlink combiner 306 and the first filter circuit 316 respectively.
  • the first downlink combiner 302 is used for combining downlink radio frequency signals filtered by the second filter circuit 314 .
  • the second downlink combiner 306 is used for splitting the output of the first downlink combiner 302 .
  • the third downlink combiner 308 and 310 combine the downlink radio frequency signal filtered by the first filter circuit 312 and 316 and the split output of the second downlink combiner, and the generated combined radio frequency signal is output to the DAS through the corresponding output port Transmission medium 318 in the system.
  • the described downlink signal processing circuit 300 may include additional functions not shown and/or may omit the functions shown, and the scope of the present disclosure is not limited in this respect.
  • FIG. 4 shows a schematic diagram of an uplink signal processing circuit 400 according to an embodiment of the present disclosure.
  • the uplink signal processing circuit 400 is connected to the first filter circuit 412 , the first filter circuit 416 and the second filter circuit 414 , and the DAS transmission medium 420 respectively.
  • the uplink signal processing circuit 400 includes a first uplink power divider 402 connected to the second filter circuit 414, a first uplink combiner 404 connected to the first uplink power divider 402, a first uplink combiner 404 and a first uplink combiner 404.
  • a filter circuit 416 is connected to the second uplink combiner 408 and the second uplink combiner 410 respectively.
  • the second uplink combiner 408 and the second uplink combiner 410 are used to split the uplink radio frequency signal transmitted through the transmission medium 420 in the DAS system, and output the generated first uplink split signal to the first filter circuit 416 and the first filter circuit 412 and the first uplink combiner 404 .
  • the first uplink combiner 404 is configured to combine the first uplink split signals of the second uplink combiners 408 and 410 and output the generated uplink combiner signal to the first uplink power divider 402 .
  • the first uplink power splitter 402 is used to split the uplink combined signal of the first uplink combiner 404 and output the generated second uplink split signal to the second filter circuit 414 .
  • uplink signal processing circuit 400 may include additional functions not shown and/or the shown functions may be omitted, and the scope of the present disclosure is not limited in this respect.
  • FIG. 5 shows a schematic diagram of a synchronization unit 500 according to an embodiment of the present disclosure.
  • the synchronization unit 500 is connected to the first signal transceiving port 508, the second signal transceiving port 510, and the signal processing unit 506, respectively, for modulating, demodulating, and analyzing downlink radio frequency signals. TDD switching signal.
  • the synchronization unit includes a modulation and demodulation circuit 504 and an analysis circuit 502 .
  • the synchronization unit 500 transmits the modulated TDD switch signal to the remote end of the DAS system by being connected to the downlink signal processing circuit of the signal processing unit 506 .
  • depicted synchronization unit 500 may include additional functionality not shown and/or may omit the functionality shown, and that the scope of the present disclosure is not limited in this regard.
  • Fig. 6 shows a schematic diagram of a network access device 600 according to an embodiment of the present disclosure.
  • the first signal transceiving port includes two radio frequency signal ports of the 5G network, and transmits and receives radio frequency signals in a multiple-input multiple-output manner.
  • the second signal transceiving port includes a 2G network, a 3G network and a 4G network transceiving port, and transmits and receives radio frequency signals in a single-input-single-output manner.
  • the 2-way 5G network uplink/downlink radio frequency signal ports of the first signal transceiving port are respectively connected to the corresponding filter elements of the first filter circuit, and the 6 radio frequency signal ports of different networks of the second signal transceiving port are respectively connected to the second filter circuit The corresponding filter elements are connected.
  • the first filter circuit and the second filter circuit are composed of package-compatible PA daughter boards.
  • the second filtering circuit may consist of diplexer elements.
  • the first downlink combiner is composed of a six-in-one combiner 614 for combining downlink radio frequency signals of the second transceiver port filtered by the second filter circuit.
  • the second downlink combiner is composed of two-in-one combiner elements and is used as a splitter to split the output of the first downlink combiner 614 .
  • the third downstream combiner is composed of two 2-in-1 combiner elements 622 and 630 .
  • Each combiner element is respectively connected to the first filter circuit 612, the first filter circuit 650 and the second downlink combiner 620, and combines the downlink radio frequency signals filtered by the first filter circuit 612, the first filter circuit 650 and The split output of the second downlink combiner 620 generates a combined radio frequency signal that is output to the transmission medium 646 in the DAS system through corresponding output ports.
  • the second uplink combiner is composed of two two-in-one combiner elements 642 and 644, and is used for splitting and transmitting the uplink radio frequency signal through the transmission medium 646 in the DAS system, and outputs the generated first uplink split signal to The first filter circuit 612 , the first filter circuit 650 and the first uplink combiner 640 .
  • the first uplink combiner 640 is composed of a two-in-one combiner element, which is used to combine the first uplink split signals of the second uplink combiners 642 and 644 and output the generated uplink combiner signal to the first uplink Power splitter 638.
  • the first uplink power splitter is composed of 638 six-in-one power splitters, which are used to split the uplink combining signal of the first uplink combiner 640 and output the generated second uplink splitting signal to the second filtering circuit. filter or duplexer.
  • the modulation and demodulation circuit includes a first modem 610 connected to the first signal transceiving port and a second modem 608 connected to the second signal transceiving port, which are used to demodulate the TDD switch signal in the downlink radio frequency signal to generate a pulse signal, and generate modulated TDD switching signal.
  • the first modem 610 is used for modulating and demodulating the first radio frequency signal
  • the second modem 608 is used for modulating and demodulating the second radio frequency signal.
  • the first signal transceiving port includes a 5G network port
  • the first modem 610 is used for modulating and demodulating 5G downlink radio frequency signals
  • the second signal transceiving port includes a 4G network port
  • the second modem 608 is used for modulating and demodulating 4G downlink radio frequency signals.
  • the pulse signal generated by the modulation and demodulation circuit is a square wave with a period of 10 ms or 5 ms, and the modulated TDD switching signal is generated by modulating the TDD switching signal to a fixed frequency.
  • the analysis circuit is connected with the modulation and demodulation circuit, and is used for analyzing the pulse signal output by the modulation and demodulation circuit.
  • the analysis circuit includes MCU602 and CPLD604.
  • the downlink radio frequency signal of the 5G standard is received through the two signal ports of the first signal transceiving port, and sent to the first filter circuit for filtering processing.
  • the filtered downlink radio frequency signal is sent to the third downlink combiner 622 and 630.
  • the downlink radio frequency signal of 2G, 3G and 4G standard is received through the corresponding 6 different signal ports of the second signal transceiver port, and sent to The second filtering circuit performs filtering processing.
  • the processed downlink radio frequency signal is sent to the first downlink combiner 614 for combining.
  • the combined downlink radio frequency signal is sent to the second downlink combiner 620 .
  • the second downlink combiner 620 splits the downlink radio frequency signals combined by the first downlink combiner 614, so as to send the combined downlink radio frequency signals to the combiners of the two third downlink combiners Elements 622 and 630.
  • the number of combiner elements in the third downlink combiner is quite corresponding to the number of ports in the first signal transceiver port, so as to combine the multiple 5G downlink radio frequency signals with the 2G, 3G and 4G signals output by the second downlink combiner Combined downlink radio frequency signals of different standards.
  • the multiple downlink radio frequency signals output by the combiner elements 622 and 630 in the third downlink combiner are transmitted to the far end of the DAS via multiple different transmission media 646 (for example, optical transmission modules) in the DAS system, and are transmitted by the remote end to the mobile terminal, so as to realize the multi-channel networking access of the downlink radio frequency signal.
  • multiple different transmission media 646 for example, optical transmission modules
  • the following describes the process of receiving uplink radio frequency signals through multiple channels through the network access device with reference to FIG. 6 .
  • the near end of the DAS system receives the uplink radio frequency signal transmitted from the far end of the DAS system through the transmission medium 646 through the networking access device
  • the combined uplink radio frequency signal of 2G, 3G, 4G and 5G standards is sent to the 2 combiner elements 642 and 644 in the second upstream combiner.
  • the two combiner elements 642 and 644 in the second uplink combiner split the uplink radio frequency signals to generate four uplink radio frequency signals, and send two of the uplink radio frequency signals to the first filter circuits 612 and 650, Send the other two radio frequency signals to the first uplink combiner 640 .
  • the uplink radio frequency signal is sent to two different 5G network ports in the first signal transceiving port.
  • the first uplink combiner 640 combines the two input uplink radio frequency signals, and then sends the combined uplink radio frequency signal to the first uplink power divider 638 .
  • the first uplink power divider 638 divides the input uplink radio frequency signal to generate six uplink radio frequency signals, and after being filtered by different filter elements of the corresponding second filter circuit, the signal is sent to the corresponding 2G channel in the second signal transceiver port. , 3G, 4G network standard transceiver ports, so as to realize the multi-channel networking access of uplink radio frequency signals.
  • the first modem 610 in the synchronization unit demodulates the switch frame header signal in the signal, and sends the demodulated square wave pulse signal with a period of 10 ms or 5 ms to the CPLD 604 for analysis.
  • the first modem 610 modulates the switch signal to a fixed frequency to obtain a modulated TDD switch signal, and sends the modulated TDD switch signal to multiple DAS systems via the upstream signal processing circuit of the signal processing unit.
  • a different transmission medium 646 (for example, an optical transmission module) is used to transmit to the far end of the DAS, so as to realize the processing of the TDD switching signal at the near end of the DAS system.
  • Fig. 7 shows a block diagram of a networking access system 700 according to an embodiment of the present disclosure.
  • the first signal transceiving port 702 is configured to transmit and receive a first radio frequency signal in a multiple-input multiple-output manner
  • the second signal transceiving port 704 is configured to transmit and receive a second radio frequency signal in a single-input-single-output manner
  • the signal processing module 708 is configured to filter and combine and/or split the first radio frequency signal and the second radio frequency signal, and the signal processing module 708 is connected to the first signal transceiving port 702 and the second signal transceiving port 704 respectively;
  • the synchronization module 706 is configured to demodulate, analyze and modulate the TDD switch signal in the first radio frequency signal and the second radio frequency signal, the synchronization module 706 is connected with the first signal transceiving port 702, the second signal transceiving port 704, and the signal processing module 708 connected separately.
  • networking access system 700 For other aspects of the networking access system 700, refer to the specific embodiments of the above-mentioned networking access device.

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Abstract

本公开的实施例涉及组网接入装置（100）及系统。该装置包括：第一信号收发端口（102），用于通过多输入多输出方式收发第一射频信号；第二信号收发端口（104），用于通过单输入单输出方式收发第二射频信号；信号处理单元（108），用于滤波以及合路和/或分路第一射频信号和第二射频信号，信号处理单元（108）与第一信号收发端口（102）、第二信号收发端口（104）分别相连；同步单元（106），用于调制、解调以及分析第一射频信号以及第二射频信号中的TDD开关信号，同步单元（106）与第一信号收发端口（102）、第二信号收发端口（104）、信号处理单元（108）分别相连。本公开能够实现MIMO的组网接入方式，同时实现在DAS系统的近端对TDD开关信号进行解调、分析以及调制，并且将TDD开关信号传输到DAS系统的远端。

Description

一种组网接入装置及系统 技术领域
本实用新型涉及移动通信领域，具体涉及一种组网接入装置及系统。
背景技术
随着互联网的发展，用户对于数据业务的需求日益增长，同时调查显示更多的数据业务高发于室内场景。多输入多输出(Multiple Input Multiple Output，MIMO)技术是长期演进(Long Term Evolution，LTE)提升系统容量的重要手段之一，但目前无论是2G通信还是3G、4G通信，其室内覆盖系统(DAS)都只是单路布线设计，即单入单出(single-input and single-output，SISO)，无法支持多输入多输出。
然而，随着5G通信的崛起，其慢慢占据了越来越大的市场份额，网络普及率也越来越高，在对5G网络进行网络优化的过程中，关键是要实现5G通信的MIMO技术，即必须在DAS中达到至少两路室内信号覆盖。
若依照传统设计方法，或者摒弃已有的仅支持SISO的DAS，重新布置全新的线路，都会出现改造成本高的问题，同时还容易对现有的物业带来影响，改造难度大。并且现有DAS系统将TDD开关信号的解调放在远端模块，成本较高。
实用新型内容
提供了一种组网接入装置及系统，能够在DAS系统的近端实现MIMO的组网接入方式，以及针对TDD开关信号进行处理。
根据本公开的第一方面，提供了一种组网接入装置。该装置包括：第一信号收发端口，用于通过多输入多输出方式收发第一射频信号；第二信号收发端口，用于通过单输入单输出方式收发第二射频信号； 信号处理单元，用于滤波以及合路和/或分路第一射频信号和第二射频信号，信号处理单元与第一信号收发端口、第二信号收发端口分别相连；同步单元，用于解调、分析以及调制第一射频信号以及第二射频信号中的TDD开关信号，同步单元与第一信号收发端口、第二信号收发端口、信号处理单元分别相连。
在一些实施例中，信号处理单元包括：与第一信号收发端口相连的第一滤波电路；与第二信号收发端口相连的第二滤波电路；与第一滤波电路和第二滤波电路分别相连的上行信号处理电路；以及与第一滤波电路和第二滤波电路分别相连的下行信号处理电路。
在一些实施例中，下行信号处理电路包括：第一下行合路器，与第二滤波电路相连，第一下行合路器用于合路第二滤波电路输出的下行射频信号并且将将经由合路而生成的下行合路信号输出到第二下行合路器；第二下行合路器，与第一下行合路器和PLL元件分别相连，第二下行合路器用于分路下行合路信号和通过PLL元件输入的同步单元的TDD开关信号，并且将经由分路而生成的下行分路信号输出到第三下行合路器；以及第三下行合路器，与第二下行合路器和第一滤波电路分别相连，第三下行合路器用于合路第一滤波电路输出的下行射频信号和第二下行分路器输出的下行分路信号以便生成下行输出信号。
在一些实施例中，上行信号处理电路包括：第一上行功分器，与第二滤波电路相连，第一上行功分器用于分路第一上行合路器输出的上行合路信号并且将经由分路而生成的第二上行分路信号输出到第二滤波电路；第一上行合路器，与第一上行功分器相连，第一上行合路器用于合路第二上行合路器输出的第一上行分路信号并且将生成的上行合路信号输出到第一上行功分器；第二上行合路器，与第一上行合路器和第一滤波电路分别相连，第二上行合路器用于分路第一射频信号的上行射频信号和第二射频信号的上行射频信号，并且将经由分路而生成的第一上行分路信号输出到第一滤波电路和第一上行合路器。
在一些实施例中，第一滤波电路是滤波器，第二滤波电路是滤波 器或者双工器。
在一些实施例中，第一信号收发端口包括5G网络端口，第二信号收发端口包括4G网络端口。
在一些实施例中，第二信号收发端口还包括2G网络端口和3G网络端口中的至少一种。
在一些实施例中，同步单元包括：调制解调电路，用于解调TDD开关信号以输出脉冲信号，以及生成经调制的TDD开关信号；以及信号分析电路，与调制解调电路相连，以用于分析调制解调电路所输出的脉冲信号。
在一些实施例中，调制解调电路包括：第一调制解调器，与第一信号收发端口相连，以用于调制解调第一射频信号中的TDD开关信号；第二调制解调器，与第二信号收发端口相连，以用于调制解调第二射频信号中的TDD开关信号。
在一些实施例中，经调制的TDD开关信号通过信号处理单元输出。
在一些实施例中，信号分析电路包括：MCU电路，用于脉冲信号的分析控制；以及CPLD电路，用于脉冲信号的分析计算。
根据本公开的第二方面，提供了一种组网接入系统。该系统包括本公开的第一方面的任一组网接入装置。
本公开的有益效果包括：通过在组网接入装置中包括多输入多输出的第一信号收发端口，实现了对MIMO的射频信号的支持；通过在组网接入装置中包括单输入单输出的第二信号收发端口，实现了对现有DAS系统中SISO的射频信号的支持；通过在组网接入装置中包括上述两种不同的收发端口，可以实现灵活组网。另一方面，通过在组网接入装置中包括同步单元，可以实现对射频信号中的TDD开关信号的解调、分析，并且调制分析后的TDD开关信号以通过信号处理电路发送到DAS系统的远端，实现了TDD开关信号在DAS系统近端的处理。进一步的，本公开节省DAS系统中远端模块的成本。
应当理解，本部分所描述的内容并非旨在标识本公开的实施例的关键或者重要特征，也不用于限制本公开的范围。本公开的其它特征 将通过以下的说明书而变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标注表示相同或相似的元素。
图1示出了根据本公开的实施例的组网接入装置架构100的示意图；
图2示出了根据本公开的实施例的信号处理单元200的示意图；
图3示出了根据本公开的实施例的下行信号处理电路300的示意图；
图4示出了根据本公开的实施例的上行信号处理电路400的示意图；
图5示出了根据本公开的实施例的同步单元500的示意图；
图6示出了根据本公开的实施例的组网接入装置600的示意图；
图7示出了根据本公开的实施例的组网接入系统700的框图。
具体实施方式
以下结合附图对本公开的示范性实施例做出说明，其中包括本公开实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本公开的范围和精神。同样，为了清楚和简明，以下的描述中省略了对公知功能和结构的描述。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“第一”、“第二”等等可以指代不同的或相同的样本。下文还可能包括其他明确的和隐含的定义。
如上所描述，目前无论是2G通信还是3G、4G通信，其室内覆 盖系统(DAS)都只是单路布线设计，无法针对多个制式网络系统进行网络覆盖。但随着5G通信的崛起，关键的是需要实现5G通信的MIMO技术，即必须在DAS中达到至少两路室内信号覆盖。若依照传统设计方法，或者摒弃已有的仅支持SISO的DAS，重新布置全新的线路，都会出现改造成本高的问题，同时还容易对现有的物业带来影响，改造难度大。同时现有DAS系统将TDD开关信号解调放在远端，成本较高。
为了至少部分地解决上述问题以及其他潜在问题中的一个或者多个，本公开的示例实施例提出了一种组网接入装置。在该方案中，组网接入装置包括不同输入输出方式的多个收发端口。其中第一收发端口以多输入多输出的方式收发射频信号，实现了对MIMO的射频信号的支持，第二收发端口以单输入单输出的方式收发射频信号，实现了对SISO的射频信号的支持。通过在组网接入装置中包括上述两种不同的收发端口，可以实现在同一DAS中以不同方式灵活组网。另一方面，组网接入装置中还包括同步单元，可以对射频信号中的TDD开关信号进行解调、分析，并且调制分析后的TDD开关信号，使得调制后的TDD开关信号通过组网接入装置中的信号处理电路被发送到DAS系统的远端。通过上述技术方案，该组网接入装置实现了在DAS系统中对MIMO射频信号的支持和与现有SISO射频信号的灵活组网，并且实现了在DAS系统近端中处理TDD开关信号。另外，本公开还节省DAS系统中远端模块的成本。
在下文中，将结合附图更详细地描述本方案的具体示例。为了便于理解，在下文描述中提及的具体数据均是示例性的，并不用于限定本公开的保护范围。
图1示出了根据本公开的实施例的组网接入装置架构100的示意图。如图1所示，装置包括第一信号收发端口102、第二信号收发端口104、信号处理单元108和同步单元106。第一信号收发端口102，第二信号收发端口104与RRU110相连接。信号处理单元108与第一信号收发端口102、第二信号收发端口104以及DAS传输介质112相连。同步单元106与第一信号收发端口102、第二信号收发端口104 以及信号处理单元108相连。
第一信号收发端口102用于通过多输入多输出方式收发第一射频信号,第二信号收发端口104用于通过单输入单输出方式收发第二射频信号。
信号处理单元108用于滤波以及合路和/或分路第一射频信号和第二射频信号，信号处理单元108与第一信号收发端口102、第二信号收发端口104分别相连。
应当理解，所描述的信号处理单元108可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
同步单元106与第一信号收发端口102，第二信号收发端口104，信号处理单元108分别相连。同步单元106从第一信号收发端口102，第二信号收发端口104分别接收射频信号以解调其中的TDD开关信号。在分析该TDD开关信号之后，同步单元106调制该TDD开关信号并且通过连接的信号处理单元108将该TDD开关信号发送到DAS系统的远端。
应当理解，所描述的同步单元106可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
在一些实施例中，第一信号收发端口102包括5G网络端口，第二信号收发端口104包括4G网络端口。在一些实施例中，第二信号收发端口104还包括2G网络和3G网络端口中的至少一种。
图2示出了根据本公开的实施例的信号处理单元200的示意图。如图2所示，在一些实施例中，信号处理单元200与第一信号收发端口210以及第二信号收发端口212分别相连，用于合路上行射频信号，以及分路下行射频信号，并且对上行射频信号和下行射频信号进行滤波处理。信号处理单元200包括第一滤波电路202、第二滤波电路206、上行信号处理电路208以及下行信号处理电路204。
应当理解，所描述的信号处理单元200可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
在一些实施例中，第一滤波电路202是滤波器，第二滤波电路是 滤波器或者双工器。
图3示出了根据本公开的实施例的下行信号处理电路300的示意图。如图3所示，在一些实施例中，下行信号处理电路300与第一滤波电路312、第一滤波电路316和第二滤波电路314、DAS传输介质318分别相连。下行信号处理电路300包括与第二滤波电路314相连的第一下行合路器302、与第一下行合路器302以及PPL元件304分别相连的第二下行合路器306、与第二下行合路器306和第一滤波电路312分别相连的第三下行合路器308、与第二下行合路器306和第一滤波电路316分别相连的第三下行合路器310。第一下行合路器302用于合路经由第二滤波电路314滤波的下行射频信号。第二下行合路器306用以分路第一下行合路器302的输出。第三下行合路器308和310合路经由第一滤波电路312和316滤波的下行射频信号和第二下行合路器的分路输出，生成的合路射频信号经由相应的输出端口输出到DAS系统中的传输媒介318。
应当理解，所描述的下行信号处理电路300可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
图4示出了根据本公开的实施例的上行信号处理电路400的示意图。如图4所示，在一些实施例中，上行信号处理电路400与第一滤波电路412、第一滤波电路416和第二滤波电路414、DAS传输介质420分别相连。上行信号处理电路400包括与第二滤波电路414相连的第一上行功分器402、与第一上行功分器402相连的第一上行合路器404、与第一上行合路器404和第一滤波电路416分别相连的第二上行合路器408和第二上行合路器410。第二上行合路器408和第二上行合路器410用于分路经由DAS系统中的传输媒介420传输的上行射频信号，并且将生成的第一上行分路信号输出到第一滤波电路416和第一滤波电路412以及第一上行合路器404。第一上行合路器404用于合路第二上行合路器408和410的第一上行分路信号并且将生成的上行合路信号输出到第一上行功分器402。第一上行功分器402 用于分路第一上行合路器404的上行合路信号并且将生成的第二上行分路信号输出到第二滤波电路414。
应当理解，所描述的上行信号处理电路400可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
图5示出了根据本公开的实施例的同步单元500的示意图。如图5所示，在一些实施例中，同步单元500与第一信号收发端口508、第二信号收发端口510以及信号处理单元506分别相连，用于调制、解调以及分析下行射频信号中的TDD开关信号。同步单元包括调制解调电路504和分析电路502。同步单元500通过与信号处理单元506的下行信号处理电路相连，将调制的TDD开关信号传输到DAS系统的远端。
应当理解，所描述的同步单元500可以包括未示出的附加功能和/或可以省略所示出的功能，本公开的范围在此方面不受限制。
图6示出了根据本公开的实施例的组网接入装置600的示意图。如图6所示，在一些实施例中，第一信号收发端口包括5G网络的2路射频信号端口，通过多输入多输出方式收发射频信号。第二信号收发端口包括2G网络、3G网络以及4G网络收发端口，通过单输入单输出方式收发射频信号。
第一信号收发端口的2路5G网络上行/下行射频信号端口分别与第一滤波电路的相应滤波器元件相连，并且第二信号收发端口的6路不同网络的射频信号端口分别与第二滤波电路的相应的滤波器元件相连。
在一些实施例中，第一滤波电路和第二滤波电路通过封装兼容的PA子板组成。第二滤波电路可以由双工器元件组成。
第一下行合路器由六合一合路器614组成，用于合路经由第二滤波电路滤波的第二收发端口的下行射频信号。第二下行合路器由二合一合路器元件组成，被作为分路器使用以分路第一下行合路器614的输出。第三下行合路器由2个二合一合路器元件622和630组成。每 个合路器元件分别连接到第一滤波电路612、第一滤波电路650和第二下行合路器620，并且合路经由第一滤波电路612、第一滤波电路650滤波的下行射频信号和第二下行合路器620的分路输出，生成的合路射频信号经由相应的输出端口输出到DAS系统中的传输媒介646。
第二上行合路器由2个二合一合路器元件642和644组成，用于分路经由DAS系统中的传输媒介646传输上行射频信号，并且将生成的第一上行分路信号输出到第一滤波电路612、第一滤波电路650和第一上行合路器640。第一上行合路器640由二合一合路器元件组成，用于合路第二上行合路器642和644的第一上行分路信号并且将生成的上行合路信号输出到第一上行功分器638。第一上行功分器由638六合一功分器组成，用于分路第一上行合路器640的上行合路信号并且将生成的第二上行分路信号输出到第二滤波电路中的不同滤波器或者双工器。
调制解调电路包括与第一信号收发端口相连的第一调制解调器610以及与第二信号收发端口相连的第二调制解调器608，用于解调下行射频信号中的TDD开关信号以生成脉冲信号，并且生成调制的TDD开关信号。第一调制解调器610用于调制解调第一射频信号，第二调制解调器608用于调制解调第二射频信号。第一信号收发端口包括5G网络端口，第一调制解调器610用于调制解调5G下行射频信号，第二信号收发端口包括4G网络端，第二调制解调器608用于调制解调4G下行射频信号。
在一些实施例中，调制解调电路生成的脉冲信号是以10ms或者5ms为周期的方波，并且通过将TDD开关信号调制到固定的频率以生成调制的TDD开关信号。分析电路与调制解调电路相连，用于分析调制解调电路输出的脉冲信号。分析电路包括MCU602和CPLD604。
以下结合图6说明经由组网接入装置以实现多通道发送下行射频信号的过程。
如图6所示，不同的RRU信号经由组网接入装置接入DAS系统。5G制式的下行射频信号经由第一信号收发端口的2路信号端口接收，并且发送到第一滤波电路进行滤波处理。滤波处理后的下行射频信号被发送到第三下行合路器622和630。2G、3G以及4G制式的下行射频信号经由第二信号收发端口的相应的6路不同的信号端口接收，并且发送给第二滤波电路进行滤波处理。处理后的下行射频信号被发送到第一下行合路器614进行合路。合路后的下行射频信号被发送到第二下行合路器620。第二下行合路器620将第一下行合路器614合路后的下行射频信号进行分路，以将合路后的下行射频信号发送到2个第三下行合路器的合路器元件622和630。第三下行合路器中的合路器元件的数量与第一信号收发端口中的端口数量相当对应，以将多路5G下行射频信号分别与第二下行合路器输出的2G、3G以及4G制式的合路下行射频信号进行合路。第三下行合路器中的合路器元件622和630输出的多路下行射频信号经由DAS系统中多个不同的传输介质646(例如，光传输模块)传输到DAS的远端，并且由远端发送到移动终端，从而实现下行射频信号的多通道组网接入。
以下结合图6说明经由组网接入装置以实现多通道接收上行射频信号的过程。
如图6所示，当DAS系统近端通过组网接入装置接收从DAS系统远端经由传输媒介646传输的上行射频信号时，2G、3G、4G以及5G制式的合路上行射频信号被发送到第二上行合路器中的2个合路器元件642和644。第二上行合路器中的2个合路器元件642和644对上行射频信号进行分路，生成4路上行射频信号，并且将其中2路上行射频信号发送到第一滤波电路612和650，将另外2路射频信号发送到第一上行合路器640。第一滤波电路中的2个滤波器元件612和650对上行射频信号进行滤波后，将上行射频信号发送到第一信号收发端口中的两路不同的5G网络端口。另一方面，第一上行合路器640将2路输入的上行射频信号进行合路，之后将合路的上行射频信号发送到第一上行功分器638。第一上行功分器638将输入的上行射 频信号进行分路，生成6路上行射频信号，并且经由相应的第二滤波电路的不同滤波元件滤波后，发送到第二信号收发端口中相应的2G、3G、4G网络制式的收发端口，从而实现上行射频信号的多通道组网接入。
以下结合图6说明经由组网接入装置以实现调制解调以及传输TDD开关信号的过程。
如图6所示，5G制式的下行射频信号经由第一信号收发端口的2路信号端口接收后，一部分信号被发送到同步单元。同步单元中的第一调制解调器610对信号中的开关帧头信号进行解调，并且将解调出的以10ms或者5ms为周期的方波脉冲信号发送到CPLD604进行分析。在CPLD604分析之后，第一调制解调器610将开关信号调制到固定的频率以得到调制后的TDD开关信号，并且经由信号处理单元的上行信号处理电路将调制后的TDD开关信号发送到DAS系统中多个不同的传输介质646(例如，光传输模块)以传输到DAS的远端，从而实现TDD开关信号在DAS系统近端的处理。
图7示出了根据本公开的实施例的组网接入系统700的框图。
第一信号收发端口702，被配置为通过多输入多输出方式收发第一射频信号；
第二信号收发端口704，被配置为通过单输入单输出方式收发第二射频信号；
信号处理模块708，被配置为滤波以及合路和/或分路第一射频信号和第二射频信号，信号处理模块708与第一信号收发端口702、第二信号收发端口704分别相连；
同步模块706，被配置为解调、分析以及调制第一射频信号以及第二射频信号中的TDD开关信号，同步模块706与第一信号收发端口702、第二信号收发端口704、信号处理模块708分别相连。
组网接入系统700的其他方面参照上述组网接入装置的具体实施例。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非 穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或者对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (12)

  1. 一种组网接入装置，其特征在于，包括：
    第一信号收发端口，用于通过多输入多输出方式收发第一射频信号；
    第二信号收发端口，用于通过单输入单输出方式收发第二射频信号；
    信号处理单元，用于滤波以及合路和/或分路所述第一射频信号和第二射频信号，所述信号处理单元与所述第一信号收发端口、所述第二信号收发端口分别相连；
    同步单元，用于解调、分析以及调制所述第一射频信号以及所述第二射频信号中的TDD开关信号，所述同步单元与所述第一信号收发端口、所述第二信号收发端口、所述信号处理单元分别相连。
  2. 根据权利要求1所述的组网接入装置，其特征在于，所述信号处理单元包括：
    与所述第一信号收发端口相连的第一滤波电路；
    与所述第二信号收发端口相连的第二滤波电路；
    与所述第一滤波电路和所述第二滤波电路分别相连的上行信号处理电路；以及
    与所述第一滤波电路和所述第二滤波电路分别相连的下行信号处理电路。
  3. 根据权利要求2所述的组网接入装置，其特征在于，所述下行信号处理电路包括：
    第一下行合路器，与所述第二滤波电路相连，所述第一下行合路器用于合路第二滤波电路输出的下行射频信号并且将经由合路而生成的下行合路信号输出到第二下行合路器；
    第二下行合路器，与所述第一下行合路器和PLL元件分别相连，所述第二下行合路器用于分路所述下行合路信号和通过PLL元件输入的所述同步单元的所述TDD开关信号，并且将经由分路而生成的 下行分路信号输出到所述第三下行合路器；以及
    第三下行合路器，与所述第二下行合路器和所述第一滤波电路分别相连，所述第三下行合路器用于合路所述第一滤波电路输出的下行射频信号和所述第二下行分路器输出的所述下行分路信号以便生成下行输出信号。
  4. 根据权利要求2所述的组网接入装置，其特征在于，所述上行信号处理电路包括：
    第一上行功分器，与所述第二滤波电路相连，所述第一上行功分器用于分路第一上行合路器输出的上行合路信号并且将经由分路而生成的第二上行分路信号输出到所述第二滤波电路；
    第一上行合路器，与所述第一上行功分器相连，所述第一上行合路器用于合路第二上行合路器输出的第一上行分路信号并且将经由合路而生成的上行合路信号输出到所述第一上行功分器；以及
    第二上行合路器，与所述第一上行合路器和所述第一滤波电路分别相连，所述第二上行合路器用于分路所述第一射频信号的上行射频信号和所述第二射频信号的上行射频信号，并且将经由分路而生成的第一上行分路信号输出到所述第一滤波电路和所述第一上行合路器。
  5. 根据权利要求2所述的组网接入装置，其特征在于，所述第一滤波电路是滤波器，所述第二滤波电路是滤波器或者双工器。
  6. 根据权利要求1所述的组网接入装置，其特征在于，所述第一信号收发端口包括5G网络端口，所述第二信号收发端口包括4G网络端口。
  7. 根据权利要求6所述的组网接入装置，其特征在于，所述第二信号收发端口还包括2G网络端口和3G网络端口中的至少一种。
  8. 根据权利要求1所述的组网接入装置，其特征在于，所述同步单元包括：
    调制解调电路，用于解调所述TDD开关信号以输出脉冲信号，以及生成经调制的TDD开关信号；以及
    信号分析电路，与所述调制解调电路相连，以用于分析所述调制 解调电路所输出的所述脉冲信号。
  9. 根据权利要求8所述的组网接入装置，其特征在于，所述调制解调电路包括：
    第一调制解调器，与所述第一信号收发端口相连，以用于调制解调所述第一射频信号中的TDD开关信号；
    第二调制解调器，与所述第二信号收发端口相连，以用于调制解调所述第二射频信号中的TDD开关信号。
  10. 根据权利要求8所述的组网接入装置，其特征在于，所述经调制的TDD开关信号通过所述信号处理单元输出。
  11. 根据权利要求8所述的组网接入装置，其特征在于，所述信号分析电路包括：
    MCU电路，用于所述脉冲信号的分析控制；以及
    CPLD电路，用于所述脉冲信号的分析计算。
  12. 一种组网接入系统，其特征在于，包括权利要求1至11任一项所述的组网接入装置。
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