WO2023065143A1 - 显示面板的驱动方法及显示装置 - Google Patents

显示面板的驱动方法及显示装置 Download PDF

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Publication number
WO2023065143A1
WO2023065143A1 PCT/CN2021/124944 CN2021124944W WO2023065143A1 WO 2023065143 A1 WO2023065143 A1 WO 2023065143A1 CN 2021124944 W CN2021124944 W CN 2021124944W WO 2023065143 A1 WO2023065143 A1 WO 2023065143A1
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Prior art keywords
sub
pixels
row
picture
display
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PCT/CN2021/124944
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English (en)
French (fr)
Inventor
帅孟超
肖利军
李冰
张峻敏
江峰
冯蒙
向建民
杨子铭
白鋆
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/124944 priority Critical patent/WO2023065143A1/zh
Priority to CN202180002990.0A priority patent/CN116348807A/zh
Publication of WO2023065143A1 publication Critical patent/WO2023065143A1/zh
Priority to US18/604,355 priority patent/US20240221602A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving method of a display panel and a display device.
  • Displays such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) generally include a plurality of pixels. Each pixel may include: a red sub-pixel, a green sub-pixel and a blue sub-pixel. By controlling the display data corresponding to each sub-pixel, the display brightness of each sub-pixel is controlled, so as to display the color image by mixing the required displayed colors.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • control the display panel When it is determined that the second picture is a bad picture, control the display panel to scan and drive at least one row of sub-pixels apart, and in the two rows of sub-pixels that are scanned and driven, the first row of sub-pixels is driven and the second row of sub-pixels is completely driven.
  • the data lines connected to the sub-pixels in the second row are loaded with display data corresponding to the sub-pixels in the second row.
  • the bad picture determination condition includes: a set area threshold of the bad area and a set gray scale difference threshold between the gray scales of the display data corresponding to two adjacent sub-pixels in the same column;
  • the determining that the second picture is a bad picture specifically includes:
  • the target area satisfies the set area threshold, it is determined that the second picture is a bad picture.
  • the determining the target area formed by the sub-pixels corresponding to the display data satisfying the set difference threshold in the display data of the second picture specifically includes:
  • All of the target cell groups form the target region.
  • the display panel is controlled to scan and drive at least one row of sub-pixels apart, and in the two rows of sub-pixels that are scanned and driven, when the first row of sub-pixels is driven and the second row of sub-pixels is being driven, the The data lines connected to the sub-pixels in the second row load the display data of the second picture, specifically including:
  • the display panel is controlled to scan and drive at least one row of sub-pixels, and in the two rows of sub-pixels that are scanned and driven, the first row of sub-pixels is driven and the second row of sub-pixels is completely driven.
  • the data lines connected to the sub-pixels in the second row are loaded with the display data of the second picture.
  • the display panel is controlled to scan and drive at least one row of sub-pixels apart, and in the two rows of sub-pixels that are scanned and driven, when the first row of sub-pixels is driven and the second row of sub-pixels is being driven, the The data lines connected to the sub-pixels in the second row load the display data of the second picture, specifically including:
  • control the sub-pixels in the even-numbered row of the display panel to scan and drive, and output display data corresponding to the sub-pixels in the even-numbered row to each of the data lines.
  • controlling the display panel to scan and drive at least one row of sub-pixels includes:
  • control the sub-pixels in the even-numbered row of the display panel to scan and drive, and output the display data corresponding to the sub-pixels in the even-numbered row to each of the data lines;
  • control the sub-pixels in the odd-numbered row of the display panel to scan and drive, and output display data corresponding to the sub-pixels in the odd-numbered row to each of the data lines.
  • the second picture is a bad picture according to the display data of the second picture and a bad picture determination condition.
  • the timing controller is configured to receive the first picture in the current display frame of the second picture when the first picture is switched to the second picture and the second picture is displayed in at least two consecutive display frames.
  • the display data of two pictures according to the display data of the second picture and the bad picture determination condition, determine whether the second picture is a bad picture; when it is determined that the second picture is a bad picture, send to the display panel
  • the gate drive circuit of the input interlace scan control signal and the source drive circuit in the display panel input the interlace data control signal to control the display panel to scan and drive at least one row of sub-pixels, and to scan and drive two rows of sub-pixels In the pixel, when the sub-pixels in the first row are driven and the sub-pixels in the second row are being driven, the data lines connected to the sub-pixels in the second row are loaded with display data corresponding to the sub-pixels in the second row.
  • the timing controller is further configured to input a progressive scan control signal to a gate drive circuit in the display panel and to input a progressive scan control signal to the display panel when determining that the second picture is not a bad picture
  • the source driving circuit in the circuit inputs a row-by-row data control signal to control the row-by-row sub-pixels of the display panel to scan and drive, and load the display data corresponding to each row of sub-pixels to each of the data lines.
  • the timing controller is coupled to the source driving circuit through a general-purpose input-output interface
  • the timing controller is further configured to output the interlaced data control signal as the interlaced data control signal by setting the drive enable pin of the general-purpose input and output interface to an interlaced drive active level; and by setting the general-purpose The drive enable pin of the input and output interface is set to drive the active level progressively, so as to output as the progressive data control signal;
  • the source driving circuit is further configured to generate an interlaced data output signal when it detects that the level of the drive enable pin is an active level for interlaced driving, and according to the generated interlaced data output signal, to the second
  • the data line connected to the sub-pixels in the row loads the display data corresponding to the sub-pixels in the second row; and when it is detected that the level of the driving enable pin is an active level for progressive driving, a progressive data output signal is generated, and According to the generated progressive data output signal, the display data corresponding to each row of sub-pixels is loaded to each of the data lines.
  • the timing controller is further configured to switch the level of the drive enable pin from a first level to a second level as the active level of the interlaced drive; and set the The level of the driving enable pin maintains the first level as the active level of the progressive driving;
  • the source drive circuit is further configured to compare the voltage corresponding to the level of the drive enable pin with the stored set voltage threshold, where the voltage corresponding to the level of the drive enable pin is higher than When the voltage threshold is set, the interlaced data output signal is generated; when the voltage corresponding to the level of the driving enable pin is not higher than the set voltage threshold, the progressive data output signal is generated.
  • the timing controller is coupled to the level conversion circuit through a general-purpose input-output interface
  • the timing controller is further configured to output the first setting bit with the first number and the second setting bit with the first number and the second number through the input and output interface of the general-purpose, as The interlaced data control signal output; and by using the input and output of the general-purpose type with the first setting bit of the second number as the progressive drive enable signal output;
  • the source drive circuit is further configured to generate the interlaced data output signal according to the second set bit when detecting that the first set bit is a first number; When the first set bit is the second number, the progressive data output signal is generated.
  • Fig. 1a is some structural schematic diagrams of a display device in an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of a drive enable pin in an embodiment of the present disclosure
  • FIG. 1c is another structural schematic diagram of a display device in an embodiment of the present disclosure.
  • FIG. 2 is a flowchart of a driving method in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a bad area in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a target area of a second screen in an embodiment of the present disclosure.
  • Fig. 5a is some schematic diagrams of a second frame determined as a bad frame in an embodiment of the present disclosure
  • Fig. 5b is another schematic diagram of a second frame determined as a bad frame in an embodiment of the present disclosure
  • Fig. 5c is still some schematic diagrams of the second picture determined as a bad picture in the embodiment of the present disclosure.
  • Fig. 5d is still some schematic diagrams of the second picture determined as a bad picture in the embodiment of the present disclosure.
  • Fig. 5e is still some schematic diagrams of the second picture determined as a bad picture in the embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of some signals in an embodiment of the present disclosure.
  • FIG. 7 is another timing diagram of signals in an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of some other signals in the embodiment of the present disclosure.
  • the display device may include a display panel 100 , a level shift (Level Shift) circuit 200 and a timing controller 300 .
  • the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines (for example, GA1, GA2, GA3, GA4), a plurality of data lines (for example, DA1, DA2, DA3), a gate driving circuit 110 and source drive circuit 120.
  • the gate driving circuit 110 is coupled to the gate lines GA1 , GA2 , GA3 , GA4 respectively
  • the source driving circuit 120 is coupled to the data lines DA1 , DA2 , DA3 respectively.
  • each pixel unit includes a plurality of sub-pixels SPX.
  • a pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that color mixing can be performed through red, green, blue and white to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the practical application environment, which is not limited here.
  • each sub-pixel includes a transistor 01 and a pixel electrode 02 .
  • one row of sub-pixels corresponds to one gate line
  • one column of sub-pixels corresponds to one data line.
  • the gate of the transistor 01 is electrically connected to the corresponding gate line
  • the source of the transistor 01 is electrically connected to the corresponding data line
  • the drain of the transistor 01 is electrically connected to the pixel electrode 02.
  • the pixel array structure of the present disclosure can also be It is a double-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, there are data lines between two adjacent columns of pixels, and some adjacent two rows of pixels.
  • the data lines are not included between the pixels in the columns, and the specific arrangement structure of the pixels and the data lines, and the arrangement manner of the scanning lines are not limited.
  • the driving method of the display panel provided by the embodiment of the present disclosure may include the following steps:
  • S30 Control the display panel to scan and drive at least one row of sub-pixels at intervals, and in the two rows of sub-pixels that are scanned and driven, when the first row of sub-pixels is driven and the second row of sub-pixels is being driven, the second row of sub-pixels connected
  • the data lines load the display data corresponding to the sub-pixels in the second row.
  • the display panel when the first screen is switched to the second screen, it can be indicated that the display panel has switched screens.
  • the second picture is displayed in at least two consecutive display frames, which means that the display panel can maintain the display of the same picture within a certain period of time, for example, the displayed second picture can be a static picture.
  • the display data of the second picture can be analyzed according to the bad picture judgment conditions, and whether the second picture is a bad picture can be determined.
  • the display panel can be controlled to scan and drive at least one row of sub-pixels apart, and in the two rows of sub-pixels that are scanned and driven, when the first row of sub-pixels is driven and the second row of sub-pixels is being driven , loading the display data corresponding to the sub-pixels in the second row to the data lines connected to the sub-pixels in the second row.
  • the timing controller may be configured to: when the first picture is switched to the second picture and the second picture is displayed in at least two consecutive display frames, in the current display frame of the second picture Receive the display data of the second picture; determine whether the second picture is a bad picture according to the display data of the second picture and the judgment condition of the bad picture; when it is determined that the second picture is a bad picture, input the The interlaced scanning control signal and the interlaced data control signal input to the source drive circuit in the display panel control the display panel to scan and drive at least one row of sub-pixels, and in the two rows of sub-pixels that are scanned and driven, the first row of sub-pixels When the driving is completed and the subpixels in the second row are being driven, the data lines connected to the subpixels in the second row are loaded with display data corresponding to the subpixels in the second row.
  • the two rows of sub-pixels here refer to the two rows corresponding to the open gate lines, such as interlaced scanning driving
  • the two rows of sub-pixels here can refer to The sub-pixels in the first row and the third row; that is, when the scanning signal including the active level is input interlacedly, for example, the first row inputs the scanning signal including the active level, and the third row inputs the scanning signal including the active level, then
  • the display data is to input the display data in the first row, and the third row to input the display data.
  • the continuous output of the first row and the second row is the first row display data
  • the third row and The fourth line continuously outputs the display data of the third line, so when the second picture is displayed, when the timing controller determines that the second picture is a bad picture, by enabling the interlaced driving mode, at least one line can be separated
  • the pixel displays the picture, and the sub-pixels in the remaining rows are in the black state, and the sub-pixel row in the black state no longer displays the corresponding picture, so it can avoid the gray scale caused by insufficient charging time of the pixel and the corresponding two adjacent rows of sub-pixels in the same column. The difference is large, resulting in poor picture problems.
  • the timing controller 300 is connected to the gate drive circuit 110 through the level conversion circuit 200, and the timing controller 300 and the source drive circuit 120 can be connected through a general-purpose input and output (General Purpose Input Output, GPIO) interface coupling to transmit signals through the GPIO interface.
  • GPIO General Purpose Input Output
  • a driving enable pin OE_EN of the GPIO interface coupled between the timing controller and the source driving circuit 120 is schematically shown.
  • 120 represents the source drive circuit
  • 12 represents the printed circuit board (Printed Circuit Board, PCB)
  • 13 represents the flexible circuit board (Flexible Printed Circuit, FPC)
  • 14 represents the timing circuit board where the timing controller is located.
  • a resistor NS may be provided on the printed circuit board 12 to improve the pull-up driving capability of the drive enable pin OE_EN.
  • the resistance value of the resistor NS may be 4.7K ⁇ , of course, the resistance value of the resistor NS may also be determined according to the requirements of practical applications, which is not limited herein.
  • a timing controller may be provided on the timing circuit board, which can reduce integration difficulty.
  • Two timing controllers (for example, one as a master timing controller and the other as a slave timing controller) can also be set on the timing circuit board to improve the driving capability and computing capability, which is beneficial for high refresh rates (such as 120Hz, 240Hz etc.) in the display panel.
  • the timing controller 300 can set the driving enable pin OE_EN of the general-purpose input and output interface to an active level of interlaced driving, so as to output it as an interlaced data control signal. And, when the source driving circuit detects that the level of the drive enable pin OE_EN is an active level for interlaced driving, it can generate an interlaced data output signal, and connect the second row of sub-pixels according to the generated interlaced data output signal. The data line loads the display data corresponding to the second row of sub-pixels.
  • the active level of interlaced driving is high level, and when the source drive circuit detects that the level of the drive enable pin OE_EN is high level, it can generate an interlaced data output signal, thereby inputting a corresponding signal to the data line in the display panel. display data.
  • the timing controller can switch the level of the driving enable pin OE_EN from the first level to the second level as the active level of the interlaced driving.
  • the source drive circuit can compare the voltage corresponding to the level of the drive enable pin OE_EN with the stored set voltage threshold, and when the voltage corresponding to the level of the drive enable pin OE_EN is higher than the set voltage threshold , generating the interlaced data output signal (tp shown in FIG. 6 and FIG. 7). For example, if the active level of interlaced driving is high level, the first level may be low level and the second level may be high level. H stands for high level and L stands for high level. Referring to FIG. 1a to FIG. 1c and FIG. 6 and FIG.
  • the display data of the second picture and the judgment condition of the bad picture are input into the data comparison module to determine whether the second picture is a bad picture.
  • the drive enable pin OE_EN is the active level of interlaced drive.
  • the source drive circuit can compare the voltage corresponding to H of the drive enable pin OE_EN with the stored set voltage threshold through the voltage comparator, and when the voltage corresponding to H is higher than the set voltage threshold, the source drive can be enabled
  • the working mode corresponding to the interlaced data control signal in the circuit so that the source drive circuit outputs the display data to the buffer through the CDES receiver under the control of the interlaced data control signal, so as to output the display data to the data line through the buffer, thereby Realize interlaced output of corresponding display data to the data lines in the display panel.
  • the timing controller also outputs an interlaced scanning control signal (stv-od, stv-ev as shown in FIG. 6 and FIG.
  • tp represents the interlaced data output signal, signal tp, can be rising edge latch data, falling edge output data, or can be falling edge latch data, rising edge output data, accompanying drawing Only the rising edge is shown to latch the data, and the falling edge is to output the data.
  • the set voltage threshold can be determined according to the requirements of practical applications, and is not limited here.
  • the timing controller when the timing controller determines that the second picture is not a bad picture, it can control the display panel to scan and drive the sub-pixels row by row, and load the display data corresponding to each row of sub-pixels to each data line, so that the display Each sub-pixel in the panel performs data refresh.
  • the timing controller determines that the second picture is not a defective picture
  • the progressive scan control signal may be input to the gate drive circuit through the level conversion circuit, and the progressive data control signal may be input to the source drive circuit, so as to The display panel is controlled to scan and drive row-by-row sub-pixels, and the display data corresponding to each row of sub-pixels is loaded to each data line.
  • the active level of row-by-row driving is low level, and when the source driving circuit detects that the level of the drive enable pin OE_EN is low level, it can load the display data corresponding to each row of sub-pixels to each of the data lines.
  • the timing controller judges that the second picture is not a defective picture
  • the progressive data control signal is input to the source drive circuit to enable the operation mode corresponding to the progressive data control signal, so that the source drive circuit can respond accordingly.
  • the display panel when displaying the second picture, the sub-pixels can be driven row by row to display the picture, thereby improving the display resolution.
  • the timing controller can set the driving enable pin OE_EN of the GPIO interface to the active level of the progressive driving, so as to output it as the progressive data control signal.
  • the source drive circuit can generate a progressive data output signal (tp as shown in FIG. 8 ) when it detects that the level of the drive enable pin OE_EN is the active level of the progressive drive, and according to the generated progressive data Outputting signals, loading the display data corresponding to each row of sub-pixels to each of the data lines.
  • the active level of the progressive driving is low level, and when the source driving circuit detects that the level of the driving enable pin OE_EN is low level, the progressive data output signal can be generated.
  • the timing controller may keep the level of the driving enable pin OE_EN at the first level as the active level of the row-by-row driving.
  • the source driving circuit can generate the progressive data output signal when the voltage corresponding to the level of the driving enable pin OE_EN is not higher than the preset voltage threshold. For example, if the active level of the row-by-row driving is low, then the first level can be made low. L stands for high level.
  • the display data of the second picture and the judgment condition of the bad picture are input into the data comparison module to determine whether the second picture is a bad picture.
  • the drive enable pin OE_EN When it is determined that the second picture is not a defective picture, set the drive enable pin OE_EN to a voltage corresponding to L, for example, keep the drive enable pin OE_EN at a voltage corresponding to L, which can illustrate outputting a progressive data control signal.
  • the source drive circuit can compare the voltage corresponding to L of the drive enable pin OE_EN with the stored set voltage threshold through the voltage comparator, and when the voltage corresponding to L is lower than the set voltage threshold, the source drive can be enabled
  • the circuit corresponds to the working mode of the progressive data control signal, so that the source drive circuit can generate a progressive data output signal (tp as shown in FIG. 8 ).
  • the source drive circuit outputs the display data to the buffer through the CDES receiver under the control of the progressive data output signal, so as to output the display data to the data line through the buffer, thereby realizing interlaced output to the data line in the display panel corresponding display data.
  • the timing controller also outputs progressive scan control signals (stv-od, stv-ev shown in FIG. 8 ) to the gate drive circuit through the level conversion circuit, so as to drive the gate lines row by row, and then drive the display panel.
  • the bad picture determination conditions may be stored in the timing controller.
  • the bad picture determination condition may include: a set area threshold of the bad area.
  • P represents a picture displayed on the display panel, the lower left corner of the picture P is taken as the origin O(0,0), the lower edge of the picture P is taken as the horizontal axis x, and the left edge of the picture P is taken as the vertical axis Axis y.
  • the coordinates of the four top corners of the bad area BW are: upper left corner coordinate Z1 (x1, y2), lower left corner coordinate Z2 (x1, y1), lower right corner coordinate Z3 (x2, y1 ), coordinates Z4(x2, y2) of the upper right corner.
  • x1 and x2 can be selected from 0 to A according to the setting of x2>x1
  • y1 and y2 can be selected according to the setting of y2>y1. Select from 0 ⁇ B.
  • the area of the defective area in the screen can be set to 1/4 of the original screen.
  • x1, x2, y1 and y2 are selected from other values, so that the area of the defective area in the picture is set to be 1/4 of the original picture.
  • x1, x2, y1 and y2 are selected from other values, so that the area of the defective area in the picture is set to 1/2 of the original picture.
  • x1, x2, y1 and y2 are selected from other values, so that the area of the defective area in the picture is set to 1/3 of the original picture.
  • the specific values selected for x1, x2, y1, and y2 may be determined according to requirements of practical applications, and are not limited here.
  • the defective area may also be a circle, an ellipse, a polygon, etc., which is not limited here.
  • the condition for judging a bad picture may further include: a set gray scale difference threshold between gray scales of display data corresponding to two adjacent sub-pixels in the same column.
  • the set gray scale difference threshold may be selected from 10-150 gray scales.
  • the grayscale difference threshold can be set to 150 grayscales
  • the grayscale difference threshold can be set to 127 grayscales
  • the grayscale difference threshold can also be set to 100 grayscales
  • the grayscale difference threshold can also be set to 100 grayscales.
  • the grayscale difference threshold can also be set to grayscale 63
  • the grayscale difference threshold can be set to grayscale 50
  • the grayscale difference threshold can also be set to grayscale 10.
  • the gray scale difference threshold can be set according to the requirements of practical applications, which is not limited here.
  • determining that the second picture is a bad picture may specifically include: determining a target area formed by sub-pixels corresponding to display data satisfying the set gray scale difference threshold in the display data of the second picture. When the target area satisfies the set area threshold, it is determined that the second picture is a bad picture. In this way, whether the second picture is a bad picture is judged by two conditions included in the bad picture judging conditions, which can improve the accuracy of judging that the second picture is a bad picture. Exemplarily, in the display data of the second frame, the target area formed by the sub-pixels corresponding to the display data not smaller than the set gray scale difference threshold is determined.
  • the target area is not smaller than the set area threshold, it is determined that the second frame is a defective frame.
  • the sub-pixels corresponding to the display data not less than the set gray scale difference threshold can be preliminarily screened out to form the target area, and then by comparing the target area with the set area threshold, the target area is not less than the set area threshold , it can be determined that the second picture is a bad picture, so that the accuracy of determining that the second picture is a bad picture can be improved.
  • Sba represent the position of each sub-pixel of the display panel
  • a and b are both integers, 1 ⁇ a ⁇ A, 1 ⁇ b ⁇ B.
  • the sub-pixels in the first row to the tenth row in the first column are respectively S11-S101
  • the sub-pixels in the first row to the tenth row in the second column are They are respectively S12 ⁇ S102
  • the sub-pixels in the first row to the tenth row in the third column are respectively S13-S103
  • the sub-pixels in the first row to the tenth row in the fourth column are respectively S14-S104
  • the sub-pixels in the fifth column are the first
  • the sub-pixels from the first row to the tenth row are respectively S15-S105
  • the sub-pixels from the first row to the tenth row in the sixth column are respectively S16-S106
  • the sub-pixels from the first row to the tenth row in the seventh column are respectively
  • the difference between the grayscales of the display data corresponding to the sub-pixels S11 and S21 is smaller than the set grayscale difference threshold, and the difference between the grayscales of the display data corresponding to the sub-pixels S31 and S41 is also smaller than Set the gray scale difference threshold, the difference between the gray scales of the display data corresponding to the sub-pixels S51 and S61 is not less than the set gray scale difference threshold, the gray scale of the display data corresponding to the sub-pixels S71 and S81
  • the difference threshold is not less than the set gray scale difference threshold, and the difference threshold between the gray scales of the display data corresponding to the sub-pixels S91 and S101 is not less than the set gray scale difference threshold.
  • the difference between the gray scales of the display data corresponding to the sub-pixels S12 and S22 is smaller than the set gray scale difference threshold, and the difference between the gray scales of the display data corresponding to the sub-pixels S32 and S42 Also less than the set gray scale difference threshold, the difference between the gray scales of the display data corresponding to the sub-pixels S52 and S62 is not less than the set gray scale difference threshold, and the gray scale difference between the display data corresponding to the sub-pixels S72 and S82
  • the difference threshold between the sub-pixels S92 and S102 is not less than the set gray scale difference threshold, and the difference threshold between the gray scales of the display data corresponding to the sub-pixels S92 and S102 is not less than the set gray scale difference threshold.
  • the difference between the gray scales of the display data corresponding to the sub-pixels S13 and S23 is smaller than the set gray scale difference threshold, and the difference between the gray scales of the display data corresponding to the sub-pixels S33 and S43 is also smaller than the set gray scale difference threshold, the difference between the gray scales of the display data corresponding to the sub-pixels S53 and S63 is not less than the set gray scale difference threshold, and the gray scale difference between the display data corresponding to the sub-pixels S73 and S83
  • the difference threshold between the sub-pixels S93 and S103 is not less than the set gray scale difference threshold, and the difference threshold between the gray scales of the display data corresponding to the sub-pixels S93 and S103 is not less than the set gray scale difference threshold.
  • the difference between the gray scales of the display data corresponding to the sub-pixels in two adjacent rows in the same column are all smaller than the set gray scale difference threshold.
  • the timing controller may determine that the second frame is a defective frame. If the area of the target area M1 is smaller than the set area threshold, the target area M1 may be made too small to be easily perceived by human eyes, and the timing controller may determine that the second frame is not a defective frame.
  • determining the target area formed by the sub-pixels corresponding to the display data that satisfies the set difference threshold in the display data of the second screen may specifically include: using at least one column of pixel units in at least two adjacent rows As a unit group, the pixel unit in the display panel is divided into a plurality of unit groups. For the display data corresponding to each unit group, the gray scale difference between the gray scales of the display data corresponding to two adjacent rows of sub-pixels in the same column is determined. When the gray scale difference satisfies the set gray scale difference threshold, the unit group in which the sub-pixel corresponding to the gray scale difference satisfying the set gray scale difference threshold is defined as the target unit group. All target cell groups form a target region. In this way, by setting the unit group, at least two pixel units can be used as the minimum unit to screen the target area, reducing the amount of calculation and power consumption.
  • a pixel unit includes three sub-pixels, and a column of pixel units in two adjacent rows is taken as a unit group.
  • sub-pixels S11, S12, S13, S21, S22, and S23 are used as the first unit group
  • sub-pixels S31, S32, S33, S41, S42, and S43 are used as the second unit group.
  • the sub-pixels S51, S52, S53, S61, S62, S63 serve as the third unit group.
  • the sub-pixels S71, S72, S73, S81, S82, and S83 serve as the fourth unit group.
  • the sub-pixels S91, S92, S93, S101, S102, and S103 serve as the fifth unit group. If in the first unit group, the difference between the gray scales of the display data corresponding to the sub-pixels S11 and S21, the difference between the gray scales of the display data corresponding to the sub-pixels S12 and S22, and the difference between the gray scales of the display data corresponding to the sub-pixels S13 and S23 If the differences between the gray scales of the corresponding display data are all smaller than the set gray scale difference threshold, then the first unit group does not need to be defined as the target unit group. For the same reason, it is not necessary to define the second unit group as the target unit group.
  • the gray scale corresponding to the sub-pixel S51 is greater than the gray scale corresponding to the sub-pixel S61, the difference between the gray scales of the display data corresponding to the sub-pixels S51 and S61 is not less than the set gray scale difference threshold .
  • the gray scale corresponding to the sub-pixel S52 is greater than the gray scale corresponding to the sub-pixel S62, and the difference between the gray scales of the display data corresponding to the sub-pixels S52 and S62 is not less than the set gray scale difference threshold.
  • the gray scale corresponding to the sub-pixel S53 is greater than the gray scale corresponding to the sub-pixel S63, and the difference between the gray scales of the display data corresponding to the sub-pixel S53 and S63 is not less than the set gray scale difference threshold, then the third unit can be Groups are defined as target cell groups. Similarly, the fourth unit group and the fifth unit group are defined as target unit groups.
  • the sub-pixels S14, S15, S16, S24, S25, S26 are used as the sixth unit group, and the sub-pixels S34, S35, S36, S44, S45, S46 are used as the seventh unit group.
  • the sub-pixels S54, S55, S56, S64, S65, and S66 serve as the eighth unit group.
  • the sub-pixels S74, S75, S76, S84, S85, and S86 serve as the ninth unit group.
  • the sub-pixels S94, S95, S96, S104, S105, and S106 serve as the tenth unit group.
  • the sixth unit group If in the sixth unit group, the difference between the gray scales of the display data corresponding to the sub-pixels S14 and S24, the difference between the gray scales of the display data corresponding to the sub-pixels S15 and S25, and the difference between the gray scales of the display data corresponding to the sub-pixels S16 and S26 If the differences between the gray scales of the corresponding display data are all smaller than the set gray scale difference threshold, then the sixth unit group does not need to be defined as the target unit group. Similarly, it is not necessary to define the seventh unit group as the target unit group.
  • the gray scale corresponding to the sub-pixel S54 is smaller than the gray scale corresponding to the sub-pixel S64, the difference between the gray scales of the display data corresponding to the sub-pixels S54 and S64 is not less than the set gray scale difference threshold .
  • the grayscale corresponding to the sub-pixel S55 is smaller than the grayscale corresponding to the sub-pixel S65, and the difference between the grayscales of the display data corresponding to the sub-pixels S55 and S65 is not less than the set grayscale difference threshold.
  • the gray scale corresponding to the sub-pixel S56 is smaller than the gray scale corresponding to the sub-pixel S66, and the difference between the gray scales of the display data corresponding to the sub-pixel S56 and S66 is not less than the set gray scale difference threshold, then the eighth unit can be Groups are defined as target cell groups. Similarly, the ninth unit group and the tenth unit group are defined as target unit groups.
  • the sub-pixels S17, S18, S19, S27, S28, and S29 are used as the eleventh unit group, and the sub-pixels S37, S38, S39, S47, S48, and S49 are used as the twelfth unit group .
  • the sub-pixels S57, S58, S59, S67, S68, and S69 serve as the thirteenth unit group.
  • the sub-pixels S77, S78, S79, S87, S88, and S89 serve as the fourteenth unit group.
  • the sub-pixels S97, S98, S99, S107, S108, and S109 serve as the fifteenth unit group.
  • the gray scale corresponding to the sub-pixel S57 is greater than the gray scale corresponding to the sub-pixel S67, the difference between the gray scales of the display data corresponding to the sub-pixels S57 and S67 is not less than the set gray scale difference threshold.
  • the gray scale corresponding to the sub-pixel S58 is greater than the gray scale corresponding to the sub-pixel S68, and the difference between the gray scales of the display data corresponding to the sub-pixels S58 and S68 is not less than the set gray scale difference threshold.
  • the grayscale corresponding to the sub-pixel S59 is greater than the grayscale corresponding to the sub-pixel S69, and the difference between the grayscales of the display data corresponding to the sub-pixels S59 and S69 is not less than the set grayscale difference threshold, then the thirteenth A cell group is defined as a target cell group. Similarly, define the fourteenth unit group and the fifteenth unit group as the target unit group to form the target area M1. Also, the rest of the unit groups need not be defined as target unit groups.
  • sub-pixels S11, S12, S13, S21, S22, and S23 are used as the first unit group, and sub-pixels S31, S32, S33, S41, S42, and S43 as the second unit group.
  • the sub-pixels S51, S52, S53, S61, S62, S63 serve as the third unit group.
  • the sub-pixels S71, S72, S73, S81, S82, and S83 serve as the fourth unit group.
  • the sub-pixels S91, S92, S93, S101, S102, and S103 serve as the fifth unit group.
  • the sub-pixels S14, S15, S16, S24, S25, and S26 are used as the sixth unit group, and the sub-pixels S34, S35, S36, S44, S45, and S46 are used as the seventh unit group.
  • the sub-pixels S54, S55, S56, S64, S65, and S66 serve as the eighth unit group.
  • the sub-pixels S74, S75, S76, S84, S85, and S86 serve as the ninth unit group.
  • the sub-pixels S94, S95, S96, S104, S105, and S106 serve as the tenth unit group.
  • the sub-pixels S17, S18, S19, S27, S28, S29 are used as the eleventh unit group, and the sub-pixels S37, S38, S39, S47, S48, S49 are used as the twelfth unit group.
  • the sub-pixels S57, S58, S59, S67, S68, and S69 serve as the thirteenth unit group.
  • the sub-pixels S77, S78, S79, S87, S88, and S89 serve as the fourteenth unit group.
  • the sub-pixels S97, S98, S99, S107, S108, and S109 serve as the fifteenth unit group.
  • the rest of the division unit groups can be obtained in the same way.
  • the third unit group can be defined as the target unit group.
  • the fourth unit group and the fifth unit group are defined as target unit groups.
  • the eighth unit group, the ninth unit group, the tenth unit group, the thirteenth unit group, the fourteenth unit group and the fifteenth unit group are defined as the target unit group to form the target Area M1.
  • sub-pixels S11, S12, S13, S21, S22, and S23 are used as the first unit group, and sub-pixels S31, S32, S33, S41, S42, and S43 as the second unit group.
  • the sub-pixels S51, S52, S53, S61, S62, S63 serve as the third unit group.
  • the sub-pixels S71, S72, S73, S81, S82, and S83 serve as the fourth unit group.
  • the sub-pixels S91, S92, S93, S101, S102, and S103 serve as the fifth unit group.
  • the sub-pixels S14, S15, S16, S24, S25, and S26 are used as the sixth unit group, and the sub-pixels S34, S35, S36, S44, S45, and S46 are used as the seventh unit group.
  • the sub-pixels S54, S55, S56, S64, S65, and S66 serve as the eighth unit group.
  • the sub-pixels S74, S75, S76, S84, S85, and S86 serve as the ninth unit group.
  • the sub-pixels S94, S95, S96, S104, S105, and S106 serve as the tenth unit group.
  • the sub-pixels S17, S18, S19, S27, S28, S29 are used as the eleventh unit group, and the sub-pixels S37, S38, S39, S47, S48, S49 are used as the twelfth unit group.
  • the sub-pixels S57, S58, S59, S67, S68, and S69 serve as the thirteenth unit group.
  • the sub-pixels S77, S78, S79, S87, S88, and S89 serve as the fourteenth unit group.
  • the sub-pixels S97, S98, S99, S107, S108, and S109 serve as the fifteenth unit group.
  • the rest of the division unit groups can be obtained in the same way.
  • the gray scale corresponding to the sub-pixel S51 is greater than the gray scale corresponding to the sub-pixel S61, the difference between the gray scales of the display data corresponding to the sub-pixels S51 and S61 is not less than the set gray scale difference threshold .
  • the gray scale corresponding to the sub-pixel S52 is greater than the gray scale corresponding to the sub-pixel S62, and the difference between the gray scales of the display data corresponding to the sub-pixels S52 and S62 is not less than the set gray scale difference threshold.
  • the gray scale corresponding to the sub-pixel S53 is greater than the gray scale corresponding to the sub-pixel S63, and the difference between the gray scales of the display data corresponding to the sub-pixel S53 and S63 is not less than the set gray scale difference threshold, then the third unit can be Groups are defined as target cell groups.
  • the fourth unit group and the fifth unit group are defined as target unit groups.
  • the eighth unit group, the ninth unit group, the tenth unit group, the thirteenth unit group, the fourteenth unit group and the fifteenth unit group are defined as the target unit group to form the target Area M1.
  • sub-pixels S11, S12, S13, S21, S22, and S23 are used as the first unit group, and sub-pixels S31, S32, S33, S41, S42, and S43 as the second unit group.
  • the sub-pixels S51, S52, S53, S61, S62, S63 serve as the third unit group.
  • the sub-pixels S71, S72, S73, S81, S82, and S83 serve as the fourth unit group.
  • the sub-pixels S91, S92, S93, S101, S102, and S103 serve as the fifth unit group.
  • the sub-pixels S14, S15, S16, S24, S25, and S26 are used as the sixth unit group, and the sub-pixels S34, S35, S36, S44, S45, and S46 are used as the seventh unit group.
  • the sub-pixels S54, S55, S56, S64, S65, and S66 serve as the eighth unit group.
  • the sub-pixels S74, S75, S76, S84, S85, and S86 are used as the ninth unit group.
  • the sub-pixels S94, S95, S96, S104, S105, and S106 serve as the tenth unit group.
  • the sub-pixels S17, S18, S19, S27, S28, S29 are used as the eleventh unit group, and the sub-pixels S37, S38, S39, S47, S48, S49 are used as the twelfth unit group.
  • the sub-pixels S57, S58, S59, S67, S68, and S69 serve as the thirteenth unit group.
  • the sub-pixels S77, S78, S79, S87, S88, and S89 serve as the fourteenth unit group.
  • the sub-pixels S97, S98, S99, S107, S108, and S109 serve as the fifteenth unit group.
  • the rest of the division unit groups can be obtained in the same way.
  • the third unit group can be defined as the target unit group.
  • the fourth unit group and the fifth unit group are defined as target unit groups.
  • the eighth unit group, the ninth unit group, the tenth unit group, the thirteenth unit group, the fourteenth unit group and the fifteenth unit group are defined as the target unit group to form the target Area M1.
  • a pixel unit includes three sub-pixels, and a column of pixel units in four adjacent rows is taken as a unit group.
  • sub-pixels S11, S12, S13, S21, S22, S23, S31, S32, S33, S41, S42, S43 are used as the first unit group, and sub-pixels S51, S52 , S53, S61, S62, S63, S71, S72, S73, S81, S82, S83 as the second unit group.
  • sub-pixels S91, S92, S93, S101, S102, S103, S111, S112, S113, S121, S122, S123 serve as the third unit group.
  • sub-pixels S14, S15, S16, S24, S25, S26, S34, S35, S36, S44, S45, and S46 are used as the fourth unit group, and sub-pixels S54, S55, S56, S64, and S65 , S66, S74, S75, S76, S84, S85, S86 as the fifth unit group.
  • sub-pixels S94, S95, S96, S104, S105, S106, S114, S115, S116, S124, S125, S126 serve as the sixth unit group.
  • sub-pixels S17, S18, S19, S27, S28, S29, S37, S38, S39, S47, S48, and S49 are used as the seventh unit group, and sub-pixels S57, S58, S59, S67, and S68 , S69, S77, S78, S79, S87, S88, S89 as the eighth unit group.
  • the sub-pixels S97, S98, S99, S107, S108, S109, S117, S118, S119, S127, S128, S129 serve as the ninth unit group.
  • the rest are divided into unit groups in the same way.
  • the first unit group, the second unit group, the fourth unit group, the fifth unit group, the seventh unit group, and the eighth unit group can be defined as the target unit group according to the above rules to form the target area M1 .
  • the target area M1 is formed by the target cell group. Afterwards, the area of the target area M1 may be compared with the set area threshold, and if the area of the target area M1 is not smaller than the set area threshold, it is determined that the second frame is a defective frame. If the area of the target area M1 is smaller than the set area threshold, the target area M1 may be made too small to be easily perceived by human eyes, and it may be determined that the second frame is not a defective frame. In this way, the sub-pixels of the display panel can be controlled to scan and drive row by row, and the display data of the second picture can be loaded to each data line, so that each sub-pixel in the display panel can perform data refresh.
  • the control display panel scans and drives at least one row of sub-pixels, and in the two rows of sub-pixels that are scanned and driven, when the first row of sub-pixels is driven and the second row of sub-pixels is being driven, The data lines connected to the sub-pixels in the second row are loaded with the display data of the second picture.
  • the display panel can be controlled to scan and drive row-by-row sub-pixels in the current display frame, and the display data of the second picture can be loaded to each data line, so that each sub-pixel in the display panel can perform data refresh. That is, in the current display frame, each row of sub-pixels is controlled to be turned on normally, and the timing controller needs one display frame time to determine whether the second picture is a bad picture, so that it can be used to determine whether the second picture is a bad picture in the current display frame.
  • some rows of sub-pixels may be controlled to be turned on, and some rows of sub-pixels shall be in a black state. In this way, the screen display and the judgment process can be performed at the same time, without making the judgment process take up extra time.
  • the timing controller can determine whether the second picture is a bad picture in the first display frame of the second picture, and determine whether the second picture is a bad picture in the second display frame and the second display frame of the second picture. Interlaced driving is performed in subsequent display frames.
  • the pictures can be displayed through successive display frames. Wherein, the first picture is displayed in the first display frame of the video, the first picture is also displayed in the second display frame, the first picture is also displayed in the third display frame, and the second picture is displayed in the fourth display frame , the second picture is also displayed in the fifth display frame, the second picture is also displayed in the sixth display frame, the second picture is also displayed in the seventh display frame, the second picture is also displayed in the eighth display frame, etc. wait. In this way, the timing controller can determine whether the second picture is a defective picture in the fourth display frame, and perform interlaced driving in the fifth display frame, the sixth display frame, the seventh display frame, and the eighth display frame.
  • the display panel may be controlled to scan and drive the sub-pixels at intervals of one row, or the display panel may be controlled to scan and drive the sub-pixels at intervals of two rows.
  • the sub-pixels in odd-numbered rows are controlled to perform scan driving.
  • the first row of sub-pixels and the third row of sub-pixels can be used as two rows of sub-pixels for scanning drive.
  • the second row of sub-pixels is connected The data line loads the display data corresponding to the second row of sub-pixels.
  • the sub-pixels in the third row and the sub-pixels in the fifth row can be used as two rows of sub-pixels for scan driving. At this time, when the sub-pixels in the third row are driven and the sub-pixels in the fifth row are being driven, the data lines connected to the sub-pixels in the fifth row are loaded Display data corresponding to the fifth row of sub-pixels.
  • the fifth row of sub-pixels and the seventh row of sub-pixels can be used as two rows of sub-pixels for scanning drive. At this time, when the fifth row of sub-pixels is driven and the seventh row of sub-pixels is being driven, the data lines connected to the seventh row of sub-pixels Load the display data corresponding to the seventh row of sub-pixels. The rest can be deduced in the same way, and will not be repeated here.
  • the sub-pixels in the even-numbered row are controlled to perform scan driving in one display frame. Then the sub-pixels of the second row and the sub-pixels of the fourth row can be used as two rows of sub-pixels for scan driving. At this time, when the sub-pixels of the second row are driven and the sub-pixels of the fourth row are being driven, the sub-pixels of the fourth row are connected The data line loads the display data corresponding to the fourth row of sub-pixels. The sub-pixels in the fourth row and the sub-pixels in the sixth row can be used as two rows of sub-pixels for scan driving.
  • the sub-pixels connected to the sixth row The data lines load the display data corresponding to the sixth row of sub-pixels.
  • the sixth row of sub-pixels and the eighth row of sub-pixels can be used as two rows of sub-pixels for scan driving.
  • the sub-pixels connected to the eighth row The data line loads the display data corresponding to the eighth row of sub-pixels. The rest can be deduced in the same way, and will not be repeated here.
  • the display panel may also be controlled to scan and drive the sub-pixels at intervals of three rows.
  • the display panel for example, when the sub-pixels in the first row, the fourth row, and the seventh row are controlled to perform scan driving in one display frame. Then the first row of sub-pixels and the fourth row of sub-pixels can be used as two rows of sub-pixels for scanning drive. At this time, when the first row of sub-pixels is driven and the fourth row of sub-pixels is being driven, the fourth row of sub-pixels is connected The data line loads the display data corresponding to the fourth row of sub-pixels.
  • the fourth row of sub-pixels and the seventh row of sub-pixels can be used as two rows of sub-pixels for scan driving. At this time, when the fourth row of sub-pixels is driven and the seventh row of sub-pixels is being driven, the sub-pixels connected to the seventh row The data line loads the display data corresponding to the sub-pixels in the seventh row. The rest can be deduced in the same way, and will not be repeated here.
  • the display panel may also be controlled to scan and drive the sub-pixels at intervals of four rows, or the display panel may be controlled to scan and drive the sub-pixels at intervals of five or more rows, which is not limited herein.
  • FIG. 6 schematically shows a schematic diagram of signals in the first display frame after the current display frame when the second picture is determined to be a bad picture.
  • the sub-pixels in the odd-numbered row of the display panel may be controlled to scan and drive, and output to each data line The display data corresponding to the sub-pixels in the odd row.
  • the timing controller may input interlaced scanning control signals (such as stv-od, stv-ev, clk1, clk2, clk3, clk4), to control the gate drive circuit to scan and drive the sub-pixels in the odd row of the display panel (such as outputting the signal ga1 to the gate line GA1 coupled to the sub-pixels in the first row, and to output the signal ga1 to the sub-pixels in the second row
  • the gate line GA2 coupled to the pixels outputs a signal ga2, the gate line GA3 coupled to the subpixels in the third row outputs a signal ga3, and the gate line GA4 coupled to the subpixels in the fourth row outputs a signal ga4).
  • the timing controller may input an interlaced data control signal to the source driving circuit in the display panel in the odd-numbered display frame after the current display frame, so that the source driving circuit generates an interlaced data output signal (such as signal tp) , to output the display data corresponding to the sub-pixels of the odd-numbered row to each data line (such as the source drive circuit is triggered by the rising edge of the signal tp, and can output the display data corresponding to the sub-pixels of one row.)
  • the first row the first row
  • the clock signal (CLK) of the odd-numbered rows such as the third row and the fifth row
  • the grid lines of the first row, the third row, the fifth row and the like are opened correspondingly.
  • the display under the control of the data control signal TP, the display
  • the overlap of data and clock signals is 2H, and H represents the charging time of a row of pixels. This setting is equivalent to blanking out the data of even-numbered rows, charging each odd-numbered row for 2H, which can ensure a more sufficient charging rate.
  • display data and clock The signal overlap can be greater than 2H, and it can be set according to actual needs, as long as the display panel has sufficient charging rate.
  • the high level of the signal ga1 controls the transistors 01 in the first row of sub-pixels to be turned on
  • the low level of the signal gal controls the transistors 01 of the first row of sub-pixels to be turned off
  • the high level of the signal ga3 controls the transistors 01 in the third row of sub-pixels to be turned on
  • the low level of the signal ga3 controls the transistors 01 of the third row of sub-pixels to be turned off.
  • the signal ga2 is at low level in the first display frame, so as to control the transistors 01 in the sub-pixels in the second row to be turned off in the first display frame.
  • the signal ga4 is at a low level in the first display frame, so as to control the transistors 01 in the sub-pixels in the fourth row to be turned off in the first display frame.
  • the display data corresponding to each sub-pixel in the first row is output, for example, the display data da1 of the first row and first column is output to the data line DA1, so that the first The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the first row and the second column are output to the data line DA2, so that the sub-pixels of the first row and the second column input corresponding display data.
  • the display data da3 of the first row and the third column are output to the data line DA3, so that the sub-pixels of the first row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the third row is output, for example, the display data da1 of the first column of the third row is output to the data line DA1, so that the third row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the third row and the second column are output to the data line DA2, so that the sub-pixels of the third row and the second column input corresponding display data.
  • the display data da3 of the third row and third column is output to the data line DA3, so that the sub-pixels of the third row and third column input corresponding display data.
  • FIG. 7 schematically shows a schematic diagram of signals in a second display frame after the current display frame when the second picture is determined to be a bad picture.
  • the sub-pixels in the even-numbered row of the display panel may be controlled to scan and drive, and output to each data line The display data corresponding to the sub-pixels in the even-numbered row.
  • the level conversion circuit can input an interlaced control signal (such as stv-od, stv-ev, etc.) to the gate drive circuit in the display panel through the level conversion circuit , clk1, clk2, clk3, clk4), to control the gate drive circuit to scan and drive the sub-pixels in the even-numbered row of the display panel (such as outputting a signal ga1 to the gate line GA1 coupled to the sub-pixels in the first row, and outputting a signal ga1 to the second row
  • the gate line GA2 coupled to the subpixels outputs a signal ga2, the gate line GA3 coupled to the subpixels in the third row outputs a signal ga3, and the gate line GA4 coupled to the subpixels in the fourth row outputs a signal ga4).
  • the timing controller can input an interlaced data control signal to the source driving circuit in the display panel in the even-numbered display frame after the current display frame, so that the source driving circuit can generate an interlaced data output signal (such as the signal tp ), so as to output the display data corresponding to the sub-pixels in the even-numbered row for each data line.
  • an interlaced data output signal such as the signal tp
  • the source drive circuit is triggered by the rising edge of the signal tp, it can output the display data corresponding to a row of sub-pixels.
  • CLK even-numbered row clock signal
  • the display data and the clock signal overlap to 2H, and H represents a row of pixel charging
  • the time, so set is equivalent to blanking out the data of odd-numbered lines, charging each even-numbered line for 2H, which can ensure that the charging rate of each line is more sufficient.
  • the overlap between the display data and the clock signal can be greater than 2H, and it can be set according to actual needs. Just make sure that the display panel has a sufficient charge rate.
  • the high level of the signal ga2 controls the transistors 01 in the second row of sub-pixels to be turned on, and the low level of the signal ga2 controls the transistors 01 of the second row of sub-pixels to be turned off.
  • the high level of the signal ga4 controls the transistors 01 in the fourth row of sub-pixels to be turned on, and the low level of the signal ga4 controls the transistors 01 of the fourth row of sub-pixels to be turned off.
  • the signal ga1 is at low level in the second display frame, so as to control the transistors 01 in the first row of sub-pixels to be turned off in the second display frame.
  • the signal ga3 is at a low level in the second display frame, so as to control the transistors 01 in the sub-pixels in the third row to be turned off in the second display frame.
  • the display data corresponding to each sub-pixel in the second row is output, such as the display data da1 of the first column of the second row is output to the data line DA1, so that the second The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the second row and the second column is output to the data line DA2, so that the sub-pixels of the second row and the second column input corresponding display data.
  • the display data da3 of the second row and the third column are output to the data line DA3, so that the sub-pixels of the second row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the fourth row is output, for example, the display data da1 of the first column of the fourth row is output to the data line DA1, so that the fourth row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the fourth row and the second column are output to the data line DA2, so that the sub-pixels of the fourth row and the second column input corresponding display data.
  • the display data da3 of the fourth row and third column is output to the data line DA3, so that the sub-pixels of the fourth row and third column input corresponding display data.
  • FIG. 8 schematically shows a schematic diagram of signals in the first display frame after the current display frame when it is determined that the second picture is not a bad picture.
  • the timing controller may input a step-by-step Row scanning control signals (such as stv-od, stv-ev, clk1, clk2, clk3, clk4), to control the gate drive circuit to scan and drive each row of sub-pixels of the display panel (such as coupling the first row of sub-pixels
  • the connected gate line GA1 outputs a signal ga1, the gate line GA2 coupled to the second row of sub-pixels outputs a signal ga2, the gate line GA3 coupled to the third row of sub-pixels outputs a signal ga3, and the gate line GA3 coupled to the third row of sub-pixels outputs a signal ga3, and the gate line GA3 coupled to the third row of sub-pixels outputs a signal ga3, and the gate line GA3 coupled to the third row of sub-pixels outputs a
  • the timing controller can input progressive data control signals to the source driving circuit in the display panel in each display frame after the current display frame, so that the source driving circuit generates progressive data output signals (such as signal tp ) to output display data corresponding to each row of sub-pixels for each data line. (If the source driving circuit is triggered by the rising edge of the signal tp, it can output the display data corresponding to one row of sub-pixels.).
  • progressive data output signals such as signal tp
  • the high level of the signal ga1 controls the transistors 01 in the first row of sub-pixels to be turned on, and the low level of the signal gal controls the transistors 01 of the first row of sub-pixels to be turned off.
  • the high level of the signal ga2 controls the transistors 01 in the second row of sub-pixels to be turned on, and the low level of the signal ga2 controls the transistors 01 of the second row of sub-pixels to be turned off.
  • the high level of the signal ga3 controls the transistors 01 in the third row of sub-pixels to be turned on, and the low level of the signal ga3 controls the transistors 01 of the third row of sub-pixels to be turned off.
  • the high level of the signal ga4 controls the transistors 01 in the fourth row of sub-pixels to be turned on, and the low level of the signal ga4 controls the transistors 01 of the fourth row of sub-pixels to be turned off.
  • the display data corresponding to each sub-pixel in the first row is output, for example, the display data da1 of the first row and first column is output to the data line DA1, so that the first The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the first row and the second column are output to the data line DA2, so that the sub-pixels of the first row and the second column input corresponding display data.
  • the display data da3 of the first row and the third column are output to the data line DA3, so that the sub-pixels of the first row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the second row is output, such as the display data da1 of the first column of the second row is output to the data line DA1, so that the second The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the second row and the second column is output to the data line DA2, so that the sub-pixels of the second row and the second column input corresponding display data.
  • the display data da3 of the second row and the third column are output to the data line DA3, so that the sub-pixels of the second row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the third row is output, for example, the display data da1 of the first column of the third row is output to the data line DA1, so that the third row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the third row and the second column are output to the data line DA2, so that the sub-pixels of the third row and the second column input corresponding display data.
  • the display data da3 of the third row and third column is output to the data line DA3, so that the sub-pixels of the third row and third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the fourth row is output, for example, the display data da1 of the first column of the fourth row is output to the data line DA1, so that the fourth row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the fourth row and the second column are output to the data line DA2, so that the sub-pixels of the fourth row and the second column input corresponding display data.
  • the display data da3 of the fourth row and third column is output to the data line DA3, so that the sub-pixels of the fourth row and third column input corresponding display data.
  • the corresponding working processes of the second display frame, the third display frame, and the fourth display frame after the current display frame are basically the same, and will not be repeated here.
  • the embodiments of the present disclosure provide some other driving methods of the display panel, which are modified with respect to the implementation manners in the above-mentioned embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • FIG. 9 shows a schematic diagram of signals in a first display frame after the current display frame when the second picture is determined to be a bad picture.
  • the sub-pixels in the even-numbered row of the display panel may be controlled to scan and drive, and output to each data line The display data corresponding to the sub-pixels in the even-numbered row.
  • the timing controller may input interlaced scanning control signals (such as stv-od, stv-ev, clk1, clk2, clk3, clk4), to control the gate drive circuit to scan and drive the sub-pixels in the even-numbered row of the display panel (such as outputting a signal ga1 to the gate line GA1 coupled to the sub-pixels in the first row, and outputting a signal ga1 to the sub-pixels in the second row
  • the gate line GA2 coupled to the pixels outputs a signal ga2, the gate line GA3 coupled to the subpixels in the third row outputs a signal ga3, and the gate line GA4 coupled to the subpixels in the fourth row outputs a signal ga4).
  • the timing controller can input an interlaced data control signal to the source driving circuit in the display panel in the even-numbered display frame after the current display frame, so that the source driving circuit generates an interlaced data output signal (such as signal tp) , so as to output the display data corresponding to the sub-pixels in the even row to each data line.
  • the source driving circuit may output display data corresponding to one row of sub-pixels when triggered by the rising edge of the signal tp).
  • the high level of the signal ga2 controls the transistors 01 in the second row of sub-pixels to be turned on, and the low level of the signal ga2 controls the transistors 01 of the second row of sub-pixels to be turned off.
  • the high level of the signal ga4 controls the transistors 01 in the fourth row of sub-pixels to be turned on, and the low level of the signal ga4 controls the transistors 01 of the fourth row of sub-pixels to be turned off.
  • the signal ga1 is at low level in the first display frame, so as to control the transistors 01 in the first row of sub-pixels to be turned off in the first display frame.
  • the signal ga3 is at a low level in the first display frame, so as to control the transistors 01 in the sub-pixels in the third row to be turned off in the first display frame.
  • the display data corresponding to each sub-pixel in the second row is output, such as the display data da1 of the first column of the second row is output to the data line DA1, so that the second The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the second row and the second column is output to the data line DA2, so that the sub-pixels of the second row and the second column input corresponding display data.
  • the display data da3 of the second row and the third column are output to the data line DA3, so that the sub-pixels of the second row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the fourth row is output, for example, the display data da1 of the first column of the fourth row is output to the data line DA1, so that the fourth row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the fourth row and the second column are output to the data line DA2, so that the sub-pixels of the fourth row and the second column input corresponding display data.
  • the display data da3 of the fourth row and third column is output to the data line DA3, so that the sub-pixels of the fourth row and third column input corresponding display data.
  • FIG. 10 shows a schematic diagram of signals in a second display frame after the current display frame when the second frame is determined to be a bad frame.
  • the sub-pixels in the odd-numbered row of the display panel may be controlled to scan and drive, and output to each data line The display data corresponding to the sub-pixels in the odd row.
  • the timing controller may input an interlaced scanning control signal (such as stv-od, stv-ev, clk1, clk2, clk3, clk4), to control the gate drive circuit to scan and drive the sub-pixels in the odd row of the display panel (such as outputting the signal ga1 to the gate line GA1 coupled to the sub-pixels in the first row, and to output the signal ga1 to the sub-pixels in the second row
  • the gate line GA2 coupled to the pixels outputs a signal ga2, the gate line GA3 coupled to the subpixels in the third row outputs a signal ga3, and the gate line GA4 coupled to the subpixels in the fourth row outputs a signal ga4).
  • the timing controller can input an interlaced data control signal to the source driving circuit in the display panel in the even-numbered display frame after the current display frame, so that the source driving circuit generates an interlaced data output signal (such as signal tp) , so as to output the display data corresponding to the sub-pixels of the odd-numbered row to each data line (for example, the source drive circuit is triggered by the rising edge of the signal tp, and can output the display data corresponding to the sub-pixels of one row, for example, the first row of the control signal tp Triggered by a rising edge, the display data corresponding to each sub-pixel in the first row is output.
  • an interlaced data control signal such as signal tp
  • the display data da1 of the first row and the first column are output to the data line DA1, and the display data da2 of the first row and the second column are output to the data line On the line DA2, the display data da3 of the third column of the first row is output to the data line DA3.
  • the display data corresponding to each sub-pixel in the third row is output, such as the third
  • the display data da1 of the first column of the row is output to the data line DA1, the display data da2 of the third row and the second column are output to the data line DA2, and the display data da3 of the third row and the third column are output to the data line DA3.
  • the high level of the signal ga1 controls the transistors 01 in the first row of sub-pixels to be turned on
  • the low level of the signal gal controls the transistors 01 of the first row of sub-pixels to be turned off
  • the high level of the signal ga3 controls the transistors 01 in the third row of sub-pixels to be turned on
  • the low level of the signal ga3 controls the transistors 01 of the third row of sub-pixels to be turned off.
  • the signal ga2 is at low level in the second display frame, so as to control the transistors 01 in the sub-pixels in the second row to be turned off in the second display frame.
  • the signal ga4 is at a low level in the second display frame, so as to control the transistors 01 in the sub-pixels in the fourth row to be turned off in the second display frame.
  • the display data corresponding to each sub-pixel in the first row is output, for example, the display data da1 of the first row and first column is output to the data line DA1, so that the first The corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the first row and the second column are output to the data line DA2, so that the sub-pixels of the first row and the second column input corresponding display data.
  • the display data da3 of the first row and the third column are output to the data line DA3, so that the sub-pixels of the first row and the third column input corresponding display data.
  • the display data corresponding to each sub-pixel in the third row is output, for example, the display data da1 of the first column of the third row is output to the data line DA1, so that the third row
  • the corresponding display data is input to the sub-pixels in the first column of the row.
  • the display data da2 of the third row and the second column are output to the data line DA2, so that the sub-pixels of the third row and the second column input corresponding display data.
  • the display data da3 of the third row and third column is output to the data line DA3, so that the sub-pixels of the third row and third column input corresponding display data.
  • Embodiments of the present disclosure provide still some driving methods of the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the timing controller and the source driving circuit may be coupled through a general purpose input output (GPIO) interface, so as to transmit signals through the GPIO interface.
  • GPIO general purpose input output
  • the timing controller can output the first setting bit with the first number and the second setting bit with the first number and the second number from the general-purpose input and output interface as interlaced data control signal output.
  • the source driving circuit can generate an interlaced data output signal according to the second set bit when detecting that the first set bit is the first number.
  • the first number may be "1”
  • the second number may be "0”
  • the first setting bit may be the 22nd bit
  • the second setting bit may be the 23rd bit.
  • the 22nd bit can carry the digital signal "1”
  • the 23rd bit can carry the digital signals "1" and "0".
  • the source drive circuit can store the received 22nd bit and 23rd bit into the control unit (Control packets).
  • the working mode corresponding to the interlaced data control signal in the source driving circuit is enabled, so that the source driving circuit can correspondingly drive the display panel.
  • the digital signal "1" carried by the 23rd bit in the even-numbered display frame after the current display frame, the sub-pixels in the even-numbered row of the display panel are controlled to scan and drive, and the even-numbered row is output to each data line The display data corresponding to the sub-pixel.
  • the digital signal "0" carried by the 23rd bit in the odd-numbered display frame after the current display frame, control the sub-pixels in the odd-numbered row of the display panel to scan and drive, and output the odd-numbered row to each data line
  • the digital signal "1" carried by the 23rd bit in the even-numbered display frame after the current display frame, the sub-pixels in the odd-numbered row of the display panel are controlled to scan and drive, and the odd-numbered row is output to each data line The display data corresponding to the sub-pixel.
  • control the sub-pixels in the even-numbered row of the display panel in the odd-numbered row of the display panel to scan and drive, and output the display data corresponding to the sub-pixels in the even-numbered row to each data line.
  • the timing controller can output the first set bit with the second number as a progressive data control signal.
  • the source driving circuit can generate a progressive data output signal when detecting that the first set bit is the second number.
  • the first number may be "1”
  • the second number may be "0”
  • the first setting bit may be the 22nd bit
  • the second setting bit may be the 23rd bit. This allows the 22nd bit to carry the digital signal "0".
  • the source drive circuit can store the received 22nd bit into the control unit (Control packets), so that according to the digital signal "0" carried by the 23rd bit, the corresponding progressive data control signal in the source drive circuit working mode, so that the source driving circuit can drive the display panel accordingly.
  • the first number can also be “0”
  • the second number can also be “1”
  • the first setting bit and the second setting bit can be other bits, which are not limited here.
  • the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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Abstract

一种显示面板的驱动方法及显示装置，在由第一画面切换到第二画面，且第二画面在连续的至少两个显示帧显示时，在第二画面的当前显示帧中接收第二画面的显示数据（S10）；根据第二画面的显示数据以及不良画面判定条件，确定第二画面是否为不良画面（S20）；当确定第二画面为不良画面时，控制显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对第二行子像素连接的数据线加载第二行子像素对应的显示数据（S30）。

Description

显示面板的驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法及显示装置。
背景技术
在诸如液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器中，一般包括多个像素。每个像素可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的显示数据，以控制每个子像素的显示亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本公开实施例提供的显示面板的驱动方法，包括：
在由第一画面切换到第二画面，且所述第二画面在连续的至少两个显示帧显示时，在所述第二画面的当前显示帧中接收所述第二画面的显示数据；
根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面；
当确定所述第二画面为不良画面时，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。
在一些示例中，所述不良画面判定条件包括：不良区域的设定面积阈值以及同一列中相邻两个子像素对应的显示数据的灰阶之间的设定灰阶差值阈值；
所述确定所述第二画面为不良画面，具体包括：
确定所述第二画面的显示数据中，满足所述设定灰阶差值阈值的显示数 据对应的子像素形成的目标区域；
在所述目标区域满足所述设定面积阈值时，确定所述第二画面为不良画面。
在一些示例中，所述确定所述第二画面的显示数据中，满足所述设定差值阈值的显示数据对应的子像素形成的目标区域，具体包括：
以相邻至少两行中的至少一列像素单元作为一个单元组，将所述显示面板中的像素单元分为多个单元组；
针对每个所述单元组对应的显示数据，确定同一列中相邻两行子像素对应的显示数据的灰阶之间的灰阶差值；
在所述灰阶差值满足所述设定灰阶差值阈值时，将满足所述设定灰阶差值阈值的灰阶差值对应的子像素所在的单元组定义为目标单元组；
所有所述目标单元组形成所述目标区域。
在一些示例中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据，具体包括：
在所述当前显示帧后的显示帧中，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据。
在一些示例中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据，具体包括：
在所述当前显示帧后的第奇数个显示帧中，控制所述显示面板的第奇数行子像素进行扫描驱动，并对各所述数据线输出第奇数行子像素对应的显示数据；
在所述当前显示帧后的第偶数个显示帧中，控制所述显示面板的第偶数行子像素进行扫描驱动，并对各所述数据线输出第偶数行子像素对应的显示数据。
在一些示例中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，具体包括：
在所述当前显示帧后的第奇数个显示帧中，控制所述显示面板的第偶数行子像素进行扫描驱动，并对各所述数据线输出第偶数行子像素对应的显示数据；
在所述当前显示帧后的第偶数个显示帧中，控制所述显示面板的第奇数行子像素进行扫描驱动，并对各所述数据线输出第奇数行子像素对应的显示数据。
在一些示例中，在所述当前显示帧中，根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面。
本公开实施例提供的显示装置，包括：
显示面板；
时序控制器，被配置为在由第一画面切换到第二画面，且所述第二画面在连续的至少两个显示帧显示时，在所述第二画面的当前显示帧中接收所述第二画面的显示数据；根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面；在确定所述第二画面为不良画面时，向所述显示面板中的栅极驱动电路输入隔行扫描控制信号和向所述显示面板中的源极驱动电路输入隔行数据控制信号，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。
在一些示例中，所述时序控制器还被配置为在确定所述第二画面不为不良画面时，向所述显示面板中的栅极驱动电路输入逐行扫描控制信号和向所述显示面板中的源极驱动电路输入逐行数据控制信号，控制所述显示面板逐 行子像素进行扫描驱动，并对各所述数据线加载各行子像素对应的显示数据。
在一些示例中，所述时序控制器与所述源极驱动电路通过通用型之输入输出接口耦接；
所述时序控制器进一步被配置为通过将所述通用型之输入输出接口的驱动使能引脚设置为隔行驱动有效电平，以作为所述隔行数据控制信号输出；以及通过将所述通用型之输入输出接口的驱动使能引脚设置为逐行驱动有效电平，以作为所述逐行数据控制信号输出；
所述源极驱动电路进一步被配置为在检测到所述驱动使能引脚的电平为隔行驱动有效电平时，生成隔行数据输出信号，并根据生成的隔行数据输出信号，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据；以及在检测到所述驱动使能引脚的电平为逐行驱动有效电平时，生成逐行数据输出信号，并根据生成的逐行数据输出信号，对各所述数据线加载各行子像素对应的显示数据。
在一些示例中，所述时序控制器进一步被配置为将所述驱动使能引脚的电平由第一电平切换为第二电平，作为所述隔行驱动有效电平；以及将所述驱动使能引脚的电平保持所述第一电平，作为所述逐行驱动有效电平；
所述源极驱动电路进一步被配置为将所述驱动使能引脚的电平对应的电压与存储的设定电压阈值进行比较，在所述驱动使能引脚的电平对应的电压高于所述设定电压阈值时，生成所述隔行数据输出信号；在所述驱动使能引脚的电平对应的电压不高于所述设定电压阈值时，生成所述逐行数据输出信号。
在一些示例中，所述时序控制器与所述电平转换电路通过通用型之输入输出接口耦接；
所述时序控制器进一步被配置为通过将所述通用型之输入输出接口输出具有第一数字的第一设定比特位、以及具有第一数字和第二数字的第二设定比特位，作为所述隔行数据控制信号输出；以及通过将所述通用型之输入输出具有第二数字的第一设定比特位，作为所述逐行驱动使能信号输出；
所述源极驱动电路进一步被配置为在检测到所述第一设定比特位为第一数字时，根据所述第二设定比特位，生成所述隔行数据输出信号；以及在检测到所述第一设定比特位为第二数字时，生成所述逐行数据输出信号。
附图说明
图1a为本公开实施例中的显示装置的一些结构示意图；
图1b为本公开实施例中的驱动使能引脚的结构示意图；
图1c为本公开实施例中的显示装置的又一些结构示意图；
图2为本公开实施例中的驱动方法的流程图；
图3为本公开实施例中的不良区域的示意图；
图4为本公开实施例中的第二画面的目标区域的示意图；
图5a为本公开实施例中的确定为不良画面的第二画面的一些示意图；
图5b为本公开实施例中的确定为不良画面的第二画面的另一些示意图；
图5c为本公开实施例中的确定为不良画面的第二画面的又一些示意图；
图5d为本公开实施例中的确定为不良画面的第二画面的又一些示意图；
图5e为本公开实施例中的确定为不良画面的第二画面的又一些示意图；
图6为本公开实施例中的一些信号时序图；
图7为本公开实施例中的另一些信号时序图；
图8为本公开实施例中的又一些信号时序图；
图9为本公开实施例中的又一些信号时序图；
图10为本公开实施例中的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所 描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的阈值。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1a，显示装置可以包括显示面板100、电平转换(Level Shift)电路200以及时序控制器300。其中，显示面板100可以包括多个阵列排布的像素单元，多条栅线(例如，GA1、GA2、GA3、GA4)、多条数据线(例如，DA1、DA2、DA3)、栅极驱动电路110以及源极驱动电路120。栅极驱动电路110分别与栅线GA1、GA2、GA3、GA4耦接，源极驱动电路120分别与数据线DA1、DA2、DA3耦接。示例性地，每个像素单元包括多个子像素SPX。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
参见图1a所示，每个子像素中包括晶体管01和像素电极02。其中，一行子像素对应一条栅线，一列子像素对应一条数据线。晶体管01的栅极与对应的栅线电连接，晶体管01的源极与对应的数据线电连接，晶体管01的漏极与像素电极02电连接，需要说明的是，本公开像素阵列结构还可以是双栅 结构，即相邻两行像素之间设置两条栅极线，此排布方式可以减少一半的数据线，即包含相邻两列像素之间有的数据线，有的相邻两列像素之间不包括数据线，具体像素排布结构和数据线，扫描线的排布方式不限定。
随着显示面板在高刷新率、高分辨率领域的快速发展，对画质及驱动能力要求也日益增加，大尺寸显示面板在显示某些特殊画面时很难保证良好的充电率，会出现某些不良画面及驱动IC温度过高等问题。例如，8K显示面板，其刷新频率可以为120Hz，每行子像素的打开时间例如有1/(120Hz×4500行)＝1.85μs，像素充电时间已远远不足。若刷新频率为240Hz或更高时，对子像素的充电时间会再进一步的压缩，保证子像素的充电率，显示画质的质量保证将会是更大的挑战。例如，在显示面板显示静态画面时，由于像素充电时间不足以及同一列中相邻两个子像素对应的灰阶差异较大，会导致显示面板产生不良。
本公开实施例提供的显示面板的驱动方法，如图2所示，可以包括如下步骤：
S10、在由第一画面切换到第二画面，且第二画面在连续的至少两个显示帧显示时，在第二画面的当前显示帧中接收第二画面的显示数据。
S20、根据第二画面的显示数据以及不良画面判定条件，确定第二画面是否为不良画面；其中，当确定第二画面为不良画面时，执行步骤S30；当确定第二画面不为不良画面时，执行步骤S40。
S30、控制显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对第二行子像素连接的数据线加载第二行子像素对应的显示数据。
S40、控制显示面板逐行子像素进行扫描驱动，并在扫描驱动子像素时，对各数据线加载各行子像素对应的显示数据。
本公开实施例提供的驱动方法，在由第一画面切换到第二画面时，可以说明显示面板进行了画面切换。并且，第二画面在连续的至少两个显示帧显示，可以说明显示面板可以在一定时间内维持同一画面的显示，例如显示的 第二画面可以为静态画面。通过设置的不良画面判定条件，可以根据不良画面判定条件对第二画面的显示数据进行分析，可以确定第二画面是否为不良画面。当确定第二画面为不良画面时，可以控制显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对第二行子像素连接的数据线加载第二行子像素对应的显示数据。这样可以在显示第二画面时，通过执行部分子像素显示，部分子像素不显示的策略，可以在显示静止画面时，仅对需要显示的部分子像素进行扫描驱动以及输出显示数据，而不用对全部子像素均进行扫描驱动以及输出显示数据，因此可以降低功耗，降低器件温度过高的问题。以及，在显示第二画面时，由于间隔至少一行子像素进行显示画面，其余行子像素呈黑态，该呈黑态的子像素行不再显示相应的画面，因此可以避免由于像素充电时间不足以及同一列中相邻两行子像素对应的灰阶差异较大，导致的画面不良的问题。
在本公开实施例中，时序控制器可以被配置为：在由第一画面切换到第二画面，且第二画面在连续的至少两个显示帧显示时，在第二画面的当前显示帧中接收第二画面的显示数据；根据第二画面的显示数据以及不良画面判定条件，确定第二画面是否为不良画面；在确定第二画面为不良画面时，向显示面板中的栅极驱动电路输入隔行扫描控制信号和向所述显示面板中的源极驱动电路输入隔行数据控制信号，控制显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对第二行子像素连接的数据线加载第二行子像素对应的显示数据。需要说明的是，所述并在扫描驱动的两行子像素中，这里的两行子像素指的是对应栅线打开的两行，例如是隔行扫描驱动，则这里的两行子像素可以指的是第一行和第三行子像素；即包括有效电平的扫描信号隔行输入时，例如第一行输入包括有效电平的扫描信号，第三行输入包括有效电平的扫描信号，则显示数据是在第一行输入显示数据，第三行输入显示数据，可选的，对于显示数据而言，第一行和第二行均持续输出的是第一行显示数据，第三 行和第四行均持续输出的是第三行的显示数据，这样在显示第二画面时，在时序控制器判定第二画面为不良画面时，通过使能隔行驱动的工作模式，可以间隔至少一行子像素进行显示画面，其余行子像素呈黑态，该呈黑态的子像素行不再显示相应的画面，因此可以避免由于像素充电时间不足以及同一列中相邻两行子像素对应的灰阶差异较大，导致的画面不良的问题。
在本公开实施例中，如图1a所示，时序控制器300通过电平转换电路200与栅极驱动电路110连接，时序控制器300与源极驱动电路120可以通过通用型之输入输出(General Purpose Input Output，GPIO)接口耦接，以通过GPIO接口传输信号。在本公开实施例中，如图1b所示，示意出了时序控制器与源极驱动电路120之间耦接的GPIO接口的驱动使能引脚OE_EN。其中，120代表源极驱动电路，12代表印刷电路板(Printed Circuit Board，PCB)，13代表柔性电路板(Flexible Printed Circuit，FPC)，14代表时序控制器所在的时序电路板。示例性地，印刷电路板12上可以设置电阻NS，以提高驱动使能引脚OE_EN的拉高驱动能力。示例性地，电阻NS的电阻值可以为4.7KΩ，当然，电阻NS的电阻值也可以根据实际应用的需求进行确定，在此不作限定。
示例性地，时序电路板上可以设置一个时序控制器，这样可以降低集成难度。时序电路板上也可以设置两个时序控制器(例如一个作为主时序控制器，另一个作为从时序控制器)，以提高驱动能力和运算能力，有利于应用于高刷新率(例如120Hz，240Hz等)的显示面板中。
示例性地，时序控制器300可以通过将通用型之输入输出接口的驱动使能引脚OE_EN设置为隔行驱动有效电平，以作为隔行数据控制信号输出。以及，源极驱动电路可以在检测到驱动使能引脚OE_EN的电平为隔行驱动有效电平时，生成隔行数据输出信号，并根据生成的隔行数据输出信号，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。例如，隔行驱动有效电平为高电平，在源极驱动电路检测到驱动使能引脚OE_EN的电平为高电平时，可以生成隔行数据输出信号，从而向显示面板中的数据线输入相应的显示数据。
在本公开实施例中，时序控制器可以将驱动使能引脚OE_EN的电平由第一电平切换为第二电平，以作为隔行驱动有效电平。以及，源极驱动电路可以将驱动使能引脚OE_EN的电平对应的电压与存储的设定电压阈值进行比较，在驱动使能引脚OE_EN的电平对应的电压高于设定电压阈值时，生成所述隔行数据输出信号(如图6与图7所示的tp)。例如，隔行驱动有效电平为高电平，则可以使第一电平为低电平，第二电平为高电平。以H代表高电平，L代表高电平。结合图1a至图1c以及图6与图7，第二画面的显示数据和不良画面判定条件输入数据比较模块，以确定第二画面是否为不良画面。在确定第二画面是不良画面时，将驱动使能引脚OE_EN设置为H对应的电压，例如可以在将驱动使能引脚OE_EN由L对应的电压拉高为H对应的电压时，可以说明驱动使能引脚OE_EN为隔行驱动有效电平。源极驱动电路可以将驱动使能引脚OE_EN此时对应H的电压与存储的设定电压阈值通过电压比较器进行比较，在对应H的电压高于设定电压阈值时，可以使能源极驱动电路中对应隔行数据控制信号的工作模式，从而使源极驱动电路在隔行数据控制信号的控制下将显示数据通过CDES接收器输出给缓冲器，以通过缓冲器将显示数据输出给数据线，从而实现向显示面板中的数据线隔行输出对应的显示数据。以及，时序控制器还通过电平转换电路向栅极驱动电路输出隔行扫描控制信号(如图6与图7所示的stv-od，stv-ev)，以隔行驱动栅线，进而隔行驱动显示面板。参照图6和图7，可选的，tp代表隔行数据输出信号，信号tp，可以是上升沿锁存数据，下降沿输出数据，或者可以是下降沿锁存数据，上升沿输出数据，附图仅示意了上升沿锁存数据，下降沿输出数据。需要说明的是，设定电压阈值可以根据实际应用的需求进行确定，在此不做限定。
在本公开实施例中，在时序控制器确定第二画面不为不良画面时，可以控制显示面板逐行子像素进行扫描驱动，并对各数据线加载各行子像素对应的显示数据，以使显示面板中的每一个子像素均进行数据刷新。示例性地，时序控制器在确定第二画面不为不良画面时，可以通过电平转换电路向栅极驱动电路输入逐行扫描控制信号，以及向源极驱动电路输入逐行数据控制信 号，以控制显示面板逐行子像素进行扫描驱动，并对各数据线加载各行子像素对应的显示数据。例如，逐行驱动有效电平为低电平，在源极驱动电路检测到驱动使能引脚OE_EN的电平为低电平时，可以对各所述数据线加载各行子像素对应的显示数据。这样在时序控制器判定第二画面不为不良画面时，通过向源极驱动电路输入逐行数据控制信号，以使能对应逐行数据控制信号的工作模式，从而使源极驱动电路可以相应的驱动显示面板。进而在显示第二画面时，可以逐行驱动子像素进行显示画面，从而提高显示分辨率。
在本公开实施例中，时序控制器可以通过将GPIO接口的驱动使能引脚OE_EN设置为逐行驱动有效电平，以作为逐行数据控制信号输出。以及，源极驱动电路可以在检测到驱动使能引脚OE_EN的电平为逐行驱动有效电平时，生成逐行数据输出信号(如图8所示的tp)，并根据生成的逐行数据输出信号，对各所述数据线加载各行子像素对应的显示数据。例如，逐行驱动有效电平为低电平，在源极驱动电路检测到驱动使能引脚OE_EN的电平为低电平时，可以生成逐行数据输出信号。
在本公开实施例中，时序控制器可以将驱动使能引脚OE_EN的电平保持第一电平，作为逐行驱动有效电平。以及，源极驱动电路可以在驱动使能引脚OE_EN的电平对应的电压不高于设定电压阈值时，生成所述逐行数据输出信号。例如，逐行驱动有效电平为低电平，则可以使第一电平为低电平。以L代表高电平。结合图1a至图1c以及图8，第二画面的显示数据和不良画面判定条件输入数据比较模块，以确定第二画面是否为不良画面。在确定第二画面不是不良画面时，将驱动使能引脚OE_EN设置为L对应的电压，例如可以将驱动使能引脚OE_EN保持为L对应的电压，可以说明输出逐行数据控制信号。源极驱动电路可以将驱动使能引脚OE_EN此时对应L的电压与存储的设定电压阈值通过电压比较器进行比较，在对应L的电压低于设定电压阈值时，可以使能源极驱动电路中对应逐行数据控制信号的工作模式，从而使源极驱动电路可以生成逐行数据输出信号(如图8所示的tp)。从而使源极驱动电路在逐行数据输出信号的控制下将显示数据通过CDES接收器输出给缓冲器， 以通过缓冲器将显示数据输出给数据线，从而实现向显示面板中的数据线隔行输出对应的显示数据。以及，时序控制器还通过电平转换电路向栅极驱动电路输出逐行扫描控制信号(如图8所示的stv-od，stv-ev)，以逐行驱动栅线，进而驱动显示面板。
在本公开实施例中，不良画面判定条件可以存储在时序控制器中。示例性地，不良画面判定条件可以包括：不良区域的设定面积阈值。示例性地，如图3所示，P代表显示面板显示的一个画面，画面P的左下角作为原点O(0,0)，画面P的下边缘作为横轴x，画面P的左边缘作为纵轴y。若不良区域BW可以为矩形，则不良区域BW的四个顶角的坐标分别为：左上角坐标Z1(x1，y2)、左下角坐标Z2(x1，y1)、右下角坐标Z3(x2，y1)、右上角坐标Z4(x2，y2)。例如，显示面板的分辨率为A列×B行，则可以根据x2>x1的设定，使x1和x2可以从0～A中选取，以及根据y2>y1的设定，使y1和y2可以从0～B中选取。例如，8K显示面板的分辨率为7680列×4320行，即A＝7680，B＝4320，则可以使x1和x2从0～7680中选取，使y1和y2从0～4320中选取。例如，x1＝0，x2＝3840，y1＝0，y2＝2160。这样可以使画面中不良区域的面积设定为原画面的1/4。或者，也可以说使x1、x2、y1以及y2选取其他的数值，以使画面中不良区域的面积设定为原画面的1/4。或者，也可以说使x1、x2、y1以及y2选取其他的数值，以使画面中不良区域的面积设定为原画面的1/2。或者，也可以说使x1、x2、y1以及y2选取其他的数值，以使画面中不良区域的面积设定为原画面的1/3。当然，在实际应用中，x1、x2、y1以及y2选取的具体数值，可以根据实际应用的需求进行确定，在此不作限定。
在本公开实施例中，也可以使不良区域为圆形、椭圆形、多边形等，在此不作限定。
在本公开实施例中，不良画面判定条件还可以包括：同一列中相邻两个子像素对应的显示数据的灰阶之间的设定灰阶差值阈值。示例性地，在显示面板采用256灰阶时，设定灰阶差值阈值可以从10～150灰阶中进行选取。例 如，设定灰阶差值阈值可以为150灰阶，设定灰阶差值阈值可以为127灰阶，设定灰阶差值阈值也可以为100灰阶，设定灰阶差值阈值也可以为80灰阶，设定灰阶差值阈值也可以为63灰阶，设定灰阶差值阈值也可以为50灰阶，设定灰阶差值阈值也可以为10灰阶。当然，在实际应用中，设定灰阶差值阈值可以根据实际应用的需求进行确定，在此不作限定。
在本公开实施例中，确定第二画面为不良画面，具体可以包括：确定第二画面的显示数据中，满足设定灰阶差值阈值的显示数据对应的子像素形成的目标区域。在目标区域满足设定面积阈值时，确定第二画面为不良画面。这样通过不良画面判定条件中具有的两个条件来判定第二画面是否为不良画面，可以提高判定第二画面为不良画面的准确性。示例性地，确定第二画面的显示数据中，不小于设定灰阶差值阈值的显示数据对应的子像素形成的目标区域。在目标区域不小于设定面积阈值时，确定第二画面为不良画面。这样可以通过将不小于设定灰阶差值阈值的显示数据对应的子像素初步筛选出来，形成目标区域，再通过将目标区域与设定面积阈值进行比较，在目标区域不小于设定面积阈值时，可以确定第二画面为不良画面，从而可以提高判定第二画面为不良画面的准确性。
例如，以Sba代表显示面板的各子像素所在的位置，a和b均为整数，1≤a≤A，1≤b≤B。如图4所示，以A＝12，B＝10为例，则第一列中第一行至第十行子像素分别为S11～S101，第二列中第一行至第十行子像素分别为S12～S102，第三列中第一行至第十行子像素分别为S13～S103，第四列中第一行至第十行子像素分别为S14～S104，第五列中第一行至第十行子像素分别为S15～S105，第六列中第一行至第十行子像素分别为S16～S106，第七列中第一行至第十行子像素分别为S17～S107，第八列中第一行至第十行子像素分别为S18～S108，第九列中第一行至第十行子像素分别为S19～S109，第十列中第一行至第十行子像素分别为S110～S1010，第十一列中第一行至第十行子像素分别为S111～S1011，第十二列中第一行至第十行子像素分别为S112～S1012。
第一列中，子像素S11与S21对应的显示数据的灰阶之间的差值小于设 定灰阶差值阈值，子像素S31与S41对应的显示数据的灰阶之间的差值也小于设定灰阶差值阈值，子像素S51与S61对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，子像素S71与S81对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值，子像素S91与S101对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值。
以及，第二列中，子像素S12与S22对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值，子像素S32与S42对应的显示数据的灰阶之间的差值也小于设定灰阶差值阈值，子像素S52与S62对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，子像素S72与S82对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值，子像素S92与S102对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值。
以及，第三列中，子像素S13与S23对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值，子像素S33与S43对应的显示数据的灰阶之间的差值也小于设定灰阶差值阈值，子像素S53与S63对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，子像素S73与S83对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值，子像素S93与S103对应的显示数据的灰阶之间的差值阈值不小于设定灰阶差值阈值。以及，第四列至第十二列中，同列相邻两行的子像素对应的显示数据的灰阶之间的差值均小于设定灰阶差值阈值。
则第一列中的子像素S51～S101，第二列中的子像素S52～S102，以及第三列中的子像素S53～S103，形成了目标区域M1。若目标区域M1的面积不小于设定面积阈值时，则时序控制器可以确定第二画面为不良画面。若目标区域M1的面积小于设定面积阈值时，可能使得目标区域M1较小，人眼不容易察觉，则时序控制器可以确定第二画面不为不良画面。
在本公开实施例中，确定第二画面的显示数据中，满足设定差值阈值的显示数据对应的子像素形成的目标区域，具体可以包括：以相邻至少两行中的至少一列像素单元作为一个单元组，将显示面板中的像素单元分为多个单 元组。针对每个单元组对应的显示数据，确定同一列中相邻两行子像素对应的显示数据的灰阶之间的灰阶差值。在灰阶差值满足设定灰阶差值阈值时，将满足设定灰阶差值阈值的灰阶差值对应的子像素所在的单元组定义为目标单元组。所有目标单元组形成目标区域。这样通过设置单元组，可以将至少两个像素单元作为最小单位进行目标区域的筛选，降低计算量，降低功耗。
示例性地，以像素单元包括三个子像素，相邻两行中的一列像素单元作为一个单元组为例。如图5a所示，第一列像素单元中，子像素S11、S12、S13、S21、S22、S23作为第一个单元组，子像素S31、S32、S33、S41、S42、S43作为第二个单元组。子像素S51、S52、S53、S61、S62、S63作为第三个单元组。子像素S71、S72、S73、S81、S82、S83作为第四个单元组。子像素S91、S92、S93、S101、S102、S103作为第五个单元组。若第一个单元组中，子像素S11与S21对应的显示数据的灰阶之间的差值，子像素S12与S22对应的显示数据的灰阶之间的差值，以及子像素S13与S23对应的显示数据的灰阶之间的差值，均小于设定灰阶差值阈值，则不用将第一个单元组定义为目标单元组。同理，不用将第二个单元组定义为目标单元组。若第三个单元组中，子像素S51对应的灰阶大于子像素S61对应的灰阶，子像素S51与S61对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S52对应的灰阶大于子像素S62对应的灰阶，子像素S52与S62对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S53对应的灰阶大于子像素S63对应的灰阶，子像素S53与S63对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，则可以将第三个单元组定义为目标单元组。同理，将第四个单元组和第五个单元组定义为目标单元组。
以及，第二列像素单元中，子像素S14、S15、S16、S24、S25、S26作为第六个单元组，子像素S34、S35、S36、S44、S45、S46作为第七个单元组。子像素S54、S55、S56、S64、S65、S66作为第八个单元组。子像素S74、S75、S76、S84、S85、S86作为第九个单元组。子像素S94、S95、S96、S104、S105、S106作为第十个单元组。若第六个单元组中，子像素S14与S24对应的显示 数据的灰阶之间的差值，子像素S15与S25对应的显示数据的灰阶之间的差值，以及子像素S16与S26对应的显示数据的灰阶之间的差值，均小于设定灰阶差值阈值，则不用将第六个单元组定义为目标单元组。同理，不用将第七个单元组定义为目标单元组。若第八个单元组中，子像素S54对应的灰阶小于子像素S64对应的灰阶，子像素S54与S64对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S55对应的灰阶小于子像素S65对应的灰阶，子像素S55与S65对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S56对应的灰阶小于子像素S66对应的灰阶，子像素S56与S66对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，则可以将第八个单元组定义为目标单元组。同理，将第九个单元组和第十个单元组定义为目标单元组。
以及，第三列像素单元中，子像素S17、S18、S19、S27、S28、S29作为第十一个单元组，子像素S37、S38、S39、S47、S48、S49作为第十二个单元组。子像素S57、S58、S59、S67、S68、S69作为第十三个单元组。子像素S77、S78、S79、S87、S88、S89作为第十四个单元组。子像素S97、S98、S99、S107、S108、S109作为第十五个单元组。若第十一个单元组中，子像素S17与S27对应的显示数据的灰阶之间的差值，子像素S18与S28对应的显示数据的灰阶之间的差值，以及子像素S19与S29对应的显示数据的灰阶之间的差值，均小于设定灰阶差值阈值，则不用将第十一个单元组定义为目标单元组。同理，不用将第十二个单元组定义为目标单元组。若第十三个单元组中，子像素S57对应的灰阶大于子像素S67对应的灰阶，子像素S57与S67对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S58对应的灰阶大于子像素S68对应的灰阶，子像素S58与S68对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S59对应的灰阶大于子像素S69对应的灰阶，子像素S59与S69对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，则可以将第十三个单元组定义为目标单元组。同理，将第十四个单元组和第十五个单元组定义为目标单元组，形成目标区域 M1。并且，其余单元组均不用定义为目标单元组。
示例性地，如图5b所示，第一列像素单元中，子像素S11、S12、S13、S21、S22、S23作为第一个单元组，子像素S31、S32、S33、S41、S42、S43作为第二个单元组。子像素S51、S52、S53、S61、S62、S63作为第三个单元组。子像素S71、S72、S73、S81、S82、S83作为第四个单元组。子像素S91、S92、S93、S101、S102、S103作为第五个单元组。第二列像素单元中，子像素S14、S15、S16、S24、S25、S26作为第六个单元组，子像素S34、S35、S36、S44、S45、S46作为第七个单元组。子像素S54、S55、S56、S64、S65、S66作为第八个单元组。子像素S74、S75、S76、S84、S85、S86作为第九个单元组。子像素S94、S95、S96、S104、S105、S106作为第十个单元组。第三列像素单元中，子像素S17、S18、S19、S27、S28、S29作为第十一个单元组，子像素S37、S38、S39、S47、S48、S49作为第十二个单元组。子像素S57、S58、S59、S67、S68、S69作为第十三个单元组。子像素S77、S78、S79、S87、S88、S89作为第十四个单元组。子像素S97、S98、S99、S107、S108、S109作为第十五个单元组。其余划分单元组同理可得。若第三个单元组中，子像素S51对应的灰阶大于子像素S61对应的灰阶，子像素S51与S61对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S52与S62对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值。子像素S53与S63对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值，则可以将第三个单元组定义为目标单元组。同理，将第四个单元组和第五个单元组定义为目标单元组。同理，将第八个单元组、第九个单元组、第十个单元组、第十三个单元组、第十四个单元组以及第十五个单元组定义为目标单元组，形成目标区域M1。
示例性地，如图5c所示，第一列像素单元中，子像素S11、S12、S13、S21、S22、S23作为第一个单元组，子像素S31、S32、S33、S41、S42、S43作为第二个单元组。子像素S51、S52、S53、S61、S62、S63作为第三个单元组。子像素S71、S72、S73、S81、S82、S83作为第四个单元组。子像素S91、 S92、S93、S101、S102、S103作为第五个单元组。第二列像素单元中，子像素S14、S15、S16、S24、S25、S26作为第六个单元组，子像素S34、S35、S36、S44、S45、S46作为第七个单元组。子像素S54、S55、S56、S64、S65、S66作为第八个单元组。子像素S74、S75、S76、S84、S85、S86作为第九个单元组。子像素S94、S95、S96、S104、S105、S106作为第十个单元组。第三列像素单元中，子像素S17、S18、S19、S27、S28、S29作为第十一个单元组，子像素S37、S38、S39、S47、S48、S49作为第十二个单元组。子像素S57、S58、S59、S67、S68、S69作为第十三个单元组。子像素S77、S78、S79、S87、S88、S89作为第十四个单元组。子像素S97、S98、S99、S107、S108、S109作为第十五个单元组。其余划分单元组同理可得。若第三个单元组中，子像素S51对应的灰阶大于子像素S61对应的灰阶，子像素S51与S61对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S52对应的灰阶大于子像素S62对应的灰阶，子像素S52与S62对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S53对应的灰阶大于子像素S63对应的灰阶，子像素S53与S63对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值，则可以将第三个单元组定义为目标单元组。同理，将第四个单元组和第五个单元组定义为目标单元组。同理，将第八个单元组、第九个单元组、第十个单元组、第十三个单元组、第十四个单元组以及第十五个单元组定义为目标单元组，形成目标区域M1。
示例性地，如图5d所示，第一列像素单元中，子像素S11、S12、S13、S21、S22、S23作为第一个单元组，子像素S31、S32、S33、S41、S42、S43作为第二个单元组。子像素S51、S52、S53、S61、S62、S63作为第三个单元组。子像素S71、S72、S73、S81、S82、S83作为第四个单元组。子像素S91、S92、S93、S101、S102、S103作为第五个单元组。第二列像素单元中，子像素S14、S15、S16、S24、S25、S26作为第六个单元组，子像素S34、S35、S36、S44、S45、S46作为第七个单元组。子像素S54、S55、S56、S64、S65、S66作为第八个单元组。子像素S74、S75、S76、S84、S85、S86作为第九个 单元组。子像素S94、S95、S96、S104、S105、S106作为第十个单元组。第三列像素单元中，子像素S17、S18、S19、S27、S28、S29作为第十一个单元组，子像素S37、S38、S39、S47、S48、S49作为第十二个单元组。子像素S57、S58、S59、S67、S68、S69作为第十三个单元组。子像素S77、S78、S79、S87、S88、S89作为第十四个单元组。子像素S97、S98、S99、S107、S108、S109作为第十五个单元组。其余划分单元组同理可得。
若第三个单元组中，子像素S51对应的灰阶大于子像素S61对应的灰阶，子像素S51与S61对应的显示数据的灰阶之间的差值不小于设定灰阶差值阈值。子像素S52与S62对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值。子像素S53与S63对应的显示数据的灰阶之间的差值小于设定灰阶差值阈值，则可以将第三个单元组定义为目标单元组。同理，将第四个单元组和第五个单元组定义为目标单元组。同理，将第八个单元组、第九个单元组、第十个单元组、第十三个单元组、第十四个单元组以及第十五个单元组定义为目标单元组，形成目标区域M1。
示例性地，以像素单元包括三个子像素，相邻四行中的一列像素单元作为一个单元组为例。如图5e所示，第一列像素单元中，子像素S11、S12、S13、S21、S22、S23、S31、S32、S33、S41、S42、S43作为第一个单元组，子像素S51、S52、S53、S61、S62、S63、S71、S72、S73、S81、S82、S83作为第二个单元组。子像素S91、S92、S93、S101、S102、S103、S111、S112、S113、S121、S122、S123作为第三个单元组。第二列像素单元中，子像素S14、S15、S16、S24、S25、S26、S34、S35、S36、S44、S45、S46作为第四个单元组，子像素S54、S55、S56、S64、S65、S66、S74、S75、S76、S84、S85、S86作为第五个单元组。子像素S94、S95、S96、S104、S105、S106、S114、S115、S116、S124、S125、S126作为第六个单元组。第三列像素单元中，子像素S17、S18、S19、S27、S28、S29、S37、S38、S39、S47、S48、S49作为第七个单元组，子像素S57、S58、S59、S67、S68、S69、S77、S78、S79、S87、S88、S89作为第八个单元组。子像素S97、S98、S99、S107、S108、 S109、S117、S118、S119、S127、S128、S129作为第九个单元组。其余同理划分单元组。可以根据上述规则将第一个单元组、第二个单元组、第四个单元组、第五个单元组、第七个单元组、第八个单元组定义为目标单元组，形成目标区域M1。
需要说明的是，图5a至图5e中，通过阴影将目标区域M1中灰阶较高的子像素标示出。
在本公开实施例中，通过目标单元组形成了目标区域M1。之后，可以将目标区域M1的面积与设定面积阈值进行比较，若目标区域M1的面积不小于设定面积阈值时，则确定第二画面为不良画面。若目标区域M1的面积小于设定面积阈值时，可能使得目标区域M1较小，人眼不容易察觉，则可以确定第二画面不为不良画面。这样可以控制显示面板逐行子像素进行扫描驱动，并对各数据线加载第二画面的显示数据，以使显示面板中的每一个子像素均进行数据刷新。
在本公开实施例中，在当前显示帧中，根据第二画面的显示数据以及不良画面判定条件，确定第二画面是否为不良画面。在当前显示帧后的显示帧中，控制显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对第二行子像素连接的数据线加载第二画面的显示数据。在实际应用中，可以在当前显示帧中控制显示面板逐行子像素进行扫描驱动，并对各数据线加载第二画面的显示数据，以使显示面板中的每一个子像素均进行数据刷新。即在当前显示帧中控制每行子像素都正常开启，并且，时序控制器需要一个显示帧的时间去判定第二画面是否为不良画面，这样可以在当前显示帧中去判定第二画面是否为不良画面，在判定完成后，可以将用于显示第二画面的显示帧中，在当前显示帧之后出现的显示帧中，控制部分行子像素开启，部分行子像素呈黑态。这样可以将画面显示和判定过程同时进行，不用使判定过程占用额外的时间。
在本公开实施例中，时序控制器可以在显示第二画面的第一个显示帧中 去判定第二画面是否为不良画面，在显示第二画面的第二个显示帧及第二个显示帧之后的显示帧中进行隔行驱动。例如，在一个视频中，可以通过连续的显示帧显示画面。其中，在该视频的第一个显示帧显示第一画面，在第二个显示帧也显示第一画面，在第三个显示帧也显示第一画面，在第四个显示帧显示第二画面，在第五个显示帧也显示第二画面，在第六个显示帧也显示第二画面，在第七个显示帧也显示第二画面，在第八个显示帧也显示第二画面，等等。这样时序控制器可以在第四个显示帧去判定第二画面是否为不良画面，在第五个显示帧、第六个显示帧、第七个显示帧、第八个显示帧中进行隔行驱动。
在本公开实施例中，可以控制显示面板间隔一行子像素进行扫描驱动，也可以控制显示面板间隔两行子像素进行扫描驱动。例如，在一个显示帧内控制第奇数行子像素进行扫描驱动。则第一行子像素和第三行子像素可以作为扫描驱动的两行子像素，此时第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。第三行子像素和第五行子像素可以作为扫描驱动的两行子像素，此时第三行子像素驱动完且第五行子像素驱动中时，对所述第五行子像素连接的数据线加载所述第五行子像素对应的显示数据。第五行子像素和第七行子像素可以作为扫描驱动的两行子像素，此时第五行子像素驱动完且第七行子像素驱动中时，对所述第七行子像素连接的数据线加载所述第七行子像素对应的显示数据。其余以此类推，在此不作赘述。
例如，在一个显示帧内控制第偶数行子像素进行扫描驱动。则第二行子像素和第四行子像素可以作为扫描驱动的两行子像素，此时第二行子像素驱动完且第四行子像素驱动中时，对所述第四行子像素连接的数据线加载所述第四行子像素对应的显示数据。第四行子像素和第六行子像素可以作为扫描驱动的两行子像素，此时第四行子像素驱动完且第六行子像素驱动中时，对所述第六行子像素连接的数据线加载所述第六行子像素对应的显示数据。第六行子像素和第八行子像素可以作为扫描驱动的两行子像素，此时第六行子 像素驱动完且第八行子像素驱动中时，对所述第八行子像素连接的数据线加载所述第八行子像素对应的显示数据。其余以此类推，在此不作赘述。
在本公开实施例中，也可以控制显示面板间隔三行子像素进行扫描驱动。在本公开实施例中，例如，在一个显示帧内控制第一行、第四行、第七行子像素等进行扫描驱动时。则第一行子像素和第四行子像素可以作为扫描驱动的两行子像素，此时第一行子像素驱动完且第四行子像素驱动中时，对所述第四行子像素连接的数据线加载所述第四行子像素对应的显示数据。第四行子像素和第七行子像素可以作为扫描驱动的两行子像素，此时第四行子像素驱动完且第七行子像素驱动中时，对所述第七行子像素连接的数据线加载所述第七行子像素对应的显示数据。其余以此类推，在此不作赘述。
在本公开实施例中，也可以控制显示面板间隔四行子像素进行扫描驱动，也可以控制显示面板间隔五行或更多行子像素进行扫描驱动，在此不作限定。
结合图1a与图6，图6示意出了在确定第二画面为不良画面时，当前显示帧后的第一个显示帧中的信号示意图。在本公开实施例中，在确定第二画面为不良画面时，可以在当前显示帧后的第奇数个显示帧中，控制显示面板的第奇数行子像素进行扫描驱动，并对各数据线输出第奇数行子像素对应的显示数据。示例性地，在当前显示帧后的第奇数个显示帧中，时序控制器可以通过电平转换电路向显示面板中的栅极驱动电路输入隔行扫描控制信号(如stv-od，stv-ev，clk1，clk2，clk3，clk4)，以控制栅极驱动电路对显示面板的第奇数行子像素进行扫描驱动(如对第一行子像素耦接的栅线GA1输出信号ga1，对第二行子像素耦接的栅线GA2输出信号ga2，对第三行子像素耦接的栅线GA3输出信号ga3，对第四行子像素耦接的栅线GA4输出信号ga4)。以及，时序控制器可以在当前显示帧后的第奇数个显示帧中，向显示面板中的源极驱动电路输入隔行数据控制信号，以使源极驱动电路生成隔行数据输出信号(如信号tp)，以对各数据线输出第奇数行子像素对应的显示数据(如源极驱动电路受信号tp的上升沿的触发，可以输出一行子像素对应的显示数据。)例如，当第一行，第三行，第五行等奇数行时钟信号(CLK)输入有效 电平，则对应打开第一行，第三行，第五行等奇数行的栅线，此时在数据控制信号TP的控制下，显示数据与时钟信号交叠为2H，H代表一行像素充电时间，如此设置，相当于消隐掉偶数行的数据，对每个奇数行充电2H，可以保证充电率更足，当然，显示数据与时钟信号交叠可以大于2H，根据实际需要设置，只要保证显示面板有足够的充电率即可。
例如，结合图6，信号ga1中的高电平控制第一行子像素中的晶体管01均导通，且信号ga1中的低电平控制第一行子像素中的晶体管01均截止。信号ga3中的高电平控制第三行子像素中的晶体管01均导通，且信号ga3中的低电平控制第三行子像素中的晶体管01均截止。以及，信号ga2在第一个显示帧中均为低电平，以控制第二行子像素中的晶体管01在第一个显示帧中均截止。并且，信号ga4在第一个显示帧中均为低电平，以控制第四行子像素中的晶体管01在第一个显示帧中均截止。
以及，受控制信号tp的第一个上升沿的触发，输出第一行中各子像素对应的显示数据，如第一行第一列的显示数据da1输出到数据线DA1上，以使第一行第一列子像素输入相应的显示数据。第一行第二列的显示数据da2输出到数据线DA2上，以使第一行第二列子像素输入相应的显示数据。第一行第三列的显示数据da3输出到数据线DA3上，以使第一行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第三行中各子像素对应的显示数据，如第三行第一列的显示数据da1输出到数据线DA1上，以使第三行第一列子像素输入相应的显示数据。第三行第二列的显示数据da2输出到数据线DA2上，以使第三行第二列子像素输入相应的显示数据。第三行第三列的显示数据da3输出到数据线DA3上，以使第三行第三列子像素输入相应的显示数据。
其余第奇数行对应的驱动过程，以此类推，在此不作赘述。
并且，当前显示帧后的第三个显示帧、第五个显示帧等对应的工作过程与此基本相同，在此不作赘述。
结合图1a与图7，图7示意出了在确定第二画面为不良画面时，当前显示帧后的第二个显示帧中的信号示意图。在本公开实施例中，在确定第二画面为不良画面时，可以在当前显示帧后的第偶数个显示帧中，控制显示面板的第偶数行子像素进行扫描驱动，并对各数据线输出第偶数行子像素对应的显示数据。示例性地，在当前显示帧后的第偶数个显示帧中，电平转换电路可以通过电平转换电路向显示面板中的栅极驱动电路输入隔行扫描控制信号(如stv-od，stv-ev，clk1，clk2，clk3，clk4)，以控制栅极驱动电路对显示面板的第偶数行子像素进行扫描驱动(如对第一行子像素耦接的栅线GA1输出信号ga1，对第二行子像素耦接的栅线GA2输出信号ga2，对第三行子像素耦接的栅线GA3输出信号ga3，对第四行子像素耦接的栅线GA4输出信号ga4)。以及，时序控制器可以在当前显示帧后的第偶数个显示帧中，向显示面板中的源极驱动电路输入隔行数据控制信号，以使源极驱动电路可以生成隔行数据输出信号(如信号tp)，以对各数据线输出第偶数行子像素对应的显示数据。(如源极驱动电路受信号tp的上升沿的触发，可以输出一行子像素对应的显示数据。)例如，当第二行，第四行，第六行等偶数行时钟信号(CLK)输入有效电平，则对应打开第二行，第四行，第六行等偶数行的栅线，此时在数据控制信号TP的控制下，显示数据与时钟信号交叠为2H，H代表一行像素充电时间，如此设置，相当于消隐掉奇数行的数据，对每个偶数行充电2H，可以保证每行充电率更足，当然，显示数据与时钟信号交叠可以大于2H，根据实际需要设置，只要保证显示面板有足够的充电率即可。
例如，结合图7，信号ga2中的高电平控制第二行子像素中的晶体管01均导通，且信号ga2中的低电平控制第二行子像素中的晶体管01均截止。信号ga4中的高电平控制第四行子像素中的晶体管01均导通，且信号ga4中的低电平控制第四行子像素中的晶体管01均截止。以及，信号ga1在第二个显示帧中均为低电平，以控制第一行子像素中的晶体管01在第二个显示帧中均截止。并且，信号ga3在第二个显示帧中均为低电平，以控制第三行子像素中的晶体管01在第二个显示帧中均截止。
以及，受控制信号tp的第一个上升沿的触发，输出第二行中各子像素对应的显示数据，如第二行第一列的显示数据da1输出到数据线DA1上，以使第二行第一列子像素输入相应的显示数据。第二行第二列的显示数据da2输出到数据线DA2上，以使第二行第二列子像素输入相应的显示数据。第二行第三列的显示数据da3输出到数据线DA3上，以使第二行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第四行中各子像素对应的显示数据，如第四行第一列的显示数据da1输出到数据线DA1上，以使第四行第一列子像素输入相应的显示数据。第四行第二列的显示数据da2输出到数据线DA2上，以使第四行第二列子像素输入相应的显示数据。第四行第三列的显示数据da3输出到数据线DA3上，以使第四行第三列子像素输入相应的显示数据。
其余第偶数行对应的驱动过程，以此类推，在此不作赘述。
并且，当前显示帧后的第四个显示帧、第六个显示帧等对应的工作过程与此基本相同，在此不作赘述。
结合图1a与图8，图8示意出了在确定第二画面不为不良画面时，当前显示帧后的第一个显示帧中的信号示意图。在本公开实施例中，在确定第二画面不为不良画面时，在当前显示帧后的每一个显示帧中，时序控制器可以通过电平转换电路向显示面板中的栅极驱动电路输入逐行扫描控制信号(如stv-od，stv-ev，clk1，clk2，clk3，clk4)，以控制栅极驱动电路对显示面板的每一行子像素均进行扫描驱动(如对第一行子像素耦接的栅线GA1输出信号ga1，对第二行子像素耦接的栅线GA2输出信号ga2，对第三行子像素耦接的栅线GA3输出信号ga3，对第四行子像素耦接的栅线GA4输出信号ga4)。以及，时序控制器可以在当前显示帧后的每一个显示帧中，向显示面板中的源极驱动电路输入逐行数据控制信号，以使源极驱动电路生成逐行数据输出信号(如信号tp)，以对各数据线输出每一行子像素对应的显示数据。(如源极驱动电路受信号tp的上升沿的触发，可以输出一行子像素对应的显示数据。)。
例如，结合图8，信号ga1中的高电平控制第一行子像素中的晶体管01均导通，且信号ga1中的低电平控制第一行子像素中的晶体管01均截止。信号ga2中的高电平控制第二行子像素中的晶体管01均导通，且信号ga2中的低电平控制第二行子像素中的晶体管01均截止。信号ga3中的高电平控制第三行子像素中的晶体管01均导通，且信号ga3中的低电平控制第三行子像素中的晶体管01均截止。信号ga4中的高电平控制第四行子像素中的晶体管01均导通，且信号ga4中的低电平控制第四行子像素中的晶体管01均截止。
以及，受控制信号tp的第一个上升沿的触发，输出第一行中各子像素对应的显示数据，如第一行第一列的显示数据da1输出到数据线DA1上，以使第一行第一列子像素输入相应的显示数据。第一行第二列的显示数据da2输出到数据线DA2上，以使第一行第二列子像素输入相应的显示数据。第一行第三列的显示数据da3输出到数据线DA3上，以使第一行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第二行中各子像素对应的显示数据，如第二行第一列的显示数据da1输出到数据线DA1上，以使第二行第一列子像素输入相应的显示数据。第二行第二列的显示数据da2输出到数据线DA2上，以使第二行第二列子像素输入相应的显示数据。第二行第三列的显示数据da3输出到数据线DA3上，以使第二行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第三行中各子像素对应的显示数据，如第三行第一列的显示数据da1输出到数据线DA1上，以使第三行第一列子像素输入相应的显示数据。第三行第二列的显示数据da2输出到数据线DA2上，以使第三行第二列子像素输入相应的显示数据。第三行第三列的显示数据da3输出到数据线DA3上，以使第三行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第四个上升沿的触发，输出第四行中各子像素对应的显示数据，如第四行第一列的显示数据da1输出到数据线DA1上，以使 第四行第一列子像素输入相应的显示数据。第四行第二列的显示数据da2输出到数据线DA2上，以使第四行第二列子像素输入相应的显示数据。第四行第三列的显示数据da3输出到数据线DA3上，以使第四行第三列子像素输入相应的显示数据。
其余行对应的驱动过程，以此类推，在此不作赘述。
并且，当前显示帧后的第二个显示帧、第三个显示帧、第四个显示帧等对应的工作过程与此基本相同，在此不作赘述。
本公开实施例提供了另一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，结合图1a与图9，图9示意出了在确定第二画面为不良画面时，当前显示帧后的第一个显示帧中的信号示意图。在本公开实施例中，在确定第二画面为不良画面时，可以在当前显示帧后的第奇数个显示帧中，控制显示面板的第偶数行子像素进行扫描驱动，并对各数据线输出第偶数行子像素对应的显示数据。示例性地，在当前显示帧后的第奇数个显示帧中，时序控制器可以通过电平转换电路向显示面板中的栅极驱动电路输入隔行扫描控制信号(如stv-od，stv-ev，clk1，clk2，clk3，clk4)，以控制栅极驱动电路对显示面板的第偶数行子像素进行扫描驱动(如对第一行子像素耦接的栅线GA1输出信号ga1，对第二行子像素耦接的栅线GA2输出信号ga2，对第三行子像素耦接的栅线GA3输出信号ga3，对第四行子像素耦接的栅线GA4输出信号ga4)。以及，时序控制器可以在当前显示帧后的第偶数个显示帧中，向显示面板中的源极驱动电路输入隔行数据控制信号，以使源极驱动电路生成隔行数据输出信号(如信号tp)，以对各数据线输出第偶数行子像素对应的显示数据。(如源极驱动电路受信号tp的上升沿的触发，可以输出一行子像素对应的显示数据)。
例如，结合图9，信号ga2中的高电平控制第二行子像素中的晶体管01均导通，且信号ga2中的低电平控制第二行子像素中的晶体管01均截止。信 号ga4中的高电平控制第四行子像素中的晶体管01均导通，且信号ga4中的低电平控制第四行子像素中的晶体管01均截止。以及，信号ga1在第一个显示帧中均为低电平，以控制第一行子像素中的晶体管01在第一个显示帧中均截止。并且，信号ga3在第一个显示帧中均为低电平，以控制第三行子像素中的晶体管01在第一个显示帧中均截止。
以及，受控制信号tp的第一个上升沿的触发，输出第二行中各子像素对应的显示数据，如第二行第一列的显示数据da1输出到数据线DA1上，以使第二行第一列子像素输入相应的显示数据。第二行第二列的显示数据da2输出到数据线DA2上，以使第二行第二列子像素输入相应的显示数据。第二行第三列的显示数据da3输出到数据线DA3上，以使第二行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第四行中各子像素对应的显示数据，如第四行第一列的显示数据da1输出到数据线DA1上，以使第四行第一列子像素输入相应的显示数据。第四行第二列的显示数据da2输出到数据线DA2上，以使第四行第二列子像素输入相应的显示数据。第四行第三列的显示数据da3输出到数据线DA3上，以使第四行第三列子像素输入相应的显示数据。
其余行对应的驱动过程，以此类推，在此不作赘述。
并且，当前显示帧后的第三个显示帧、第五个显示帧等对应的工作过程与此基本相同，在此不作赘述。
在本公开实施例中，结合图1a与图10，图10示意出了在确定第二画面为不良画面时，当前显示帧后的第二个显示帧中的信号示意图。在本公开实施例中，在确定第二画面为不良画面时，可以在当前显示帧后的第偶数个显示帧中，控制显示面板的第奇数行子像素进行扫描驱动，并对各数据线输出第奇数行子像素对应的显示数据。示例性地，在当前显示帧后的第偶数个显示帧中，时序控制器可以通过电平转换电路向显示面板中的栅极驱动电路输入隔行扫描控制信号(如stv-od，stv-ev，clk1，clk2，clk3，clk4)，以控制栅 极驱动电路对显示面板的第奇数行子像素进行扫描驱动(如对第一行子像素耦接的栅线GA1输出信号ga1，对第二行子像素耦接的栅线GA2输出信号ga2，对第三行子像素耦接的栅线GA3输出信号ga3，对第四行子像素耦接的栅线GA4输出信号ga4)。以及，时序控制器可以在当前显示帧后的第偶数个显示帧中，向显示面板中的源极驱动电路输入隔行数据控制信号，以使源极驱动电路生成隔行数据输出信号(如信号tp)，以对各数据线输出第奇数行子像素对应的显示数据(如源极驱动电路受信号tp的上升沿的触发，可以输出一行子像素对应的显示数据，例如，受控制信号tp的第一个上升沿的触发，输出第一行中各子像素对应的显示数据，如第一行第一列的显示数据da1输出到数据线DA1上，第一行第二列的显示数据da2输出到数据线DA2上，第一行第三列的显示数据da3输出到数据线DA3上。受控制信号tp的第二个上升沿的触发，输出第三行中各子像素对应的显示数据，如第三行第一列的显示数据da1输出到数据线DA1上，第三行第二列的显示数据da2输出到数据线DA2上，第三行第三列的显示数据da3输出到数据线DA3上。)。
例如，结合图10，信号ga1中的高电平控制第一行子像素中的晶体管01均导通，且信号ga1中的低电平控制第一行子像素中的晶体管01均截止。信号ga3中的高电平控制第三行子像素中的晶体管01均导通，且信号ga3中的低电平控制第三行子像素中的晶体管01均截止。以及，信号ga2在第二个显示帧中均为低电平，以控制第二行子像素中的晶体管01在第二个显示帧中均截止。并且，信号ga4在第二个显示帧中均为低电平，以控制第四行子像素中的晶体管01在第二个显示帧中均截止。
以及，受控制信号tp的第一个上升沿的触发，输出第一行中各子像素对应的显示数据，如第一行第一列的显示数据da1输出到数据线DA1上，以使第一行第一列子像素输入相应的显示数据。第一行第二列的显示数据da2输出到数据线DA2上，以使第一行第二列子像素输入相应的显示数据。第一行第三列的显示数据da3输出到数据线DA3上，以使第一行第三列子像素输入相应的显示数据。
以及，受控制信号tp的第二个上升沿的触发，输出第三行中各子像素对应的显示数据，如第三行第一列的显示数据da1输出到数据线DA1上，以使第三行第一列子像素输入相应的显示数据。第三行第二列的显示数据da2输出到数据线DA2上，以使第三行第二列子像素输入相应的显示数据。第三行第三列的显示数据da3输出到数据线DA3上，以使第三行第三列子像素输入相应的显示数据。
其余第奇数行对应的驱动过程，以此类推，在此不作赘述。
并且，当前显示帧后的第四个显示帧、第六个显示帧等对应的工作过程与此基本相同，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，时序控制器与源极驱动电路可以通过通用型之输入输出(General Purpose Input Output，GPIO)接口耦接，以通过GPIO接口传输信号。
示例性地，时序控制器可以通过将通用型之输入输出接口输出具有第一数字的第一设定比特位、以及具有第一数字和第二数字的第二设定比特位，作为隔行数据控制信号输出。以及源极驱动电路可以在检测到第一设定比特位为第一数字时，根据第二设定比特位，生成隔行数据输出信号。例如，第一数字可以为“1”，第二数字可以为“0”，第一设定比特位可以为第22比特位，第二设定比特位可以为第23比特位。这样可以使第22比特位携带数字信号“1”，第23比特位携带数字信号“1”和“0”。源极驱动电路可以将接收到的第22比特位和第23比特位存储到控制单元(Control packets)中。以根据第22比特位携带的数字信号“1”，使能源极驱动电路中对应隔行数据控制信号的工作模式，从而使源极驱动电路可以相应的驱动显示面板。并且，根据第23比特位携带的数字信号“1”，在当前显示帧后的第偶数个显示帧中，控制显示面板的第偶数行子像素进行扫描驱动，并对各数据线输出第偶数行 子像素对应的显示数据。以及，根据第23比特位携带的数字信号“0”，在当前显示帧后的第奇数个显示帧中，控制显示面板的第奇数行子像素进行扫描驱动，并对各数据线输出第奇数行子像素对应的显示数据。或者，根据第23比特位携带的数字信号“1”，在当前显示帧后的第偶数个显示帧中，控制显示面板的第奇数行子像素进行扫描驱动，并对各数据线输出第奇数行子像素对应的显示数据。以及，在当前显示帧后的第奇数个显示帧中，控制显示面板的第偶数行子像素进行扫描驱动，并对各数据线输出第偶数行子像素对应的显示数据。
示例性地，时序控制器可以通过将通用型之输入输出具有第二数字的第一设定比特位，作为逐行数据控制信号输出。以及源极驱动电路可以在检测到第一设定比特位为第二数字时，生成逐行数据输出信号。例如，第一数字可以为“1”，第二数字可以为“0”，第一设定比特位可以为第22比特位，第二设定比特位可以为第23比特位。这样可以使第22比特位携带数字信号“0”。源极驱动电路可以将接收到的第22比特位存储到控制单元(Control packets)中，以根据第23比特位携带的数字信号“0”，使能源极驱动电路中对应逐行数据控制信号的工作模式，从而使源极驱动电路可以相应的驱动显示面板。
当然，第一数字也可以为“0”，第二数字也可以为“1”，第一设定比特位和第二设定比特位可以为其他比特位，在此不作限定。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、 嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开阈值的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和阈值。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的阈值之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种显示面板的驱动方法，包括：
    在由第一画面切换到第二画面，且所述第二画面在连续的至少两个显示帧显示时，在所述第二画面的当前显示帧中接收所述第二画面的显示数据；
    根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面；
    当确定所述第二画面为不良画面时，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。
  2. 如权利要求1所述的显示面板的驱动方法，其中，所述不良画面判定条件包括：不良区域的设定面积阈值以及同一列中相邻两个子像素对应的显示数据的灰阶之间的设定灰阶差值阈值；
    所述确定所述第二画面为不良画面，具体包括：
    确定所述第二画面的显示数据中，满足所述设定灰阶差值阈值的显示数据对应的子像素形成的目标区域；
    在所述目标区域满足所述设定面积阈值时，确定所述第二画面为不良画面。
  3. 如权利要求2所述的显示面板的驱动方法，其中，所述确定所述第二画面的显示数据中，满足所述设定差值阈值的显示数据对应的子像素形成的目标区域，具体包括：
    以相邻至少两行中的至少一列像素单元作为一个单元组，将所述显示面板中的像素单元分为多个单元组；
    针对每个所述单元组对应的显示数据，确定同一列中相邻两行子像素对应的显示数据的灰阶之间的灰阶差值；
    在所述灰阶差值满足所述设定灰阶差值阈值时，将满足所述设定灰阶差 值阈值的灰阶差值对应的子像素所在的单元组定义为目标单元组；
    所有所述目标单元组形成所述目标区域。
  4. 如权利要求1-3任一项所述的显示面板的驱动方法，其中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据，具体包括：
    在所述当前显示帧后的显示帧中，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据。
  5. 如权利要求4所述的显示面板的驱动方法，其中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二画面的显示数据，具体包括：
    在所述当前显示帧后的第奇数个显示帧中，控制所述显示面板的第奇数行子像素进行扫描驱动，并对各所述数据线输出第奇数行子像素对应的显示数据；
    在所述当前显示帧后的第偶数个显示帧中，控制所述显示面板的第偶数行子像素进行扫描驱动，并对各所述数据线输出第偶数行子像素对应的显示数据。
  6. 如权利要求4所述的显示面板的驱动方法，其中，所述控制所述显示面板间隔至少一行子像素进行扫描驱动，具体包括：
    在所述当前显示帧后的第奇数个显示帧中，控制所述显示面板的第偶数行子像素进行扫描驱动，并对各所述数据线输出第偶数行子像素对应的显示数据；
    在所述当前显示帧后的第偶数个显示帧中，控制所述显示面板的第奇数行子像素进行扫描驱动，并对各所述数据线输出第奇数行子像素对应的显示 数据。
  7. 如权利要求1-3任一项所述的显示面板的驱动方法，其中，在所述当前显示帧中，根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面。
  8. 一种显示装置，包括：
    显示面板；
    时序控制器，被配置为在由第一画面切换到第二画面，且所述第二画面在连续的至少两个显示帧显示时，在所述第二画面的当前显示帧中接收所述第二画面的显示数据；根据所述第二画面的显示数据以及不良画面判定条件，确定所述第二画面是否为不良画面；在确定所述第二画面为不良画面时，向所述显示面板中的栅极驱动电路输入隔行扫描控制信号和向所述显示面板中的源极驱动电路输入隔行数据控制信号，控制所述显示面板间隔至少一行子像素进行扫描驱动，并在扫描驱动的两行子像素中，第一行子像素驱动完且第二行子像素驱动中时，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据。
  9. 如权利要求8所述的显示装置，其中，所述时序控制器还被配置为在确定所述第二画面不为不良画面时，向所述显示面板中的栅极驱动电路输入逐行扫描控制信号和向所述显示面板中的源极驱动电路输入逐行数据控制信号，控制所述显示面板逐行子像素进行扫描驱动，并对各所述数据线加载各行子像素对应的显示数据。
  10. 如权利要求9所述的显示装置，其中，所述时序控制器与所述源极驱动电路通过通用型之输入输出接口耦接；
    所述时序控制器进一步被配置为通过将所述通用型之输入输出接口的驱动使能引脚设置为隔行驱动有效电平，以作为所述隔行数据控制信号输出；以及通过将所述通用型之输入输出接口的驱动使能引脚设置为逐行驱动有效电平，以作为所述逐行数据控制信号输出；
    所述源极驱动电路进一步被配置为在检测到所述驱动使能引脚的电平为 隔行驱动有效电平时，生成隔行数据输出信号，并根据生成的隔行数据输出信号，对所述第二行子像素连接的数据线加载所述第二行子像素对应的显示数据；以及在检测到所述驱动使能引脚的电平为逐行驱动有效电平时，生成逐行数据输出信号，并根据生成的逐行数据输出信号，对各所述数据线加载各行子像素对应的显示数据。
  11. 如权利要求10所述的显示装置，其中，所述时序控制器进一步被配置为将所述驱动使能引脚的电平由第一电平切换为第二电平，作为所述隔行驱动有效电平；以及将所述驱动使能引脚的电平保持所述第一电平，作为所述逐行驱动有效电平；
    所述源极驱动电路进一步被配置为将所述驱动使能引脚的电平对应的电压与存储的设定电压阈值进行比较，在所述驱动使能引脚的电平对应的电压高于所述设定电压阈值时，生成所述隔行数据输出信号；在所述驱动使能引脚的电平对应的电压不高于所述设定电压阈值时，生成所述逐行数据输出信号。
  12. 如权利要求9所述的显示装置，其中，所述时序控制器与所述电平转换电路通过通用型之输入输出接口耦接；
    所述时序控制器进一步被配置为通过将所述通用型之输入输出接口输出具有第一数字的第一设定比特位、以及具有第一数字和第二数字的第二设定比特位，作为所述隔行数据控制信号输出；以及通过将所述通用型之输入输出具有第二数字的第一设定比特位，作为所述逐行驱动使能信号输出；
    所述源极驱动电路进一步被配置为在检测到所述第一设定比特位为第一数字时，根据所述第二设定比特位，生成所述隔行数据输出信号；以及在检测到所述第一设定比特位为第二数字时，生成所述逐行数据输出信号。
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