WO2023061171A1 - 接口控制电路、集成电路及电子设备 - Google Patents

接口控制电路、集成电路及电子设备 Download PDF

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Publication number
WO2023061171A1
WO2023061171A1 PCT/CN2022/120278 CN2022120278W WO2023061171A1 WO 2023061171 A1 WO2023061171 A1 WO 2023061171A1 CN 2022120278 W CN2022120278 W CN 2022120278W WO 2023061171 A1 WO2023061171 A1 WO 2023061171A1
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Prior art keywords
circuit
signal
channel
interface
comparator
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PCT/CN2022/120278
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English (en)
French (fr)
Inventor
欧阳振华
韩雪峰
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芯海科技（深圳）股份有限公司
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Publication of WO2023061171A1 publication Critical patent/WO2023061171A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Definitions

  • the present application relates to the technical field of communication, and more specifically, relates to an interface control circuit, an integrated circuit, and an electronic device.
  • Type-C is more and more widely used in mobile terminals.
  • a DC offset may occur due to the large current, which may easily lead to errors in the judgment of the back-end system, making the signal transmission accuracy of the Type-C controller lower.
  • the present application proposes an interface control circuit, an integrated circuit and electronic equipment to solve the above problems in the prior art.
  • An embodiment of the present application provides an interface control circuit, including an interface circuit, a capacitive isolation channel, a signal transmission channel, a channel switching circuit, and a receiving circuit.
  • the capacitive isolation channel is connected to the interface circuit, and the capacitive isolation channel includes a signal node.
  • One end of the signal transmission channel is connected to the interface circuit, and the other end is connected to the signal node.
  • the channel switching circuit is connected to the capacitive isolation channel and the signal transmission channel.
  • the input terminal of the receiving circuit is connected to the signal node.
  • An embodiment of the present application further provides an integrated circuit, including the above-mentioned interface control circuit.
  • the embodiment of the present application also provides an electronic device, including a device body and the above-mentioned integrated circuit disposed in the device body.
  • FIG. 1 shows a block diagram of an interface control circuit provided by an embodiment of the present application
  • Fig. 2 shows another block diagram provided by the embodiment of the present application.
  • FIG. 3 shows a schematic circuit structure diagram of an interface control circuit provided by an embodiment of the present application.
  • Type-C is more and more widely used in mobile terminals.
  • a DC offset may occur due to the large current, which may easily lead to errors in the judgment of the back-end system, making the signal transmission accuracy of the Type-C controller lower.
  • the interface control circuit is provided with an interface circuit, a capacitive isolation channel, a signal transmission channel, and a channel switching circuit. and a receiving circuit; wherein the capacitive isolation channel is connected to the interface circuit and includes a signal node; one end of the signal transmission channel is connected to the interface circuit, and the other end is connected to the signal node; the channel switching circuit is connected to the capacitive isolation channel and the signal transmission channel; the receiving circuit
  • the input terminal is connected to the signal node.
  • the interface control circuit provided by the embodiment of the present application can switch the transmission channel of the input signal between the capacitive isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit.
  • the transmission channel is switched to the capacitive isolation channel , the DC voltage of the signal node can be maintained at a stable value, maintaining the stability of the DC component in the input signal, thereby suppressing the offset of the DC component of the input signal, and improving the accuracy of signal transmission.
  • an interface control circuit 10 provided in the present application includes an interface circuit 11 , a capacitive isolation channel 13 , a signal transmission channel 15 , a channel switching circuit 19 and a receiving circuit 17 .
  • the capacitive isolation channel 13 is connected to the interface circuit 11
  • the capacitive isolation channel 13 includes a signal node 131 connected to the receiving circuit 17 .
  • One end of the signal transmission channel 15 is connected to the interface circuit 11 , and the other end is connected to the signal node 131 .
  • the channel switching circuit 19 is connected to the capacitive isolation channel 13 and the signal transmission channel 15 , and the input terminal of the receiving circuit 17 is connected to the signal node 131 .
  • the interface circuit 11 can be used to connect to an external interface and receive an input signal through the external interface.
  • the external interface can be a power delivery port.
  • the interface circuit 11 can be used to interface with a Micro USB interface or a Type-C USB interface. , Lightning USB interface or other interface connections.
  • the interface circuit 11 may include one or more channels, and when the interface circuit 11 includes multiple configuration channels, the interface circuit 11 may also include a data selector (Multiplexer, MUX).
  • the MUX can receive multiple input data or signals, and can output any one of the multiple input data or signals.
  • the interface circuit 11 when the interface circuit 11 is used to connect with the Type-C USB interface, the interface circuit 11 includes a plurality of configuration channels (Configuration Channel, CC) and MUX, and the signals of the plurality of configuration channels are selected and output through the MUX.
  • the MUX may be, but not limited to, a 4-to-1 data selector, a 6-to-1 data selector, an 8-to-1 data selector, and a 16-to-1 data selector.
  • the interface circuit 11 can be used to connect external devices.
  • the interface circuit 11 when the interface circuit 11 is a USB interface, the interface circuit 11 can be connected to an external device through a USB data cable.
  • the external devices may include but not limited to smart phones, tablet computers, smart watches, smart bracelets, electronic scales, earphones and electronic paper book readers.
  • the capacitive isolation channel 13 includes a signal node 131 , and the input terminal of the receiving circuit 17 is connected to the signal node 131 .
  • the capacitive isolation channel 13 can be used to provide a transmission channel for the input signal of the interface control circuit 10 , so that the input signal is input from the interface circuit 11 to the receiving circuit 17 .
  • the capacitive isolation channel 13 is turned on, the signal node 131 maintains a stable DC level.
  • the input signal is transmitted to the receiving circuit 17 through the isolation capacitor in the capacitive isolation channel 13 based on the principle of charge conservation, and the DC level of the signal node 131 remain unchanged, thereby suppressing the offset of the DC component of the input signal and reducing the offset of the input signal received by the receiving circuit 17 .
  • the signal transmission channel 15 can be connected to the interface circuit 11 and the signal node 131, the signal transmission channel 15 can be used to provide another transmission channel for the signal of the interface control circuit 10, and make the input signal from the interface circuit 11 Input to the receiving circuit 17.
  • the channel switching circuit 19 is connected to the capacitive isolation channel 13 and the signal transmission channel 15 , and can be used to switch the transmission channel of the input signal between the capacitive isolation channel 13 and the signal transmission channel 15 .
  • the transmission channel of the input signal can be switched to the capacitive isolation channel 13
  • the transmission channel of the input signal can be switched to Signal transmission channel 15.
  • the transmission channel of the input signal can be switched to the capacitive isolation channel 13 through the channel switching circuit 19 as required, so that the DC voltage of the signal node 131 can be maintained at a stable value, that is, the input received by the receiving circuit 17 can be maintained.
  • the DC component in the signal is stable, thereby suppressing the offset of the DC component of the input signal and improving the accuracy of signal transmission.
  • the capacitive isolation channel 13 may include a capacitor C and a first comparator A1, one end of the capacitor C may be connected to the interface circuit 11, and the other end of the capacitor C may be connected to the first comparator output of A1. Wherein, the other end of the capacitor C may be the signal node 131 .
  • the other end of the capacitor C may be directly connected to the output end of the first comparator A1, or indirectly connected to the output end of the first comparator A1 through other components.
  • the other end of the capacitor C may be indirectly connected to the output end of the first comparator A1 through one or more switches.
  • the capacitive isolation channel 13 can isolate the DC component of the input signal input from the interface circuit 11 to the capacitive isolation channel 13 through the characteristics of the capacitor C communicating AC and blocking DC.
  • the first comparator A1 can compare a preset input signal with a reference voltage, so that the first comparator A1 outputs a preset level signal to the signal node 131, and the preset level signal can make the signal node
  • the voltage at 131 is maintained at a stable value, so that the DC component in the input signal received by the receiving circuit 17 remains stable, so it is equivalent to providing a stable DC component for the input signal, thereby realizing the control of the DC component of the input signal Drift suppression.
  • the preset reference voltage V0 may be the same as or different from the voltage value of the preset input signal of the first comparator A1.
  • the signal transmission channel 15 can also receive the input signal input from the interface circuit 11 , and can output the input signal to the receiving circuit 17 . It should be noted that the signal transmission channel 15 can be a conventional transmission channel of the interface control circuit 10 .
  • the channel switching circuit 19 may include a first switch 191 and a second switch 193 .
  • the first switch 191 can be set in the capacitive isolation channel 13, wherein, one end of the first switch 191 can be connected to the output end of the first comparator A1, and the other end of the first switch 191 can be connected to the signal node 131, that is, the first
  • the switch 191 is connected in series between the output terminal of the first comparator A1 and the signal node 131 .
  • one end of the first switch 191 may be connected to the output end of the first comparator A1, and the other end of the first switch 191 may be connected to the capacitor C.
  • the second switch 193 can be disposed on the signal transmission channel 15 , wherein one end of the second switch 193 can be connected to the interface circuit 11 , and the other end of the second switch 193 can be connected to the signal node 131 .
  • the first switch 191 can be used to turn on or turn off the capacitive isolation channel 13
  • the second switch 193 can be used to turn on or turn off the signal transmission channel 15 .
  • the capacitive isolation channel 13 is turned on, and the signal transmission channel 15 is turned off, at this time, the input signal is input to the receiving circuit 17 through the capacitive isolation channel 13;
  • the capacitive isolation channel 13 is turned off, and the signal transmission channel 15 is turned on, and the input signal is input to the receiving circuit 17 through the signal transmission channel 15 .
  • the first switch 191 includes a first transmission gate, and the first transmission gate may be connected between the output terminal of the first comparator A1 and the signal node 131 .
  • the first transmission gate may include a first field effect transistor Q1 and a second field effect transistor Q2.
  • a first terminal of the first field effect transistor Q1 can be connected to the output terminal of the first comparator A1
  • a second terminal of the first field effect transistor Q1 can be connected to the signal node 131 .
  • the first end of the second field effect transistor Q2 can be connected to the output end of the first comparator A1
  • the second end of the second field effect transistor Q2 can be connected to the signal node 131 .
  • the first end of the first field effect transistor Q1 can be connected to the first end of the second field effect transistor Q2, and the second end of the first field effect transistor Q1 can be connected to the second end of the second field effect transistor Q2. connect.
  • the channel types of the first field effect transistor Q1 and the second field effect transistor Q2 are opposite.
  • the first field effect transistor Q1 may be an N-MOS transistor
  • the second field effect transistor Q2 may be a P-MOS transistor. Tube.
  • the first terminal and the second terminal of the first field effect transistor Q1 and the second field effect transistor Q2 are source/drain respectively.
  • the gates of the first field effect transistor Q1 and the second field effect transistor Q2 are used to receive a pair of control signals with opposite phases.
  • the gate of the first field effect transistor Q1 is used to receive the first control signal ena
  • the gate of the second field effect transistor Q2 is used to receive the second control signal enb
  • the second control signal enb can be controlled by the first control signal ena Obtained by inverting the phase of the inverter A5.
  • first field effect transistor Q1 and the second field effect transistor Q2 may also be replaced by transistors with opposite polarities.
  • the second switch 193 includes a second transmission gate, which may be connected between the interface circuit 11 and the signal node 131 .
  • the second transmission gate may include a third field effect transistor Q3 and a fourth field effect transistor Q4.
  • a first end of the third field effect transistor Q3 can be connected to the interface circuit 11 , and a second end of the third field effect transistor Q3 can be connected to the signal node 131 .
  • a first end of the fourth field effect transistor Q4 can be connected to the interface circuit 11 , and a second end of the fourth field effect transistor Q4 can be connected to the signal node 131 .
  • the first end of the third field effect transistor Q3 can be connected to the first end of the fourth field effect transistor Q4, and the second end of the third field effect transistor Q3 can be connected to the second end of the fourth field effect transistor Q4. connect.
  • the channel types of the third field effect transistor Q3 and the fourth field effect transistor Q4 are opposite.
  • the third field effect transistor Q3 may be an N-MOS transistor
  • the fourth field effect transistor Q4 may be a P-MOS transistor. Tube.
  • the first terminal and the second terminal of the third field effect transistor Q3 and the fourth field effect transistor Q4 are source/drain respectively.
  • the gates of the third field effect transistor Q3 and the fourth field effect transistor Q4 are used to receive a pair of control signals with opposite phases.
  • the gate of the third field effect transistor Q3 is used to receive the first control signal ena
  • the gate of the fourth field effect transistor Q4 is used to receive the second control signal enb
  • the second control signal enb can be controlled by the first control signal ena Obtained by inverting the phase of the inverter A5.
  • the third field effect transistor Q3 and the fourth field effect transistor Q4 may also be replaced by transistors with opposite polarities.
  • the receiving circuit 17 may include a second comparator A2, wherein the first input terminal of the second comparator A2 is connected to the signal node 131, and the second input terminal of the second comparator A2 is used to receive the preset Reference voltage (Voltage Reference, VREF), the second comparator A2 can be used to compare the input signal with the preset reference voltage VREF.
  • a second comparator A2 wherein the first input terminal of the second comparator A2 is connected to the signal node 131, and the second input terminal of the second comparator A2 is used to receive the preset Reference voltage (Voltage Reference, VREF), the second comparator A2 can be used to compare the input signal with the preset reference voltage VREF.
  • the preset reference voltage VREF may include at least two reference voltages
  • the receiving circuit 17 may further include a reference switching circuit 171 .
  • the reference switching circuit 171 is connected to the second input terminal of the second comparator A2 to input any one of at least two reference voltages.
  • the second comparator A2 is used to compare the preset reference voltage V0 with any one of at least two reference voltages.
  • the interface control circuit 10 may further include an enable control circuit 12, the enable control circuit 12 is connected to the enable terminal of the first comparator A1, and is used to maintain the DC voltage at the signal node 131 at a stable value When , the first comparator A1 is controlled to be turned off, so as to reduce the power consumption of the interface control circuit 10 .
  • the enable control circuit 12 may include a NAND gate circuit A3 and an inverter A4. Wherein, the output terminal of the NAND gate circuit A3 is connected to the input terminal of the inverter A4, and the output terminal of the inverter A4 is connected to the enabling terminal of the first comparator A1.
  • the interface control circuit 10 can be controlled by a pair of inverted control signals (the first control signal ena and the second control signal enb).
  • the second control signal enb can be generated by the first control signal ena via an inverter. Specifically, the The first control signal ena is input into the inverter A5 to obtain the second control signal enb.
  • the first FET Q1 is an N-MOS tube
  • the second FET Q2 is a P-MOS tube
  • the third FET Q3 is a P-MOS tube
  • the third FET Q4 is an N-MOS tube .
  • the first FET Q1 and the third FET Q3 are controlled by the first control signal ena
  • the second FET Q2 and the fourth FET Q4 are controlled by the second control signal enb.
  • the NAND gate circuit A3 can be controlled by an enable signal EN and a first control signal ena.
  • the first control signal ena is at a high level
  • the second control signal enb is at a low level
  • the enable signal EN is at a low level.
  • the first field effect transistor Q1 and the second field effect transistor Q2 are turned on, and the third field effect transistor Q3 and the fourth field effect transistor Q4 are turned off. That is, the capacitive isolation channel 13 is activated, the signal transmission channel 15 is closed, and the transmission channel of the input signal is switched to the capacitive isolation channel 13 , and the input signal is input to the second comparator A2 through the capacitive isolation channel 13 .
  • the enable control circuit 12 inputs a low level signal to the enable terminal of the first comparator A1 to enable the first comparator A1.
  • the capacitor C can isolate the DC component of the input signal through the AC and DC isolation characteristics of the capacitor C, and at the same time, the first comparator A1 compares a preset input signal with a reference voltage, so that The first comparator A1 outputs a preset level signal to the signal node 131, and the preset level signal maintains the voltage at the signal node 131 at a stable value, so that the DC component in the input signal received by the receiving circuit 17 Maintaining stability is equivalent to providing a stable DC component for the input signal, thereby realizing the suppression of the offset of the DC component of the input signal and improving the accuracy of the input signal transmission.
  • the enable signal EN can be changed from a low level to a high level, and at this time, both the enable signal EN and the first control signal ena are at a high level , the enable control circuit 12 outputs a high-level signal to the enable terminal of the first comparator A1, so that the first comparator A1 is turned off.
  • the interface control circuit 10 can save power consumption.
  • the second control signal enb When the first control signal ena changes from high level to low level, the second control signal enb is high level. At this moment, the first field effect transistor Q1 and the second field effect transistor Q2 are turned off, and the third field effect transistor Q3 and the fourth field effect transistor Q4 are turned on. That is, the capacitive isolation channel 13 is closed, the signal transmission channel 15 is enabled, and the transmission channel of the input signal is switched to the signal transmission channel 15 , and the input signal is input to the second comparator A2 through the signal transmission channel 15 .
  • the different preset reference voltage VREF of the second comparator A2 can be switched by the reference switching circuit 171, thereby suppressing the generation of idle noise and further ensuring that the interface control circuit 10 The accuracy of the transmitted signal.
  • the interface control circuit provided in the embodiment of the present application is provided with an interface circuit, a capacitive isolation channel, a signal transmission channel, a channel switching circuit, and a receiving circuit; the capacitive isolation channel is connected to the interface circuit and includes a signal node; one end of the signal transmission channel is connected to the interface circuit , the other end is connected to the signal node; the channel switching circuit is connected to the capacitive isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node.
  • the interface control circuit provided by the embodiment of the present application receives the input signal through the interface circuit, the transmission channel of the input signal can be switched between the capacitive isolation channel and the signal transmission channel through the channel switching circuit.
  • the DC voltage of the signal node can be maintained at a stable value, maintaining the stability of the DC component in the input signal, thereby suppressing the offset of the DC component of the input signal, and improving the accuracy of signal transmission.
  • the present application also provides an integrated circuit, which includes the above-mentioned interface control circuit 10 .
  • the integrated circuit provided in the embodiment of the present application is provided with an interface circuit, a capacitive isolation channel, a signal transmission channel, a channel switching circuit, and a receiving circuit;
  • the capacitive isolation channel is connected to the interface circuit and includes a signal node; one end of the signal transmission channel is connected to the interface circuit, The other end is connected to the signal node;
  • the channel switching circuit is connected to the capacitive isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node.
  • the DC voltage of the signal node can be maintained at a stable value, maintaining the stability of the DC component in the input signal, thereby suppressing the offset of the DC component of the input signal, and improving the accuracy of signal transmission.
  • the present application also provides an electronic device.
  • the electronic device may include a device main body and the integrated circuit provided in the above embodiments.
  • the integrated circuit is disposed in the device main body, and the device main body may be used to provide an installation carrier for the integrated circuit.
  • the electronic device can be any one of multiple electronic devices, including but not limited to mobile power supplies, charging back clips, adapters, car chargers, cellular phones, smart phones, and other wireless communication devices , personal digital assistants, audio players, other media players, music recorders, video recorders, cameras, other media recorders, radios, wearable devices (e.g., such as electronic glasses, electronic clothes, electronic bracelets, electronic necklaces, electronic tattoos Head-mounted devices (HMD) or smart watches, etc.), medical equipment, vehicle transportation instruments, calculators, programmable remote controls, pagers, laptop computers, desktop computers, printers, netbook computers, personal digital assistants (PDAs) , Portable Multimedia Players (PMP), Moving Picture Experts Group (MPEG-1 or MPEG-2) Audio Layer 3 (MP3) Players, Portable Medical Devices, and Digital Cameras and combinations thereof.
  • PDAs Personal digital assistants
  • PMP Portable Multimedia Players
  • MPEG-1 or MPEG-2 Moving Picture Experts Group
  • MP3 Audio Layer 3
  • the electronic device provided in the embodiment of the present application is provided with an interface circuit, a capacitive isolation channel, a signal transmission channel, a channel switching circuit, and a receiving circuit;
  • the capacitive isolation channel is connected to the interface circuit and includes a signal node; one end of the signal transmission channel is connected to the interface circuit, The other end is connected to the signal node;
  • the channel switching circuit is connected to the capacitive isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node.
  • the DC voltage of the signal node can be maintained at a stable value, maintaining the stability of the DC component in the input signal, thereby suppressing the offset of the DC component of the input signal, and improving the accuracy of signal transmission.
  • the terms “installation” and “connection” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated Ground connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • installation and “connection” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated Ground connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • a first feature "on" a second feature may include that the first and second features are in direct contact, and may also include that the first and second features are not in direct contact but through additional feature contacts between them.
  • the first feature being "above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.

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Abstract

本申请公开了一种接口控制电路、集成电路及电子设备，其中，接口控制电路包括接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路。电容隔离通道连接于接口电路，电容隔离通道包括信号节点。信号传输通道的一端连接于接口电路，另一端连接于信号节点。通道切换电路连接于电容隔离通道以及信号传输通道。接收电路的输入端连接于信号节点。

Description

接口控制电路、集成电路及电子设备
相关申请的交叉引用
本申请要求于2021年10月11日提交的申请号为202122450741.8的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请涉及通信技术领域，更具体地，涉及一种接口控制电路、集成电路及电子设备。
背景技术
Type-C越来越广泛地被使用于移动终端。传统的Type-C控制器在工作时，由于电流较大可能产生直流偏移，容易导致后端系统的判断出现错误，使得Type-C控制器的信号传输的准确性较低。
发明内容
鉴于上述问题，本申请提出了一种接口控制电路、集成电路及电子设备，以解决以上现有技术的问题。
本申请实施例提供了一种接口控制电路，包括接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路。电容隔离通道连接于接口电路，电容隔离通道包括信号节点。信号传输通道的一端连接于接口电路，另一端连接于信号节点。通道切换电路连接于电容隔离通道以及信号传输通道。接收电路的输入端连接于信号节点。
本申请实施例还提供一种集成电路，包括如上述的接口控制电路。
本申请实施例还提供一种电子设备，包括设备主体以及设于设备主体 内的如上述集成电路。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请实施例提供的接口控制电路的一种模块框图；
图2示出了本申请实施例提供的另一种模块框图；和
图3示出了本申请实施例提供的接口控制电路的一种电路结构示意图。
具体实施方式
下面详细描述本申请的实施方式，实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本实用新型的限制。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
Type-C越来越广泛地被使用于移动终端。传统的Type-C控制器在工作时，由于电流较大可能产生直流偏移，容易可导致后端系统的判断出线错误，使得Type-C控制器的信号传输的准确性较低。
为了解决上述技术问题，发明人经过长期研究，提出了本申请实施例中的接口控制电路、集成电路及电子设备，该接口控制电路设置有接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路；其中电 容隔离通道连接于接口电路，且包括信号节点；信号传输通道一端连接于接口电路，另一端连接于信号节点；通道切换电路连接于电容隔离通道以及信号传输通道；接收电路的输入端连接于信号节点。本申请实施例提供的接口控制电路在通过接口电路接收到输入信号后，可以通过通道切换电路将输入信号的传输通道在电容隔离通道与信号传输通道之间切换，当传输通道切换为电容隔离通道时，能够将信号节点的直流电压维持在一稳定值，维持了输入信号中的直流分量的稳定，从而抑制输入信号的直流分量偏移，提高了信号传输的准确性。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
如图1所示，本申请提供的一种接口控制电路10，包括接口电路11、电容隔离通道13、信号传输通道15、通道切换电路19以及接收电路17。电容隔离通道13连接于接口电路11，电容隔离通道13包括信号节点131，该信号节点131连接于接收电路17。信号传输通道15的一端连接于接口电路11，另一端连接于信号节点131。通道切换电路19连接于电容隔离通道13以及信号传输通道15，接收电路17的输入端连接于信号节点131。
在本实施例中，接口电路11可以用于连接外部接口，并通过外部接口接收输入信号，外部接口可以为电力输送口，例如，接口电路11可以用于与Micro USB接口、Type-C USB接口、Lightning USB接口或其他接口连接。
作为一种方式，接口电路11可以包括一个或多个通道，当接口电路11包括多个配置通道时，接口电路11还可以包括数据选择器(Multiplexer，MUX)。MUX可以接收多路输入数据或信号，并可以将多路输入数据或信号中的任意一路进行输出。例如，当接口电路11用于与Type-C USB接口连接时，接口电路11包括多个配置通道(Configuration Channel,CC)和MUX，通过MUX对多个配置通道的信号进行选择输出。可选地，MUX可以为但不限于为4选1数据选择器、6选1数据选择器、8选1数据选择器以及16选1数据选择器。
在一些实施方式中，接口电路11可以用于连接外接设备。例如，当接口电路11为USB接口时，接口电路11可以通过USB数据线连接外接设备。其中，外接设备可以包括但不限于智能手机、平板电脑、智能手表、智能手环、电子秤、耳机以及电纸书阅读器。
在一些实施例中，电容隔离通道13包括信号节点131，接收电路17的输入端连接于信号节点131。电容隔离通道13可以用于为接口控制电路10的输入信号提供一种传输通道，使得输入信号从接口电路11输入至接收电路17。当电容隔离通道13导通时，信号节点131维持一稳定的直流电平，此时输入信号经由电容隔离通道13中的隔离电容，基于电荷守恒原理传输至接收电路17，而信号节点131的直流电平保持不变，从而抑制输入信号的直流分量偏移，并减小接收电路17接收到的输入信号的偏差。
在一些实施例中，信号传输通道15可以连接于接口电路11以及信号节点131，信号传输通道15可以用于为接口控制电路10的信号提供另一种传输通道，并使得输入信号从接口电路11输入至接收电路17。
通道切换电路19连接于电容隔离通道13以及信号传输通道15，并可以用于将输入信号的传输通道在电容隔离通道13和信号传输通道15之间切换。例如，当需要抑制输入信号的直流分量偏移时，可以将输入信号的传输通道切换为电容隔离通道13，当不需要抑制输入信号的直流分量偏移时，可以将输入信号的传输通道切换为信号传输通道15。本实施例中，根据需要可以通过通道切换电路19将输入信号的传输通道切换为电容隔离通道13，进而能够将信号节点131的直流电压维持在一稳定值，即维持接收电路17所接收的输入信号中的直流分量稳定，从而抑制输入信号的直流分量偏移，提高了信号传输的准确性。
如图2所示，在一些实施方式中，电容隔离通道13可以包括电容C以及第一比较器A1，电容C的一端可以连接于接口电路11，电容C的另一端可以连接于第一比较器A1的输出端。其中，电容C的另一端可以为信号节点131。 可选地，电容C的另一端可以直接连接于第一比较器A1的输出端，也可以通过其他元器件间接连接于第一比较器A1的输出端。例如，电容C的另一端可以通过一个或多个开关间接连接于第一比较器A1的输出端。
电容隔离通道13通过电容C通交流隔直流的特性，可以隔离从接口电路11输入至电容隔离通道13的输入信号中的直流分量。进一步地，第一比较器A1可以将一预设输入信号与一基准电压比较，使得第一比较器A1输出预设的电平信号至信号节点131，该预设的电平信号可以将信号节点131处的电压维持在一稳定值，使接收电路17所接收到的输入信号中的直流分量维持稳定，因此相当于为输入信号提供了稳定的直流分量，从而实现了对输入信号的直流分量的漂移的抑制。值得说明的是，该预设参考电压V0可以与第一比较器A1的预设输入信号的电压值相同或不同。
信号传输通道15同样可以接收从接口电路11输入的输入信号，并可以将该输入信号输出至接收电路17。值得说明的是，信号传输通道15可以为接口控制电路10的一种常规的传输通道。
在一些实施方式中，通道切换电路19可以包括第一开关191以及第二开关193。第一开关191可以设于电容隔离通道13中，其中，第一开关191的一端可以连接于第一比较器A1的输出端，第一开关191的另一端可以连接于信号节点131，即第一开关191串接在第一比较器A1的输出端与信号节点131之间。具体地，第一开关191的一端可以连接第一比较器A1的输出端，第一开关191的另一端可以连接电容C。第二开关193可以设于信号传输通道15，其中，第二开关193的一端可以连接于接口电路11，第二开关193的另一端可以连接于信号节点131。
一些实施方式中，第一开关191可以用于导通或者关断电容隔离通道13，第二开关193可以用于导通或者关断信号传输通道15。通过控制第一开关191的开关状态和第二开关193的开关状态，可实现电容隔离通道13和信号传输通道15之间的切换。例如，当第一开关191闭合且第二开关193断开 时，电容隔离通道13导通，且信号传输通道15关断，此时输入信号经由电容隔离通道13输入至接收电路17；当第一开关191断开且第二开关193闭合时，电容隔离通道13关断，且信号传输通道15导通，此时输入信号经由信号传输通道15输入至接收电路17。
如图3所示，在一些实施方式中，第一开关191包括第一传输门，第一传输门可以连接于第一比较器A1的输出端与信号节点131之间。作为一种示例，第一传输门可以包括第一场效应管Q1以及第二场效应管Q2。第一场效应管Q1的第一端可以连接于第一比较器A1的输出端，第一场效应管Q1的第二端可以连接于信号节点131。第二场效应管Q2的第一端可以连接于第一比较器A1的输出端，第二场效应管管Q2的第二端可以连接于信号节点131。其中，第一场效应管Q1的第一端可以与第二场效应管Q2的第一端相互连接，第一场效应管Q1的第二端可以与第二场效应管Q2的第二端相互连接。本实施方式中，第一场效应管Q1和第二场效应管Q2的沟道类型相反，例如，第一场效应管Q1可以为N-MOS管，第二场效应管Q2可以为P-MOS管。其中，第一场效应管Q1与第二场效应管Q2的第一端和第二端分别为源/漏极。第一场效应管Q1和第二场效应管的Q2的栅极用于接收一对相位相反的控制信号。例如，第一场效应管Q1的栅极用于接收第一控制信号ena，第二场效应管Q2的栅极用于接收第二控制信号enb,第二控制信号enb可以由第一控制信号ena经反相器A5反相得到。
在其他的实施方式中，第一场效应管Q1和第二场效应管Q2也可以替换为极性相反的晶体管。
在一些实施方式中，第二开关193包括第二传输门，第二传输门可以连接于接口电路11与信号节点131之间。作为一种示例，第二传输门可以包括第三场效应管Q3以及第四场效应管Q4。第三场效应管Q3的第一端可以连接于接口电路11，第三场效应管Q3的第二端可以连接于信号节点131。第四场效应管Q4的第一端可以连接于接口电路11，第四场效应管Q4的第二端可以连 接于信号节点131。其中，第三场效应管Q3的第一端可以与第四场效应管Q4的第一端相互连接，第三场效应管Q3的第二端可以与第四场效应管Q4的第二端相互连接。本实施方式中，第三场效应管Q3和第四场效应管Q4的沟道类型相反，例如，第三场效应管Q3可以为N-MOS管，第四场效应管Q4可以为P-MOS管。其中，第三场效应管Q3与第四场效应管Q4的第一端和第二端分别为源/漏极。第三场效应管Q3和第四场效应管的Q4的栅极用于接收一对相位相反的控制信号。例如，第三场效应管Q3的栅极用于接收第一控制信号ena，第四场效应管Q4的栅极用于接收第二控制信号enb,第二控制信号enb可以由第一控制信号ena经反相器A5反相得到。
在其他的实施方式中，第三场效应管Q3和第四场效应管Q4也可以替换为极性相反的晶体管。
在一些实施方式中，接收电路17可以包括第二比较器A2，其中，第二比较器A2的第一输入端连接于信号节点131，第二比较器A2的第二输入端用于接收预设基准电压(Voltage Reference，VREF)，第二比较器A2可以用于将输入信号与预设基准电压VREF比较。
在一些实施方式中，预设基准电压VREF可以包括至少两个基准电压，且接收电路17还可以包括基准切换电路171。基准切换电路171连接于第二比较器A2的第二输入端输入至少两个基准电压中的任一个。进一步地，第二比较器A2用于将预设参考电压V0与至少两个基准电压中的任一个基准电压比较。通过切换不同的预设基准电压VREF，在接收电路17工作时可抑制空闲噪声的产生，保证接口控制电路10传输信号的准确性。
在一些实施方式中，接口控制电路10还可以包括使能控制电路12，使能控制电路12连接于第一比较器A1的使能端，并用于在信号节点131的直流电压维持在一稳定值时，控制第一比较器A1关闭，以降低接口控制电路10的功耗。
在一些实施方式中，使能控制电路12可以包括与非门电路A3以及反相 器A4。其中，与非门电路A3的输出端连接于反相器A4的输入端，反相器A4的输出端连接于第一比较器A1的使能端。
作为一种示例，以下将结合图3详细阐述接口控制电路10的工作原理。
该接口控制电路10可由一对反相控制信号(第一控制信号ena和第二控制信号enb)控制，第二控制信号enb可以由第一控制信号ena经由反相器产生，具体地，可将第一控制信号ena输入反相器A5得到第二控制信号enb。
进一步地，第一场效应管Q1为N-MOS管，第二场效应管Q2为P-MOS管，第三场效应管Q3为P-MOS管，第三场效应管Q4为N-MOS管。其中，第一场效应管Q1和第三场效应管Q3受控于第一控制信号ena，第二场效应管Q2和第四场效应管Q4受控于第二控制信号enb。进一步地，与非门电路A3可以受控于一使能信号EN以及第一控制信号ena。
在初始阶段，第一控制信号ena为高电平，第二控制信号enb为低电平，且使能信号EN为低电平。此时第一场效应管Q1和第二场效应管Q2导通，且第三场效应管Q3和第四场效应管Q4关闭。也即电容隔离通道13启用，信号传输通道15关闭，输入信号的传输通道切换为电容隔离通道13，此时输入信号经由电容隔离通道13输入至第二比较器A2。与此同时，当使能信号EN为低电平，第一控制信号ena为高电平时，使能控制电路12输入低电平信号至第一比较器A1的使能端，启用第一比较器A1。在输入信号经由电容隔离通道13传输期间，通过电容C通交流隔直流的特性，电容C可以隔离输入信号的直流分量，同时第一比较器A1将一预设输入信号与一基准电压比较，使得第一比较器A1输出预设的电平信号至信号节点131，预设的电平信号将信号节点131处的电压维持在一稳定值，使得接收电路17所接收到的输入信号中的直流分量维持稳定，相当于为输入信号提供了稳定的直流分量，从而实现了对输入信号的直流分量的偏移的抑制，提高了输入信号传输的准确性。
在一些实施方式中，在输入信号经由电容隔离通道13传输期间，可以 将使能信号EN由低电平转变为高电平，此时使能信号EN与第一控制信号ena均为高电平，使能控制电路12输出高电平信号至第一比较器A1的使能端，使得第一比较器A1关闭。当第一比较器A1关闭后，接口控制电路10能够节省功耗。
当第一控制信号ena由高电平转变为低电平时，第二控制信号enb为高电平。此时第一场效应管Q1和第二场效应管Q2关闭，且第三场效应管Q3和第四场效应管Q4导通。也即电容隔离通道13关闭，信号传输通道15启用，输入信号的传输通道切换为信号传输通道15，此时输入信号经由信号传输通道15输入至第二比较器A2。
在一些实施方式中，在输入信号输入至第二比较器A2之后，通过基准切换电路171可以切换第二比较器A2不同的预设基准电压VREF，从而抑制空闲噪声的产生，进一步保证接口控制电路10传输信号的准确性。
本申请实施例提供的接口控制电路设置有接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路；电容隔离通道连接于接口电路，且包括信号节点；信号传输通道一端连接于接口电路，另一端连接于信号节点；通道切换电路连接于电容隔离通道以及信号传输通道；接收电路的输入端连接于信号节点。本申请实施例提供的接口控制电路通过接口电路接收到输入信号后，可以通过通道切换电路可以将输入信号的传输通道在电容隔离通道与信号传输通道之间切换，当传输通道切换为电容隔离通道时，能够将信号节点的直流电压维持在一稳定值，维持了输入信号中的直流分量的稳定，从而抑制输入信号的直流分量偏移，提高了信号传输的准确性。
本申请还提供一种集成电路，集成电路包括上述的接口控制电路10。
本申请实施例提供的集成电路设置有接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路；电容隔离通道连接于接口电路，且包括信号节点；信号传输通道一端连接于接口电路，另一端连接于信号 节点；通道切换电路连接于电容隔离通道以及信号传输通道；接收电路的输入端连接于信号节点。本申请实施例提供的接口控制电路通过接口电路接收到输入信号后，可以通过通道切换电路可以将输入信号的传输通道在电容隔离通道与信号传输通道之间切换，当传输通道切换为电容隔离通道时，能够将信号节点的直流电压维持在一稳定值，维持了输入信号中的直流分量的稳定，从而抑制输入信号的直流分量偏移，提高了信号传输的准确性。
本申请还提供一种电子设备，电子设备可以包括设备主体以及如上述实施例提供的集成电路，集成电路设于设备主体内，且设备主体可以用于为集成电路提供安装载体。
在本实施例中，电子设备可以为多个电子设备中的任何一个，多个电子设备包括但不限于移动电源、充电背夹、适配器、车载充电器、蜂窝电话、智能电话、其他无线通信设备、个人数字助理、音频播放器、其他媒体播放器、音乐记录器、录像机、照相机、其他媒体记录器、收音机、可穿戴设备(例如，诸如电子眼镜、电子衣服、电子手镯、电子项链、电子纹身或智能手表的头戴式设备(HMD)等)、医疗设备、车辆运输仪器、计算器、可编程遥控器、寻呼机、膝上型计算机、台式计算机、打印机、上网本电脑、个人数字助理(PDA)、便携式多媒体播放器(PMP)、运动图像专家组(MPEG-1或MPEG-2)音频层3(MP3)播放器、便携式医疗设备以及数码相机及其组合。
本申请实施例提供的电子设备设置有接口电路、电容隔离通道、信号传输通道、通道切换电路以及接收电路；电容隔离通道连接于接口电路，且包括信号节点；信号传输通道一端连接于接口电路，另一端连接于信号节点；通道切换电路连接于电容隔离通道以及信号传输通道；接收电路的输入端连接于信号节点。本申请实施例提供的接口控制电路通过接口电路接收到输入信号后，可以通过通道切换电路可以将输入信号的传输通道在 电容隔离通道与信号传输通道之间切换，当传输通道切换为电容隔离通道时，能够将信号节点的直流电压维持在一稳定值，维持了输入信号中的直流分量的稳定，从而抑制输入信号的直流分量偏移，提高了信号传输的准确性。
在本说明书的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本申请的描述中，需要理解的是，术语“长度”、“上方”、“前”、“顶”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电性连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“上方”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。
尽管已经示出和描述了本申请的实施方式，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施方式进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (10)

  1. 一种接口控制电路，其特征在于，包括：
    接口电路；
    电容隔离通道，连接于所述接口电路，所述电容隔离通道包括信号节点；
    信号传输通道，一端连接于所述接口电路，另一端连接于所述信号节点；
    通道切换电路，连接于所述电容隔离通道以及所述信号传输通道；以及
    接收电路，其输入端连接于所述信号节点。
  2. 如权利要求1所述的接口控制电路，其特征在于，所述电容隔离通道包括电容以及第一比较器，所述电容的一端连接于所述接口电路，另一端连接于所述第一比较器的输出端；其中，所述电容的另一端为所述信号节点。
  3. 如权利要求2所述的接口控制电路，其特征在于，所述接口控制电路还包括：
    使能控制电路，连接于所述第一比较器的使能端。
  4. 如权利要求3所述的接口控制电路，其特征在于，所述使能控制电路包括：
    与非门电路；以及
    反相器，输入端连接于所述与非门电路的输出端，输出端连接于所述第一比较器的使能端。
  5. 如权利要求1所述的接口控制电路，其特征在于，所述通道切换电路包括：
    第一开关，设于所述电容隔离通道，其中，所述第一开关的一端连接 于所述第一比较器的输出端，另一端连接于所述信号节点；以及
    第二开关，设于所述信号传输通道，其中，所述第二开关的一端连接于所述接口电路，另一端连接于所述信号节点。
  6. 如权利要求5所述的接口控制电路，其特征在于，所述第一开关包括第一传输门，所述第一传输门连接于所述第一比较器的输出端与所述信号节点之间；
    所述第二开关包括第二传输门，所述第二传输门连接于所述接口电路与所述信号节点之间。
  7. 根据权利要求1至6任一项所述的接口控制电路，其特征在于，所述接收电路包括：
    第二比较器，所述第二比较器的第一输入端连接于所述信号节点，所述第二比较器的第二输入端用于接收预设基准电压。
  8. 根据权利要求7所述的接口控制电路，其特征在于，所述预设基准电压包括至少两个基准电压，所述接收电路还包括：
    基准切换电路，连接于所述第二比较器的第二输入端，以用于向所述第二比较器的第二输入端输入所述至少两个基准电压中的任一个。
  9. 一种集成电路，其特征在于，包括如权利要求1至8任一项所述的接口控制电路。
  10. 一种电子设备，其特征在于，包括设备主体以及设于所述设备主体内的如权利要求9所述的集成电路。
PCT/CN2022/120278 2021-10-11 2022-09-21 接口控制电路、集成电路及电子设备 WO2023061171A1 (zh)

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