WO2023057339A3 - Flip chip package and method for fabricating a flip chip package - Google Patents

Flip chip package and method for fabricating a flip chip package Download PDF

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Publication number
WO2023057339A3
WO2023057339A3 PCT/EP2022/077324 EP2022077324W WO2023057339A3 WO 2023057339 A3 WO2023057339 A3 WO 2023057339A3 EP 2022077324 W EP2022077324 W EP 2022077324W WO 2023057339 A3 WO2023057339 A3 WO 2023057339A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
backside
flip chip
chip package
lid
Prior art date
Application number
PCT/EP2022/077324
Other languages
French (fr)
Other versions
WO2023057339A2 (en
Inventor
Navas Khan Oratti Kalandar
Do Hyung Kim
Ariel Lizaba Miranda
Ingolf Rau
Mario Soric
Kesvakumar V C MUNIANDY
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2023057339A2 publication Critical patent/WO2023057339A2/en
Publication of WO2023057339A3 publication Critical patent/WO2023057339A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A flip chip package comprises a substrate, a semiconductor die comprising a front side, an opposing backside and lateral sides connecting the front side and the backside, the semi-conductor die being arranged on the substrate such that the front side faces the substrate, a molded body at least partially encapsulating the lateral sides of the semiconductor die, a lid arranged at the backside of the semiconductor die, a layer of thermally conductive material arranged between the backside of the semiconductor die and the lid, and an adhesive mechanically coupling the lid to the semiconductor die and/or to the molded body, the adhesive being arranged at least partially along edges between the backside and the lateral sides of the semiconductor die, wherein the adhesive has an elastic modulus that is at least 50 times greater than an elastic modulus of the thermally conductive material.
PCT/EP2022/077324 2021-10-07 2022-09-30 Flip chip package and method for fabricating a flip chip package WO2023057339A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102021126041.8A DE102021126041B3 (en) 2021-10-07 2021-10-07 FLIP CHIP PACKAGE AND METHOD OF MAKING FLIP CHIP PACKAGE
DE102021126041.8 2021-10-07

Publications (2)

Publication Number Publication Date
WO2023057339A2 WO2023057339A2 (en) 2023-04-13
WO2023057339A3 true WO2023057339A3 (en) 2023-07-20

Family

ID=83995157

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2022/077324 WO2023057339A2 (en) 2021-10-07 2022-09-30 Flip chip package and method for fabricating a flip chip package

Country Status (2)

Country Link
DE (1) DE102021126041B3 (en)
WO (1) WO2023057339A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030168749A1 (en) * 2001-03-06 2003-09-11 Masahiro Koike Semiconductor device, resin sealing method and resin sealing device
US20140264813A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Package and Method
US20180358280A1 (en) * 2017-06-08 2018-12-13 Xilinx, Inc. Methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management
US20200294880A1 (en) * 2019-03-12 2020-09-17 International Business Machines Corporation Heterogeneous Thermal Interface Material for Corner and or Edge Degradation Mitigation
US20220157683A1 (en) * 2020-11-17 2022-05-19 Stmicroelectronics (Grenoble 2) Sas Integrated circuit package with heat sink and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4390541B2 (en) 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US9041192B2 (en) 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030168749A1 (en) * 2001-03-06 2003-09-11 Masahiro Koike Semiconductor device, resin sealing method and resin sealing device
US20140264813A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Package and Method
US20180358280A1 (en) * 2017-06-08 2018-12-13 Xilinx, Inc. Methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management
US20200294880A1 (en) * 2019-03-12 2020-09-17 International Business Machines Corporation Heterogeneous Thermal Interface Material for Corner and or Edge Degradation Mitigation
US20220157683A1 (en) * 2020-11-17 2022-05-19 Stmicroelectronics (Grenoble 2) Sas Integrated circuit package with heat sink and manufacturing method thereof

Also Published As

Publication number Publication date
WO2023057339A2 (en) 2023-04-13
DE102021126041B3 (en) 2022-12-01

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