WO2023056012A1 - Effets de fabrication de masque dans des simulations de masque tridimensionnel utilisant des images caractéristiques - Google Patents

Effets de fabrication de masque dans des simulations de masque tridimensionnel utilisant des images caractéristiques Download PDF

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Publication number
WO2023056012A1
WO2023056012A1 PCT/US2022/045380 US2022045380W WO2023056012A1 WO 2023056012 A1 WO2023056012 A1 WO 2023056012A1 US 2022045380 W US2022045380 W US 2022045380W WO 2023056012 A1 WO2023056012 A1 WO 2023056012A1
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Prior art keywords
mask
filter
feature
filters
edge
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PCT/US2022/045380
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English (en)
Inventor
Peng Liu
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Synopsys, Inc.
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Priority claimed from US17/956,550 external-priority patent/US20230104510A1/en
Application filed by Synopsys, Inc. filed Critical Synopsys, Inc.
Publication of WO2023056012A1 publication Critical patent/WO2023056012A1/fr

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Definitions

  • the present disclosure relates to lithographic mask simulations, including for full— chip or large-scale computational lithography applications.
  • One step in the manufacture of semiconductor wafers involves lithography.
  • a source produces light that is collected and directed by collection/illumination optics to illuminate a lithographic mask.
  • Projection optics relay the pattern produced by the illuminated mask onto a wafer, exposing resist on the wafer according to the illumination pattern.
  • the patterned resist is then used in a process to fabricate structures on the wafer.
  • Various technologies are directed to improving the lithography process, including the design of the lithographic mask.
  • the lithographic mask design is used as an input to a three-dimensional mask model, which is used to compute a mask function that describes the electromagnetic field scattering characteristics of the mask illuminated by the light source.
  • the mask function may then be used as input to an optical imaging model (e.g., Abbe imaging model or Hopkins imaging model) to predict the printed pattern in resist. It is desirable that the three-dimensional mask model is accurate as well as fast.
  • an optical imaging model e.g., Abbe imaging model or Hopkins imaging model
  • M3D three-dimensional mask
  • FIG. 1A depicts an extreme ultraviolet (EUV) lithography process suitable for use with embodiments of the present disclosure.
  • EUV extreme ultraviolet
  • FIG. 1B is a flowchart for calculating scattering from a mask according to embodiments of the present disclosure.
  • FIG. 1C is a flowchart for adjusting M3D filters to account for mask fabrication effects according to embodiments of the present disclosure.
  • FIG. 1D is another flowchart for adjusting M3D filters to account for mask fabrication effects according to embodiments of the present disclosure.
  • FIG. 2 depicts partitioning a mask layout geometry into feature images according to embodiments of the present disclosure.
  • FIG. 3 depicts feature images in a library according to embodiments of the present disclosure.
  • FIG. 4A is a flowchart for calculating an M3D filter for a feature image according to embodiments of the present disclosure.
  • FIG. 4B depicts an example M3D filter calculation according to embodiments of the present disclosure.
  • FIG. 5 depicts an example of adjusting M3D filters according to embodiments of the present disclosure.
  • FIGS. 6A-6C depict adjusting M3D filters for variation in sidewall angle according to embodiments of the present disclosure.
  • FIGS. 7A-7C depict adjusting M3D filters for variation in mask thickness according to embodiments of the present disclosure.
  • FIGS. 8A-8C depict adjusting M3D filters for variation in mask material properties according to embodiments of the present disclosure.
  • FIG. 9 depicts a flowchart of various processes used during the design and manufacture of an integrated circuit according to embodiments of the present disclosure.
  • FIG. 10 depicts a diagram of an example computer system in which embodiments of the present disclosure may operate.
  • aspects of the present disclosure relate to three-dimensional mask simulations based on feature images.
  • the illumination pattern that exposes resist on a wafer depends on the geometric layout of the lithographic mask and the source illumination, among other factors.
  • Simulation of the lithographic process depends on an accurate prediction of the electromagnetic field produced by the source illumination incident on the lithographic mask. This field may be predicted using rigorous, three-dimensional simulations of Maxwell's equations, accounting for diffraction and scattering effects. However, such simulations are computationally intensive and have long run times. As a result, in many cases, it is prohibitive to run rigorous three- dimensional simulations for the mask area covering an entire chip.
  • aspects of the present disclosure relate to calculating the electromagnetic field diffraction and scattering characteristics, as represented by a mask function (MF), by using a set of feature images (a.k.a. feature vectors) and corresponding filters (referred to as mask three- dimensional (3D) or M3D filters), some of which are modified to account for effects from the mask fabrication process.
  • the feature images represent basic geometries that may be present in the mask, and the corresponding M3D filters represent the scattering effects resulting from the feature images.
  • the M3D filters may be determined based on rigorous electromagnetic simulation of the scattering effects of the feature images given the source illumination.
  • the features images are selected from a library of predefined feature images and their corresponding precalculated mask 3D (M3D) filters.
  • the feature images in the library include, but are not limited to, the following:
  • edge feature images combinations of three or more edges (e.g., polygon shapes)
  • the actual layout geometry of the lithographic mask will include effects resulting from the mask fabrication process.
  • certain mask features may be reflective stacks constructed from layers of materials. The stacks may not have perfectly vertical sidewalls. The thicknesses of the layers may not exactly match the nominal design values. The material properties also may not exactly match the nominal design values.
  • the topography of the lithographic mask may be represented by an idealized model that does not take into account the limitations and resulting effects of the mask making process. As a result, lithography simulations that assume idealized topographies may be less accurate than desired.
  • the M3D filters are modified to account for effects arising from the mask fabrication process.
  • the M3D filters may be parameterized to provide additional degrees of freedom to account for these effects.
  • parameters include a spatial shift or biasing of the M3D filter, and additive and multiplicative constants for terms in the filter.
  • the values of these parameters are determined based on measurements of wafers fabricated using lithographic masks, where the masks were fabricated using the mask fabrication process.
  • the modified M3D filters which will be referred to as mask-corrected M3D filters, are computed and saved as lookup tables (LUT) or other data structures. These LUTs are re-used in 3D mask simulations, thus accounting for mask fabrication effects.
  • the electromagnetic field diffraction and scattering characteristics, as represented by a mask function (MF), are calculated by using a set of feature images which are convolved with the corresponding mask-corrected M3D filters.
  • Additional technical advantages of the present disclosure include, but are not limited to, the following.
  • This approach does not create additional layouts for the subsequent simulation flow to process and therefore improves simulation runtime compared to alternative approaches. It may be more suitable for use with both machine learning (ML) and non-ML frameworks as well as for graphics processing units (GPU). Compared to the full rigorous simulation, the approach is more computationally efficient for model creation, training and calibration and runtime is also reduced, while still producing accurate results for the mask function. The resulting mask function may also be used efficiently in both Hopkins and Abbe imaging models, which may be the next steps in the lithography simulation.
  • ML machine learning
  • GPU graphics processing units
  • FIG. 1A depicts an EUV lithography process suitable for use with embodiments of the present disclosure.
  • a source 102 produces EUV light that is collected and directed by collection/illumination optics 104 to illuminate a mask 110.
  • Projection optics 116 relay the pattern produced by the illuminated mask 110 onto a wafer 118, exposing resist on the wafer according to the illumination pattern.
  • the exposed resist is then developed, producing patterned resist on the wafer. This is used to fabricate structures on the wafer, for example through deposition, doping, etching or other processes.
  • the light is in the EUV wavelength range, around 13.5nm or in the range 13.3 — 13.7nm.
  • the components may be reflective, rather than transmissive.
  • the mask 110 is a reflective mask, that may be implemented as a stack of different materials, and the optics 104, 116 are also reflective and off-axis. This is just an example. Other types of lithography systems may also be used, including at other wavelengths including deep ultraviolet (DUV), using transmissive masks and/or optics, and using positive or negative resist.
  • FIG. IB is a flowchart for calculating scattering from a mask 110, taking into account effects from the mask fabrication process.
  • the diffraction and scattering from the mask 110 is represented by a mask function (MF) 150.
  • the process of FIG. IB uses a description 115 of the mask and a library 120 to determine the mask function 150 for the mask.
  • the library contains feature images 122 (e.g., predefined feature images) and corresponding filters 129, which will be referred to as mask 3D (M3D) filters because they represent the contribution to the overall mask function from that type of feature image for a given source illumination.
  • the M3D filters 129 include effects of the source illumination and have been adjusted to account for mask fabrication effects, as described in more detail herein. [0034] As shown in FIG.
  • the layout geometry of the mask is received at 130 and partitioned into feature images 142, based on the feature images 122 from library 120 at 140.
  • the mask function (MF) contribution from each feature image 142 is calculated by convolving the feature image 142 with the corresponding M3D filter 129 at 144.
  • the aggregate mask function for the mask and given source illumination is determined by combining (e.g., summing) the MF contributions from the individual feature images at 146.
  • the mask function may then be used in various design flows.
  • the mask function may be used to estimate a result of a lithography process, such as an aerial image or a printed mask pattern produced by the lithographic mask.
  • Mask correction may then be applied to the design of the lithographic mask based on the estimated result. Examples of mask correction include optical proximity correction, sub-resolution assist features, phase shifting masks, inverse lithography techniques, and source mask optimization.
  • FIG. 1C is a flowchart for developing mask-corrected M3D filters 129.
  • Uncorrected M3D filters may be developed as described below in FIGS. 2-4. These filters may be parameterized to add more degrees of freedom to account for mask fabrication effects.
  • the values of the parameters are determined by comparing predictions of simulations at 125 against measurements of actual wafers at 128. For example, wafers may be fabricated using lithographic masks, where the masks are fabricated by the mask fabrication process. Various measurements may be made, for example widths or spacings of features printed on the wafer.
  • the M3D filters may be used in simulations to predict the same measurements 126.
  • the parameters may be determined at 127 based on reducing the difference between the predicted measurement 126 and the actual measurement 128, resulting in the mask-corrected M3D filter at 129.
  • the wafer measurements 128 are used as the ground truth to directly calibrate the parameterized M3D filters 124.
  • wafer measurements 128 may be used to generate a ground truth which is then used to calibrate the parameterized M3D filters 124.
  • the three-dimensional profile of features on the wafer may be measured. These can then be used as input to an accurate simulation, which predicts the line width.
  • the measured three-dimensional profile on the wafer may be used to directly calibrate the parameterized M3D filters 124 using a model that relates the two. Measurements of the lithographic mask itself, in addition to or in place of measurements of the wafer, may also be used.
  • FIG. ID is another flowchart for adjusting M3D filters to account for mask fabrication effects according to embodiments of the disclosure.
  • the righthand side shows the fabrication of physical wafers 164 based on a test mask design 115.
  • the lefthand side shows simulation of the same process.
  • the test mask design 115 is first used in the mask fabrication process 161 to produce a printed mask (physical mask) 162.
  • the physical lithographic mask is then used in a lithography process 163 to fabricate the printed wafer (physical wafer) 164.
  • Various metrics 166 of the wafer may then be measured at 165, such as sizes of various features.
  • the test mask design 115 is used as input to a simulation that predicts the wafer characteristics that were measured in the physical fabrication flow.
  • the tunable M3D model 171 using feature images and parameterized M3D filters, predicts the diffracted mask field or mask function 172. This step accounts for the source illumination and mask fabrication effects. This result is propagated through a lens imaging model 173 to predict the aerial image 174 in resist on the wafer.
  • a resist and etch model 175 is used to predict the fabricated wafer 176, from which the same wafer metrics 177 may be estimated.
  • comparison of the measured wafer metrics 166 to the simulated predictions of the same metrics 177 is used to tune 182 the parameters for M3D filters. This feedback may also be used to adjust the other models in the simulation flow.
  • FIGS. 2-4 first describe the use of feature images without correction for mask fabrication effects.
  • FIG. 2 depicts partitioning a mask layout geometry into feature images.
  • FIG. 2 depicts partitioning a mask layout geometry into feature images.
  • Shape 210 is partitioned into the following features images: one area image, six edge images, six corner images, and two edge-to-edge (E2E) images.
  • the shape 210 may be partitioned into the feature images based on rules to identify different features present in the mask layout.
  • the interior area of the polygon shape 210 and its contribution to the mask function is represented by the Area 1 feature image. This defines which areas of the mask are opaque versus transmissive or reflective.
  • the edge feature images (Edge 1 - Edge 6) account for diffraction and scattering of the electromagnetic wave at edges.
  • the remaining feature images are based on combinations of two edges, where there will be interaction between the two edges.
  • the comer feature images (Comer 1 — Comer 6) account for interactions at corners, which is beyond just the individual contributions of the two edges. Note that in FIG. 2, the corners include both inside comers and outside comers.
  • the edge- to-edge (E2E) feature images account for interactions between parallel edges. E2E 1 accounts for interactions between Edges 1 and 3.
  • E2E 2 accounts for interactions between Edge 2 and the left edge of shape 220.
  • Each of the feature images is an image.
  • the area image may be the polygon of shape 210.
  • Each of the edge images may be a filtered version of the relevant edge. In some cases, rasterization filters are applied to generate the feature images.
  • the partitioning of the layout geometry uses feature images 122 from library 120.
  • the feature images in the library may be selected based on an understanding of scattering, and what types of geometric features contribute to scattering.
  • FIG. 3 depicts some examples of feature images in a library.
  • the features images in FIG. 3 are classified according to the number of edges in the feature image.
  • the feature images in the top row have 0 edges, the ones in the next row have 1 edge, and then 2 edges, and then 3+ edges. These are just examples and are not exhaustive.
  • the area feature image determines which areas of the mask are opaque versus transmissive or reflective. Actual instances of the area feature images may have different shapes, sizes and locations, depending on the geometric layout of shapes on the mask.
  • the M3D filter corresponding to the area feature image represents the scattering produced by each point in the area assuming an infinitely large area, i.e., the contribution to the mask function from each point within a bulk area of the geometric layout ignore any edge effects.
  • the convolution of the M3D filter with an instance of the area feature image (e.g., Area 1 in FIG. 2) yields the MF contribution from the bulk area of that shape in the mask.
  • the edge feature image is another class of feature images, because diffraction or scattering of the electromagnetic wave occurs at edges.
  • FIG. 3 shows one edge feature image, but the library may have many types of edge images.
  • four edge feature images are included in the library, corresponding to the four possible orientations of an edge in the Manhattan geometry. Some masks may also allow edges at multiples of 45 degrees, or even at arbitrary angles.
  • the M3D filter corresponding to the Edge feature image represents the scattering produced by each point along the edge assuming an infinitely long edge.
  • the third row shows another important class of feature images, which are combinations of two edges. When two edges become close enough, there will be interaction between the two edges.
  • FIG. 3 In the first two examples, the two edges are parallel. This is generally referred to as edge-to-edge (labelled E2E in FIG. 2).
  • FIG. 3 shows two different polarities, depending on whether the area between the two edges is filled by mask material or not.
  • the library may also contain edge-to-edge feature images with different separations between the edges, and with the edges oriented at different angles (horizontal, vertical, at multiples of 45 degrees, etc.).
  • the two edges In the last two examples of the third row, the two edges are perpendicular to each other.
  • comer feature images an inside corner and an outside comer, depending on the polarity.
  • the library may contain comers oriented at different angles.
  • Other two-edge feature images are also possible.
  • the two edges may be at different angles to each other.
  • the two edges may be separated but not parallel to each other. Thus, the two edges will be slowly converging or diverging. Corners at angles other than 90 degrees are also possible.
  • the bottom row shows feature images with three or more edges.
  • the first two examples are tips of both polarities.
  • the library may contain versions of different widths and at different angular orientations.
  • the next two examples are holes or vias of both polarities. Different versions may have different widths, heights and angular orientations.
  • Each of the feature images has a corresponding M3D filter that is used to produce the MF contribution from the feature image. That is, the scattering effects of the feature image are captured by the M3D filter.
  • rigorous simulations are performed for the feature images and the rigorous results are used to determine the M3D filters.
  • the M3D filters may be calculated by starting with lower order effects.
  • the effect of an Area image (0-order feature image) depends only on the transmission or reflection of the area in question.
  • the mask structure for this feature image is a plane of constant value.
  • the M3D filter is a constant equal to the transmission or reflection computed from the rigorous simulation.
  • edge feature image An edge in the layout geometry is partitioned into an area feature image plus an edge feature image.
  • the rigorous simulation of edge scattering is then modeled by the MF contribution from the Area feature image plus the MF contribution from the edge feature image.
  • the MF contribution from the Area feature image is already determined, so the mask function contribution from the Edge feature image and the corresponding M3D filter may then be determined.
  • FIG. 4A is a flowchart for calculating M3D filters for feature images, progressing from lower-order to higher-order feature images.
  • FIG. 4B depicts an example M3D filter calculation for the two-edge Gap feature image shown in FIG. 3.
  • the M3D filters for 0-edge and 1-edge feature images have already been calculated and the process moves 405 to more complex feature images: two- edge feature images.
  • the gap feature image with a specific spacing A is considered next at 410.
  • the mask structure for the gap feature image is determined to be two edges separated by a spacing A at 420.
  • Three-dimensional simulation may be executed 430 for this mask structure, yielding the mask function for this mask structure.
  • l i are the feature images
  • K i are the corresponding M3D filters
  • N is the number of feature images.
  • MF is the mask function, which in this case is known from the rigorous simulation.
  • the MF contributions for the lower-order feature images may be calculated 450 using the previously calculated M3D filters for those images. This leaves one unknown in Eqn. 1, shown pictorially at the bottom of FIG. 4B. That is the M3D filter for the gap feature image, which may then be calculated 460. In some cases, this may be used as the M3D filter 122 in the library 120, or as the basis for the parameterized M3D filter 124 in FIG. 1C.
  • the feature images may be grayscale representations of features, which allow sparse sampling of the images.
  • an edge has infinite frequency components and would require infinite bandwidth to represent with 100% fidelity.
  • it may instead be represented by a low-pass filtered version of the edge, which is like a grayscale blurry edge.
  • Polygon shapes in the mask may be rasterized using a low-pass rasterization function. This removes high frequency components of the feature, retaining only the low frequency components. This is acceptable because the projection optics is actually a low pass system, so it will naturally filter out the high (spatial) frequency components.
  • the low-pass rasterization filter is designed to have a non-uniform response in the frequency passband as compared to the uniform response of a sine or sinc-like function.
  • an equalizing filter 470 may be added to compensate for the non-uniform response.
  • the M3D filter 490 is then a combination of the electromagnetic scattering and the equalization.
  • Eqn. 1 may be calculated and solved in the spatial domain using direct convolutions. However, it may also be processed in the spatial frequency domain. The quantities are converted to the spatial frequency domain, and the convolution becomes a product. The equivalent equation is then
  • I AREA is the area feature image and F FG and F BG represent the foreground and background light reflectance / transmittance in bulk areas, which is an expression of the corresponding area M3D filter K AREA .
  • the first summation is for edge images, where I EDGE are the edge feature images and K EDGE are the corresponding M3D filters.
  • the second summation is for edge-to-edge (E2E) images, where I E2E are the E2E feature images (with parallel edges) and K E2E are the corresponding M3D filters.
  • E2E edge-to-edge
  • the Area filters may be parameterized by multiplicative constants C BG and C FG :
  • additive constants may be used:
  • the edge and E2E filters may be parameterized by a multiplicative constant C and spatial shift or bias b:
  • the shift is in coordinate x, but the shift direction will depend on the orientation of the feature image and M3D filter.
  • FIG. 5 shows an example using a ridge feature of width w.
  • the mask fabrication effects result in a feature that behaves more like a ridge feature with a width of (w+ ⁇ ).
  • this feature is partitioned into four feature images: an area image, a left edge image, a right edge image, and an E2E image as shown in the top row of FIG. 5. These images are not changed.
  • the corresponding M3D filters 550A-D are adjusted to account for the difference.
  • the Area M3D filter 550A will be scaled so that when it is applied to the Area image of width w, it produces the scattering prediction of an Area image of width (w+ ⁇ ).
  • FIGS. 6-9 show examples using four different mask fabrication effects.
  • FIGS. 6A-6C consider variations in the mask sidewall angle.
  • sidewall angles of mask features may be assumed to be perfectly vertical (sidewall angle of 90 degrees), as shown in the top mask profile of FIG. 6A.
  • the sidewalls When fabricated, the sidewalls may be sloped, as shown in the bottom mask profile of FIG. 6A.
  • the mask profiles in FIG. 6A are shown in wafer scale, which is 4x smaller than the actual mask size.
  • This sidewall variation causes changes in diffraction from the mask.
  • One possible effect is on shadowing. This type of mask feature causes shadow, but the non-vertical sidewalls will reduce the amount of shadow, particularly for off- axis illumination.
  • the mask feature shown may be partitioned into an area image, two edge images and an E2E image.
  • the effects of non-vertical sidewalls may be accounted for by applying a spatial shift to the corresponding Edge and E2E filters.
  • the area filter may or may not be affected, depending on whether the angled sidewall affects the total light reflection/transmission of the feature.
  • FIGS. 6B and 6C show the effectiveness of this approach.
  • the nominal mask feature has vertical sidewalls and the actual mask feature has sidewalls that are 2 degrees off vertical (88 degree angle).
  • FIG. 6B plots the difference between aerial image (Al) predicted by a simulation of the 88 degree sidewall versus as predicted by the approach described herein.
  • the x-axis is the spatial shift or bias b in nm
  • the y-axis is the normalized RMS value of the difference between the aerial images.
  • a bias of b -0.3nm yields good matching to the results predicted by the more rigorous simulation.
  • the negative bias means that the absorber appears to be smaller than nominal, which is consistent with what is expected.
  • FIGS. 7A-7C consider variations in the mask stack thickness.
  • Mask features may be implemented as a stack of one or more materials of nominal thicknesses. The actual thicknesses may be greater or less than the nominal values. If the stack is absorptive, then thinner stacks may have a reduced shadowing effect and therefore appear smaller than the nominal version.
  • the thickness variation can also impact the amplitude and phase of the overall transmission or reflection. These effects may be accounted for by shifting the Edge-based filter and also adjusting the Area filter.
  • FIGS. 7B and 7C are analogous to FIGS. 6B and 6C, but for thickness change.
  • the nominal thickness is 76.5nm and the actual thickness is 69nm.
  • the z-axis in FIG. 7 A is wafer scale which is 4x smaller than the mask scale, so the 76.5nm mask will appear as 19.1nm according to the z scale in FIG. 7A.
  • FIGS. 7B and 7C plot the RMS values of the differences between aerial images and between critical dimensions, respectively, as a function of bias b.
  • the corresponding M3D filters are adjusted in two ways. First, curves 720B and 720C show the difference metrics as a function of bias b. Second, a phase shift of -8.09 degrees is also applied to the area filter. Curves 730B and 730C plot the difference metrics as a function of bias b, including the phase shift of -8.09 degrees.
  • FIGS. 8A-8C consider variations in the material properties of the mask, such as index of refraction (n) and dielectric constant (k). These material properties are assumed to have certain nominal values, but the actual values in the fabricated mask may vary. If the stack is absorptive, then lower contrast materials (i.e., the difference in n or k between different materials is less than nominal), then the stack will have weaker diffraction and may appear smaller than the nominal version. These variations can also affect the amplitude and phase of the overall transmission or reflection. These effects may be accounted for by shifting the Edge-based filter and also adjusting the Area filter.
  • n index of refraction
  • k dielectric constant
  • FIGS. 8B and 8C are analogous to FIGS. 7B and 7C, but for changes in index of refraction.
  • the corresponding M3D filters are adjusted as in FIG. 7.
  • Curves 820B and 820C show the difference metrics as a function of bias b.
  • a phase shift of -8 degrees and amplitude scaling of 1.0063 are also applied to the Area filter.
  • Curves 830B and 830C plot the difference metrics as a function of bias b with these additional adjustments.
  • the bias b is feature— dependent. It is larger for narrower features and smaller for wider features.
  • FIG. 9 illustrates an example set of processes 900 used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit.
  • Each of these processes can be structured and enabled as multiple modules or operations.
  • the term ‘EDA’ signifies the term ‘Electronic Design Automation.’
  • These processes start with the creation of a product idea 910 with information supplied by a designer, information which is transformed to create an article of manufacture that uses a set of EDA processes 912.
  • the design is taped-out 934, which is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit.
  • a semiconductor die is fabricated 936 and packaging and assembly processes 938 are performed to produce the finished integrated circuit 940.
  • Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages.
  • a high-level of representation may be used to design circuits and systems, using a hardware description language (‘HDL’) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera.
  • the HDL description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description.
  • RTL logic-level register transfer level
  • Each lower representation level that is a more detailed description adds more useful detail into the design description, for example, more details for the modules that include the description.
  • the lower levels of representation that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process.
  • An example of a specification language at a lower level of representation language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of representation are enabled for use by the corresponding systems of that layer (e.g., a formal verification system).
  • a design process may use a sequence depicted in Fig. 9. The processes described by be enabled by EDA products (or EDA systems).
  • system design 914 functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or lines of code), and reduction of costs, etc. Partitioning of the design into different types of modules or components can occur at this stage.
  • modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy.
  • the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed.
  • Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers.
  • simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers.
  • special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification.
  • HDL code is transformed to a netlist.
  • a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected.
  • Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design.
  • the netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.
  • netlist verification 920 the netlist is checked for compliance with timing constraints and for correspondence with the HDL code.
  • design planning 922 an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.
  • layout or physical implementation 924 physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the circuit components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions can be performed.
  • the term ‘cell’ may specify a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop or latch).
  • a circuit ‘block’ may refer to two or more cells. Both a cell and a circuit block can be referred to as a module or component and are enabled as both physical structures and in simulations.
  • Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products.
  • the circuit function is verified at the layout level, which permits refinement of the layout design.
  • the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification.
  • the geometry of the layout is transformed to improve how the circuit design is manufactured.
  • tape-out data is created to be used (after lithographic enhancements are applied if appropriate) for production of lithography masks.
  • mask data preparation 932 the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits.
  • a storage subsystem of a computer system may be used to store the programs and data structures that are used by some or all of the EDA products described herein, and products used for development of cells for the library and for physical and logical design that use the library.
  • FIG. 10 illustrates an example machine of a computer system 1000 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed.
  • the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet.
  • the machine may operate in the capacity of a server or a client machine in client- server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.
  • the machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine.
  • PC personal computer
  • PDA Personal Digital Assistant
  • STB set-top box
  • STB set-top box
  • a Personal Digital Assistant PDA
  • a cellular telephone a web appliance
  • server a server
  • network router a network router
  • switch or bridge any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine.
  • machine shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
  • the example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.
  • processing device 1002 represents one or more processors such as a microprocessor, a central processing unit, or the like.
  • the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets.
  • Processing device 1002 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • DSP digital signal processor
  • the processing device 1002 may be configured to execute instructions 1026 for performing the operations and steps described herein.
  • the computer system 1000 may further include a network interface device 1008 to communicate over the network 1020.
  • the computer system 1000 also may include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), graphics processing unit 1022, video processing unit 1028, and audio processing unit 1032.
  • a video display unit 1010 e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)
  • an alphanumeric input device 1012 e.g., a keyboard
  • a cursor control device 1014 e.g., a mouse
  • graphics processing unit 1022 e.g., a graphics processing unit 1022
  • signal generation device 1016
  • the data storage device 1018 may include a machine-readable storage medium 1024 (also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein.
  • the instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and/or within the processing device 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media.
  • the instructions 1026 include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium 1024 is shown in an example implementation to be a single medium, the term “machine- readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 1002 to perform any one or more of the methodologies of the present disclosure.
  • machine-readable storage medium shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
  • the present disclosure also relates to an apparatus for performing the operations herein.
  • This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic- optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
  • the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure.
  • a machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).
  • a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

Abstract

Des images caractéristiques représentant une géométrie de disposition d'un masque lithographique sont reçues. Des contributions de fonction de masque (MF) provenant d'images caractéristiques individuelles sont calculées en effectuant une convolution de l'image caractéristique avec un filtre de masque tridimensionnel (M3D) correspondant. Les filtres M3D représentent un effet de diffusion électromagnétique de cette image caractéristique. Au moins un filtre M3D tient également compte des effets résultant d'un processus de fabrication du masque lithographique.
PCT/US2022/045380 2021-10-01 2022-09-30 Effets de fabrication de masque dans des simulations de masque tridimensionnel utilisant des images caractéristiques WO2023056012A1 (fr)

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US17/956,550 US20230104510A1 (en) 2021-10-01 2022-09-29 Mask fabrication effects in three-dimensional mask simulations using feature images

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7703069B1 (en) * 2007-08-14 2010-04-20 Brion Technologies, Inc. Three-dimensional mask model for photolithography simulation
WO2014127985A1 (fr) * 2013-02-22 2014-08-28 Asml Netherlands B.V. Modèle de lithographie pour dispositif de formation de motifs tridimensionnels
WO2019162346A1 (fr) * 2018-02-23 2019-08-29 Asml Netherlands B.V. Procédés d'entraînement de modèle d'apprentissage automatique pour une lithographie par calcul
US20200004161A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Lithographic mask correction using volume correction techniques
WO2021091838A1 (fr) * 2019-11-04 2021-05-14 Synopsys, Inc. Utilisation de modèles de fabrication de masque dans la correction de masques lithographiques

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7703069B1 (en) * 2007-08-14 2010-04-20 Brion Technologies, Inc. Three-dimensional mask model for photolithography simulation
WO2014127985A1 (fr) * 2013-02-22 2014-08-28 Asml Netherlands B.V. Modèle de lithographie pour dispositif de formation de motifs tridimensionnels
WO2019162346A1 (fr) * 2018-02-23 2019-08-29 Asml Netherlands B.V. Procédés d'entraînement de modèle d'apprentissage automatique pour une lithographie par calcul
US20200004161A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Lithographic mask correction using volume correction techniques
WO2021091838A1 (fr) * 2019-11-04 2021-05-14 Synopsys, Inc. Utilisation de modèles de fabrication de masque dans la correction de masques lithographiques

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