WO2023051998A1

WO2023051998A1 - Integrated circuit arrangement having a controllable current source, and method for controlling a current source

Info

Publication number: WO2023051998A1
Application number: PCT/EP2022/073162
Authority: WO
Inventors: Volker Pesahl; Andreas HINDEMIT; Konrad Hirsch; Stefan Haimerl
Original assignee: Vitesco Technologies GmbH
Priority date: 2021-10-01
Filing date: 2022-08-19
Publication date: 2023-04-06
Also published as: DE102021211116A1

Abstract

The invention relates to an integrated circuit arrangement (100) having a controllable current source (10) for producing an AC current (I) having an adjustable mean value, wherein the current source (10) comprises two respectively controllable DC current sources (10-1, 10-2), which use opposite current directions to energize a common circuit node (K) that is connected, via a current path (P), to an output connection (OUT) for outputting the AC current (I). According to the invention, it is proposed that, in a normal operating mode, the two DC current sources (10-1, 10-2) are switched on and off in complementary fashion with respect to one another using PWM modulation and, in the process, the currents (I1, I2) of the two DC current sources (10-1, 10-2) are adjusted in accordance with a respective preset (B1, B2), and, in a calibration mode, the current path (P) is interrupted and the circuit node (K) is discharged, then the two DC current sources (10-1, 10-2) are simultaneously switched on and the currents (I1, I2) thereof are adjusted in accordance with the respective preset (B1, B2), and finally at least one of the two presets (B1, B2) is altered on the basis of a potential (pot) detected at the circuit node (K), in order to align the two currents (I1, I2) with one another in the normal operating mode. A corresponding method for controlling a controllable current source (10) of an integrated circuit arrangement (100) is also proposed.

Description

Integrated circuit arrangement with a controllable current source and method for controlling a current source

The present invention relates to an integrated circuit arrangement with at least one controllable current source for generating an adjustable current. Furthermore, the invention relates to a method for controlling such a current source and the use of such a circuit arrangement or such a method.

Current sources of this type, often referred to as “charge pumps”, as well as integrated circuit configurations equipped therewith are known in a wide variety of designs from the prior art.

Reference is made to the publications DE 100 32 248 B4, DE 10 2006 018 236 A1 and US Pat. No. 6,989,698 B2, merely by way of example. Circuit arrangements with a controllable current source for generating an adjustable current are described therein. For this purpose, the current source has two direct current sources, each of which can be controlled, which energize a common circuit node with current directions opposite to one another, which is connected to an output connection of the circuit arrangement for outputting the current. Depending on which of the two direct current sources is switched on, a current can be generated that flows out of the circuit arrangement from the output connection or into the circuit arrangement via the output connection. During operation of the current source, the two direct current sources are switched on and off complementarily to one another by means of respective switching signals in order to provide a required direction of current at the output connection, with the current strength also being able to be set by means of additionally specified respective bias signals. The circuits described in these publications can the adjustable current with an output voltage within a

supply voltage range. In addition, are from the state However, controllable current sources or charge pumps are also known in the art, in which adjustable currents can be generated and delivered at a voltage higher than the supply voltage.

There are many areas of application for such power sources. A widespread application is, for example, the energization of a control loop filter in a phase-locked loop ("phase-locked loop", PLL), in which a voltage-controlled oscillator is controlled by means of the current generated by the current source after its conversion (by means of the loop filter) into a voltage.

Another application is the energization of a sensor, the operation of which requires such an energization with at least one current (often with several currents) with a current intensity that can be specified as precisely as possible.

An example of this is an exhaust gas sensor used on an internal combustion engine to measure a NOx concentration and/or an air/fuel ratio. In such sensors, electrical currents are used as so-called "pump currents" to accomplish the electrochemical transport processes in the sensor provided according to the sensor functional principle (e.g. "pumping" oxygen ions through a solid electrolyte), with the accuracy of the measurement result of the sensor, among other things, being as exact as possible Ability to adjust or knowledge of the current strength of the current or currents generated for energizing the sensor is of great importance.

It is an object of the present invention to show a new way of achieving the most exact possible adjustability of the current strength in a current source formed in an integrated circuit arrangement.

According to the present invention, this object is achieved by an integrated circuit arrangement according to claim 1 or a method for controlling a controllable current source of an integrated circuit arrangement according to claim 10 solved. The dependent claims relate to advantageous developments of the invention.

The integrated circuit arrangement according to the invention can, for. B. as an application-specific integrated circuit (ASIC) and can be implemented in addition to at least one controllable power source depending on the application z. B. have one or more other controllable power sources and / or other application-specific devices.

The (at least one) current source is used to generate an alternating current with an adjustable mean value and for this purpose has two controllable direct current sources that energize a common circuit node with current directions opposite to one another, which is connected via a current path to an output terminal for outputting the alternating current. In this respect one can also speak of a controllable "bipolar" current source.

If the circuit arrangement has a plurality of current sources, a plurality of respectively associated current paths and output connections for outputting the individual alternating currents, each with an adjustable mean value, must accordingly be provided. In the following description, the (simplest) case is discussed first, in which the circuit arrangement has only one current source.

The term "mean value" (of the alternating current to be output) is to be understood in the context of this description without loss of generality as being signed so that a positive mean value means that the alternating current output has a positive current direction when viewed on average over time, and that a negative mean value means that the alternating current output has a negative current direction when viewed on average over time.

The terms "positive current direction" and "negative current direction" in relation to the output connection are used in this description without limitation Generality defined in such a way that a positive current direction means that the current in question, be it an instantaneous current or the alternating current output as an average over time, flows into the circuit arrangement via the output connection, whereas a negative current direction means that the current in question flows through the output connection flows out of the circuit arrangement.

The circuit arrangement according to the invention has a control device which is designed to switch the two direct current sources on and off in a normal operating mode based on a pulse width modulation (PWM) signal supplied to the control device in a PWM-modulated manner complementary to one another by means of respective switching signals and by means of switching signals specified by the control device respective bias signals (e.g. bias currents) to set the current strengths of the two direct current sources.

The "complementary" switching provided for in normal operation (for power generation and delivery) means that one of the two direct current sources is always switched on while the other is switched off, and vice versa.

In the simplest case, the control device generates a switching signal identical to the supplied PWM signal for switching one direct current source on and off and outputs it to this direct current source, and a switching signal corresponding to the inverted PWM signal for switching the other direct current source on and off is generated and sent to it issued.

Each edge of the PWM signal causes a complementary switching of the two DC sources, so that the specification of the PWM signal (which is either generated within the integrated circuit arrangement or generated externally and supplied to the integrated circuit arrangement) specifies the frequency of the alternating current output by the circuit arrangement becomes. A special feature of the circuit arrangement according to the invention is that the control device is also designed to use a "calibration mode" to match the two current levels supplied by the two direct current sources when they are switched on.

The more precisely these two current intensities match, the more precisely the mean value of the alternating current generated is set by the duty cycle of the PWM signal supplied to the control device (ratio of pulse duration to period duration).

The ability to calibrate the current source, which is provided according to the invention, thus advantageously enables an exact setting of the mean value of the alternating current that is output based on a correspondingly predefined PWM signal.

In order to enable the calibration, the circuit arrangement according to the invention also has:

- a potential detection device for detecting a potential at the circuit node,

a first switch (e.g. transistor) arranged in the course of the current path and controllable by the control device by means of a first switching signal, and

- a second switch (e.g. transistor) which can be controlled by the control device by means of a second switching signal and which is electrically connected to the circuit node on the one hand and has a predetermined reference potential applied to it on the other, the control device being designed for this purpose in the calibration mode - bring about an interruption of the current path and a discharge of the circuit node to the reference potential by outputting corresponding first and second switching signals to the first and second switches,

- then switch on both direct current sources at the same time using the respective switching signals and set their current levels using the specified respective bias signals, and finally, depending on the potential detected at the circuit node, change the specification of at least one of the two bias signals in order to align the two current levels in the normal operating mode with one another.

The term "circuit node" is to be understood in the topological sense as an electrically conductively connected area in the design of the integrated circuit arrangement with connection to the direct current sources and the current path.

The term "discharging the circuit node" takes account of the fact that the area of the circuit arrangement forming the circuit node always has a certain capacitance (for example at least a so-called parasitic capacitance) in practice.

The function of the calibration provided according to the invention can be described as follows:

1 . Step: The interruption of the current path prevents an external device (e.g. an exhaust gas sensor) connected in practice to the output connection from being able to influence the potential of the circuit node. the z. B. simultaneously (or shortly before or shortly after) initiated discharge of the circuit node to the reference potential then results in a well-defined and stable state of the circuit node (potential = reference potential). 2nd step: By switching on and setting both at the same time

Direct current sources according to the "bias specifications" will change more or less rapidly at the circuit node in the event of an inequality of the current strengths of the two direct current sources. If the potential z. B. gradually becomes "more positive", the current strength of the DC source energizing "towards the circuit node" is greater. Conversely, if the potential becomes "more negative", then the current strength of the direct current source energizing "away from the circuit node" is greater. Both cases can be identified from the potential detected by the potential detection device.

3rd step: By changing the specification of at least one of the two bias signals as a result of this detection in a suitable manner depending on the potential detected at the circuit node, the difference between the said current intensities is finally reduced and the two current intensities are thus matched to one another. In one embodiment, only the specification of one of the two bias signals is changed accordingly for this purpose.

In the calibration mode, the output terminal is not electrically connected to the current path and the DC sources are needed "otherwise" (when performing step 2 above). In principle, the calibration mode can be carried out in any "currentless" phase, i.e. while no current is provided via the output connection.

In one embodiment, it is provided that the integrated circuit arrangement has a first and a second supply connection for applying a first and a second supply potential (or at least internal first and second supply nodes for providing such first and second supply potentials), in order to be able to connect to these supply potentials, e.g. B. to supply all devices of the circuit arrangement electrically. The first supply connection can be electrically connected to the circuit node via the first controllable direct current source and the second supply connection can be electrically connected to the circuit node via the second controllable direct current source.

In one embodiment it is provided that the two direct current sources each have a transistor (e.g. FET) controlled by the switching signal specified by the control device and a transistor (e.g. FET) controlled by the bias signal specified by the control device arranged in series connection thereto. exhibit.

In this case, such a voltage-supplied series connection of two transistors (e.g. FETs) can form a controllable current path, with one transistor functioning as a "switching transistor" and the other transistor as a "setting transistor" (cf. e.g. 5).

Alternatively, z. B. be provided that the two DC sources each have only a single transistor (z. B. FET) or consist of a single transistor. In this case, the transistor supplied with a voltage (e.g. source-drain voltage in the case of an FET) can form said controllable current path, whereby this transistor, according to this alternative, however, simultaneously has the functions "switching" and "setting (of the current intensity) " of the direct current source in question. In practice, this z. B. be provided on the part of the control device that a bias signal representing the bias signal or generated based on the bias signal via a switched on and off by means of the switching signal transistor (e.g. FET) to a control input (e.g. gate of a FET) of the first-mentioned transistor (see e.g. Fig. 4).

Deviating from such embodiments, numerous other circuit implementations of the current sources are also possible within the scope of the invention (eg with operational amplifiers). In one embodiment, it is provided that the control device is designed to, in calibration mode, depending on the at the circuit node after a predetermined delay period (e.g. at least 0.5 ps and e.g. at most 100 ps) after the two have been switched on DC sources detected value of the potential to change the specification of at least one of the bias signals.

This embodiment takes into account the fact that in the calibration mode, depending on the capacitance of the circuit node and depending on the current of the two DC sources, it takes a certain amount of time before any (possibly very small) inequality in the currents supplied by the two DC sources results in a mean the potential detection leads to a clearly recognizable change in the potential at the circuit node.

In an advantageously particularly simple embodiment, it is provided that the potential detection device is designed as a comparator which compares the potential at the circuit node with the reference potential and outputs a result signal representing the result of this comparison to the control device.

On the basis of the result signal, the control device can change at least one of the two specifications as a function of the comparison result, in order to align the two current intensities with one another in the normal operating mode.

In one embodiment variant, the control device is designed to change only one of the two bias specifications in this step, specifically by a “small step” in the right direction (depending on the result of the comparison). After the calibration mode has been repeated several times during operation of the integrated circuit arrangement, a "calibrated state" will then finally set in in which the comparison result supplied by the comparator to the control device jumps back and forth more or less alternately between the two possible results. In another embodiment variant, the control device is designed to change both bias specifications in opposite directions by a "small step" in the correct direction in each case in order to achieve the "calibrated state" again after repeating the calibration mode several times.

Another embodiment provides that the potential detection device is designed as a voltage measuring device that measures the difference between the potential at the circuit node and the reference potential and outputs a result signal representing the result of this voltage measurement to the control device.

In one embodiment variant, the control device is designed to change one of the bias specifications (alternatively: both bias specifications in each case) in this step by an amount in the correct direction (depending on the sign of the measured voltage), which is greater in terms of amount, the greater the amount of the measured voltage is. This can be advantageous z. B. faster or after fewer executions of the calibration mode, the "calibrated state" of the power source can be reached.

In a preferred embodiment, the integrated circuit arrangement has a first and a second supply connection for applying a first and a second supply potential, the specified reference potential being at least approximately in the middle between the two supply potentials (example: first supply potential=−5V; second supply potential = +5V; reference potential = 0V).

In the context of the invention z. B. it can be provided that the reference potential is generated within the integrated circuit arrangement from the externally applied first and second supply potentials and is thus made available for use. Deviating from this, however, e.g. It can be provided, for example, that the reference potential, like the first and second supply potentials, is applied externally to the integrated circuit arrangement and can be used in this way in the integrated circuit arrangement.

Also within the scope of the invention z. B. be provided that the reference potential (z. B. ground potential) and z. B. one of the first and second supply potentials, z. B. a positive supply potential, is applied externally to the integrated circuit arrangement and the other of these two supply potentials, z. B. a negative supply potential is generated within the integrated circuit arrangement.

Against this background, it should be noted that for all the embodiments described here, in which the integrated circuit arrangement has "a first and a second supply connection for applying a first and a second supply potential", a modified embodiment in each case also lies within the scope of the invention, in which the integrated circuit arrangement instead z. B. "a first and a second supply node for providing a first and a second supply potential". This takes into account the fact explained above that for each potential required for the operation of a circuit arrangement according to the invention and thus to be provided, both an external application and an internal generation (from other externally applied potentials) are in principle possible. Apart from that, the modified embodiments then have the structure and function of the explicitly described embodiments.

In one embodiment it is provided that an ESD protection device is provided at a point of the current path which is permanently electrically connected to the output connection, with a replica of the ESD protection device being provided which in calibration mode can be electrically connected to a point of the current path which is also is electrically connected to the circuit node in the calibration mode. The term "ESD protective device" designates a device for protecting the integrated circuit arrangement against destruction by large electrostatic potential differences or voltage breakdowns ("electrostatic discharge", ESD) caused thereby.

With this embodiment, ESD protection can advantageously be implemented against any electrostatic potential that would otherwise penetrate via the output connection to the current path within the integrated circuit arrangement. At the same time, with this embodiment, any influence of the ESD protection device on the power generation in normal operating mode (e.g. due to leakage currents between current path and ESD protection device) can be advantageously simulated in calibration mode using the "replica that can be switched on the current path" in calibration mode. It should be noted here that the actual ESD protection device is, so to speak, “switched off from the current path” by the interruption of the current path provided in the calibration mode.

The ESD protection device can e.g. B. have two diodes oriented in the reverse direction, which are electrically connected on the one hand to the relevant point of the current path and on the other hand electrically connected to one of the two supply terminals.

In this case, the replica of the ESD protection device would accordingly also have two diodes oriented in the reverse direction, which on the one hand are each "switchably" electrically connected to the relevant point of the current path and on the other hand z. B. are permanently electrically connected to one of the two supply terminals. Switching the replica on and off in calibration mode can e.g. B. be realized by means of switching transistors arranged in series with the diodes.

In one embodiment, the integrated circuit arrangement also has a control device which is designed to, depending on at least to determine a specification for the mean value of the alternating current to be generated from a control signal supplied to the control device and/or at least one measurement signal supplied to the control device, and to generate a suitable PWM signal based on the specification for the mean value and to output it to the control device.

In a further development of this embodiment, the integrated circuit arrangement is designed as a sensor interface module for operating at least one sensor, for example an exhaust gas sensor on an internal combustion engine (e.g. Otto engine or diesel engine, e.g. of a vehicle), with one connection of the sensor being connected to the output connection the integrated circuit arrangement and thus an energization of the sensor with the alternating current with an adjustable mean value is provided.

In this case in particular, the aforementioned “measurement signal” can be e.g. B. be a potential measured on the current path in question, which is representative of a pump voltage and/or Nernst voltage present in the sensor in question. As an alternative or in addition to taking the measurement signal into account when specifying the mean value of the alternating current to be generated, the measurement signal can be B. also represent a component of sensor measurement data that are provided or sent by the integrated circuit arrangement (z. B. via a digital communication bus). In particular in the case of use as a sensor interface module for an exhaust gas sensor, the circuit arrangement (e.g. within the named control device) can also have at least one control device which calculates the mean value of the alternating current to be generated based on a voltage (simultaneously or previously) tapped off at the sensor (e.g. B. Nernst voltage) specifies. This specification as such, which is set as a result of the regulation, can also represent a component of the sensor measurement data provided or sent by the integrated circuit arrangement. According to a further aspect of the present invention, the object stated at the outset is achieved by a method for controlling a controllable current source of an integrated circuit arrangement according to claim 10.

The current source controlled by the method according to the invention for generating an alternating current with an adjustable mean value has two controllable direct current sources that energize a common circuit node with opposite current directions, which is connected via a current path to an output terminal for outputting the alternating current. The integrated circuit arrangement also has: a potential detection device for detecting a potential at the circuit node; a controllable first switch arranged in the course of the current path; and a controllable second switch which, on the one hand, is electrically connected to the circuit node and, on the other hand, has a predetermined reference potential applied to it.

The method according to the invention has the following steps:

- in a normal operating mode: PWM-modulated switching on and off of the two direct current sources complementary to one another and setting the current strengths of the two direct current sources according to a respective specification,

- In a calibration mode: interrupting the current path by opening the first switch and discharging the circuit node to the reference potential by closing the second switch, then simultaneously switching on the two DC sources using the respective switching signals and setting their current levels according to the respective specification, and finally changing at least one of the two specifications as a function of the potential detected at the circuit node in order to align the two current levels in the normal operating mode with one another. The embodiments and special configurations described here for the integrated circuit arrangement according to the invention can, individually or in any combination, also be provided in an analogous manner as embodiments or special configurations of the method according to the invention, and vice versa.

In one embodiment of the invention, at least one of the following is provided in the calibration mode:

- the opening of the first switch and the closing of the second switch occur simultaneously,

- the two direct current sources are switched on and the second switch is opened simultaneously,

- the opening of the second switch takes place after a fixed predetermined delay period (e.g. at least 0.5 ps and e.g. at most 100 ps) after the closing of the second switch,

- The change in at least one of the two specifications depends significantly on one or more values of the potential detected at the circuit node, which are detected at one or more corresponding detection times, with each detection time being provided by a fixed predetermined detection delay period after the opening of the second switch is.

In one embodiment of the invention, it is provided that in the calibration mode the change in the at least one of the two specifications depends to a large extent on a single value of the potential detected at the circuit node, which is detected at a detection time which is a fixed, predefined detection delay period after the opening of the second switch is provided. In a further development of this embodiment, it is provided that the change in the at least one of the two defaults depends significantly on whether the value of the potential detected at the circuit node is greater or less than the reference potential.

According to a further aspect of the invention, the use of an integrated circuit arrangement and/or a method of the type described here for realizing the operation of a sensor is proposed.

Within the scope of this use according to the invention, the operated sensor can be, for example, in particular an exhaust gas sensor on an internal combustion engine, in particular a sensor for measuring a NOx concentration and/or an air/fuel ratio.

The invention is described in more detail below using exemplary embodiments with reference to the accompanying drawings. They represent:

1 shows a block diagram of an integrated circuit arrangement with at least one controllable current source according to an exemplary embodiment,

FIG. 2 shows an illustration of exemplary time profiles of various signals and an output current in a normal operating mode of the current source shown in FIG. 1 ,

3 shows an illustration of exemplary time profiles of various signals and currents in a calibration mode of the current source shown in FIG. 1 ,

4 shows a representation to illustrate a circuit implementation of a controllable current source of an integrated circuit arrangement according to an embodiment, and FIG. 5 shows a representation corresponding to FIG. 4 according to a further exemplary embodiment.

1 shows an exemplary embodiment of an integrated circuit arrangement 100, which in this example is in the form of an application-specific sensor interface module (ASIC) and is intended for use in operating a sensor (not shown).

It is essential here that the sensor requires an electrical current supply with at least one precisely adjustable current during its operation. For this purpose, the integrated circuit arrangement 100 has an output connection OUT, to which the sensor can be connected in the usage situation and thus supplied with a current.

The integrated circuit arrangement 100 shown in Fig. 1 has a controllable current source 10 for generating an alternating current I with an adjustable mean value Im, the current source 10 having two controllable direct current sources 10-1, 10-2, which share a common circuit node with mutually opposite current directions Energize K, which is connected via a current path P to the output terminal OUT for outputting the alternating current I.

Deviating from this, and preferred in many applications, the integrated circuit arrangement 100 could also be equipped with a plurality of such controllable current sources 10, i.e. to generate a plurality of respective alternating currents with adjustable average values, the sensor in question then being electrically connected via a plurality of output connections formed on the integrated circuit arrangement 100 is to be connected. This could be the connected sensor z. B. be an exhaust gas sensor on an internal combustion engine of a vehicle, in particular a sensor for measuring a NOx concentration and / or an air / fuel ratio, for the operation of which usually several "pump currents" are required. The integrated circuit arrangement 100 shown also has a drive device 12 which is designed to switch the two direct current sources 10-1, 10-2 in a normal operating mode (for the operation of the sensor) based on a PWM signal PWM supplied to the drive device 12 in a complementary manner to one another Switching on and off PWM-modulated by respective switching signals S1, S2 and by means of respective bias signals B1, B2 predetermined by the control device 12 to set the current intensities 11, I2 of the two direct current sources 10-1, 10-2.

The circuit arrangement 100 has a first supply connection K1 for applying a first (eg negative) supply potential V1 and a second supply connection K2 for applying a second (eg positive) supply potential V2. From the applied supply potentials V1, V2 (not shown), a reference potential GND is also generated within the integrated circuit arrangement 100, which is in the middle between the supply potentials V1, V2 (example: V1=-2.5 V, V2=+2, 5V, GND = 0V).

The first supply connection K1 is electrically connected to the circuit node K via the first controllable direct current source 10-1 and the second supply connection K2 is electrically connected to the circuit node K via the second controllable direct current source 10-2.

The circuit arrangement 100 also has a potential detection device 14, by means of which a potential pot at the circuit node K can be detected during operation (eg in relation to GND).

The circuit arrangement 100 also has a first switch 16, which is arranged in the course of the current path P and can be actuated by the actuation device 12 by means of a first switching signal SU, and a second switch 18, which can be actuated by the actuation device 12 by means of a second switching signal SE and which, on the one hand, is electrically connected to the circuit node K is connected and on the other hand with the specified reference potential GND (here z. B. 0V) is applied. The drivable switches 16, 18 shown as switches in FIG. B. be formed by a switching transistor (z. B. FET).

In the aforementioned "normal operating mode" the first switch 16 is closed and the second switch 18 is open.

Fig. 2 illustrates the normal operating mode using an example profile of a PWM signal PWM output by the control device 12 as a function of the time t and the resulting profiles of the switching signals S1, S2 and the current I provided at the output terminal OUT in the example shown.

A PWM signal PWM with a period Tpwm can be seen by way of example in FIG. 2 . During each period duration Tpwm, the signal PWM initially has the logical value 1 for a positive pulse duration (hereinafter referred to as "pulse duration") Tpos and then the logical value 0 for a negative pulse duration Tneg.

Very generally advantageous in many applications of the invention is a period of the PWM signal of at least 10 ps, in particular at least 100 ps, and on the other hand z. B. a maximum of 10 ms, in particular a maximum of 5 ms.

In the example shown (Fig. 2), a (current) duty cycle of the PWM signal, defined as the ratio of pulse duration to period duration, i.e. Tpos / Tpwm, is approximately 0.63.

The switching signal S1 is output or forwarded by the control device 12 to the first direct current source 10-1 identically to the supplied signal PWM.

The switching signal S2 is output by the control device 12 as an inverted version of the signal PWM to the second direct current source 10-2. The two direct current sources 10-1, 10-2 are thus switched on and off complementarily to one another based on the signal PWM. It is assumed that the direct current sources 10-1, 10-2 are switched on in each case if (and as long as) the assigned switching signal S1 or S2 has the logic value 1.

The two direct current sources 10-1, 10-2 are designed identically to one another and are initially set with mutually corresponding bias signals B1, B2, so that the following applies to their current intensities I1, I2 in the “ideal case”: I1=I2.

If this identical "nominal" current intensity is referred to as Ipeak (= 11 = I2), then in normal operating mode the following applies to the current I flowing at the output connection OUT in the "ideal case": if (as long as) the direct current source 10-1 is switched on: I = +lpeak if (while) DC source 10-2 is on: I = -Ipeak

This results in the time profile of the alternating current I that can be seen in FIG. 2, which ideally corresponds exactly to the time profile of the signal PWM.

In particular for the application mentioned here as an example of energizing an exhaust gas sensor with "pump currents", a nominal value of the current strength of the two direct current sources (Ipeak) is often advantageous within the scope of the invention, which is at least 1 pA, in particular at least 2 pA, and on the other hand z. B. is a maximum of 50 mA, in particular a maximum of 20 mA. If the circuit arrangement has a plurality of current sources of the type described here, according to one embodiment of the invention, their values (Ipeak) are not all of the same size, but at least partially different from one another.

Coming back to Fig. 2, a frequency as well as the (time) mean value Im of the current I can easily be specified by a suitable specification of the signal PWM: Frequency of the alternating current I = frequency of the PWM signal

Average value Im of the alternating current I = (2 x duty cycle - 1 ) x Ipeak

For the duty cycle of 0.63 assumed in the example, this results in Im = (2 x 0.63 - 1 ) x Ipeak = 0.26 x Ipeak.

With knowledge of "Ipeak" or under the assumption of "Ipeak = 11 = I2" a suitable PWM signal can be determined very easily for each alternating current I to be output with a specified frequency and a specified mean value in the range [-Ipeak, +lpeak] (e.g. B. calculated) and the control device 12 for the purpose of generating and outputting the switching signals S1, S2 are provided:

Frequency of the signal PWM = Frequency of the desired alternating current I Duty cycle of the signal PWM = (Im / Ipeak + 1 ) / 2

In practice, however, there is the problem that the above-mentioned ideal case, i.e. the requirement 11 = I2 (= Ipeak), i.e. equality of the two currents 11 and I2, often cannot be ensured with sufficient accuracy by a corresponding technological design (microelectronic design) and the resulting in practice inequality of the values of I1 and I2 ("mismatching") leads to inaccuracies in the setting of the current I to be output.

In order to eliminate this problem, a calibration is provided in the circuit arrangement, as a result of which any unequal current intensities I1, I2 are matched to one another by suitably changing one or both specifications for the bias signals B1, B2 for this purpose.

Coming back to FIG. 1 , in this example the control device 12 can be set either to the normal operating mode or to a calibration mode by a mode control signal MOD that is supplied. Such a calibration mode can be used during operation of the circuit arrangement 100, e.g. B. from time to time (generally possible in every "currentless" phase). The control device 12 is designed to be in the calibration mode

- bring about an interruption of the current path P and a discharge of the circuit node K to the reference potential GND by outputting corresponding first and second switching signals SU, SE to the first and second switches 16, 18, so that the switch 16 opens and the switch 18 is closed,

- Then switch on both direct current sources 10-1, 10-2 simultaneously by means of the respective switching signals S1, S2 and set their current intensities 11, I2 by means of the predetermined respective bias signals B1, B2, and finally depending on the potential detected at the circuit node K pot the specification to change at least one of the two bias signals B1, B2 in order to align the two current intensities 11, I2 with one another in the normal operating mode.

3 illustrates the calibration mode using an example profile of the signals SU, SE, S1, S2 output by the control device 12, a signal DET generated in the control device 12 and the resulting profiles of the currents 11, I2 energizing the circuit node K. In the calibration mode, the switching signals S1, S2 are not generated based on the signal PWM as in the normal operating mode, but according to a predetermined “calibration algorithm” as described below.

At the beginning of the calibration mode, at a point in time t1, the signal SU changes from 0 to 1, so that the switch 16 is opened.

At a point in time t2, where t1=t2 applies in the example shown, the signal SE changes from 0 to 1, so that the switch 18 is closed. This begins the discharge of the circuit node K to the reference potential GND.

At a point in time t3, which in the example is a fixed, predefined delay period after t1 and t2, the signal SE changes from 1 back to 0, so that the switch 18 is opened again.

The delay period is selected such that at time t3 it can be reliably assumed that the circuit node K (including the parts electrically connected thereto) will be completely discharged. Then pot = GND applies.

At a point in time t-4, where t4=t3 applies in the example shown, the signals S1 and S2 change from 0 to 1, so that both direct current sources 10-1, 10-2 are switched on at the same time, the predetermined respective bias signals B1, B2 set their current levels 11, I2.

The current intensities I1, I2 then increase, which means that the circuit node K (FIG. 1) will be recharged in accordance with any inequality in the current intensities I1, I2 (integrated over time).

At a point in time t5, which in the example is a fixed predetermined delay time after t4 (and consequently also t1 and t2), a detection signal DET is briefly set from logic 0 to logic 1 in the control device 12, which defines t5 as a “detection time”. at which a result signal R output by the potential detection device 14 as a result of the detection of the potential pot is registered by the control device 12.

The delay period (e.g. at least 0.5 ps and e.g. a maximum of 100 ps) is chosen such that at time t5 even in the case of a rather slight difference between the current intensities 11, 12 (integrated over time), charging can be clearly detected of the circuit node K at time t5. At a point in time t6, the signals S1 and S2 change from 1 back to 0, so that both direct current sources 10-1, 10-2 are switched off and the currents I1, I2 come to a standstill.

At a point in time t7, where t7=t6 applies in the example shown, the signal SU changes from 1 back to 0, so that the switch 16 is closed.

Depending on the registered result signal R, which represents the potential pot detected at the circuit node K at time t5, the specification of at least one of the two bias signals B1, B2 is changed in such a way that an adjustment of the current intensities I1, I2 is achieved, which in a subsequent Normal operating mode advantageously leads to a more precise setting of the mean value Im of the alternating current I.

In a particularly simple embodiment, the potential detection device 14 is designed as a comparator which compares the potential pot at the circuit node K with the reference potential GND. The comparator can display the result of this comparison (pot>GND or pot<GND) to be registered by the control unit 12 as the result signal R in the form of a logical signal with possible values of 0 and 1.

Deviating from this, however, the potential detection device 14 could also be designed to measure the voltage between the potentials pot and GND and to output a corresponding analog result signal R.

Also deviating from the example shown, it could also be provided that values of the potential pot recorded successively at a plurality of different recording times were used as decisive, with z. B. after the opening of the second switch 18 temporally equidistant detection times can be defined. This could be advantageous z. For example, it can be determined whether the potential pot "rises or falls" in the time between two detection times (instead of determining "pot>GND or pot<GND" in the example shown). This completes the calibration mode and the control device 12 can be switched back to the normal operating mode (or eg to a "standby mode" without power generation with S1=S2=0) using the mode control signal MOD.

Returning again to FIG. 1 , the integrated circuit arrangement 100 in this example has a control device 20 which generates the mode control signal MOD and (at least in the normal operating mode) the PWM signal PWM and outputs them to the drive device 12 .

In the example shown, the control device 20 is designed to communicate with external devices via a digital communication bus (eg CAN or LIN bus) (symbolized on the far left in FIG. 1).

In particular, it can be provided that the control device 20 takes into account an externally supplied control signal C (eg control data and/or control commands) for its operation.

For example, a specification for the mean value Im of the alternating current I to be generated could be transmitted using the control signal C, whereupon the control device 20 generates a suitable or the corresponding PWM signal PWM based on this specification of the value Im and outputs it to the control device 12 .

In the example shown, such a control signal C is used to control activation and deactivation of operation of the sensor connected to circuit arrangement 100, with the operation of the sensor being managed autonomously by control device 20, and with digital sensor measurement data being transmitted during sensor operation via the connected communication bus are provided or sent.

In the example shown, in which the integrated circuit arrangement 100 is provided as a sensor interface module for operating a sensor the specification for the mean value Im made by control device 20 also as a function of a measurement signal M supplied to control device 20, which is generated and output by a further potential detection device 22 and is representative of a voltage measured on current path P in relation to, for example, reference potential GND (or e.g. another potential, e.g. tapped at the sensor).

The measurement signal M supplied to the control device 20 (here: voltage on the current path P) can, if the circuit arrangement 100 is used to operate an exhaust gas sensor on an internal combustion engine, e.g. B. be representative of a pumping voltage present in the relevant sensor (and possibly also represent a potential of a Nernst voltage that is generated in the exhaust gas sensor according to the concentration of an exhaust gas component).

In this example, in the normal operating mode, the control device 20 generates digital sensor measurement data from time-dependent (e.g. time-equidistant) registered values of the set mean value "Im" and the temporally associated values of the voltage (signal M) measured by the further potential detection device 22 . If necessary, this data can also be temporarily stored and/or further processed in the control device 20 and is then made available or sent via the communication bus connected to the circuit arrangement 100 .

The same can be provided for the case in which the circuit arrangement 100 has a plurality of current sources 10 and accordingly a plurality of current paths P and output terminals OUT. In this case, the control device 20 can generate digital sensor measurement data, which contain the aforementioned (e.g. time-equidistantly registered) pairs of values (from values of “Im” and associated values of the signal “M”) for several, in particular all, current paths P.

Deviating from the example shown in Fig. 1, in which the

Mode control signal MOD within the circuit arrangement 100 (in the Control device 20) is generated and the circuit arrangement 100 can thus "autonomously" define certain time phases for carrying out the calibration mode, it could also be provided that the mode control signal MOD is transmitted externally (e.g. as part of the control data C) to the circuit arrangement 100.

Deviating from the example shown in Fig. 1, in which the first and second supply terminals K1, K2 are provided for applying the first and second supply potentials V1, V2, the integrated circuit arrangement 100 could instead have at least one of the potentials V1, V2 internally (from other of externally applied potentials), but otherwise function exactly as described for the example of FIG. 1 using the then differently provided potentials V1, V2. In particular, e.g. B. be provided that the reference potential GND and one of the first and second supply potentials V1, V2 (z. B. the positive supply potential V2) is applied externally to the integrated circuit arrangement and the other of the supply potentials (z. B. the negative supply potential V1) is generated within the circuit arrangement 100 and is thus provided at a corresponding “internal supply node”.

4 and 5 illustrate two (relatively simple) circuit implementations of a controllable current source that can be used in the invention (e.g. for the current source 10 shown in FIG. 1) (however, other implementations can also be used within the scope of the invention , e.g. using operational amplifiers).

4 shows a current source having two direct current sources, each of which can be driven, which are each formed by a transistor T1 or T2 and energize a circuit node K with current directions opposite to one another. Each of the transistors T1, T2 forms a controllable current path and at the same time implements the functions “switching” and “setting (of the current intensity I1 or I2)”. Bias currents Ibias1, Ibias2 representing respective bias signals B1, B2 generate here in a current mirror arrangement (T1 to T4) corresponding bias voltages Vbias1, Vbias2, which are applied to a control input (e.g. gate of an FET) of the respective transistor T1, T2 via a switching transistor (symbolized as a switch in the figure) controlled by the respective switching signal S1, S2. By means of inverted switching signals S1*, S2*, respective further switching transistors are controlled, via which, when the respective transistor T1 or T2 is switched off, its potential at the control input (e.g. gate in the case of an FET) is determined accordingly.

Fig. 5 shows a current source in which, in contrast to Fig. 4, the two direct current sources each have a “switching transistor” T1, T2, which is controlled by means of the switching signal S1, S2, and arranged in series connection thereto by means of a bias voltage Vbiasl, Vbias2 (bias signals B1, B2 ) controlled "adjustment transistor" Tbiasl, Tbias2.

When the circuit arrangement 100 shown in FIG. 1 is implemented with a current source of the type shown in FIG. 4 or 5, the bias signals B1, B2 output by the drive device 12 can be used to control the bias currents Ibias1, Ibias2 in FIG. 4 or the bias voltages Vbias1, Vbias2 in FIG. 5 (the latter bias voltages Vbias1, Vbias2 could also be generated here, for example via a current mirror arrangement of the type shown in FIG. 4).

Deviating from the case shown in Fig. 1, in which the circuit arrangement 100 has a single current source 10, several such current sources 10 together with associated components such as current paths P, output terminals OUT, detection devices 14 etc. as well as a shared control device 20 could be in the circuit arrangement 100 to be present. Such a circuit arrangement 100 can advantageously be used for energizing an external device (e.g. sensor) with a plurality of currents which can be set independently of one another and/or for energizing a number of external devices (e.g. sensors). If a circuit arrangement 100 is equipped with several current sources 10, these several current sources 10 can be designed with "nominal" current intensities I1, I2 that differ from one another, in order to allow the circuit arrangement 100 to be used more universally.

Reference List

100 integrated circuit arrangement

K1, K2 supply connections

V1, V2 supply potentials

GND reference potential

10 controllable power source

I alternating current

In mean value (of alternating current I)

P current path

OUT output connector

10-1 first direct current source

10-2 second direct current source

K circuit node pot potential (at the circuit node)

12 control device

S1, S2 switching signals

B1 , B2 bias signals

11 , I2 currents (of the direct current sources)

16 first switch

SU first switching signal

18 second switch

SE second switching signal

C control signal

20 controller

MOD mode control signal

PWM PWM signal

14 potential detection device

R result signal

22 further potential detection device

M measurement signal

Claims

patent claims

1. Integrated circuit arrangement (100) with at least one controllable current source (10) for generating an alternating current (I) with an adjustable mean value (Im), the current source (10) having two direct current sources (10-1, 10-2) that can be controlled in each case, which energize a common circuit node (K) with mutually opposite current directions, which is connected via a current path (P) to an output connection (OUT) for outputting the alternating current (I), with a control device (12) which is designed for this purpose, in a Normal operating mode, the two direct current sources (10-1, 10-2) are switched on and off based on a PWM signal (PWM) fed to the control device (12) in a complementary PWM-modulated manner by means of respective switching signals (S1, S2) and by means of the Control device (12) to set the current strengths (11, I2) of the two direct current sources (10-1, 10-2) using predetermined respective bias signals (B1, B2), with a potential detection device (14) for detecting the potential (pot) at the circuit node (K ), with a first switch (16) arranged in the course of the current path (P) that can be controlled by the control device (12) by means of a first switching signal (SU), and with a switch that can be controlled by the control device (12) by means of a second switching signal (SE). second switch (18), which on the one hand is electrically connected to the circuit node (K) and on the other hand has a predetermined reference potential (GND) applied to it, the control device (12) also being designed to be in a calibration mode - bring about an interruption of the current path (P) and a discharge of the circuit node (K) to the reference potential (GND) by outputting corresponding first and second switching signals (SU, SE) to the first and second switches (16, 18),

- then switch on both direct current sources (10-1, 10-2) simultaneously by means of the respective switching signals (S1, S2) and set their current intensities (11, I2) by means of the predetermined respective bias signals (B1, B2), and finally depending on the at the circuit node (K) detected potential (pot) to change the specification of at least one of the two bias signals (B1, B2) in order to align the two currents (11, I2) in the normal operating mode to each other.

2. Integrated circuit arrangement (100) according to claim 1, having a first and a second supply connection (K1, K2) for applying a first and a second supply potential (V1, V2), wherein the first supply connection (K1) via the first controllable direct current source (10-1) is electrically connected to the circuit node (K) and the second supply connection (K2) is electrically connected to the circuit node (K) via the second controllable direct current source (10-2).

3. Integrated circuit arrangement (100) according to one of the preceding claims, wherein the two direct current sources (10-1, 10-2) each have a transistor which is controlled by means of the switching signal (S1, S2) and arranged in series connection thereto by means of the bias signal (B1, B2) have driven transistor.

4. Integrated circuit arrangement (100) according to any one of the preceding claims, wherein the control device (12) is designed to, in the calibration mode depending on the at the circuit node (K) after expiration a predetermined delay period after switching on the two direct current sources (10-1, 10-2) detected value of the potential (pot) to change the specification of the at least one of the bias signals (B1, B2).

5. Integrated circuit arrangement (100) according to one of the preceding claims, wherein the potential detection device (14) is designed as a comparator which compares the potential (pot) at the circuit node (K) with the reference potential (GND) and represents the result of this comparison Outputs result signal (R) to the control device (12).

6. Integrated circuit arrangement (100) according to any one of the preceding claims, having a first and a second supply terminal (K1, K2) for applying a first and a second supply potential (V1, V2), wherein the predetermined reference potential (GND) in the middle between the two supply potentials (V1, V2).

7. Integrated circuit arrangement (100) according to any one of the preceding claims, wherein an ESD protection device is provided at a point of the current path (P) which is permanently electrically connected to the output terminal (OUT), and wherein a replica of the ESD protection device is provided which can be electrically connected to a point of the current path (P) in the calibration mode, which is also electrically connected to the circuit node (K) in the calibration mode.

8. Integrated circuit arrangement (100) according to any one of the preceding claims, further comprising a control device (20) which is designed to

- to determine a specification for the mean value (Im) of the alternating current (I) to be generated as a function of at least one control signal (C) fed to the control device (20) and/or at least one measurement signal (M) fed to the control device (20), and to generate a suitable PWM signal (PWM) based on the specification for the mean value (Im) and to output it to the control device (12).

9. The integrated circuit arrangement (100) as claimed in claim 8, designed as a sensor interface module for operating at least one sensor, for example an exhaust gas sensor on an internal combustion engine, with a connection of the sensor being connected to the output connection (OUT) of the integrated circuit arrangement (100) and thus energizing the Sensor with the alternating current (I) with an adjustable mean value (Im) is provided.

10. A method for controlling a controllable current source (10) of an integrated circuit arrangement (100), the controllable current source (10) for generating an alternating current (I) with an adjustable mean value (Im) being provided, and the current source (10) having two controllable direct current sources (10-1, 10-2) which, with mutually opposite current directions, energize a common circuit node (K) which is connected via a current path (P) to an output connection (OUT) for outputting the alternating current (I), wherein the integrated circuit arrangement (100) also has:

- a potential detection device (14) for detecting the potential (pot) at the circuit node (K),

- A controllable first switch (16) arranged in the course of the current path (P), and

- a controllable second switch (18), which on the one hand is electrically connected to the circuit node (K) and on the other hand is acted upon by a predetermined reference potential (GND), the method having: - In a normal operating mode: PWM-modulated switching on and off of the two direct current sources (10-1, 10-2) complementary to one another and setting the current strengths (11, I2) of the two direct current sources (10-1,

10-2) according to a respective specification (B1, B2),

- In a calibration mode: interrupting the current path (P) by opening the first switch (16) and discharging the circuit node (K) to the reference potential (GND) by closing the second switch (18), then simultaneously switching on the two direct current sources (10- 1, 10-2) by means of the respective switching signals (S1, S2) and setting their current intensities (11, I2) according to the respective specification (B1, B2), and finally changing at least one of the two specifications (B1, B2) as a function from the potential (pot) detected at the circuit node (K) in order to align the two current intensities (11, I2) with one another in the normal operating mode.

11 . The method of claim 10, wherein in the calibration mode at least one of the following is provided:

- the opening of the first switch (16) and the closing of the second switch (18) take place simultaneously,

- the two direct current sources (10-1, 10-2) are switched on and the second switch (18) is opened simultaneously,

- the opening of the second switch (18) takes place after a fixed predetermined delay period after the closing of the second switch (18),

- The change in at least one of the two specifications (B1, B2) depends significantly on one or more values of the potential (pot) detected at the circuit node (K), which are detected at one or more corresponding detection times, with each detection time at a fixed predetermined detection delay period is provided after the opening of the second switch (18).

12. The method according to claim 10 or 11, wherein in the calibration mode the change in the at least one of the two specifications (B1, B2) depends significantly on a single value of the potential (pot) detected at the circuit node (K), which is detected at a detection time, which is provided by a fixed predetermined detection delay margin after opening of the second switch (18).

13. The method according to claim 12, wherein the change in the at least one of the two specifications (B1, B2) depends significantly on whether the value of the potential (pot) detected at the circuit node (K) is greater or less than the reference potential (GND).

14. Use of an integrated circuit arrangement (100) according to one of claims 1 to 9 and/or a method according to one of claims 10 to 13 for implementing the operation of an exhaust gas sensor on an internal combustion engine, in particular a sensor for measuring a NOx concentration and/or or an air/fuel ratio.