WO2023050052A1

WO2023050052A1 - Display substrate and display apparatus

Info

Publication number: WO2023050052A1
Application number: PCT/CN2021/121280
Authority: WO
Inventors: 徐攀; 袁志东
Original assignee: 京东方科技集团股份有限公司; 合肥京东方卓印科技有限公司
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2023-04-06
Also published as: US20230157111A1; CN116210369A

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises: a base substrate, wherein the base substrate comprises a display region and a peripheral region at least located at the first side of the display region; a plurality of pixel units, wherein the plurality of pixel units are arranged in an array in the display region of the base substrate in a first direction and a second direction, the pixel units comprise a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit, and the light emitting device comprises a cathode, an anode, and a light emitting layer provided between the cathode and the anode; and a cathode wire located at the peripheral region, wherein the cathode wire is electrically connected to the cathode, the cathode wire basically surrounds the display region, the cathode is electrically connected to the cathode wire at a plurality of positions, the cathode wire comprises a first sub-cathode wire, and the first sub-cathode wire and the anode are located on the same layer.

Description

Display substrate and display device

technical field

The present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.

Background technique

An organic light emitting diode (OLED) display device is a self-emitting device that does not require a backlight. OLED display devices also provide more vivid colors and a larger color gamut than conventional liquid crystal display (LCD) devices. Furthermore, OLED display devices can be made more flexible, thinner and lighter than typical LCD devices. An OLED display device generally includes an anode, an organic layer including an organic light emitting layer, and a cathode. The OLED may be a bottom emitting OLED, or a top emitting OLED. In bottom emitting OLEDs, light is extracted from the anode side. In bottom-emitting OLEDs, the anode is usually transparent, while the cathode is usually reflective. In top-emitting OLEDs, light is extracted from the cathode side. In top-emitting OLEDs, the cathode is optically transparent, while the anode is reflective. Top-emitting OLEDs are more suitable for high-PPI display products, adapt to market development trends, and conform to industry development trends. Therefore, the design of the top-emission OLED display device has gradually become one of the hot spots that research and development personnel pay attention to.

The above information disclosed in this section is only for understanding of the background of the technical idea of the present disclosure and therefore it may contain information that does not constitute prior art.

Contents of the invention

In one aspect, a display substrate is provided, comprising:

a base substrate comprising a display area and a peripheral area at least on a first side of the display area;

A plurality of pixel units, the plurality of pixel units are arranged in an array along the first direction and the second direction in the display area of the base substrate, wherein the pixel units include a pixel driving circuit and are connected with the pixel driving circuit A light-emitting device electrically connected to a circuit, the light-emitting device comprising a cathode, an anode, and a light-emitting layer disposed between the cathode and the anode;

an anode trace located in the peripheral region, the anode trace for supplying an anode voltage; and

a cathode trace located in the peripheral region, the cathode trace electrically connected to the cathode,

Wherein, the cathode trace substantially surrounds the display area, and the cathode is electrically connected to the cathode trace at multiple locations; and

The cathode wiring includes a first sub-cathode wiring, the first sub-cathode wiring is located on the same layer as the anode, and the orthographic projection of the first sub-cathode wiring on the base substrate is the same as the Orthographic projections of the anode traces on the base substrate partially overlap.

According to some exemplary embodiments, the display substrate further includes a pixel defining layer on the base substrate, the pixel defining layer is located between the layer where the anode is located and the layer where the cathode is located; the The pixel defining layer includes a first via hole and a second via hole, the first via hole and the second via hole respectively expose at least a part of the first sub-cathode wiring, and the cathode passes through the first via hole The hole and the second via hole are respectively electrically connected to the first sub-cathode wiring.

According to some exemplary embodiments, the pixel driving circuit includes at least one thin film transistor and at least one capacitor disposed on the base substrate, and the thin film transistor includes an active layer, a gate, a source and a drain; The display substrate includes: a first conductive layer disposed on the side of the active layer away from the base substrate, the gate is located on the first conductive layer; disposed on the first conductive layer away from the The second conductive layer on the side of the base substrate, the source and the drain are located on the second conductive layer; the third conductive layer arranged on the side of the second conductive layer away from the base substrate, the The third conductive layer is located between the second conductive layer and the layer where the anode is located; and the cathode wiring includes a second sub-cathode wiring, and the second sub-cathode wiring is located on the second conductive layer .

According to some exemplary embodiments, the cathode wiring includes a third sub-cathode wiring, and the third sub-cathode wiring is located on the third conductive layer.

According to some exemplary embodiments, the display substrate includes a first insulating layer disposed between the second conductive layer and the third conductive layer, and the first insulating layer includes a third via hole and a fourth via hole. The third via hole and the fourth via hole respectively expose at least a part of the second sub-cathode trace; the third sub-cathode trace passes through the third via hole and the first sub-cathode trace respectively. The four vias are electrically connected to the second sub-cathode wiring.

According to some exemplary embodiments, the first vias extend along the first direction, the pixel defining layer includes at least two second vias, and the two second vias are respectively located in the first both sides of the via.

According to some exemplary embodiments, the extending direction of the fourth via hole is the same as the direction of the second sub-cathode trace, and the fourth via hole makes the second sub-cathode trace occupy its circumference of 50 % more than part is exposed; and/or, the extension direction of the second via hole is the same as the direction of the second sub-cathode trace, and the second via hole makes the first sub-cathode trace occupy its More than 50% of the circumference is exposed.

According to some exemplary embodiments, the third via hole includes a first portion and a second portion, the first portion extends along a first direction, the second portion extends along a second direction, the first direction and the second portion cross in the second direction.

According to some exemplary embodiments, an orthographic projection of the second via hole on the base substrate at least partially overlaps an orthographic projection of the fourth via hole on the base substrate.

According to some exemplary embodiments, the anode wiring includes a first sub-anode wiring, and the first sub-anode wiring is located on the first conductive layer.

According to some exemplary embodiments, the anode wiring includes a second sub-anode wiring, the second sub-anode wiring is located on the second conductive layer, and the second sub-anode wiring passes through the fifth via hole It is electrically connected with the first sub-anode wiring.

According to some exemplary embodiments, the anode wiring includes a third sub-anode wiring, the third sub-anode wiring is located on the third conductive layer, and the third sub-anode wiring passes through the sixth via hole It is electrically connected with the second sub-anode wiring.

According to some exemplary embodiments, the first sub-anode wiring includes a first part and a second part, the first part of the first sub-anode wiring extends along a first direction, and the first sub-anode wiring The second part extends along the second direction; the orthographic projection of the fifth via hole on the base substrate and the orthographic projection of the second part of the first sub-anode trace on the base substrate are at least partly overlapping.

According to some exemplary embodiments, the orthographic projection of the first part of the first sub-anode trace on the substrate is at least partly the same as the orthographic projection of the first sub-cathode trace on the substrate overlapping.

According to some exemplary embodiments, the orthographic projection of the first part of the first sub-anode trace on the base substrate at least partially overlaps the orthographic projection of the first via hole on the base substrate.

According to some exemplary embodiments, the display substrate further includes an initialization signal wiring located in the peripheral area, and the initialization signal wiring is used to supply an initialization voltage; the initialization signal wiring includes a first sub-initialization signal wiring line and a second sub-initialization signal routing, the first sub-initialization signal routing is located in the second conductive layer, and the second sub-initialization signal routing is located in the third conductive layer; the first sub-initialization signal routing The signal wiring is electrically connected to the second sub-initialization signal wiring through the seventh via hole.

According to some exemplary embodiments, the seventh via hole and the sixth via hole extend in parallel along the first direction, and the seventh via hole and the sixth via hole are arranged at intervals along the second direction.

According to some exemplary embodiments, the orthographic projection of the initialization signal trace on the substrate is located at the same position as the orthographic projection of the second sub-cathode trace on the substrate and the anode trace. between the orthographic projections on the substrate substrate.

According to some exemplary embodiments, the orthographic projection of the first sub-anode trace on the substrate partially overlaps the orthographic projection of the first via hole on the substrate.

According to some exemplary embodiments, the dimension of the overlapping portion of the first via hole and the second portion of the first sub-anode trace along the first direction is the same as that of the second portion of the first sub-anode trace. The ratio of the size in the first direction is in the range of 0.8-1.2; and/or, the size of the part along the first direction where the first via hole overlaps with the first part of the first sub-anode wiring is the same as the size of the first sub-anode line. The ratio of the dimensions of the first part of a sub-anode line along the first direction is in the range of 0.8-1.2; and/or, the overlapping part of the first via hole and the first part of the first sub-anode line is along the The ratio of the size of the second direction to the size of the first part of the first sub-anode wiring along the second direction is in the range of 0.4-0.8; and/or, the size of the second via hole along the second direction is the same as The ratio of the dimensions of the first via hole along the second direction is in the range of 1.1-10.

According to some exemplary embodiments, the display substrate includes a second insulating layer disposed between the third conductive layer and the layer where the anode is located, the second insulating layer includes an eighth via hole, the The eighth via hole exposes at least a part of the third sub-cathode trace; the first sub-cathode trace is electrically connected to the third sub-cathode trace through the eighth via hole.

According to some exemplary embodiments, the orthographic projection of the eighth via hole on the base substrate at least partially overlaps the orthographic projection of the fourth via hole on the base substrate.

In another aspect, a display device is provided, including the above-mentioned display substrate.

Description of drawings

The features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

1 is a plan view of an OLED display panel according to some exemplary embodiments of the present disclosure;

2 is a cross-sectional view of an OLED display panel taken along line AA' in FIG. 1 according to some exemplary embodiments of the present disclosure;

3 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure;

4 is a cross-sectional view of a display substrate taken along line CC' in FIG. 3 according to some exemplary embodiments of the present disclosure;

5 to 12 are partial enlarged plan views of part I of the display substrate in FIG. 3 according to some exemplary embodiments of the present disclosure, wherein FIG. 5 schematically shows the first conductive layer at part I, and FIG. 6 schematically shows the second conductive layer at part I, Figure 7 schematically shows the combination of the first conductive layer and the second conductive layer at part I, and Figure 8 schematically shows the first conductive layer at part I Three conductive layers, Figure 9 schematically shows the combination of the first conductive layer, the second conductive layer and the third conductive layer at the part I place, and Figure 10 schematically shows the conductive layer arranged on the same layer as the anode at the part I place layer, Figure 11 schematically shows the combination of the first conductive layer at the part I, the second conductive layer, the third conductive layer and the conductive layer arranged on the same layer as the anode, and Figure 12 schematically shows the combination of the conductive layer at the part I vias in the pixel-defining layer; and

FIG. 13 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort shall fall within the protection scope of the present disclosure.

It should be noted that, in the drawings, the size and relative size of elements may be exaggerated for the purpose of clarity and/or description. As such, the sizes and relative sizes of the respective elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals designate the same or similar components.

When an element is described as being "on," "connected to," or "coupled to" another element, the element may be directly on, directly connected to, or The other element is either directly coupled to the other element, or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar fashion, for example, "between" versus "directly between," " Adjacent" vs. "directly adjacent" or "on" vs. "directly on" etc. Additionally, the term "connected" may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that although the terms "first", "second" and the like may be used herein to describe various components, components, elements, regions, layers and/or sections, these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another. Thus, for example, a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.

For ease of description, spatially relative terms such as "upper," "lower," "left," "right," etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "above" the other elements or features.

Those skilled in the art should understand that in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate. Dimensions, or referred to as the size along the normal direction of the display device, or referred to as the size along the Z direction in the drawings.

Herein, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The expression "one patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

It should be noted that the expressions "same layer", "set in the same layer" or similar expressions refer to the use of the same film forming process to form a film layer for forming a specific pattern, and then use the same mask to pass a patterning process on the film. Layer structure formed by layer patterning. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.

In this document, unless otherwise specified, the expression "electrically connected" may mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and electrical signals may be transmitted between the two; It can mean that two components or elements are electrically connected through a conductive medium such as a conductive wire, for example, a component or element A is electrically connected with a component or element B through a conductive wire, so as to transmit electrical signals between the two parts or elements; it can also represent Two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin film transistor, so as to transmit electrical signals between the two components or elements.

In this paper, unless otherwise specified, the expression "via hole" may refer to a connection structure that penetrates through the insulating layer between two conductive layers to electrically connect components located in the two conductive layers, and its forms include but are not limited to, through holes , Groove, Hollow Department, etc.

In this document, unless otherwise specified, the expressions "same" or "equal" mean substantially the same or substantially equal under actual manufacturing process conditions, and are not intended to be limited to strictly identical or strictly equal in the mathematical sense.

Embodiments of the present disclosure at least provide a display substrate and a display device. The display substrate includes: a base substrate, the base substrate includes a display area and a peripheral area at least on a first side of the display area; a plurality of pixel units, the plurality of pixel units are arranged along a first direction and a second direction. Two directions are arranged in an array in the display area of the base substrate, wherein the pixel unit includes a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit, and the light emitting device includes a cathode, an anode and a set a light-emitting layer between the cathode and the anode; and a cathode trace in the peripheral region, the cathode trace electrically connected to the cathode, wherein the cathode trace substantially surrounds the display area , the cathode is electrically connected to the cathode wiring at multiple positions; and the cathode wiring includes a first sub-cathode wiring, and the first sub-cathode wiring and the anode are located on the same layer. In the display substrate of the embodiment of the present disclosure, the equivalent resistance at the cathode wiring and the cathode connection is reduced, thereby reducing the decrease of the cathode voltage at a position farther away from the signal source.

1 is a plan view of an OLED display panel according to some exemplary embodiments of the present disclosure, and FIG. 2 is a cross-sectional view of the OLED display panel according to some exemplary embodiments of the present disclosure, taken along line AA' in FIG. 1 . Referring to FIG. 1 and FIG. 2 in conjunction, the OLED display panel may include a first substrate 1 and a second substrate 2 oppositely disposed. For example, the first substrate 1 may be an array substrate, and the second substrate 2 may be a cover plate formed of glass or the like.

For example, the OLED display panel may further include a sealant 3 arranged between the first substrate 1 and the second substrate 2, and the sealant 3 is arranged in a ring shape in the peripheral area of the first substrate 1, that is, A ring of sealant 3 is arranged in the peripheral area of the first substrate 1 . In this way, the sealant 3 can prevent the intrusion of water vapor and oxygen, maintain the box thickness of the peripheral area of the display panel, and bond the first substrate and the second substrate. For example, the gap between the first substrate and the second substrate may also be filled with a filler, and the filler may be a resin material. The packaging structure of Dam+Filler is realized by setting the filling glue and the sealing glue 3 . It should be noted that the embodiments of the present disclosure are not limited to the encapsulation structure, and other types of encapsulation structures can be used in the embodiments of the present disclosure if there is no conflict.

Referring to FIG. 1 , a first substrate 1 (ie, a display substrate according to an embodiment of the present disclosure) includes: a base substrate 10 , for example, the base substrate 10 may be formed of materials such as glass, plastic, and polyimide. The base substrate 10 includes a display area AA and a peripheral area (or referred to as a peripheral area NA) NA located on at least one side of the display area AA (for convenience of description, this side is referred to as a first side). The peripheral area NA may include a first peripheral area NA1 located on a side of the sealant 3 close to the display area AA and a second peripheral area NA2 located on a side of the sealant 3 away from the display area AA.

Continuing to refer to FIG. 1, the first substrate 1 may include a plurality of pixel units P (schematically shown in dotted line boxes in FIG. The two directions Y are arranged in an array on the base substrate 10 . Each pixel unit P may further include a plurality of sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. In FIG. 1 , one sub-pixel SP is schematically shown.

For example, the display panel includes a signal input side IN (lower side shown in FIG. 1 ). On the signal input side IN, an external drive circuit 7 such as a COF may be connected, and the external drive circuit 7 may be electrically connected to the pixel unit P located in the display area through a plurality of signal wires. In this way, signals such as a first voltage signal, a second voltage signal, an initialization voltage signal, a data signal, etc. can be transmitted to a plurality of pixel units P from the signal input side IN.

For example, the above-mentioned first side may be the signal input side IN. That is, the peripheral area NA is located at least on the signal input side IN of the display area AA. Optionally, as shown in FIG. 1 , the peripheral area NA may be located on four sides of the display area AA, that is, it surrounds the display area AA.

It should be noted that, in the drawings, pixel units and sub-pixels are schematically shown in rectangular shapes, but this does not constitute a limitation on the shape of the pixel units and sub-pixels included in the display panel provided by the embodiments of the present disclosure.

For example, FIG. 3 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure. In this embodiment, the display substrate may be a D-shaped display substrate, and of course, the display substrate may also be a display substrate of other irregular shapes. Usually, in a display substrate with a different shape, an external driving circuit such as a COF is only disposed on one side of the display substrate. As shown in FIG. 3, an external drive circuit 7 such as a COF is provided on the lower side of the display substrate.

The first substrate 1 may also include a light-emitting device, such as an OLED device 4. As shown in FIG. .

One of the cathode 41 and the anode 43 is an anode, and the other is a cathode. For example, the cathode 41 may be a transparent cathode, eg, it may be formed of a transparent conductive material, which may include indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The anode 43 can be a reflective anode, for example, it can be formed of a metal material, and the metal material can include alloys such as magnesium aluminum alloy (MgAl), lithium aluminum alloy (LiAl), or single metals such as magnesium, aluminum, lithium, etc. The light-emitting layer 42 may be a multi-layer structure, for example, it may include a multi-layer structure formed of a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer and an electron injection layer.

It should be noted that the OLED device 4 can be driven actively or passively. The passively driven OLED array substrate is composed of a cathode and an anode, the intersection of the anode and the cathode can emit light, and the driving circuit can be externally mounted by a connection method such as a tape-carrying package or a chip-on-glass. The active driving OLED array substrate can be equipped with a pixel driving circuit for each pixel, and the pixel driving circuit can include a thin film transistor with a switching function (ie, a switching transistor), a thin film transistor with a driving function (ie, a driving transistor) and a charge storage capacitor , in addition, the pixel driving circuit may also include other types of thin film transistors with a compensation function. It should be understood that, in the embodiments of the present disclosure, the display panel may be equipped with various types of known pixel driving circuits, which will not be repeated here.

Below, taking the 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit will be described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. All driving circuit structures can be applied to the embodiments of the present disclosure.

As shown in FIG. 13 , the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive organic light emitting diodes (ie OLEDs). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. Each transistor includes a gate, source and drain.

The display substrate may also include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, and a signal line 61 for transmitting a reset control signal RESET (that is, the scanning signal of the previous row) The reset signal line 62, the light emission control line 63 for transmitting the light emission control signal En, the data line 64 for transmitting the data signal Dm, the anode wiring 30 for transmitting the driving voltage VDD, and the initial initialization for transmitting the initialization voltage Vint A signal wire 60, and a cathode wire 20 for transmitting VSS voltage.

The gate G1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the source S1 of the first transistor T1 is electrically connected to the anode line 30 through the fifth transistor T5, and the drain D1 of the first transistor T1 is electrically connected to the anode line 30 through the sixth transistor T1. Transistor T6 is electrically connected to the anode of the OLED. The first transistor T1 receives the data signal Dm according to the switching operation of the second transistor T2 to supply the driving current Id to the OLED.

The gate G2 of the second transistor T2 is electrically connected to the scanning signal line 61, the source S2 of the second transistor T2 is electrically connected to the data line 64, and the drain D2 of the second transistor T2 is electrically connected to the anode wiring via the fifth transistor T5. 30, while being electrically connected to the source S1 of the first transistor T1. The second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm transmitted to the data line 64 to the source S1 of the first transistor T1.

The gate G3 of the third transistor T3 is electrically connected to the scanning signal line 61 , the source S3 of the third transistor T3 is electrically connected to the anode of the OLED via the sixth transistor T6 , and is also electrically connected to the drain D1 of the first transistor T1 . And the drain D3 of the third transistor T3 is electrically connected with one end of the storage capacitor Cst (ie, the first capacitor electrode) Cst1 , the drain D4 of the fourth transistor T4 and the gate G1 of the first transistor T1 . The third transistor T3 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to connect the gate G1 and the drain D1 of the first transistor T1 to each other, thereby performing diode connection of the first transistor T1.

The gate G4 of the fourth transistor T4 is electrically connected to the reset control signal line 62 , and the source S4 of the fourth transistor T4 is electrically connected to the initial initialization signal line 60 . And the drain D4 of the fourth transistor T4 is electrically connected with one terminal Cst1 of the storage capacitor Cst, the drain D3 of the third transistor T3 and the gate G1 of the first transistor T1. The fourth transistor T4 is turned on according to the reset control signal Sn-1 transmitted through the reset control signal line 62 to transmit the initialization voltage Vint to the gate G1 of the first transistor T1, thereby performing an initialization operation to turn the gate of the first transistor T1 The voltage of pole G1 is initialized.

The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63 , and the source S5 of the fifth transistor T5 is electrically connected to the anode wire 30 . And the drain D5 of the fifth transistor T5 is electrically connected with the source S1 of the first transistor T1 and the drain D2 of the second transistor T2.

The gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63 , the source S6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1 and to the source S3 of the third transistor T3 . And the drain D6 of the sixth transistor T6 is electrically connected to the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are turned on concurrently (eg simultaneously) according to the light emission control signal En transmitted through the light emission control line 63 to transmit the driving voltage ELVDD to the OLED, thereby allowing the driving current Id to flow into the OLED.

The seventh transistor T7 includes: a gate G7 connected to the reset control signal line 62; a source S7 connected to the drain D6 of the sixth transistor T6 and the anode of the OLED; and a drain D7 connected to the initial initialization signal line 60 . The seventh transistor T7 transmits the reset control signal Sn-1 from the reset control signal line 62 to the gate G7.

The other end Cst2 of the storage capacitor Cst is electrically connected to the anode wiring 30, and the cathode of the OLED is electrically connected to the cathode wiring 20 to receive the common voltage ELVSS. Correspondingly, the OLED receives the driving current Id from the first transistor T1 to emit light, thereby displaying images.

It should be noted that in FIG. 25 , each of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiment of the present disclosure is not limited thereto, and the thin film transistors T1 and T2 At least some of , T3, T4, T5, T6 and T7 may be n-channel field effect transistors.

In operation, during the initialization phase, the reset control signal Sn-1 having a low level is supplied through the reset control signal line 62 . Subsequently, the initialization thin film transistor T4 is turned on based on the low level of the reset control signal Sn-1, and the initialization voltage Vint from the initial initialization signal line 60 is transmitted to the gate G1 of the driving thin film transistor T1 through the initialization thin film transistor T4. Accordingly, the driving thin film transistor T1 is initialized due to the initialization voltage Vint.

During the data programming phase, the scan signal Sn having a low level is supplied through the scan signal line 61 . Subsequently, the switch thin film transistor T2 and the compensation thin film transistor T3 are turned on based on the low level of the scan signal Sn. Accordingly, the driving thin film transistor T1 is placed in a diode-connected state and biased in the forward direction through the turned-on compensating thin film transistor T3.

Subsequently, a compensation voltage Dm+Vth (for example, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied via the data line 64 is applied to the gate G1 of the driving thin film transistor T1 . Subsequently, the driving voltage ELVDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

During the light emission phase, the light emission control signal En from the light emission control line 63 changes from high level to low level. Subsequently, during the light emitting phase, the first light emitting control thin film transistor T5 and the second light emitting control thin film transistor T6 are turned on based on the low level of the light emitting control signal En.

Subsequently, a driving current is generated based on the difference between the voltage of the driving gate G1 of the driving thin film transistor T1 and the driving voltage ELVDD. The driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the second light emission controlling thin film transistor T6.

During the light emitting phase, based on the current-voltage relationship of the driving thin film transistor T1, the gate-source voltage of the driving thin film transistor T1 is maintained at (Dm+Vth)-ELVDD due to the storage capacitor Cst. The driving current Id is proportional to (Dm-ELVDD) ² . Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the driving thin film transistor T1.

For example, as shown in FIG. 2 , the first substrate 1 includes a driving circuit layer 9 , and the above-mentioned pixel driving circuit can be disposed in the driving circuit layer 9 . Between the driving circuit layer 9 and the OLED device 4 , an insulating layer 91 may be provided, and the insulating layer 91 may be a single insulating film layer or a stack of multiple insulating film layers.

The first substrate 1 can also include various signal lines arranged on the base substrate 10, and the various signal lines include scan lines, data lines, ELVDD power lines and ELVSS power lines, etc., so as to provide a pixel in each sub-pixel The drive circuit provides various signals such as control signals, data signals, and power supply voltages. In the embodiment shown in FIG. 1 , scan lines GL and data lines DL are schematically shown. The scan lines GL and the data lines DL may be electrically connected to the respective sub-pixels. For example, the scanning line GL may include the scanning signal line 61 used to transmit the scanning signal Sn in FIG. The line DL may include the data line 64 in FIG. 13 for transmitting the data signal Dm.

Referring to FIG. 3 , the first substrate 1 may include a cathode wiring 20 , a light emitting layer 42 and a cathode 41 on the base substrate 10 . The cathode wiring 20 is located in the peripheral area NA, and the cathode wiring 20 is substantially arranged around the display area AA. The light emitting layer 42 at least covers the display area AA, for example, the light emitting layer 42 may completely cover the display area AA and partially cover the peripheral area NA. The cathode 41 covers the display area AA and part of the peripheral area NA, that is, the cathode 41 is disposed on the entire surface. The cathode 41 covers the display area AA so as to serve as the cathode of each light emitting device in the display area AA to realize the display function. In addition, the cathode 41 also covers part of the peripheral area NA. In part of the peripheral area NA, the cathode 41 overlaps the cathode wiring 20 so as to be electrically connected to the cathode wiring 20 so as to obtain the cathode voltage provided by the cathode wiring 20 .

It should be noted that the expression "the cathode wiring substantially surrounds the display area" means that more than 80% (or even more than 90%) of the perimeter of the display area is surrounded by the cathode wiring.

For example, the light emitting layer 42 exposes the edge portion of the cathode 41 located in the peripheral area NA. In addition, an insulating layer is provided between the layer where the cathode wiring 20 is located and the layer where the cathode 41 is located, and the insulating layer includes a plurality of via holes, and the plurality of via holes also expose the edge portion of the cathode 41 located in the peripheral area NA. In this way, the cathode 41 and the cathode wiring 20 can be electrically connected.

In an embodiment of the present disclosure, the cathode wiring 20 substantially surrounds the display area AA, and the cathode 41 is electrically connected to the cathode wiring 20 at multiple positions. That is, the cathode wiring 20 is arranged in a circular manner, and the cathode 41 is electrically connected to the cathode wiring 20 at multiple positions or multiple areas around the display area AA. For example, the sum of the lengths of the multiple positions or the multiple areas accounts for more than 50%, or more than 70%, or more than 90% of the circumference of the cathode wiring 20 around the display area AA. The cathode 41 is electrically connected to the cathode wiring 20 in most areas around the display area AA. In this way, the contact area between the cathode wiring 20 and the cathode 41 is increased, and the equivalent resistance at the junction of the cathode wiring 20 and the cathode 41 is reduced, thereby reducing the distance from the signal source (such as external drive circuits such as COF) The magnitude of the drop in cathode voltage at a remote location. Therefore, the cathode signal is input into the cathode 41 through the cathode wiring 20, the resistance voltage drop on the cathode 41 is reduced, and the display uniformity of the display panel is improved.

In the embodiment of the present disclosure, the cathode wiring 20 is used to input the cathode signal to the cathode 41, and the cathode wiring 20 is drawn out at the lower side of the display area AA, that is, the cathode wiring 20 is arranged around the upper, left, and right areas of the display area AA , the cathode wiring 20 drawn from the lower side of the display area AA is used for electrical connection with the signal source. In the embodiment of the present disclosure, the arrangement of the cathode wiring 20 can increase the contact area between the cathode wiring 20 and the cathode 41, wherein not only the contact area is located on the lower side of the display area AA, but also on the upper side of the display area AA. , left and right regions are also in contact, thereby increasing the contact area between the cathode wiring 20 and the cathode 41, and reducing the equivalent resistance at the junction of the cathode wiring 20 and the cathode 41.

It should be noted that the luminescent layer 42 can be formed by evaporation or inkjet printing. When it is formed by evaporation, the entire surface of the luminescent layer 42 can be evaporated. For example, the evaporation area can be as shown in FIG. 1 The rectangular area shown in FIG. 3 or the shaped area shown in FIG. 3 makes the light emitting layer 42 completely cover the display area AA and partially cover the peripheral area NA. The light-emitting layer 42 has a whole-surface structure, and the overlapping part of the cathode line 20 and the cathode 41 cannot be realized in the overlapped part of the light-emitting layer 42 and the cathode line 20, and the overlapping part of the cathode line 20 and the light-emitting layer 42 can be overlapped with the cathode 41 . For example, after all the film layers of the display substrate are fabricated, the redundant light-emitting layer 42 and cathode 41 outside the peripheral area NA can be cut off to form the special-shaped display substrate shown in FIG. 3 . When formed by inkjet printing, the luminous layer 42 is discontinuous, and can be selected according to the actual process to realize as many electrical connections as possible between the cathode wiring 2 and the cathode 41 .

FIG. 4 is a cross-sectional view of the display substrate taken along line CC' in FIG. 3 according to some exemplary embodiments of the present disclosure. For example, the pixel driving circuit may include transistors and capacitors. The transistor may include an active layer, a gate, a source and a drain. The capacitor may include a first plate and a second plate.

1 to 4, the first substrate 1 may include: an active layer ACT disposed on the base substrate 10, a gate insulating layer GI1 disposed on a side of the active layer ACT away from the base substrate 10, and a The gate electrode 51 on the side of the gate insulating layer GI1 away from the base substrate 10, the interlayer insulating layer IDL disposed on the side of the gate 51 away from the base substrate 10, and the interlayer insulating layer IDL disposed on the side away from the base substrate 10 The source electrode 52 and the drain electrode 53 are covered by the passivation layer PVX1 on the source electrode 52 and the drain electrode 53 . Wherein, the source electrode 52 and the drain electrode 53 are respectively electrically connected to the active layer ACT through via holes.

As shown in FIG. 4 , the first substrate 1 may further include: a first plate Cst1 of a capacitor and a second plate Cst2 of a capacitor. For example, the first pole plate Cst1 and the second pole plate Cst2 of the capacitor can be arranged oppositely, and an insulating layer can be set between the first pole plate Cst1 and the second pole plate Cst2 of the capacitor, and the insulating layer can be as shown in FIG. 4 The gate insulating layer GI2 shown.

The first substrate 1 may further include: a planarization layer PLN1 disposed on a side of the passivation layer PVX1 away from the base substrate 10; a transfer portion 45 disposed on a side of the planarization layer PLN1 away from the base substrate 10; The passivation layer PVX2 on the side of the transfer portion 45 away from the base substrate 10 ; and the planarization layer PLN2 disposed on the side of the passivation layer PVX2 away from the base substrate 10 . The transfer portion 45 is electrically connected to the drain 53 through a via hole penetrating through the passivation layer PVX1 and the planarization layer PLN1 . The anode 43 is electrically connected to the transfer portion 45 through a via hole penetrating through the passivation layer PVX2 and the planarization layer PLN2 . In this way, the electrical connection of the transistor of the pixel drive circuit to the anode 43 is realized.

The first substrate 1 may further include a pixel defining layer PDL disposed on a side of the anode 43 away from the base substrate 10 . The pixel defining layer PDL may include openings 441 in the sub-pixels. The opening 441 exposes a portion of the anode 43 . A portion of the light emitting layer 42 is filled in the opening 441 to be in contact with the exposed portion of the anode 43 . The cathode 41 is located on the side of the light emitting layer 42 away from the base substrate 10 .

In the exemplary embodiment shown in the figure, for the convenience of description, the layer where the gate electrode 51 is located may be referred to as the first conductive layer, and the layer where the source electrode 52 and the drain electrode 53 are located may be referred to as the second conductive layer. The layer where the portion 45 is located may be referred to as a third conductive layer.

For example, the first polar plate Cst1 may be located on the first conductive layer, and the second polar plate Cst2 may be located between the first conductive layer and the second conductive layer. For the convenience of description, the layer where the second pole plate Cst2 is located may be referred to as the fourth conductive layer.

For example, the first conductive layer and the fourth conductive layer may be conductive layers made of gate material, and the second conductive layer and the third conductive layer may be conductive layers made of source and drain materials. .

For example, the gate material may include metal materials, such as Mo, Al, Cu and other metals and their alloys. The source and drain materials may include metal materials, such as Mo, Al, Cu and other metals and their alloys. The anode may include conductive metal materials, such as magnesium, aluminum, lithium and other metals and their alloys. The cathode may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

5 to 12 are partial enlarged plan views of part I of the display substrate in FIG. 3 according to some exemplary embodiments of the present disclosure, wherein FIG. 5 schematically shows the first conductive layer at part I, and FIG. 6 schematically shows the second conductive layer at part I, Figure 7 schematically shows the combination of the first conductive layer and the second conductive layer at part I, and Figure 8 schematically shows the first conductive layer at part I Three conductive layers, Figure 9 schematically shows the combination of the first conductive layer, the second conductive layer and the third conductive layer at the part I place, and Figure 10 schematically shows the conductive layer arranged on the same layer as the anode at the part I place layer, Figure 11 schematically shows the combination of the first conductive layer at the part I, the second conductive layer, the third conductive layer and the conductive layer arranged on the same layer as the anode, and Figure 12 schematically shows the combination of the conductive layer at the part I Pixels define vias in the layer.

In the embodiment of the present disclosure, the cathode wiring 20 includes a plurality of parts respectively located in a plurality of conductive layers. The cathode wiring 22 and the third sub-cathode wiring 23 . For example, the first sub-cathode wiring 21 can be located on the same layer as the anode 43, the second sub-cathode wiring 22 can be located on the second conductive layer, and the third sub-cathode wiring 23 can be located on the third conductive layer. . In an embodiment of the present disclosure, the cathode wiring 20 includes a plurality of sub-cathode wirings arranged in different layers, and at least some of the plurality of sub-cathode wirings arranged in different layers are electrically connected through via holes. In this way, a plurality of sub-cathode wirings arranged in different layers are connected in parallel to transmit the cathode signal, which is beneficial to reduce the resistance of the cathode wiring 20, thereby reducing the number of cathodes located far away from the signal source (such as external drive circuits such as COF). voltage drop.

In an embodiment of the present disclosure, the display substrate may further include an anode trace 30 and an initialization signal trace 60 disposed on the base substrate 10 . For example, the cathode wiring 20 may be a wiring that provides a VSS voltage signal, the anode wiring 30 may be a wiring that provides a VDD voltage signal, and the initialization signal wiring 60 may be a wiring that provides an initialization voltage signal (ie, Vint). For example, the cathode trace 20 is electrically connected to the cathode 41 , and the anode trace 30 is electrically connected to the anode 43 . It should be noted that "the anode wiring 30 is electrically connected to the anode 43" here may mean that the anode wiring 30 is electrically connected to the anode 43 through electronic components such as thin film transistors in the pixel driving circuit.

Exemplarily, the anode wiring 30 includes a plurality of parts respectively located in a plurality of conductive layers. For the convenience of description, the plurality of parts are referred to as the first sub-anode wiring 31 and the second sub-anode wiring 32 respectively. and the third sub-anode wire 33. For example, the first sub-cathode wiring 31 may be located on the first conductive layer, the second sub-anode wiring 32 may be located on the second conductive layer, and the third sub-anode wiring 33 may be located on the third conductive layer. In an embodiment of the present disclosure, the anode wiring 30 includes multiple sub-anode wirings arranged in different layers, and at least some of the multiple sub-anode wirings arranged in different layers are electrically connected through via holes. In this way, multiple sub-anode wires arranged in different layers are connected in parallel to transmit the anode signal, which is beneficial to reduce the resistance of the anode wire 30, thereby improving the display uniformity of the display substrate.

Exemplarily, the initialization signal wiring 60 includes a plurality of parts respectively located in a plurality of conductive layers. For the convenience of description, the plurality of parts are referred to as the first sub-initialization signal wiring 601 and the second sub-initialization signal wiring 601 respectively. Line 602. For example, the first sub-initialization signal wiring 601 may be located on the second conductive layer, and the second sub-initialization signal wiring 602 may be located on the third conductive layer. In an embodiment of the present disclosure, the initialization signal wiring 60 includes multiple sub-initialization signal wirings arranged in different layers, and the multiple sub-initialization signal wirings arranged in different layers are electrically connected through via holes. In this way, multiple sub-initialization signal wires arranged in different layers are connected in parallel to transmit the initialization voltage signal, which is beneficial to reduce the resistance of the initialization signal wire 60 , thereby improving the display uniformity of the display substrate.

4, FIG. 5 and FIG. 6, the first sub-anode wiring 31 is located in the first conductive layer, which may include a first part 311 and a second part 312, the first sub-anode wiring 31 A part 311 extends along the first direction X, and a second part 312 of the first sub-anode trace extends along the second direction Y.

Referring to FIG. 4 to FIG. 7 in conjunction, the second sub-anode wiring 32 is located on the second conductive layer. Between the first conductive layer and the second conductive layer, an insulating layer is provided, such as the insulating layers GI2 and IDL shown in FIG. 4 . The insulating layer has a fifth via hole VH1, the orthographic projection of the fifth via hole VH1 on the base substrate 10 and the second part 312 of the first sub-anode wiring on the base substrate 10 The orthographic projections of are at least partially overlapping. In this way, the second sub-anode trace 32 can be electrically connected to the second portion 312 of the first sub-anode trace through the fifth via hole VH1.

For example, the second sub-anode traces 32 may have multiple different widths. The width of the second sub-anode line 32 at the position corresponding to the fifth via hole VH1 is greater than the width at other positions of the second sub-anode line 32, so that the connection between the second sub-anode line 32 and the first line can be increased. The area of the contact portion of the second part 312 of the sub-anode trace is beneficial to reduce the contact resistance.

Referring to FIG. 6 and FIG. 7 , the second sub-cathode wiring 22 is located on the second conductive layer. The second sub-cathode wiring 22 may include a first portion 221 and a second portion 222 . For example, the first portion 221 may extend substantially along the first direction X, and the second portion 222 may substantially extend along the second direction Y.

The first sub-initialization signal wiring 601 is also located on the second conductive layer. The first sub-initialization signal routing 601 may include a first part 6011 and a second part 6012 . For example, the first portion 6011 may extend substantially along the first direction X, and the second portion 6012 may substantially extend along the second direction Y.

Referring to FIG. 4 to FIG. 9 in conjunction, the third sub-anode wiring 33 is located on the third conductive layer. Between the second conductive layer and the third conductive layer, an insulating layer is provided, such as the insulating layers PVX1 and PLN1 shown in FIG. 4 . The insulating layer has a sixth via hole VH2, and the orthographic projection of the sixth via hole VH2 on the base substrate 10 is at least at least partially overlap. In this way, the third sub-anode wiring 33 can be electrically connected to the second sub-anode wiring 32 through the sixth via hole VH2.

The third sub-cathode wiring 23 is located on the third conductive layer. Between the second conductive layer and the third conductive layer, an insulating layer is provided, such as the insulating layers PVX1 and PLN1 shown in FIG. 4 . The insulating layer includes a third via hole VH3 and a fourth via hole VH4 , and the third via hole VH3 and the fourth via hole VH4 respectively expose at least a part of the second sub-cathode wiring 22 . The third sub-cathode wiring 23 is electrically connected to the second sub-cathode wiring 22 through the third via hole VH3 and the fourth via hole VH4 respectively.

For example, the extension direction of the fourth via hole VH4 is basically the same as the direction of the second sub-cathode wiring 22, and the fourth via hole VH4 makes the second sub-cathode wiring 22 account for 50% of its circumference. The above part is exposed. Most of the third sub-cathode wire 23 (for example, a portion exceeding 50% of its circumference) and most of the second sub-cathode wire 22 (for example, a portion exceeding 50% of its circumference) are electrically connected through the fourth via hole VH4. connect. In this way, in the cathode wiring 20 , the parallel connection of the two sub-cathode wirings located in the second conductive layer and the third conductive layer is realized, which is beneficial to reduce the resistance of the cathode wiring 20 .

For example, the third via hole VH3 includes a first portion VH31 and a second portion VH32, the first portion VH31 extends along a first direction X, the second portion VH32 extends along a second direction Y, and the first direction X Intersect with the second direction Y, for example, the first direction X and the second direction Y are perpendicular to each other.

The second sub-initialization signal wiring 602 is also located on the third conductive layer. The insulating layers PVX1 and PLN1 further include a seventh via hole VH5 , and the seventh via hole VH5 exposes a part of the first sub-initialization signal wiring 601 . The second sub-initialization signal wiring 602 is electrically connected to the first sub-initialization signal wiring 601 through the seventh via hole VH5.

In the embodiment of the present disclosure, the cathode wiring, the anode wiring and the The initialization signal wires are led out to the third conductive layer. For example, an external driving circuit of COF may be provided on the same layer as the third conductive layer. Through such an extraction method, it is beneficial for the external driving circuit to supply signals to each wiring.

For example, the seventh via hole VH5 and the sixth via hole VH2 extend in parallel along the first direction X, and the seventh via hole VH5 and the sixth via hole VH2 are arranged at intervals along the second direction Y. The orthographic projections of the fifth via hole VH1 and the sixth via hole VH2 on the base substrate 10 may be basically arranged in the same row along the first direction X and separated by a certain distance.

For example, the orthographic projection of the initialization signal wiring 60 on the substrate 10 is located at the same location as the orthographic projection of the second sub-cathode wiring 22 on the substrate 10 and the anode wiring 30 on the substrate 10. between the orthographic projections on the base substrate 10 described above.

Referring to FIG. 4 to FIG. 11 in conjunction, the first sub-cathode wiring 21 and the anode 43 are arranged on the same layer. Referring to FIG. 3 , the first sub-cathode traces 21 may extend along the first direction X to electrically connect two parts of the second sub-cathode traces 22 located on both sides of the display substrate to form a surrounding The cathode wiring 20 of the display area AA.

For example, an insulating layer is provided between the third conductive layer and the layer where the anode 43 is located, such as the insulating layers PVX2 and PLN2 shown in FIG. 4 . The insulating layer includes an eighth via hole VH6. For example, the insulating layer may include two eighth via holes VH6, and the two eighth via holes VH6 are respectively located on both sides of the display area AA, so as to respectively expose the third sub-cathode traces located on both sides of the display area AA. at least a portion of line 23. The first sub-cathode traces 21 are electrically connected to the third sub-cathode traces 23 through two eighth via holes VH6 respectively.

Referring to FIGS. 4 to 12 in combination, the pixel defining layer PDL may include first via holes VH7 and VH8 , and the first via holes VH7 and VH8 respectively expose at least a part of the first sub-cathode wiring 21 . The cathode 41 can be electrically connected to the first sub-cathode wiring 21 through the first via holes VH7 and VH8 respectively. In this way, the electrical connection between the cathode 41 and the cathode trace 20 can be realized.

For example, the first via hole VH7 extends along the first direction X. Referring to FIG. The pixel defining layer PDL may include two second via holes VH8, and the two second via holes VH8 are respectively located on both sides of the display area AA to respectively expose the first sub-cathode traces located on both sides of the display area AA. At least a portion of the line 21. In other words, the two second via holes VH8 are located on both sides of the first via hole VH7 respectively. The extending direction of the second via hole VH8 is basically the same as the direction of the first sub-cathode wiring 21 or the second sub-cathode wiring 22, and the second via hole VH8 makes the first sub-cathode wiring 21 More than 50% of its circumference is exposed. In this way, the contact area between the first cathode wiring 21 and the cathode 41 can be increased, which is beneficial to reduce the contact resistance.

For example, the orthographic projection of the second via hole VH8 on the base substrate 10 at least partially overlaps the orthographic projection of the eighth via hole VH6 on the base substrate 10 .

For example, the orthographic projection of the first part 311 of the first sub-anode trace on the base substrate 10 at least partially overlaps the orthographic projection of the first sub-cathode trace 21 on the base substrate 10 .

For example, the orthographic projection of the first part 311 of the first sub-anode trace on the base substrate 10 at least partially overlaps the orthographic projection of the first via hole VH7 on the base substrate 10 .

For example, the size of the overlapping part of the first via hole VH7 and the second part 312 of the first sub-anode line along the first direction X is the same as that of the second part 312 of the first sub-anode line along the first direction X. The ratio of the size of the direction X is in the range of 0.8-1.2, for example, the size of the overlapping part of the first via hole VH7 and the second part 312 of the first sub-anode wiring along the first direction X is substantially equal to the The dimension along the first direction X of the second part 312 of the first sub-anode trace is described above.

For example, the size of the part of the first via hole VH7 overlapping the first part 311 of the first sub-anode trace along the first direction X is the same as that of the first part 311 of the first sub-anode trace along the first direction X. The ratio of the dimensions is in the range of 0.8-1.2. For example, the size of the portion of the first via hole VH7 overlapping the first part 311 of the first sub-anode trace along the first direction X is substantially equal to the size of the first part 311 of the first sub-anode trace along the first direction. X-dimensions.

For example, the size of the portion of the first via hole VH7 overlapping the first part 311 of the first sub-anode trace along the second direction Y is the same as that of the first part 311 of the first sub-anode trace along the second direction Y. The ratio of the dimensions is in the range of 0.4-0.8. For example, the portion of the first via hole VH7 overlapping the first part 311 of the first sub-anode trace along the second direction Y has a size equal to that of the first part 311 of the first sub-anode trace along the second direction Y. roughly half the size of the

For example, the ratio of the size of the second via hole VH8 along the second direction Y to the size of the first via hole VH7 along the second direction Y is in the range of 1.1-10. That is, the size of the second via hole VH8 along the second direction Y is greater than the size of the first via hole VH7 along the second direction Y.

Referring back to FIGS. 1 and 3 , a display device according to an embodiment of the present disclosure may include the above-described display substrate. For example, it includes a display area AA and a peripheral area NA, and the film layer structures in the display area AA and the peripheral area NA can refer to the descriptions of the above-mentioned embodiments, and will not be repeated here.

The display device may include any device or product with a display function. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio Players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), televisions, etc.

It should be understood that the display device according to the embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate (for example, the first substrate), for details, please refer to the above description.

Although some embodiments of the general technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principle and spirit of the general technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

A display substrate, comprising:

a base substrate comprising a display area and a peripheral area at least on a first side of the display area;

A plurality of pixel units, the plurality of pixel units are arranged in an array along the first direction and the second direction in the display area of the base substrate, wherein the pixel units include a pixel driving circuit and are connected with the pixel driving circuit A light-emitting device electrically connected to a circuit, the light-emitting device comprising a cathode, an anode, and a light-emitting layer disposed between the cathode and the anode;

an anode trace located in the peripheral region, the anode trace for supplying an anode voltage; and

a cathode trace located in the peripheral region, the cathode trace electrically connected to the cathode,

Wherein, the cathode trace substantially surrounds the display area, and the cathode is electrically connected to the cathode trace at multiple locations; and

The cathode wiring includes a first sub-cathode wiring, the first sub-cathode wiring is located on the same layer as the anode, and the orthographic projection of the first sub-cathode wiring on the base substrate is the same as the Orthographic projections of the anode traces on the base substrate partially overlap.
The display substrate according to claim 1, wherein the display substrate further comprises a pixel defining layer on the base substrate, the pixel defining layer is located between the layer where the anode is located and the layer where the cathode is located between;

The pixel defining layer includes a first via hole and a second via hole, the first via hole and the second via hole respectively expose at least a part of the first sub-cathode wiring, and the cathode passes through the first sub-cathode wiring. A via hole and the second via hole are respectively electrically connected to the first sub-cathode wiring.
The display substrate according to claim 1 or 2, wherein the pixel driving circuit comprises at least one thin film transistor and at least one capacitor arranged on the base substrate, the thin film transistor comprises an active layer, a gate, source and drain;

The display substrate includes: a first conductive layer disposed on the side of the active layer away from the base substrate, the gate is located on the first conductive layer; disposed on the first conductive layer away from the The second conductive layer on the side of the base substrate, the source and the drain are located on the second conductive layer; the third conductive layer arranged on the side of the second conductive layer away from the base substrate, the a third conductive layer located between the second conductive layer and the layer where the anode is located; and

The cathode wiring includes a second sub-cathode wiring, and the second sub-cathode wiring is located on the second conductive layer.
The display substrate according to claim 3, wherein the cathode wiring includes a third sub-cathode wiring, and the third sub-cathode wiring is located on the third conductive layer.
The display substrate according to claim 4, wherein the display substrate comprises a first insulating layer disposed between the second conductive layer and the third conductive layer, the first insulating layer comprises a third pass A hole and a fourth via hole, the third via hole and the fourth via hole respectively expose at least a part of the second sub-cathode wiring;

The third sub-cathode wiring is electrically connected to the second sub-cathode wiring through the third via hole and the fourth via hole respectively.
The display substrate according to claim 2, wherein the first via holes extend along the first direction, and the pixel defining layer includes at least two second via holes, and the two second via holes are respectively located at Both sides of the first via hole.
The display substrate according to claim 5, wherein the extending direction of the fourth via hole is the same as the direction of the second sub-cathode trace, and the fourth via hole makes the second sub-cathode trace occupy More than 50% of its circumference is exposed; and/or,

The extending direction of the second via hole is the same as the direction of the second sub-cathode wiring, and the second via hole exposes a part of the first sub-cathode wiring accounting for more than 50% of its circumference.
The display substrate according to claim 5, wherein the third via hole includes a first portion and a second portion, the first portion extends along a first direction, the second portion extends along a second direction, and the first portion extends along a second direction. A direction intersects the second direction.
The display substrate according to claim 5, wherein an orthographic projection of the second via hole on the base substrate at least partially overlaps with an orthographic projection of the fourth via hole on the base substrate.
The display substrate according to claim 1 or 2, wherein the anode wiring includes a first sub-anode wiring, and the first sub-anode wiring is located on the first conductive layer.
The display substrate according to claim 10, wherein the anode wiring includes a second sub-anode wiring, the second sub-anode wiring is located on the second conductive layer, and the second sub-anode wiring passes through The fifth via hole is electrically connected to the first sub-anode wiring.
The display substrate according to claim 11, wherein the anode wiring includes a third sub-anode wiring, the third sub-anode wiring is located on the third conductive layer, and the third sub-anode wiring passes through The sixth via hole is electrically connected to the second sub-anode wiring.
The display substrate according to claim 12, wherein the first sub-anode wiring includes a first part and a second part, the first part of the first sub-anode wiring extends along a first direction, and the first sub-anode wiring a second portion of the anode trace extends along a second direction;

The orthographic projection of the fifth via hole on the base substrate at least partially overlaps the orthographic projection of the second part of the first sub-anode trace on the base substrate.
The display substrate according to claim 13, wherein the orthographic projection of the first part of the first sub-anode wiring on the substrate is the same as that of the first sub-cathode wiring on the substrate. The orthographic projections overlap at least partially.
The display substrate according to claim 13, wherein the orthographic projection of the first part of the first sub-anode wiring on the base substrate is the same as the orthographic projection of the first via hole on the base substrate overlap at least partially.
The display substrate according to claim 1 or 2, wherein the display substrate further comprises an initialization signal wiring located in the peripheral area, and the initialization signal wiring is used to supply an initialization voltage;

The initialization signal wiring includes a first sub-initialization signal wiring and a second sub-initialization signal wiring, the first sub-initialization signal wiring is located on the second conductive layer, and the second sub-initialization signal wiring is located on the the third conductive layer;

The first sub-initialization signal wiring is electrically connected to the second sub-initialization signal wiring through a seventh via hole.
The display substrate according to claim 16, wherein the seventh via hole and the sixth via hole extend parallel to the first direction, and the seventh via hole and the sixth via hole extend along the second direction. Orientation interval setting.
The display substrate according to claim 16, wherein the orthographic projection of the initialization signal wiring on the base substrate is located between the orthographic projection of the second sub-cathode wiring on the base substrate and the The anode traces are between the orthographic projections on the base substrate.
The display substrate according to claim 10, wherein the orthographic projection of the first sub-anode trace on the base substrate partly overlaps the orthographic projection of the first via hole on the base substrate.
The display substrate according to claim 19, wherein the size of the portion of the overlapping portion of the first via hole and the second portion of the first sub-anode trace along the first direction is the same as that of the first sub-anode trace. The ratio of the dimensions of the second portion along the first direction is in the range of 0.8-1.2; and/or,

The ratio of the size along the first direction of the portion of the first via hole overlapping the first part of the first sub-anode wiring to the size of the first part of the first sub-anode wiring along the first direction is between 0.8- 1.2; and/or,

The ratio of the size along the second direction of the portion of the first via hole overlapping the first part of the first sub-anode wiring to the size of the first part of the first sub-anode wiring along the second direction is between 0.4- within 0.8; and/or,

A ratio of the size of the second via hole along the second direction to the size of the first via hole along the second direction is in the range of 1.1-10.
The display substrate according to claim 5, wherein the display substrate includes a second insulating layer disposed between the third conductive layer and the layer where the anode is located, and the second insulating layer includes an eighth pass hole, the eighth via hole exposes at least a part of the third sub-cathode wiring;

The first sub-cathode wiring is electrically connected to the third sub-cathode wiring through the eighth via hole.
The display substrate according to claim 19, wherein an orthographic projection of the eighth via hole on the base substrate at least partially overlaps with an orthographic projection of the fourth via hole on the base substrate.
A display device, comprising the display substrate according to any one of claims 1-22.