WO2023045114A1 - 存算一体芯片及数据处理方法 - Google Patents

存算一体芯片及数据处理方法 Download PDF

Info

Publication number
WO2023045114A1
WO2023045114A1 PCT/CN2021/137844 CN2021137844W WO2023045114A1 WO 2023045114 A1 WO2023045114 A1 WO 2023045114A1 CN 2021137844 W CN2021137844 W CN 2021137844W WO 2023045114 A1 WO2023045114 A1 WO 2023045114A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
calculation
processing units
storage
input data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/137844
Other languages
English (en)
French (fr)
Inventor
吴华强
江燕海
姚鹏
高滨
唐建石
钱鹤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Publication of WO2023045114A1 publication Critical patent/WO2023045114A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/21—Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
    • G06F18/211—Selection of the most significant subset of features
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present disclosure relate to a memory-computing integrated chip and a data processing method applied to the memory-computing integrated chip.
  • Memristor-based memory-computing integration technology is expected to break through the bottleneck of the von Neumann architecture of classical computing systems, bring explosive growth in hardware computing power and energy efficiency, and further promote the development and implementation of artificial intelligence.
  • One of the first-generation hardware chip technologies With its high-performance, low-power architecture advantages, the memristor-based memory-computing integrated system is expected to become a hardware carrier for intelligent computing in the post-Moore era that breaks through the von Neumann bottleneck.
  • At least one embodiment of the present disclosure provides a distributed control architecture storage-computing integrated chip, including: a plurality of processing units, each processing unit includes: a computing unit configured to store a parameter matrix, receive input data, and use the parameter matrix to process the input The data is calculated to obtain output data; and the control unit is configured to communicate with the calculation unit, and is configured to write the parameter matrix into the calculation unit to obtain the configured calculation unit, and control the configured calculation unit to use the parameter matrix to process the input data computing; and a master control unit configured to communicate with the plurality of processing units, and to provide parameter matrices respectively for the plurality of processing units to respective control units of the plurality of processing units according to the overall network parameter set.
  • the storage-computing integrated chip provided in at least one embodiment of the present disclosure further includes: a first storage unit configured to communicate with a plurality of processing units and a main control unit, store the overall input data and/or the overall output data, and Under the control of the control unit, provide the input data required by the plurality of processing units to the plurality of processing units, and/or receive the output data generated by the plurality of processing units from the plurality of processing units, wherein the overall input data includes For the input data of the multiple computing units, the overall output data includes the output data of the multiple computing units.
  • the storage-computing integrated chip provided by at least one embodiment of the present disclosure further includes: an on-chip interconnect configured to connect the main control unit, the first storage unit, and a plurality of processing units for communication.
  • the calculation unit includes: at least one memristor array, wherein the at least one memristor array is configured to store a parameter matrix and perform calculations on input data.
  • control unit includes: a parameter configuration unit configured to configure the parameter matrix into the calculation unit, and/or acquire the parameter matrix currently owned by the calculation unit from the calculation unit value.
  • control unit further includes: a read control unit configured to control the reading of input data to provide the input data to the calculation unit; a write control unit configured to Controls output of output data.
  • each processing unit further includes: a functional unit, wherein the functional unit is configured to process the calculation result of the calculation unit to obtain output data.
  • the functional unit includes: a shift and addition unit configured to obtain the calculation result from the calculation unit, and perform shift and addition operations on the calculation result; or activate A unit configured to perform activation function processing on calculation results; or a pooling unit configured to perform pooling processing on calculation results.
  • each processing unit further includes: a second storage unit configured to obtain input data from the first storage unit or send output data to the first storage unit;
  • the buffer unit is configured to buffer input data;
  • the output buffer unit is configured to buffer output data.
  • each processing unit further includes: an interconnection interface configured to communicate with the main control unit and the first storage unit.
  • At least one embodiment of the present disclosure provides a data processing method, which is applied to the memory-computing integrated chip provided by at least one embodiment of the present disclosure.
  • the data processing method includes: the main control unit receives the overall network parameter set, and according to the overall parameter set, respectively
  • the parameter matrices for the plurality of processing units are provided to respective control units of the plurality of processing units; the respective control units of the plurality of processing units configure the received parameter matrices into respective calculation units of the plurality of processing units; Input data; multiple processing units independently calculate the input data according to the received input data using the received parameter matrix to obtain output data.
  • Figure 1A shows a schematic diagram of matrix-vector multiplication
  • FIG. 1B is a schematic structural diagram of a memristor array provided by at least one embodiment of the present disclosure
  • FIG. 2A shows a schematic diagram of the control flow of the architecture with the main control unit as the central scheduling unit;
  • FIG. 2B shows a schematic diagram of a distributed control architecture based on a bus mechanism provided by at least one embodiment of the present disclosure
  • FIG. 2C shows a schematic diagram of a control flow of a distributed control architecture provided by at least one embodiment of the present disclosure
  • FIG. 2D shows a schematic diagram of the control flow of the traditional storage-computing integrated architecture and the distributed control architecture provided by the present disclosure under the on-chip routing mechanism;
  • FIG. 3A is a schematic diagram of a storage-computing integrated chip of a distributed control architecture provided by at least one embodiment of the present disclosure
  • Fig. 3B shows a schematic diagram of the data flow of the functional unit taking the memristor array outputting 8 bits as an example
  • Fig. 4 shows a flowchart of a data processing method provided by at least one embodiment of the present disclosure
  • Fig. 5 shows a working flow chart of the storage-computing integrated chip provided by at least one embodiment of the present disclosure
  • Figure 6 shows a flow chart of an exemplary read control process
  • Fig. 7 shows a schematic diagram of reading data from the second storage unit to the input buffer unit.
  • Memristor for example, resistive change memory, phase change memory, conductive bridge memory, etc.
  • memristor has the characteristics of adjustable resistance and non-volatility, so it is widely used in storage and computing integration technology.
  • Kirchhoff's current law and Ohm's law an array composed of memristors can perform multiplication and accumulation calculations in parallel, and both storage and calculation take place in each memristor of the memristor array. Based on this computing architecture, it is possible to realize storage-computing integrated computing that does not require a large amount of data movement.
  • a cross-array composed of memristors can perform matrix-vector multiplication operations in parallel, and is widely used in accelerating neural network algorithms. Therefore, memory-computing integrated chips can use memristor arrays to complete calculations.
  • Existing memory-computing integrated chips are often designed with a customized architecture for a specific neural network, which can efficiently process target tasks, but cannot effectively process multiple algorithm models at the same time due to the lack of an efficient data flow control unit.
  • Figure 1A shows a schematic diagram of matrix-vector multiplication.
  • input vector X for example, including x 1 , x 2 , ..., x m shown in Fig. 1A
  • parameter matrix G for example, including g 11 , g 12 shown in Fig. 1A , ..., g 1m , ..., g n1 , g n2 , ..., g nm
  • I for example, including I 1 , I 2 , ..., In shown in Fig. 1A
  • I 1 x 1 g 11 +x 2 g 12 + . . . + x m g 1m .
  • FIG. 1B is a schematic structural diagram of a memristor array provided by at least one embodiment of the present disclosure.
  • the memristor array structure can include a plurality of memristors arranged in an array, and the input vector X shown in Figure 1A (for example, the input vector can be encoded amplitude, width or pulse number The voltage) is supplied to the input terminal of the memristor array, the parameter matrix G shown in Figure 1A is encoded as the memristor conductance value, and the output current I is obtained by using a high-parallel, low-power array read operation, that is, Figure 1A
  • the output vector I shown can realize the common multiplication and accumulation calculation in deep learning, and then accelerate the matrix-vector multiplication.
  • I 1 x 1 g 11 +x 2 g 12 + . . . + x m g 1m .
  • the above multiplication and accumulation calculation process is realized by physical laws, which is different from the digital circuit implementation of Boolean logic. It does not need to frequently access and move weight data, which solves the von Neumann bottleneck of classical computing systems, and can achieve high computing power and high energy efficiency. Intelligent computing tasks.
  • the memristors arranged in the array in the memristor array shown in Figure 1B can be a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a switching transistor and a memristor, and the memristor of the 2T2R structure
  • the device unit includes two switching transistors and two memristors, and the embodiments of the present disclosure do not limit the type of the memristors used.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • Embodiments of the present disclosure do not limit the types of transistors used.
  • the architecture based on the main control unit can be adopted.
  • the main control unit is used as the central scheduling unit to complete the control, configuration and scheduling of multiple computing units, and the computing unit itself does not have a scheduling function.
  • frequent scheduling and data interaction between the main control unit and computing units consumes a lot of time, resulting in low computational efficiency.
  • Fig. 2A shows a schematic diagram of the control flow of the architecture with the main control unit as the central dispatching unit.
  • the main control unit 102 completes data scheduling and task allocation, and the calculation unit 103 completes calculations.
  • the dotted arrows in FIG. 2A represent the control flow of the central control architecture, and the control flow flows from the main control unit 102 to the computing unit 103 through the bus 107 .
  • frequent scheduling and data interaction between the main control unit 102 and the computing unit 103 will consume a lot of time, resulting in low computing efficiency.
  • At least one embodiment of the present disclosure provides a storage-computing integrated chip with a distributed control architecture.
  • the memory-computing integrated chip includes: a plurality of processing units, each processing unit includes: a computing unit configured to store a parameter matrix, receive input data, and use the parameter matrix to calculate the input data to obtain output data; and a control unit configured to communicate with The calculation unit communicates with each other, and is configured to write the parameter matrix into the calculation unit to obtain the configured calculation unit, and controls the configured calculation unit to use the parameter matrix to calculate the input data; and the main control unit is configured to communicate with multiple processing units communicate, and provide parameter matrices respectively for the plurality of processing units to respective control units of the plurality of processing units according to the overall network parameter set.
  • At least one embodiment of the present disclosure further provides a data processing method applied to the above integrated memory-computing chip.
  • the storage-computing integrated chip of the distributed control architecture provided by the above-mentioned embodiments of the present disclosure can utilize an efficient distributed architecture to achieve high computing power and high energy efficiency while ensuring versatility and flexibility.
  • the storage-computing integrated chip proposed in the embodiment of the present disclosure adopts a distributed control architecture, that is, a local control unit is integrated in the traditional computing unit 103 shown in FIG. 2A , Thus, a processing unit is formed, but in the distributed control architecture proposed in this disclosure, the work of data scheduling and task allocation is completed by the local control unit, and the computing efficiency is greatly improved through parallel distributed scheduling and configuration.
  • Fig. 2B shows a schematic diagram of a distributed control architecture based on a bus mechanism provided by at least one embodiment of the present disclosure.
  • the main control unit 102, the first storage unit 106, and a plurality of processing units 101 are connected through a bus 107, and local control can be realized by integrating the control unit 104 (see Figure 2C) inside the plurality of processing units 101 and flexible matrix parameter configuration and data flow scheduling, and distribute work tasks to each processing unit 101 for execution, thus overcoming the inefficiency of the central control architecture shown in Figure 2A while taking into account flexibility and versatility .
  • FIG. 2C is a schematic diagram of the control flow of the distributed control architecture shown in FIG. 2B .
  • each processing unit 101 includes a computing unit 103 and a control unit 104.
  • the computing unit 103 does not directly perform data scheduling and task assignment by the main control unit 102, but by the same processing unit.
  • the corresponding control unit 104 performs data scheduling and task allocation.
  • the dotted arrows indicate the control flow.
  • the control flow is inside the processing unit 101 , which can improve computing efficiency and energy efficiency.
  • the multiple processing units 101 , the main control unit 102 and the first storage unit 106 may also communicate based on other on-chip interconnection mechanisms.
  • the on-chip interconnection mechanism includes a switch network, an on-chip network (on-chip routing), etc., which are not limited in the embodiments of the present disclosure.
  • FIG. 2D shows a schematic diagram of the control flow of the traditional storage-computing integrated architecture and the distributed control architecture provided by the present disclosure under the on-chip routing mechanism.
  • a plurality of processing units 101, a main control unit 102, and a first storage unit 106 are respectively connected to a specific router at a network node through a network interface, and the communication between these units is converted into a router Communication with the router.
  • the on-chip routing mechanism is no longer limited by the bus architecture, so any number of routing nodes can be expanded.
  • control flow is shown by the dotted arrow marked 1.
  • the control flow goes from the routing node connected to the main control unit 102 through multiple processing units 101 to the processing unit 101 that the main control unit 102 needs to control.
  • the control flow is shown by the dotted arrow marked 2, and the control flow is inside the processing unit 101, thereby avoiding frequent scheduling and data interaction between the main control unit 102 and the processing unit 101, Improved computational efficiency.
  • the present disclosure proposes a storage-computing integrated chip using a distributed control architecture, for example, for artificial intelligence computing.
  • FIG. 3A is a schematic diagram of a storage-computing integrated chip 100 of a distributed control architecture provided by at least one embodiment of the present disclosure.
  • the storage and calculation integrated chip 100 is implemented with circuits (digital circuits and analog circuits), including a plurality of processing units 101 (only one processing unit is shown in the figure) and a main control unit 102, each processing unit 101 It includes a calculation unit 103 and a control unit 104 .
  • the calculation unit 103 is configured to store the parameter matrix, receive input data, and use the parameter matrix to calculate the input data to obtain output data
  • the control unit 104 is configured to communicate with the calculation unit 103, and is configured to write the parameter matrix into the calculation unit 103
  • the configured calculation unit 103 is obtained, and the configured calculation unit 103 is controlled to calculate the input data using the parameter matrix
  • the main control unit 102 is configured to communicate with multiple processing units 101, and according to the overall network parameter set will be used for
  • the parameter matrices of the plurality of processing units 101 are provided to respective control units 104 of the plurality of processing units 101 .
  • the calculation unit 103 includes at least one memristor array 105 configured to store a parameter matrix and perform calculations on input data.
  • the structure of the memristor array 105 is shown in FIG. 1B
  • the parameter matrix is, for example, the parameter matrix G shown in FIG. 1A , which is stored in at least one memristor array 105 in the computing unit 103 in the form of conductance.
  • the calculation unit 103 receives the input data (for example, the input data arrangement corresponds to the input vector X as shown in FIG. 1A ), and uses the parameter matrix to calculate the input data (for example, the matrix-vector multiplication operation shown in FIG. 1A ) to obtain the output data ( For example, corresponding to the output vector I) shown in Fig. 1A.
  • the number of rows and columns of each memristor array 105 may be the same, however, the number of rows and columns of each memristor array 105, The number of memristor arrays 105 can be freely designed according to actual conditions.
  • DAC digital-to-analog converter
  • ADC analog-to-digital converter
  • control unit 104 includes a parameter configuration unit 1041, and the parameter configuration unit 1040 is configured to configure the parameter matrix into the calculation unit 103, and/or obtain from the calculation unit 103 the current The value of the parameter matrix, so that the stored conductance value can be checked.
  • the control unit 104 maps the parameters of the parameter matrix corresponding to the memristor array 105 to the multiple memristor arrays 105 Resistors, so as to configure the parameter matrix into the computing unit 103.
  • the memristors contained therein face reliability problems, and have inevitable fluctuations, noises, and state drifts, etc., thereby causing calculation errors and affecting the normal function of the system.
  • the conductance value of the memristor for calculation, the actual conductance value will deviate from the ideal conductance value due to the non-ideal characteristics of the memristor, such as random fluctuations, relaxation characteristics, and retention characteristics of the memristor. , leading to deviations in the calculation results.
  • the parameter configuration unit 1040 needs to obtain the value of the parameter matrix currently owned by the calculation unit 103 from the calculation unit 103 , and compare it with the value of the parameter matrix that actually needs to be configured to correct the value of the parameter matrix in the calculation unit 103 .
  • control unit 104 further includes a read control unit 1042 and a write control unit 1043, the read control unit 1042 is configured to control the reading of input data to provide the input data to the computing unit 103, and the write control unit 1043 is configured to control output of output data.
  • the process of reading input data by the read control unit 1042 is shown in Figure 6.
  • the read control process mainly includes four parts: read address update, data read, input buffer unit filling, and input bit control, which will be specifically described in Figure 6. Be explained.
  • the storage-computing integrated chip 100 further includes a first storage unit 106 configured to communicate with a plurality of processing units 101 and the main control unit 102, store the overall input data and/or The overall output data, under the control of the main control unit 102, provides the input data required by the multiple processing units 101 to the multiple processing units 101 respectively, and/or receives the data generated by the multiple processing units 101 from the multiple processing units 101 respectively , wherein the overall input data includes input data for multiple computing units 103 , and the overall output data includes output data for multiple computing units 103 .
  • the first storage unit 106 may be a semiconductor storage device, such as a non-volatile memory or the like.
  • the first storage unit 106 may be connected to multiple processing units 101 and the main control unit 102 through a bus for communication.
  • the storage-computing integrated chip 100 also includes an on-chip interconnect, such as a bus 107 .
  • the bus is a public communication trunk line for transmitting information between various functional components of a computer. It is a transmission harness composed of wires and can be used to transmit data, data addresses and control signals. limit.
  • each processing unit 101 further includes an interconnection interface configured to communicate with the main control unit 102 and the first storage unit 106 .
  • the connection circuit between multiple processing units 101 and the bus 107 connected on the bus 107 is called a bus interface, and the bus interface is an interface for exchanging data between multiple processing units 101, the main control unit 102 and the first storage unit 106;
  • the interconnection interface is another type of interface for data and instruction interaction.
  • the overall input data refers to a collection of input data required by multiple processing units 101
  • the overall output data refers to a collection of output data generated by multiple processing units 101 .
  • the input data required by each of the multiple processing units 101 and the output data generated by each of them need to be stored by storage units inside the multiple processing units 101 .
  • each processing unit 101 further includes a second storage unit 109, an input buffer unit 110, and an output buffer unit 111, and the second storage unit 109 is configured to acquire input data from the first storage unit 106 or send data to the second storage unit 106.
  • a storage unit 106 sends output data
  • the input buffer unit 110 is configured to buffer the input data
  • the output buffer unit 111 is configured to buffer the output data.
  • the sizes of the second storage unit 109 , the input buffer unit 110 and the output buffer unit 111 can be set according to actual conditions.
  • the first storage unit 106 provides input data to the second storage unit 109 via the bus 107
  • the second storage unit 109 can be various types of storage devices, such as dual-port SRAM ( Static Random-Access Memory), dual-port SRAM includes a read port and a write port, the write port is a bus interface 107, and the read port is connected to the input buffer unit 110 of the memristor array 105.
  • the read port of the SRAM can be set to a larger bit width (for example, 512 bits).
  • the function of the input buffer unit 110 is to temporarily store the data sent by the second storage unit 109
  • the function of the output buffer unit 111 is to temporarily store the output data generated by the memristor array 105, so that it can play the role of coordinated buffering and realize Synchronization of data transfer.
  • the overall network parameter set is processed by the main control unit and distributed to each processing unit; the overall network parameter set is, for example, all or part of the weight matrix corresponding to a processing layer of a certain neural network, which is split and obtained for each The parameter matrix for the processing unit.
  • the overall network parameter set includes, for example, the number of network layers, convolution kernel size, network type, etc., and the main control unit 102 is used to provide parameter matrices for multiple processing units 101 at most according to the compiled overall network parameter set.
  • Convolutional neural networks are a class of feed-forward neural networks that include convolutional computations and have deep structures.
  • the structure of a convolutional neural network mainly includes an input layer, a hidden layer, and an output layer.
  • the hidden layer includes three common structures: a convolutional layer, a pooling layer, and a fully connected layer.
  • the function of the convolutional layer is to extract features from the input data, which contains multiple convolution kernels.
  • the 3*3 matrix is called a "filter”
  • feature map the matrix obtained by sliding the filter on the image and calculating the dot product
  • the number of convolutional layers is the number of groups of memristor arrays, each set of memristor arrays is mapped to a parameter matrix corresponding to one convolutional layer, and the memristor used in each convolutional layer
  • the number of channels of a feature map is used to represent a certain composition of the image.
  • an image captured by a standard digital camera will have three channels (red, green, and blue), each channel represents a color, and the pixel value of each channel is in the range of 0 to 255.
  • the three channels of the image can be Think of it as a two-dimensional matrix of depth 3 stacked together.
  • Convolution layer parameters include convolution kernel size, convolution stride and padding, which together determine the size of the output feature map of the convolution layer.
  • the number of convolution kernels is the same as the number of channels of the output feature map.
  • the convolution kernel size can be specified as any value smaller than the input image size, for example, 3, which means that the height and width of the convolution kernel are both 3, and the larger the convolution kernel size, the more complex the input features that can be extracted.
  • the convolution stride defines the distance between the positions of the convolution kernel when it scans the feature map twice. When the convolution stride is 1, the convolution kernel will sweep the elements of the feature map one by one. The convolution stride When it is n, the convolution kernel will skip n-1 pixels in the next scan.
  • the output feature map will be passed to the pooling layer for feature selection and information filtering.
  • the pooling process is the downsampling process. Common pooling modes include maximum pooling and average pooling. etc.
  • the fully connected layer is located in the last part of the hidden layer of the convolutional neural network. The function of the fully connected layer is to nonlinearly combine the extracted features to obtain the output.
  • each processing unit 101 further includes a function unit 108 configured to process the calculation result of the calculation unit 103 to obtain output data.
  • the functional unit 108 includes a shifting and adding unit 1081 or an activation unit 1082 or a pooling unit 1083, and the shifting and adding unit 1081 is configured to obtain the calculation result from the calculation unit 103, and perform a shift operation and an addition operation on the calculation result,
  • the activation unit 1082 is configured to perform activation function processing on the calculation result, and the pooling unit 1083 is configured to perform pooling processing on the calculation result.
  • the input data buffered in the input buffer unit 110 will be provided to the corresponding memristor array 105 for calculation, the input data can be divided into two times and provided to the memristor array 105, and the high bit of the input data will be provided for the first time Bit, the second time to provide the low bit of the input data, the purpose of this design is to ensure the accuracy of the calculation. For example, if the input data is 8 bits, the upper 4 bits are used as the input data of the memristor array 105 first, and then the lower 4 bits are used as the input data of the memristor array 105 .
  • the two calculation results output by the memristor array correspond to the calculation results of the high-bit input data and the calculation results of the low-bit input data respectively, and then the two calculation results need to be shifted and added by the shift and addition unit 1081, so that The results of the two calculations are combined to form the complete output data.
  • FIG. 3B shows a schematic diagram of the data flow of the functional unit taking the memristor array outputting 8 bits as an example.
  • the two results correspond to the 8-bit signed calculation results of the high and low bit input data respectively, and the calculation result of the high bit input data is shifted left by 4 bits and added to the calculation result of the low bit input data to obtain A 13-bit signed calculation result representing the complete matrix multiplication result of the array.
  • one convolutional layer corresponds to a group of memristor arrays, and a group of memristor arrays may contain multiple memristor arrays, and the matrix multiplication results of multiple memristor arrays are accumulated to obtain the volume The final calculation result of the stack. Then, the result is quantized into a 9-bit signed calculation result through operations such as right shift and Clip (to limit the result to a certain range). Then, the activation function is processed, and the result is converted into an 8-bit unsigned calculation result. Finally, pooling processing is performed, and the pooling result is sent to the first storage unit or the second storage unit through the above-mentioned write control unit.
  • Activation functions and pooling are concepts in neural networks. If no activation function is introduced, the output of each layer in the neural network is a linear function of the input of the previous layer. No matter how many layers the neural network has, the output is a linear combination of the inputs, which is easy to verify. Therefore, a nonlinear function is introduced as an activation function, so that the output of the neural network is no longer a linear combination of inputs, so that any function can be approximated.
  • the activation unit 1082 performs activation function processing on the calculation result to increase the nonlinearity of the calculation result.
  • the pooling process is the downsampling process. Common pooling methods include maximum pooling, average pooling, etc.
  • the pooling unit 1083 pools the calculation results to make the parameters and calculation quantity in the neural network more controllable. , so as to avoid overfitting.
  • the functional unit 108 in FIG. 2 is only exemplary, and the disclosed embodiment does not limit the specific implementation, and the included shift and addition unit 1081, activation unit 1082, and Pooling unit 1083 .
  • the functional unit 108 may include other units than the above shift and addition unit 1081, activation unit 1082 and pooling unit 1083, or only include some units in the shift and addition unit 1081, activation unit 1082 and pooling unit 1083, or not Include the above units.
  • FIG. 4 shows a flowchart of a data processing method provided by at least one embodiment of the present disclosure, and the data processing method is applied to the storage-computing integrated chip shown in FIG. 3 .
  • the data processing method includes steps S411-S414.
  • Step S411 The main control unit receives the overall network parameter set, and provides parameter matrices respectively used for the plurality of processing units to respective control units of the plurality of processing units according to the overall network parameter set.
  • the content of the overall network parameter set can refer to the parameter symbols and parameter meanings shown in Table 1.
  • Step S412 the respective control units of the multiple processing units configure the received parameter matrices into the respective calculation units of the multiple processing units.
  • the calculation unit includes at least one memristor array
  • the control unit maps the parameters of the parameter matrix corresponding to the memristor array to the memristor based on the mapping relationship between the parameters of the parameter matrix and the memristor array in the calculation unit. array of multiple memristors.
  • Step S413 Provide input data for multiple processing units.
  • the first storage unit is used to store the overall input data, and under the control of the main control unit, the input data required by each of the multiple processing units is provided from the first storage unit to the multiple processing units via the bus.
  • Step S414 the multiple processing units independently calculate the input data according to the received input data using the received parameter matrix to obtain output data.
  • each processing unit the structure of at least one memristor array included in the calculation unit is shown in Figure 1B, the received parameter matrix is stored in the memristor array, and the input data is calculated using the received parameter matrix get the output data.
  • Fig. 5 shows a working flow chart of the storage-computing integrated chip provided by at least one embodiment of the present disclosure.
  • the memory-computing integrated chip is in the initial state, and it is judged whether the overall network parameter set has been compiled. If it has been compiled, the main control unit will use the compiled overall network parameter set for multiple
  • the parameter matrices of the processing units are provided to respective control units of the plurality of processing units.
  • the respective control units of the plurality of processing units configure the parameter matrices into respective calculation units of the plurality of processing units.
  • read control is performed by the read control unit in the respective control units of the plurality of processing units, thereby reading input data to at least one memristor array in the respective calculation units of the plurality of processing units.
  • At least one memristor array in each calculation unit of the plurality of processing units performs calculation on the read input data.
  • the calculation result of at least one memristor array is provided to the functional unit for calculation to obtain output data.
  • write control is performed by the write control unit in the respective control units of the plurality of processing units.
  • the data of the first NUM_KERNELS (number of convolution kernels) channels output by the pooling unit will be stored in the output buffer unit (the data of other channels are invalid data), and then written to the first channel through the bus interface the second storage unit or the first storage unit. If the last convolutional layer is being calculated, the output data will be written to the first storage unit, otherwise it will be written to the second storage unit.
  • FIG. 6 shows a flowchart of an exemplary read control process. As shown in Figure 6, the process mainly includes four parts: read address update, data read, input buffer unit filling, input bit control, and Figure 6 also shows the pseudo code describing each part.
  • SIZE_IMAGE represents the input image's Size
  • K represents the size of the convolution kernel
  • STRIDE represents the stride of convolution
  • V represents the number of channels of the picture
  • L V*SIZE_IMAGE, the meaning of these parameters has been explained above.
  • the input data (input picture) is continuously stored in the second storage unit 109 row by row (or row by row).
  • K*K the number of channels of the input picture
  • each data corresponds to the input data of each row in the convolution kernel.
  • the second storage unit 109 is divided into many units (called blocks), for the data written into the second storage unit 109, the number of bytes of data written will be calculated, when the number of bytes of data written is equal to the block length Or when the data written is the last piece of data, the ready signal of the block is set to be valid, and the write operation to the block is no longer allowed at this time.
  • the purpose of this design is to ensure that valid data can be read in time during the read control process of the control unit. In theory, the smaller the unit length divided by the second storage unit 109, the better (the time to obtain valid data can be shortened), but so The area and power consumption of the second storage unit 109 will be increased, so the unit length of the second storage unit 109 should be divided reasonably.
  • the control unit can calculate the first address and the last address of the current required data, and then query the ready signal of the block corresponding to the first address and the last address, when the ready signal of the block is valid
  • the data read operation is performed at the same time, and then the calculation operation of the corresponding memristor array is started.
  • the control unit initiates the clearing operation of this block, and sets the ready signal of this block to invalid, and this block allows writing new data.
  • each memristor array has a corresponding input buffer unit, and the K data will be evenly distributed to the input buffer unit of each memristor array required for the calculation of the convolutional layer of this layer (NUM_ARRAYS in the pseudocode indicates that the layer The number of memristor arrays needed for convolutional layer calculations).
  • the data in the input buffer unit will be provided to the corresponding memristor array for calculation, and the data can be input twice, the high bit is input for the first time, and the low bit is input for the second time.
  • the storage-computing integrated chip of the distributed control architecture of the embodiment of the present disclosure can be used in other electronic devices, such as artificial intelligence processors (AI processors), etc., which not only has versatility and flexibility, but also can achieve high computing power and high efficiency.
  • AI processors artificial intelligence processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Software Systems (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Evolutionary Biology (AREA)
  • Memory System (AREA)

Abstract

一种存算一体芯片及应用于该存算一体芯片的数据处理方法。该存算一体芯片包括：多个处理单元（101）以及主控单元（102）。每个处理单元（101）包括计算单元（103）以及控制单元（104）。计算单元（103）配置为存储参数矩阵、接收输入数据并采用参数矩阵对输入数据进行计算得到输出数据；控制单元（104）配置为与计算单元（103）相通信，且配置为将参数矩阵写入计算单元（103）得到配置后的计算单元（103），并且控制配置后的计算单元（103）对输入数据进行计算。主控单元（102）配置为与多个处理单元（101）通信，且根据整体参数集合将分别用于多个处理单元（101）的参数矩阵提供至多个处理单元各自的控制单元（104）。该存算一体芯片利用高效的分布式架构，在保证通用性和灵活性的同时，实现高算力和高能效。

Description

存算一体芯片及数据处理方法
本申请要求于2021年9月22日递交的中国专利申请第202111109178.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种存算一体芯片及应用于该存算一体芯片的数据处理方法。
背景技术
各种深度学习算法的识别率不断改善，随之而来的是数据量和运算量的指数级增长。基于忆阻器的存算一体技术有望突破经典计算系统的冯诺依曼架构的瓶颈，带来硬件算力、能效的爆发式增长，进一步促进人工智能的发展和落地，是最具潜力的下一代硬件芯片技术之一。基于忆阻器的存算一体系统凭借其高性能、低功耗的架构优势，有望成为突破冯诺依曼瓶颈的后摩尔时代智能计算的硬件载体。
发明内容
本公开至少一实施例提供一种分布式控制架构的存算一体芯片，包括：多个处理单元，每个处理单元包括：计算单元，配置为存储参数矩阵、接收输入数据并采用参数矩阵对输入数据进行计算得到输出数据；以及控制单元，配置为与计算单元相通信，且配置为将参数矩阵写入计算单元得到配置后的计算单元，并且控制配置后的计算单元采用参数矩阵对输入数据进行计算；以及主控单元，配置为与多个处理单元通信，且根据整体网络参数集合将分别用于多个处理单元的参数矩阵提供至多个处理单元各自的控制单元。
例如，本公开至少一实施例提供的存算一体芯片还包括：第一存储单元，配置为与多个处理单元通信以及与主控单元通信，存储整体输入数据和/或整体输出数据，在主控单元的控制下，向多个处理单元分别提供多个处理单元所需的输入数据，和/或，从多个处理单元分别接收多个处理单元产生的输出数 据，其中，整体输入数据包括用于多个计算单元的输入数据，整体输出数据包括多个计算单元的输出数据。
例如，本公开至少一实施例提供的存算一体芯片还包括：片上互连，配置为连接主控单元、第一存储单元、以及多个处理单元以进行通信。
例如，在本公开至少一实施例提供的存算一体芯片中，计算单元包括：至少一个忆阻器阵列，其中，该至少一个忆阻器阵列配置为存储参数矩阵且对输入数据进行计算。
例如，在本公开至少一实施例提供的存算一体芯片中，控制单元包括：参数配置单元，配置为将参数矩阵配置到计算单元中，和/或从计算单元获取计算单元当前具有的参数矩阵的值。
例如，在本公开至少一实施例提供的存算一体芯片中，控制单元还包括：读控制单元，配置为控制输入数据的读取以将输入数据提供到计算单元中；写控制单元，配置为控制输出数据的输出。
例如，在本公开至少一实施例提供的存算一体芯片中，每个处理单元还包括：功能单元，其中，该功能单元配置为对计算单元的计算结果进行处理以得到输出数据。
例如，在本公开至少一实施例提供的存算一体芯片中，功能单元包括：移位加法单元，配置为获取来自计算单元的计算结果，并对计算结果进行移位运算和加法运算；或激活单元，配置为对计算结果进行激活函数处理；或池化单元，配置为对计算结果进行池化处理。
例如，在本公开至少一实施例提供的存算一体芯片中，每个处理单元还包括：第二存储单元，配置为从第一存储单元获取输入数据或向第一存储单元发送输出数据；输入缓冲单元，配置为缓存输入数据；输出缓冲单元，配置为缓存输出数据。
例如，在本公开至少一实施例提供的存算一体芯片中，每个处理单元还包括：互连接口，配置为与主控单元以及第一存储单元通信。
本公开至少一实施例提供一种数据处理方法，应用于本公开至少一实施例提供的存算一体芯片，该数据处理方法包括：由主控单元接收整体网络参数集合，根据整体参数集合将分别用于多个处理单元的参数矩阵提供至多个处理单元各自的控制单元；多个处理单元各自的控制单元将接收的参数矩阵配置到多个处理单元各自的计算单元中；为多个处理单元提供输入数据；由多个 处理单元独立地根据接收的输入数据采用接收的参数矩阵对输入数据进行计算以得到输出数据。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A示出了矩阵向量乘法的示意图；
图1B为本公开至少一实施例提供的一种忆阻器阵列的示意性结构图；
图2A示出了以主控单元为中央调度单元的架构的控制流的示意图；
图2B示出了本公开至少一实施例提供的基于总线机制的分布式控制架构的示意图；
图2C示出了本公开至少一实施例提供的分布式控制架构的控制流的示意图；
图2D示出了在片上路由机制下传统的存算一体架构和本公开所提供的分布式控制架构的控制流的示意图；
图3A为本公开至少一实施例提供的一种分布式控制架构的存算一体芯片的示意图；
图3B示出了以忆阻器阵列输出8比特为例的功能单元的数据流的示意图；
图4示出了本公开至少一实施例提供的数据处理方法的流程图；
图5示出了本公开至少一实施例提供的存算一体芯片的工作流程图；
图6示出了一个示例性的读控制过程的流程图；以及
图7示出了将数据从第二存储单元读取到输入缓冲单元的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”：等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
忆阻器(例如，阻变存储器、相变存储器、导电桥存储器等)是一种可以通过施加外部激励，调节其电导状态的非易失型器件。忆阻器作为一种二端器件，具有电阻可调节且非挥发的特性，因此被广泛应用于存算一体技术。根据基尔霍夫电流定律和欧姆定律，由忆阻器构成的阵列可以并行的完成乘累加计算，且存储和计算都发生在忆阻器阵列的各个忆阻器中。基于这种计算架构，可以实现不需要大量数据搬移的存算一体计算。
目前，由忆阻器构成的交叉阵列可以并行完成矩阵矢量乘法操作，并广泛应用于加速神经网络算法中，因此存算一体芯片可以采用忆阻器阵列完成计算。现有的存算一体芯片往往是面向特定的神经网络进行定制化的架构设计，能对目标任务实现高效处理，但是由于没有高效的数据流控制单元，不能够同时有效处理多种算法模型。
图1A示出了矩阵向量乘法的示意图。如图1A所示，输入向量X(例如，包括图1A所示出的x 1、x 2、……、x m)和参数矩阵G(例如，包括图1A所示出的g 11、g 12、……、g 1m，……，g n1、g n2、……、g nm)相乘得到输出向量I(例如，包括图1A所示出的I 1、I 2、……、I n)。例如，I 1＝x 1g 11+x 2g 12+…+x mg 1m。
图1B为本公开至少一实施例提供的一种忆阻器阵列的示意性结构图。
如图1B所示，忆阻器阵列结构可以包括以阵列排布的多个忆阻器，将图1A所示的输入向量X(例如，输入向量可以为已编码幅值、宽度或脉冲个数的电压)提供至忆阻器阵列的输入端，将图1A所示的参数矩阵G编码为忆阻器电导值，利用高并行、低功耗的阵列读操作获得输出电流I，即，图1A 所示的输出向量I，可以实现深度学习中普遍的乘累加计算，进而对矩阵向量乘进行加速。
例如，根据基尔霍夫定律，忆阻器阵列结构的输出电流可以根据下述公式得出：I＝G×X。例如，I 1＝x 1g 11+x 2g 12+…+x mg 1m。上述乘累加计算过程利用物理定律实现，不同于布尔逻辑的数字电路实现方式，不需要频繁访存搬移权重数据，解决了经典计算系统的冯诺依曼瓶颈，可以实现高算力、高能效的智能计算任务。
图1B所示的忆阻器阵列中的阵列排布的忆阻器可以为1T1R结构或者2T2R结构，其中，1T1R结构的忆阻器单元包括一个开关晶体管和一个忆阻器，2T2R结构的忆阻器单元包括两个开关晶体管和两个忆阻器，本公开的实施例对采用的忆阻器的类型不作限定。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管(例如MOS场效应晶体管)或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。本公开的实施例对采用的晶体管的类型不作限定。
为实现通用性，可以采用基于主控单元的架构，主控单元作为中央调度单元，完成对多个计算单元的控制、配置和调度，而计算单元本身不具有调度功能。然而，在基于主控单元的架构中，主控单元和计算单元之间频繁的调度和数据交互会消耗大量的时间，导致计算效率低下。
图2A示出了以主控单元为中央调度单元的架构的控制流的示意图。
如图2A所示，在以主控单元102为中央调度单元的架构中，由主控单元102完成数据调度和任务分配，并由计算单元103完成计算。图2A中的虚线箭头表示该中央控制架构的控制流，控制流从主控单元102流经总线107到达计算单元103。在以数据为中心的神经网络算法中，主控单元102和计算单元103之间频繁的调度和数据交互会消耗大量的时间，导致计算效率低下。
本公开至少一实施例提供一种分布式控制架构的存算一体芯片。该存算一体芯片包括：多个处理单元，每个处理单元包括：计算单元，配置为存储参数矩阵、接收输入数据并采用参数矩阵对输入数据进行计算得到输出数据；以及控制单元，配置为与计算单元相通信，且配置为将参数矩阵写入计算单元得到配置后的计算单元，并且控制配置后的计算单元采用参数矩阵对输入数据进行计算；以及主控单元，配置为与多个处理单元通信，且根据整体网络参数 集合将分别用于多个处理单元的参数矩阵提供至多个处理单元各自的控制单元。
本公开至少一实施例还提供应用于上述存算一体芯片的数据处理方法。
本公开上述实施例提供的分布式控制架构的存算一体芯片能够利用高效的分布式架构，在保证通用性和灵活性的同时，实现高算力和高能效。
与采用中央控制架构的存算一体芯片相比，本公开实施例所提出的存算一体芯片采用分布式控制架构，即，在图2A所示的传统的计算单元103中集成本地的控制单元，从而组成一个处理单元，但是在本公开提出的分布式控制架构中，数据调度和任务分配的工作由本地的控制单元完成，通过并行的分布式调度和配置，大幅提高计算效率。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图2B示出了本公开至少一实施例提供的基于总线机制的分布式控制架构的示意图。
如图2B所示，主控单元102、第一存储单元106以及多个处理单元101通过总线107连接，通过在多个处理单元101内部集成控制单元104(参见图2C)，可以实现本地的控制和灵活的矩阵参数配置、数据流调度，将工作任务分布到每个处理单元101中执行，从而在兼顾了灵活性和通用性的同时，克服了图2A所示的中央控制架构的低效性。
图2C为图2B所示的分布式控制架构的控制流的示意图。
如图2C所示，每个处理单元101包括计算单元103和控制单元104，与图2A相比，计算单元103不由主控单元102直接进行数据调度和任务分配，而是由同一个处理单元中与其相对应的控制单元104进行数据调度和任务分配。虚线箭头表示控制流，在图2C的示例中，对于分布式控制架构，控制流在处理单元101内部，能够提高计算效率和能效。
实际上，多个处理单元101、主控单元102以及第一存储单元106之间除了通过总线进行通信之外，还可以基于其他片上互连机制进行通信。该片上互连机制包括开关网络、片上网络(片上路由)等方式，本公开的实施例对此不作限制。
图2D示出了在片上路由机制下，传统的存算一体架构和本公开所提供的分布式控制架构的控制流的示意图。图2D示出的片上路由系统中，多个处理 单元101、主控单元102以及第一存储单元106分别经过网络接口与网络节点处的特定的路由器相连，将这些单元之间的通信转换为路由器与路由器的通信。相比于其它片上系统的通信方式，片上路由机制不再受限于总线架构，因此可以扩展任意数量的路由节点。此外，在需要对片上路由系统的功能进行扩展时，只需要将设计好的功能模块通过网络接口接入，而无需重新设计网络的整体架构。对于传统的存算一体架构，控制流如标号为1的虚线箭头所示，控制流从主控单元102连接的路由节点经过多个处理单元101直到主控单元102需要控制的处理单元101。对于本公开所提供的分布式架构，控制流如标号为2的虚线箭头所示，控制流在处理单元101内部，从而避免了主控单元102和处理单元101之间频繁的调度和数据交互，提高了计算效率。
由于分布式控制架构的高效率，因此本公开提出了一种采用分布式控制架构的存算一体芯片，例如用于人工智能运算。
图3A为本公开至少一实施例提供的一种分布式控制架构的存算一体芯片100的示意图。
如图3A所示，存算一体芯片100用电路(数字电路以及模拟电路)实现，包括多个处理单元101(图中仅示出了一个处理单元)和主控单元102，每个处理单元101包括计算单元103和控制单元104。计算单元103被配置为存储参数矩阵、接收输入数据并采用参数矩阵对输入数据进行计算得到输出数据，控制单元104被配置为与计算单元103相通信，且配置为将参数矩阵写入计算单元103得到配置后的计算单元103，并且控制配置后的计算单元103采用参数矩阵对输入数据进行计算，主控单元102被配置为与多个处理单元101通信，且根据整体网络参数集合将分别用于多个处理单元101的参数矩阵提供至多个处理单元101各自的控制单元104。
根据本公开的至少一实施例，计算单元103包括至少一个忆阻器阵列105，至少一个忆阻器阵列105配置为存储参数矩阵且对输入数据进行计算。
例如，忆阻器阵列105的结构如图1B所示，参数矩阵例如为图1A所示的参数矩阵G，以电导的形式存储在计算单元103中的至少一个忆阻器阵列105中。计算单元103接收输入数据(例如，输入数据排列对应于如图1A所示的输入向量X)，采用参数矩阵对输入数据进行计算(例如，图1A所示的矩阵向量乘法运算)得到输出数据(例如，对应于图1A所示的输出向量I)。
在此实施例中，在计算单元103包括多个忆阻器阵列105的情形，每个 忆阻器阵列105的行列数量可以相同，然而，每个忆阻器阵列105的行和列的数量、忆阻器阵列105的数量均可以根据实际情况自由设计。由于忆阻器阵列中的计算是基于模拟电压和模拟电流实现的，而在芯片中数据的传输是以数字信号的形式传输的，因此一种实现方式是在忆阻器阵列的输入端和输出端分别引入数模转换器(DAC)和模数转换器(ADC)等外围电路；同时，为了节省功耗与面积开销，DAC和ADC可以采用分时复用的方式设计，本公开对DAC和ADC的要求与设计不做描述。
根据本公开的实施例，控制单元104包括参数配置单元1041，该参数配置单元1040被配置为将参数矩阵配置到计算单元103中，和/或根据需要从计算单元103获取计算单元103当前具有的参数矩阵的值，从而可以对存入的电导值进行校核。
例如，控制单元104基于参数矩阵的参数与计算单元103中的忆阻器阵列105的映射关系，将参数矩阵的参数与忆阻器阵列105对应的部分映射到忆阻器阵列105的多个忆阻器，从而实现将参数矩阵配置到计算单元103中。
例如，对于忆阻器阵列105，其中包含的忆阻器面临着可靠性问题，具有不可避免的波动、噪声和状态漂移等，从而造成计算误差，影响系统的正常功能。在使用忆阻器的电导值进行计算时，由于忆阻器的波动性等非理想特性，例如忆阻器随机涨落、弛豫特性、保持特性等，会造成实际的电导值偏离理想电导值，从而使得计算结果出现偏差。因此，需要参数配置单元1040从计算单元103中获取计算单元103当前具有的参数矩阵的值，并与实际需要配置的参数矩阵的值进行比较来校正计算单元103中的参数矩阵的值。
根据本公开的实施例，控制单元104还包括读控制单元1042和写控制单元1043，读控制单元1042被配置为控制输入数据的读取以将输入数据提供到计算单元103中，写控制单元1043被配置为控制输出数据的输出。例如，读控制单元1042读取输入数据的过程如图6所示，该读控制过程主要包含四部分：读地址更新、数据读取、输入缓冲单元填充、输入比特控制，具体的将在图6进行说明。
例如，在输入数据的读取和输出数据的输出过程中，均需要存储单元来存储数据。根据本公开的实施例，存算一体芯片100还包括第一存储单元106，该第一存储单元106配置为与多个处理单元101通信以及与主控单元102通信，存储整体输入数据和/或整体输出数据，在主控单元102的控制下，向多 个处理单元101分别提供多个处理单元101所需的输入数据，和/或，从多个处理单元101分别接收多个处理单元101产生的输出数据，其中，整体输入数据包括用于多个计算单元103的输入数据，整体输出数据包括多个计算单元103的输出数据。第一存储单元106可以是半导体存储装置，例如，非易失存储器等。
例如，第一存储单元106可以通过总线与多个处理单元101以及主控单元102连接以进行通信，根据本公开的实施例，存算一体芯片100还包括片上互连，例如总线107。总线是计算机各种功能部件之间传送信息的公共通信干线，它是由导线组成的传输线束，可以用于传输数据、数据地址和控制信号，本公开的实施例对其类型和实现方式不做限制。
根据本公开的实施例，每个处理单元101还包括互连接口，互连接口被配置为与主控单元102以及第一存储单元106通信。例如，连接在总线107上的多个处理单元101与总线107的连接电路称为总线接口，总线接口是多个处理单元101与主控单元102以及与第一存储单元106交换数据的接口；在其他片上互连类型中，互连接口则是其他类型的接口，用于进行数据、指令交互。
例如，整体输入数据是指多个处理单元101所需的输入数据的集合，整体输出数据是指多个处理单元101产生的输出数据的集合。多个处理单元101各自所需的输入数据以及各自产生的输出数据需要多个处理单元101内部的存储单元来存储。
根据本公开的实施例，每个处理单元101还包括第二存储单元109、输入缓冲单元110以及输出缓冲单元111，第二存储单元109被配置为从第一存储单元106获取输入数据或向第一存储单元106发送输出数据，输入缓冲单元110被配置为缓存输入数据，输出缓冲单元111被配置为缓存输出数据。第二存储单元109、输入缓冲单元110以及输出缓冲单元111的大小可以根据实际情况自行设定。
例如，在主控单元102的控制下，第一存储单元106将输入数据经由总线107提供至第二存储单元109，第二存储单元109可以为各种类型的存储装置，例如为双口SRAM(Static Random-Access Memory，静态随机存取存储器)，双口SRAM包含读端口和写端口，写端口为总线接口107，读端口与忆阻器阵列105的输入缓冲单元110相连。为了提高数据读效率，该SRAM的 读端口可以设置成较大位宽(例如，512比特)。输入缓冲单元110的作用是将第二存储单元109送来的数据暂时存放，输出缓冲单元111的作用是将忆阻器阵列105产生的输出数据暂时存放，从而可以起到协调缓冲的作用，实现数据传送的同步。
整体网络参数集合由主控单元进行处理，并分发到各个处理单元；整体网络参数集合例如是对应于某一神经网络的处理层的权重矩阵的全部或部分，将其拆分后得到用于各个处理单元的参数矩阵。
例如，整体网络参数集合例如包括网络层数、卷积核尺寸、网络类型等，主控单元102用于根据编译好的整体网络参数集合，将分别用于多个处理单元101的参数矩阵提供至多个处理单元101的控制单元104。下面的表1列出了一个示例性的具体的神经网络结构需要配置的网络参数及其含义。
表1
Figure PCTCN2021137844-appb-000001
这里，对表1中的一些网络参数的概念进行解释。
卷积神经网络是一类包含卷积计算且具有深度结构的前馈神经网络。卷积神经网络的结构主要包括输入层、隐含层和输出层，隐含层包含卷积层、池化层和全连接层3类常见构筑。卷积层的功能是对输入数据进行特征提取，其内部包含多个卷积核。在卷积神经网络的术语中，3*3的矩阵叫做“滤波器”，通过在图像上滑动滤波器并计算点乘得到的矩阵叫做“特征图”。对于同样的 输入图像，不同值的滤波器将会生成不同的特征图。在此实施例中，卷积层的数量即为忆阻器阵列的分组数量，每一组忆阻器阵列被映射一层卷积层对应的参数矩阵，每层卷积层用到的忆阻器阵列的数量的范围是0<＝i<NUM_LAYERS(NUM_LAYERS代表卷积层的数量)。
特征图的通道数用于表示图像的某种组成。例如，一个标准数字相机拍摄的图像会有三个通道(红、绿和蓝)，每个通道代表一个颜色，每个通道的像素值在0到255的范围内，可以把该图像的三个通道看作是堆在一起的深度为3的二维矩阵。
卷积层参数包括卷积核尺寸、卷积的步幅和填充，三者共同决定了卷积层的输出特征图的尺寸。卷积核的个数和输出特征图的通道数相同。卷积核尺寸可以被指定为小于输入图像尺寸的任意值，例如3，表示卷积核的高和宽均为3，卷积核尺寸越大，可提取的输入特征越复杂。卷积的步幅定义了卷积核相邻两次扫过特征图时的位置的距离，卷积的步幅为1时，卷积核会逐个扫过特征图的元素，卷积的步幅为n时，卷积核会在下一次扫描跳过n-1个像素。在卷积层进行特征提取后，输出的特征图会被传递至池化层进行特征选择和信息过滤，池化过程即为降采样过程，常见的池化模式包括最大值池化、平均值池化等。全连接层位于卷积神经网络隐含层的最后部分，全连接层的作用是对提取的特征进行非线性组合以得到输出。
根据本公开的实施例，每个处理单元101还包括功能单元108，功能单元108被配置为对计算单元103的计算结果进行处理以得到输出数据。
例如，功能单元108包括移位加法单元1081或激活单元1082或池化单元1083，移位加法单元1081被配置为获取来自计算单元103的计算结果，并对计算结果进行移位运算和加法运算，激活单元1082被配置为对计算结果进行激活函数处理，池化单元1083被配置为对计算结果进行池化处理。
例如，输入缓冲单元110中缓存的输入数据会提供至对应的忆阻器阵列105中进行计算，可以将输入数据分成两次提供至忆阻器阵列105中，第一次提供输入数据的高比特位，第二次提供输入数据的低比特位，这样设计的目的是为了保证计算的精度。例如，输入数据为8比特，则先将高4比特作为忆阻器阵列105的输入数据，再将低4比特作为忆阻器阵列105的输入数据。忆阻器阵列输出的两次计算结果分别对应高比特位输入数据的计算结果和低比特位输入数据的计算结果，然后需要通过移位加法单元1081对两次计算结 果进行移位加法，以将两次计算结果组合成完整的输出数据。
图3B示出了以忆阻器阵列输出8比特为例的功能单元的数据流的示意图。
如图3B所示，两次结果分别对应高低比特位输入数据的8比特有符号计算结果，将高比特位输入数据的计算结果左移4比特与低比特位输入数据的计算结果相加，得到13比特有符号的计算结果，该13比特的计算结果表示阵列的完整矩阵乘法结果。在此实施例中，一个卷积层对应一组忆阻器阵列，一组忆阻器阵列可以包含多个忆阻器阵列，将多个忆阻器阵列的矩阵乘法结果进行累加，得到该卷积层的最终计算结果。然后通过右移和Clip(将结果限制在一定范围内)等操作，将结果量化为9比特有符号的计算结果。接着进行激活函数处理，将结果变成8比特无符号的计算结果。最后进行池化处理，池化结果通过上述写控制单元被送至第一存储单元或第二存储单元。
激活函数和池化是神经网络中的概念。如果不引入激活函数，神经网络中的每一层输出都是上一层输入的线性函数，无论神经网络有多少层，输出都是输入的线性组合，容易验证。因此引入非线性函数作为激活函数，这样神经网络的输出不再是输入的线性组合，从而可以逼近任意函数。在此实施例中，激活单元1082对计算结果进行激活函数处理可以增加计算结果的非线性。池化过程即为降采样过程，常见的池化方法包括最大值池化、平均值池化等，池化单元1083对计算结果进行池化处理可以使神经网络中的参数和计算数量更加可控的减小，从而可以避免过拟合。
需要说明的是，图2中的功能单元108仅是示例性的，公开的实施例对于具体的实现不做限制，可以根据实际需要增加或减少所包含的移位加法单元1081、激活单元1082以及池化单元1083。功能单元108可以包括除了上述移位加法单元1081、激活单元1082以及池化单元1083以外的其它单元，或者仅包括移位加法单元1081、激活单元1082以及池化单元1083中的部分单元，或者不包括上述单元。
图4示出了本公开至少一实施例提供的数据处理方法的流程图，该数据处理方法应用于图3所示的存算一体芯片。
如图4所示，该数据处理方法包括步骤S411～S414。
步骤S411：由主控单元接收整体网络参数集合，根据整体网络参数集合将分别用于多个处理单元的参数矩阵提供至多个处理单元各自的控制单元。
例如，整体网络参数集合的内容可以参考表1所示的参数符号和参数含义。
步骤S412：多个处理单元各自的控制单元将接收的参数矩阵配置到多个处理单元各自的计算单元中。
例如，计算单元包括至少一个忆阻器阵列，控制单元基于参数矩阵的参数与计算单元中的忆阻器阵列的映射关系，将参数矩阵的参数与忆阻器阵列对应的部分映射到忆阻器阵列的多个忆阻器。
步骤S413：为多个处理单元提供输入数据。
例如，第一存储单元用于存储整体输入数据，在主控单元的控制下，多个处理单元各自所需的输入数据经由总线从第一存储单元提供至多个处理单元。
步骤S414：由多个处理单元独立地根据接收的输入数据采用接收的参数矩阵对输入数据进行计算以得到输出数据。
例如，在每个处理单元中，计算单元中包括的至少一个忆阻器阵列的结构如图1B所示，忆阻器阵列中存储有接收的参数矩阵，采用接收的参数矩阵对输入数据进行计算得到输出数据。
图5示出了本公开至少一实施例提供的存算一体芯片的工作流程图。
如图5所示，首先，存算一体芯片处于初始状态，判断整体网络参数集合是否已经被编译好，如果已经编译好，则由主控单元根据编译好的整体网络参数集合将分别用于多个处理单元的参数矩阵提供至多个处理单元各自的控制单元。
接着，由多个处理单元各自的控制单元将参数矩阵配置到多个处理单元各自的计算单元中。
接着，由多个处理单元各自的控制单元中的读控制单元进行读控制，从而将输入数据读取到多个处理单元各自的计算单元中的至少一个忆阻器阵列。
接着，由多个处理单元各自的计算单元中的至少一个忆阻器阵列对读取到的输入数据进行计算。
接着，将至少一个忆阻器阵列的计算结果提供到功能单元中进行计算，得到输出数据。
接着，由多个处理单元各自的控制单元中的写控制单元进行写控制。
例如，在写控制过程中，池化单元输出的前NUM_KERNELS(卷积核数量)个通道的数据会被存放到输出缓冲单元(其它通道的数据均是无效数据)， 然后通过总线接口写到第二存储单元或第一存储单元中。如果正在计算的是最后一层卷积层，则输出数据会被写到第一存储单元中，否则会被写到第二存储单元。
最后，判断是否是最后一层卷积层，如果是，则对存算一体芯片进行复位，否则继续对下一层卷积层进行读控制。
图6示出了一个示例性的读控制过程的流程图。如图6所示，该过程主要包含四个部分：读地址更新、数据读取、输入缓冲单元填充、输入比特控制，图6还展示了描述各部分的伪代码。
首先，多个处理单元各自的控制单元会给出输入数据的首地址(StartA)，并且每计算完一次完整的矩阵运算后，输入数据的首地址都会更新(伪代码中，SIZE_IMAGE表示输入图片的尺寸，K表示卷积核尺寸，STRIDE表示卷积的步幅，V表示图片的通道数，L＝V*SIZE_IMAGE，这些参数的含义已经在上文进行了说明)。而当一层卷积层全部计算完成后，便会开始下一层卷积层的读地址更新，此时以上提到的SIZE_IMAGE、K、STRDE、V和L等参数会更新为下一层卷积层对应的值。
接着，当读地址对应的第二存储单元中的ready信号有效时，便会开始执行数据读取。数据读取的过程如图7所示。
在图7中，输入数据(输入图片)按照一行一行(或者一列一列)连续地存储在第二存储单元109中，对于尺寸为K*K的卷积核，总共需要读取K笔数据(每笔数据的读取由数据首地址和数据长度表征)，一笔数据的长度为K*V(V对应输入图片的通道数)，每笔数据对应卷积核中每行的输入数据。
第二存储单元109被划分为许多单元(称为块)，对于写入第二存储单元109的数据，会计算写入的数据的字节数，当写入的数据的字节数等于块长度或者写入的数据为最后一笔数据时，该块的ready信号被置为有效，此时不再允许对该块进行写入操作。这样设计的目的是为了保证在控制单元的读控制过程中能够及时读取到有效数据，理论上第二存储单元109划分的单元长度越小越好(能够缩短取得有效数据的时间)，但是如此会增加第二存储单元109的面积和功耗，因此应当合理划分第二存储单元109的单元长度。
从第二存储单元109中读取数据时，控制单元会计算当前所需数据的首地址和末地址，然后查询首地址和末地址所对应的块的ready信号，当块的ready信号均为有效时执行数据读取操作，然后启动对应的忆阻器阵列的计算 操作。当第二存储单元109的某个块的数据在计算过程中不再使用时，控制单元发起该块的清除操作，并将该块的ready信号置为无效，此时该块允许写入新的数据。
回到图6，接着，对输入缓冲单元进行填充。每个忆阻器阵列都有相应的输入缓冲单元，K笔数据将会平均分配到该层卷积层计算所需的每个忆阻器阵列的输入缓冲单元中(伪代码中NUM_ARRAYS表示该层卷积层计算需要用到的忆阻器阵列的数量)。
最后，输入缓冲单元中的数据会提供至对应的忆阻器阵列中进行计算，数据可以分两次输入，第一次输入高比特位，第二次输入低比特位。
本公开实施例的分布式控制架构的存算一体芯片可以用于其他电子装置，例如人工智能处理器(AI处理器)等，不但具有通用性和灵活性，且同时能够实现高算力和高能效。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种分布式控制架构的存算一体芯片，包括：
    多个处理单元，每个处理单元包括：
    计算单元，配置为存储参数矩阵、接收输入数据并采用所述参数矩阵对所述输入数据进行计算得到输出数据；以及
    控制单元，配置为与所述计算单元相通信，且配置为将所述参数矩阵写入所述计算单元得到配置后的计算单元，并且控制所述配置后的计算单元采用所述参数矩阵对所述输入数据进行计算；以及
    主控单元，配置为与所述多个处理单元通信，且根据整体网络参数集合将分别用于所述多个处理单元的参数矩阵提供至所述多个处理单元各自的控制单元。
  2. 根据权利要求1所述的存算一体芯片，还包括：
    第一存储单元，配置为与所述多个处理单元通信以及与所述主控单元通信，存储整体输入数据和/或整体输出数据，在所述主控单元的控制下，向所述多个处理单元分别提供所述多个处理单元所需的输入数据，和/或，从所述多个处理单元分别接收所述多个处理单元产生的输出数据，
    其中，所述整体输入数据包括用于所述多个计算单元的输入数据，所述整体输出数据包括所述多个计算单元的输出数据。
  3. 根据权利要求2所述的存算一体芯片，还包括：
    片上互连，配置为连接所述主控单元、所述第一存储单元、以及所述多个处理单元以进行通信。
  4. 根据权利要求1-3任一项所述的存算一体芯片，其中，所述计算单元包括：
    至少一个忆阻器阵列，其中，所述至少一个忆阻器阵列配置为存储所述参数矩阵且对所述输入数据进行计算。
  5. 根据权利要求4所述的存算一体芯片，其中，所述控制单元包括：
    参数配置单元，配置为将所述参数矩阵配置到所述计算单元中，和/或从所述计算单元获取所述计算单元当前具有的参数矩阵的值。
  6. 根据权利要求5所述的存算一体芯片，其中，所述控制单元还包括：
    读控制单元，配置为控制所述输入数据的读取以将所述输入数据提供到 所述计算单元中；
    写控制单元，配置为控制所述输出数据的输出。
  7. 根据权利要求1-6任一所述的存算一体芯片，其中，每个所述处理单元还包括功能单元，
    其中，所述功能单元配置为对所述计算单元的计算结果进行处理以得到所述输出数据。
  8. 根据权利要求7所述的存算一体芯片，其中，所述功能单元包括：
    移位加法单元，配置为获取来自所述计算单元的计算结果，并对所述计算结果进行移位运算和加法运算；或
    激活单元，配置为对所述计算结果进行激活函数处理；或
    池化单元，配置为对所述计算结果进行池化处理。
  9. 根据权利要求2或3所述的存算一体芯片，其中，每个所述处理单元还包括：
    第二存储单元，配置为从所述第一存储单元获取所述输入数据或向所述第一存储单元发送所述输出数据；
    输入缓冲单元，配置为缓存所述输入数据；
    输出缓冲单元，配置为缓存所述输出数据。
  10. 根据权利要求2或3所述的存算一体芯片，其中，每个所述处理单元还包括：
    互连接口，配置为与所述主控单元以及所述第一存储单元通信。
  11. 一种数据处理方法，应用于权利要求1-10任一项所述的存算一体芯片，所述数据处理方法包括：
    由所述主控单元接收所述整体网络参数集合，根据所述整体参数集合将分别用于所述多个处理单元的参数矩阵提供至所述多个处理单元各自的控制单元；
    所述多个处理单元各自的控制单元将接收的参数矩阵配置到所述多个处理单元各自的计算单元中；
    为所述多个处理单元提供所述输入数据；
    由所述多个处理单元独立地根据接收的输入数据采用所述接收的参数矩阵对所述输入数据进行计算以得到所述输出数据。
PCT/CN2021/137844 2021-09-22 2021-12-14 存算一体芯片及数据处理方法 Ceased WO2023045114A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111109178.6 2021-09-22
CN202111109178.6A CN113792010A (zh) 2021-09-22 2021-09-22 存算一体芯片及数据处理方法

Publications (1)

Publication Number Publication Date
WO2023045114A1 true WO2023045114A1 (zh) 2023-03-30

Family

ID=79184048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/137844 Ceased WO2023045114A1 (zh) 2021-09-22 2021-12-14 存算一体芯片及数据处理方法

Country Status (2)

Country Link
CN (1) CN113792010A (zh)
WO (1) WO2023045114A1 (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116306855A (zh) * 2023-05-17 2023-06-23 之江实验室 一种基于存算一体系统的数据处理方法及装置
CN116562356A (zh) * 2023-05-31 2023-08-08 上海期智研究院 一种基于存算一体架构的安防方法、系统及设备
CN116737652A (zh) * 2023-06-27 2023-09-12 无锡中微亿芯有限公司 一种支持存算的fpga
CN117289896A (zh) * 2023-11-20 2023-12-26 之江实验室 一种存算一体基本运算装置
CN117472847A (zh) * 2023-11-08 2024-01-30 海光信息技术股份有限公司 存储芯粒、数据处理方法、计算机系统
CN117519802A (zh) * 2024-01-08 2024-02-06 之江实验室 基于存算一体单元的数据处理装置
CN117744731A (zh) * 2023-12-07 2024-03-22 之江实验室 一种基于阻变存储器的模型训练方法、装置、介质及设备
CN117973468A (zh) * 2024-01-05 2024-05-03 中科南京智能技术研究院 基于存算架构的神经网络推理方法及相关设备
CN118093504A (zh) * 2024-01-04 2024-05-28 浙江大学 一种基于NoC高效互联的存算FPGA
CN119440843A (zh) * 2024-11-05 2025-02-14 南京大学 一种针对交叉开关结构存算芯片的高并行度编程方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115221111A (zh) * 2022-07-13 2022-10-21 中国电信股份有限公司 处理器数据运算方法、处理器、设备及存储介质
CN115456155A (zh) * 2022-09-15 2022-12-09 浙江大学 一种多核存算处理器架构
CN115204380B (zh) * 2022-09-15 2022-12-27 之江实验室 存算一体卷积神经网络的数据存储及阵列映射方法与装置
CN115906735B (zh) * 2023-01-06 2023-05-05 上海后摩智能科技有限公司 基于模拟信号的多比特数存算一体电路、芯片及计算装置
CN116151343B (zh) * 2023-04-04 2023-09-05 荣耀终端有限公司 数据处理电路和电子设备
CN116881195B (zh) * 2023-09-04 2023-11-17 北京怀美科技有限公司 面向检测计算的芯片系统和面向检测计算的芯片方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110990060A (zh) * 2019-12-06 2020-04-10 北京瀚诺半导体科技有限公司 一种存算一体芯片的嵌入式处理器、指令集及数据处理方法
US20200342301A1 (en) * 2018-09-11 2020-10-29 Huazhong University Of Science And Technology Convolutional neural network on-chip learning system based on non-volatile memory
CN112825153A (zh) * 2019-11-20 2021-05-21 华为技术有限公司 神经网络系统中数据处理的方法、神经网络系统
CN112836814A (zh) * 2021-03-02 2021-05-25 清华大学 存算一体处理器、处理系统以及算法模型的部署方法
WO2021115262A1 (zh) * 2019-12-09 2021-06-17 南京惟心光电系统有限公司 脉冲卷积神经网络算法、集成电路、运算装置及存储介质
CN113077829A (zh) * 2021-04-20 2021-07-06 清华大学 基于忆阻器阵列的数据处理方法、电子装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200342301A1 (en) * 2018-09-11 2020-10-29 Huazhong University Of Science And Technology Convolutional neural network on-chip learning system based on non-volatile memory
CN112825153A (zh) * 2019-11-20 2021-05-21 华为技术有限公司 神经网络系统中数据处理的方法、神经网络系统
CN110990060A (zh) * 2019-12-06 2020-04-10 北京瀚诺半导体科技有限公司 一种存算一体芯片的嵌入式处理器、指令集及数据处理方法
WO2021115262A1 (zh) * 2019-12-09 2021-06-17 南京惟心光电系统有限公司 脉冲卷积神经网络算法、集成电路、运算装置及存储介质
CN112836814A (zh) * 2021-03-02 2021-05-25 清华大学 存算一体处理器、处理系统以及算法模型的部署方法
CN113077829A (zh) * 2021-04-20 2021-07-06 清华大学 基于忆阻器阵列的数据处理方法、电子装置

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116306855B (zh) * 2023-05-17 2023-09-01 之江实验室 一种基于存算一体系统的数据处理方法及装置
CN116306855A (zh) * 2023-05-17 2023-06-23 之江实验室 一种基于存算一体系统的数据处理方法及装置
CN116562356A (zh) * 2023-05-31 2023-08-08 上海期智研究院 一种基于存算一体架构的安防方法、系统及设备
CN116737652A (zh) * 2023-06-27 2023-09-12 无锡中微亿芯有限公司 一种支持存算的fpga
CN117472847A (zh) * 2023-11-08 2024-01-30 海光信息技术股份有限公司 存储芯粒、数据处理方法、计算机系统
CN117289896A (zh) * 2023-11-20 2023-12-26 之江实验室 一种存算一体基本运算装置
CN117289896B (zh) * 2023-11-20 2024-02-20 之江实验室 一种存算一体基本运算装置
CN117744731A (zh) * 2023-12-07 2024-03-22 之江实验室 一种基于阻变存储器的模型训练方法、装置、介质及设备
CN118093504A (zh) * 2024-01-04 2024-05-28 浙江大学 一种基于NoC高效互联的存算FPGA
CN117973468A (zh) * 2024-01-05 2024-05-03 中科南京智能技术研究院 基于存算架构的神经网络推理方法及相关设备
CN117519802A (zh) * 2024-01-08 2024-02-06 之江实验室 基于存算一体单元的数据处理装置
CN117519802B (zh) * 2024-01-08 2024-04-30 之江实验室 基于存算一体单元的数据处理装置
CN119440843A (zh) * 2024-11-05 2025-02-14 南京大学 一种针对交叉开关结构存算芯片的高并行度编程方法

Also Published As

Publication number Publication date
CN113792010A (zh) 2021-12-14

Similar Documents

Publication Publication Date Title
CN113792010A (zh) 存算一体芯片及数据处理方法
CN111052153B (zh) 使用半导体存储元件的神经网络运算电路及动作方法
CN110807519B (zh) 基于忆阻器的神经网络的并行加速方法及处理器、装置
CN109800876B (zh) 一种基于NOR Flash模块的神经网络的数据运算方法
US10248906B2 (en) Neuromorphic circuits for storing and generating connectivity information
CN110598858A (zh) 基于非易失性存内计算实现二值神经网络的芯片和方法
CN112825257A (zh) 用于在存储器阵列内执行视频处理矩阵运算的方法和设备
CN107533459A (zh) 使用电阻存储器阵列的数据处理
CN108053848A (zh) 电路结构及神经网络芯片
WO2022183759A1 (zh) 存算一体处理器、处理系统、处理装置以及算法模型的部署方法
CN114781631A (zh) 卷积层的映射方法及映射装置、卷积运算方法及运算装置
CN211016545U (zh) 基于NAND Flash的存内计算芯片、存储装置以及终端
CN115719088B (zh) 一种支持存内cnn的中间缓存调度电路装置
WO2021155851A1 (zh) 神经网络电路和神经网络系统
CN111428857A (zh) 一种基于忆阻器的卷积运算装置及方法
CN117521753A (zh) 神经网络处理装置、电子设备及操作方法
CN115831185A (zh) 存算一体芯片、操作方法、制作方法和电子设备
CN102150153B (zh) 具有基本处理器的数据处理电路,包括该电路的阵列的数据处理组件以及包括该组件的矩阵传感器
WO2007094133A1 (ja) 強誘電体キャパシタを用いた演算処理回路および演算方法
WO2022179075A1 (zh) 一种数据处理方法、装置、计算机设备及存储介质
CN113592081A (zh) 数据处理装置及数据处理方法
CN118734915A (zh) 一种基于忆阻器阵列的多神经网络系统及其构建方法
CN112396176A (zh) 一种硬件神经网络批归一化系统
CN117037877A (zh) 基于NOR Flash的存内计算芯片及其控制方法
WO2024130830A1 (zh) 数据处理装置、计算机系统及其操作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21958225

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21958225

Country of ref document: EP

Kind code of ref document: A1