WO2023042498A1 - 固体撮像素子、及び撮像装置 - Google Patents

固体撮像素子、及び撮像装置 Download PDF

Info

Publication number
WO2023042498A1
WO2023042498A1 PCT/JP2022/023223 JP2022023223W WO2023042498A1 WO 2023042498 A1 WO2023042498 A1 WO 2023042498A1 JP 2022023223 W JP2022023223 W JP 2022023223W WO 2023042498 A1 WO2023042498 A1 WO 2023042498A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoelectric conversion
imaging device
solid
pixel
state imaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/023223
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
靖久 栃木
勇佑 松村
文昭 佐野
克彦 半澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to JP2023548126A priority Critical patent/JPWO2023042498A1/ja
Priority to US18/690,390 priority patent/US20240380998A1/en
Publication of WO2023042498A1 publication Critical patent/WO2023042498A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics

Definitions

  • the present disclosure relates to solid-state imaging devices and imaging devices.
  • Processing of image data captured by a solid-state image sensor is generally performed by an external device to the solid-state image sensor. If the basic operation of image processing such as convolution operation is performed by the solid-state imaging device of the imaging device, the speed of cooperation with external equipment will be increased, and the user's convenience will be improved.
  • the present disclosure provides a solid-state imaging device and an imaging device that are capable of performing arithmetic processing while suppressing an increase in the size of the solid-state imaging device.
  • a plurality of pixel regions each composed of a plurality of pixels; a plurality of first charge storage units corresponding to each of the pixel regions; a plurality of first pixels in the pixel region, a photoelectric conversion unit; a photoelectric conversion portion of a pixel adjacent to at least one of the vertical and horizontal directions and a first element that is rendered conductive or non-conductive;
  • a second pixel in the pixel region is a photoelectric conversion unit; a first element that is in a conducting state or a non-conducting state with the photoelectric conversion portion of at least one of vertically and horizontally adjacent pixels;
  • a solid-state imaging device comprising a first storage element that is brought into a conducting state or a non-conducting state with the first storage section.
  • the photoelectric conversion of the photoelectric conversion unit may be started by setting the first element and the first storage element in the pixel region to a first non-conducting state.
  • the first element that is brought into a conductive state or a non-conductive state with the other photoelectric conversion units in the pixel region may be brought into the first conductive state.
  • the first storage element may be brought into the second conduction state after being brought into the first conduction state.
  • the first element After being brought into the first conduction state, the first element, which is brought into the conduction state or the non-conduction state with the other photoelectric conversion portions in the pixel region, is further brought into the second non-conduction state, and the first capacitor element is turned into the second non-conduction state.
  • a third conducting state may be used.
  • the charges accumulated by photoelectric conversion in each of the pixel regions may be transferred to the corresponding first storage units via the first elements.
  • the pixel may include a potential adjustment element connected between the photoelectric conversion unit and the first element, and the accumulated charge may be transferred by the potential adjustment element and the first element. .
  • the photoelectric conversion period of the photoelectric conversion unit may be controlled according to the weight value of the arithmetic processing.
  • the pixel further includes a second element for discharging accumulated charges of the photoelectric conversion unit, A non-discharge period of the accumulated charge by the second element may be controlled according to the weight value.
  • the pixel area may be changeable with respect to the corresponding first power storage unit.
  • the range of the pixel region with respect to the first power storage unit may be changed according to the calculation range of the calculation process.
  • the plurality of pixels are arranged in a matrix,
  • the first element makes the connection between the photoelectric conversion units adjacent in the first direction conductive or non-conductive, or makes the connection between the photoelectric conversion units adjacent in the second direction different from the first direction conductive. It may either be in a state or in a non-conducting state.
  • the first element may be a transfer transistor, one end of which is connected to the photoelectric conversion unit, and which is rendered conductive or non-conductive by a positive voltage control signal.
  • the photoelectric conversion section and the first element may be formed in different layers.
  • the first electricity storage section may be a floating diffusion section.
  • a sixth element for resetting the charge accumulated in the first electricity storage unit may be further provided.
  • a second accumulation unit for accumulating charges accumulated by photoelectric conversion in each pixel region; a seventh element electrically connecting the first electricity storage unit and the second storage unit; may be further provided.
  • an analog-to-digital converter that is electrically connected to the fifth element and that converts into digital data corresponding to accumulated electric charges by photoelectric conversion for each pixel region; You may also prepare.
  • each of the pixels constituting the pixel region receives light through one of a plurality of color filters; Before transferring the accumulated charges corresponding to a predetermined color filter out of the plurality of color filters to the first storage unit, the accumulated charges corresponding to other color filters out of the plurality of color filters are discharged.
  • the photoelectric conversion unit may be made of at least one of silicon, indium gallium arsenide, and organic germanium.
  • the first to sixth elements may be composed of at least one of silicon, an oxide semiconductor, and an organic semiconductor.
  • An accumulation control circuit may further be provided for controlling at least one of resetting of accumulated charges in each of the photoelectric conversion units, generation of accumulated charges according to weight values, the pixel region, and potential shape, according to arithmetic processing. .
  • a solid-state imaging device and an arithmetic processing unit capable of performing a convolution operation
  • An imaging device is provided in which the information on the pixel region corresponding to the weight value and the calculation range is supplied from the calculation processing unit.
  • first digital data generated by the analog-to-digital converter after the photoelectric conversion period of the photoelectric converter is controlled according to the positive weight value of the arithmetic processing and transferred to the first electricity storage unit;
  • the photoelectric conversion period of the photoelectric conversion unit is controlled according to the absolute value of the negative weight value of the arithmetic processing, and the second digital signal generated by the analog-to-digital conversion unit after being transferred to the first storage unit You may calculate the difference of data and.
  • FIG. 1 is a block diagram showing a configuration example of an imaging device according to an embodiment of the present technology
  • FIG. 2 is a block diagram showing a configuration example of a solid-state imaging device
  • FIG. 4 is a diagram schematically showing pixels arranged in a matrix in a pixel array section
  • FIG. 4 is a diagram showing a configuration example of a reading unit
  • FIG. 4 is a diagram showing a configuration example of a pixel array section
  • 4A and 4B are diagrams showing configurations of pixels
  • FIG. FIG. 2 is a circuit diagram showing a configuration example of a pixel circuit
  • FIG. 7 is a plan view of the light receiving chip of the pixel array section shown in FIG.
  • FIG. 2 is a plan view of a detection chip of a pixel circuit
  • FIG. 4 is a diagram schematically showing a cross section of a main part of a pixel array section
  • FIG. 4 is a diagram schematically showing a time when charge accumulation in a photoelectric conversion unit is completed
  • FIG. 4 is a diagram schematically showing a case where switching elements are in a connected state
  • FIG. 4 is a diagram schematically showing a state before charges are transferred to the floating diffusion
  • FIG. 4 is a diagram showing addition ranges for respective timings and corresponding floating diffusions
  • FIG. 5 is a diagram showing addition ranges for respective timings
  • FIG. 15 is a diagram showing addition ranges at different timings from FIG.
  • FIG. 14 is a timing chart showing an example of addition range processing at timing t1 in FIG. 13 ;
  • FIG. FIG. 15 is a timing chart showing a processing example of addition range 1 at timing t5 in FIG. 14;
  • FIG. FIG. 4 is a circuit diagram showing a configuration example of a pixel circuit according to a modification of the first embodiment;
  • FIG. 7 is a diagram showing a configuration example of a pixel array section according to the second embodiment;
  • FIG. 21 is a timing chart showing an example of addition processing in the pixel array unit of FIG. 20;
  • FIG. 21 is a plan view of the detection chip of the pixel array portion shown in FIG. 20;
  • FIG. 4 is a diagram schematically showing an example of transferring accumulated charge for each pixel to a floating diffusion
  • FIG. 11 is a diagram showing a configuration example of a pixel array section according to the third embodiment
  • FIG. 11 is a diagram showing a configuration example of a pixel according to the third embodiment
  • FIG. 4 is a diagram showing a charge accumulation state
  • FIG. 4 is a diagram schematically showing a case where a switching element is in a conductive state
  • FIG. 4 is a diagram schematically showing a case where a switching element is brought into a non-conducting state
  • FIG. 14 is a timing chart showing an example of addition range processing at timing t1 in FIG. 13 ;
  • FIG. 15 is a timing chart showing an example of addition range processing at timing t5 in FIG. 14 ;
  • FIG. 4A and 4B are diagrams schematically showing charge transfer operations of adjacent photoelectric conversion units;
  • FIG. 4 is a diagram schematically showing a case where a switching element is in a conductive state;
  • FIG. 4 is a diagram schematically showing a case where a switching element is brought into a non-conducting state;
  • 4A and 4B are diagrams schematically showing charge transfer operations of adjacent photoelectric conversion units;
  • FIG. FIG. 4 is a diagram schematically showing a case where a switching element is in a conductive state;
  • FIG. 4 is a diagram schematically showing a case where a switching element is brought into a non-conducting state;
  • FIG. 4 is a diagram schematically showing a case where a switching element is brought into a non-conducting state
  • FIG. 11 is a diagram showing a configuration example of a pixel array section according to a fourth embodiment
  • 32 is a timing chart showing an example of addition processing in the pixel array unit of FIG. 31; The figure which shows typically the example of a process with respect to the weight value of (1) Formula which concerns on 4th Embodiment.
  • FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to an embodiment of the present technology.
  • This imaging apparatus 100 includes an imaging lens 110 , a solid-state imaging device 200 , a recording section 120 , a control section 130 , an analysis section 140 , a communication section 150 and a speaker section 160 .
  • the imaging device 100 is, for example, a smart phone, a mobile phone, a PC (Personal Computer), or the like.
  • the imaging lens 110 collects incident light and guides it to the solid-state imaging device 200 .
  • the solid-state imaging device 200 has a plurality of gradation pixels.
  • the gradation pixel outputs a luminance signal corresponding to the amount of received light.
  • the solid-state imaging device 200 is capable of weighted addition of luminance signals of a plurality of pixels for gradation, for example.
  • the pixel for gradation may be called a pixel.
  • the solid-state imaging device 200 can perform predetermined signal processing such as weighted addition at the analog signal stage, and outputs the processed data to the recording unit 120 via the signal line 209 .
  • the recording unit 120 records data from the solid-state imaging device 200 and the like.
  • the control unit 130 controls the imaging device 100 as a whole.
  • the control unit 130 controls the solid-state imaging device 200 to capture image data.
  • the analysis unit 140 has an arithmetic processing unit 142 .
  • the arithmetic processing unit 142 can perform arithmetic processing such as convolution operation.
  • the analysis unit 140 performs predetermined analysis processing, image processing, and the like using the calculation result of the calculation processing unit 142, for example.
  • arithmetic processing such as convolution operation performed by the arithmetic processing unit 142 is performed by the solid-state imaging device 200 at the stage of the analog signal, and subsequent arithmetic processing is performed by the arithmetic processing unit 142 .
  • the communication unit 150 performs wireless communication with an external device. Thereby, content or the like is received from an external server and recorded in the recording unit 120 via the control unit 130 .
  • the control unit 130 causes the display unit 170 to display an image based on this content, for example.
  • the speaker unit 160 has a highly directional speaker and can transmit audio information only to the user.
  • the speaker unit 160 can change the direction in which sound is transmitted.
  • FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to the embodiment of the present technology.
  • This solid-state imaging device 200 includes a detection chip 202 and a light receiving chip 201 stacked on the detection chip 202 . These substrates are electrically connected through connections such as vias. In addition to vias, Cu--Cu bonding or bumps may be used for connection.
  • FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200.
  • the solid-state imaging device 200 includes a pixel array section 30, an accumulation control circuit 210, a first access control circuit 211a, a second access control circuit 211b, and a third access control circuit. 211 c , a reading unit 212 , a signal processing unit 213 , a second signal processing unit 214 , a timing control circuit 214 and an output interface 215 .
  • FIG. 4 is a diagram schematically showing pixels Pix arranged in a matrix in the pixel array section 30.
  • a plurality of pixels Pix are two-dimensionally arranged in a matrix (array).
  • one floating diffusion FD is arranged for a processing area Afd corresponding to a predetermined number of pixels Pix. Details of the pixel Pix, the processing area Afd, and the floating diffusion FD will be described later.
  • the pixel Pix is configured in the layer of the light receiving chip 201 .
  • elements such as switching elements TR1 to T3, switching elements TRG, RST, switching elements RST, AMP, SEL, and FG, which will be described later, are configured in the detection chip 202 .
  • the pixel array section 30 is, for example, a CMOS image sensor.
  • the processing area Afd corresponds to the addition range of the floating diffusion FD described later with reference to FIGS. 12 to 14.
  • FIG. This configuration example of the pixel array unit 30 is, for example, an example suitable for a 3 ⁇ 3 weighting filter, but is not limited to this.
  • the accumulation control circuit 210 controls the photoelectric conversion units of the pixels Pix. That is, the accumulation control circuit 210 can control the resetting of the accumulated charges of each of the plurality of photoelectric conversion units, the generation of accumulated charges according to the weight values, the potential shape of the photoelectric conversion units, and the like. Details of the photoelectric conversion unit will also be described later.
  • the first access control circuit 211a can perform control to sequentially move the accumulated charges accumulated in each of the plurality of pixels Pix row by row.
  • the second access control circuit 211b can perform control to sequentially move the accumulated charges accumulated in each of the plurality of pixels Pix column by column.
  • the third access control circuit 211c controls resetting of the accumulated charge of the floating diffusion FD, accumulation of the floating diffusion FD, and amplification of the luminance signal according to the accumulated charge of the floating diffusion FD. Details of control examples of the first access control circuit 211a, the second access control circuit 211b, and the third access control circuit 211c will also be described later.
  • FIG. 5 is a diagram showing a configuration example of the reading unit 212.
  • the reading unit 212 has a plurality of constant current sources 220 and a plurality of analog to digital conversion units ADC230.
  • the plurality of constant current sources 21 and the plurality of AD converters ADC230 are provided corresponding to the plurality of signal lines VSL.
  • the constant current source 21 One end of the constant current source 21 is connected to the corresponding signal line VSL, and the other end is grounded.
  • the constant current source 21 generates a current corresponding to the accumulated charge of the selected floating diffusion FD (see FIG. 4) as the image luminance signal Sig for the corresponding signal line VSL.
  • the AD conversion unit ADC230 is configured to perform AD conversion based on the signal Sig on the corresponding signal line VSL. That is, the AD conversion unit ADC230 converts the analog gradation luminance signal Sig supplied via the vertical signal line VSL into a digital signal by time division. The AD converter ADC230 supplies the generated digital signal to the signal processor 213 .
  • the signal processing section 213 performs predetermined signal processing on the digital signal from the reading section 212 .
  • the signal processing unit 213 supplies the data indicating the processing result and the detection signal to the recording unit 120 via the signal line 209 .
  • the timing control circuit 214 controls the timing of each component of the solid-state imaging device 200 based on the time stamp information.
  • the timing control circuit 212d performs the processes of the accumulation control circuit 210, the first access control circuit 211a, the second access control circuit 211b, the third access control circuit 211c, the reading unit 212, and the signal processing unit 213. Control timing.
  • the output interface 215 outputs image data, etc., which are digital signals supplied from the signal processing unit 213 , to the recording unit 120 .
  • FIG. 6 is a diagram showing a configuration example of the pixel array section 30. As shown in FIG. For example, it is a configuration example of 3 ⁇ 3 pixels Pix on the upper left of the FD in FIG.
  • FIG. 7 is a diagram showing a configuration example of a pixel Pix. As shown in FIG. 7, the pixel Pix has switching elements TR1 to TR3 and a photoelectric converter PD. As described above, the photoelectric conversion part PD, the floating diffusion FD, the switching elements TR1 to T3, and TRG are formed in the layer of the light receiving chip 201.
  • FIG. 6 is a diagram showing a configuration example of the pixel array section 30. As shown in FIG. For example, it is a configuration example of 3 ⁇ 3 pixels Pix on the upper left of the FD in FIG.
  • FIG. 7 is a diagram showing a configuration example of a pixel Pix. As shown in FIG. 7, the pixel Pix has switching elements TR1 to TR3 and a photoelectric converter PD. As described above, the photo
  • switching elements TRST, AMP, SEL, FG are formed in layers of the detection chip 202 .
  • the switching element TR2 of the pixel Pix on the 3rd row and the 3rd column according to the present embodiment corresponds to the storage element.
  • the accumulation control lines OFG1-9 connect between each pixel Pix and the accumulation control circuit 210 (see FIG. 3).
  • the horizontal control lines HSW1-HSW3 connect between the pixels Pix in each row and the first access control circuit 211a (see FIG. 3).
  • Pulsed control signals Hsw1-3 are supplied to the horizontal control lines HSW1-HSW3 from the first access control circuit 211a (see FIG. 3).
  • the vertical control lines VSW1-3 connect between the pixels Pix in each column and the second access control circuit 211b (see FIG. 3). Pulse-shaped control signals Vsw1-3 are supplied to the vertical control lines VSW1-3 from the second access control circuit 211b (see FIG. 3).
  • the switching elements TR1 of each row are connected in series to the control lines VT1-VT3.
  • the switching elements TR2 of each column are connected in series to the control lines VH1-VH3.
  • the switching elements TR1 to T3 are, for example, N-type MOS (Metal Oxide Semiconductor) transistors.
  • One end of the switching element TR1 is connected to the other end of the left adjacent switching element TR1 and one end of the left adjacent switching element TR2.
  • the other end of the switching element TR1 is connected to one end of the switching element TR1 on the right and one end of the switching element TR2.
  • the gate of the switching element TR1 is connected to the horizontal control line HSW.
  • the switching element TR1 is in a connected state (on) when the control signals Hsw1-Hsw3 supplied via the horizontal control lines HSW1-3 are high, and is in a non-connected state (off) when the control signals Hsw1-3 are low.
  • the switching element TR1 may be referred to as a horizontal transfer transistor.
  • the connected state (ON) of the switching element may be referred to as the conducting state, and the disconnected state (OFF) may be referred to as the non-conducting state.
  • One end of the switching element TR2 is connected to the other end of the upper adjacent switching element TR2 and the other end of the switching element TR1.
  • the other end of the switching element TR2 is connected to one end of the adjacent lower switching element TR2 and the other end of the adjacent lower switching element TR1.
  • the gate of the switching element TR2 is connected to the vertical control line VSW.
  • the switching element TR2 is in a connected state (on) when the control signals Vsw1-3 supplied via the horizontal control lines VSW1-3 are high, and is in a non-connected state (off) when the control signals Vsw1-3 are low.
  • the switching element TR2 may be referred to as a vertical transfer transistor.
  • One end of the switching element TR3 is connected to the power supply VDD, and the other end is connected to one end of the photoelectric conversion section PD. Also, the gate of the switching element TR3 is connected to the accumulation control line OFG. As a result, the switching element TR3 is in a connected state (on) when the control signal Ofg supplied via the accumulation control line OFG is high, and is in a non-connected state (off) when it is low. Note that the switching element TR3 may be referred to as an OFG transistor.
  • FIG. 8 is a circuit diagram showing a configuration example of the pixel circuit AFD.
  • the pixel circuit AFD has a control line TRGL, a control line RSTL, and a control line RSEL.
  • One ends of the control lines TRGL, RSTL, and RSEL are connected to the third access control circuit 211c (see FIG. 3).
  • a pulse-shaped control signal Trg is supplied to the control line TRGL from the third access control circuit 211c.
  • a pulse-shaped control signal Rst is supplied to the control line RSTL by the third access control circuit 211c.
  • a pulse-shaped control signal Sel is supplied to the control line SELL from the third access control circuit 211c.
  • the pixel circuit AFD has four switching elements TRG, RST, AMP, SEL and a floating diffusion FD.
  • the switching elements TRG, RST, AMP, and SEL are, for example, N-type MOS (Metal Oxide Semiconductor) transistors.
  • the floating diffusion FD is configured using, for example, a diffusion layer formed on the surface of the semiconductor substrate.
  • One end of the switching element TRG is connected to the signal line VH3, and the other end is connected to the floating diffusion FD. Also, the gate of the switching element TRG is connected to the control line TRGL. As a result, the switching element TRG is connected (on) when the control signal Trg supplied via the control line TRGL is high, and is disconnected (off) when it is low. Note that the switching element TRG may be referred to as a transfer transistor.
  • One end of the switching element RST is connected to the floating diffusion FD, and the other end is connected to the power supply voltage VDD. Also, the gate of the switching element RST is connected to the control line RSTL. As a result, the switching element RST is in a connected state (on) when the control signal Rst supplied via the control line RSTL is high, and is in a non-connected state (off) when it is low. Note that the switching element RST may be referred to as a reset transistor.
  • One end of the switching element AMP is connected to the power supply voltage VDD, and the other end is connected to one end of the switching element SEL. Also, the gate of the switching element AMP is connected to the floating diffusion FD. Thereby, the switching element AMP supplies a voltage signal corresponding to the accumulated charges of the floating diffusion FD to one end of the switching element SEL. Note that the switching element AMP may be referred to as an amplification transistor.
  • One end of the switching element SEL is connected to the other end of the switching element AMP, and the other end is connected to the signal line VSL. Also, the gate of the switching element SEL is connected to the control line RSEL. As a result, the switching element SEL is in a connected state (on) when the control signal Rsel supplied via the main line RSEL is high, and is in a non-connected state (off) when it is low. Note that the switching element SEL may be referred to as a route selection transistor.
  • the electric charge accumulated in the floating diffusion FD is discharged by turning on the switching element RST based on the control signal Rst, for example.
  • the switching element TRG is turned on based on the control signal Trg. Accumulate the transferred charge.
  • the pixel circuit AFD is electrically connected to the signal line VSL by turning on the switching element SEL based on the control signal Sel.
  • the switching element AMP is connected to the constant current source 220 (see FIG. 5) of the reading section 212 and operates as a so-called source follower.
  • a voltage corresponding to the voltage of the floating diffusion FD at that time is output to the ADC 230 as the image luminance signal Sig as described above.
  • FIG. 9 is a plan view of the light-receiving chip 201 of the pixel array section 30 shown in FIG. 6 as seen from the rear side.
  • the photoelectric conversion units PD of each pixel Pix are arranged in a two-dimensional array.
  • Switching elements TR1 to T3 are arranged around the photoelectric conversion part PD.
  • the other end of the switching element TR2 of the 3 ⁇ 3 pixels Pix on the upper left and the pixel Pix on the lower right of the drawing is connected to one end of the switching element TRG. That is, the accumulated charge accumulated in the photoelectric conversion unit PD of the pixel Pix on the lower right side of the drawing of the 3 ⁇ 3 pixels Pix is finally accumulated in the floating diffusion FD and read out as the image luminance signal Sig.
  • FIG. 10 is a plan view of the detection chip 202 of the pixel circuit AFD. As shown in FIG. 10, the detection chip 202 includes switching elements SEL, AMP, and RST.
  • FIG. 11 is a diagram schematically showing a cross section of a main part of the pixel array section 30.
  • a light receiving chip 201 corresponds to the semiconductor layer 100S
  • a detection chip 202 corresponds to the semiconductor layers 100T, 200T and 200S.
  • the semiconductor layers 100S and 100T are indicated by the substrate 201a
  • the semiconductor layers 200T and 200S are indicated by the substrate 201b.
  • the substrate 201a and the substrate 201b are electrically connected by, for example, through electrodes 120E and 121E.
  • the photoelectric conversion part PD, floating diffusion FD, and VSS contact region 118 have planar regions.
  • the photoelectric conversion part PD is composed of, for example, a p-well layer 115 and an n-type semiconductor region 114 .
  • the switching element TRG may be composed of a planar transistor.
  • a transfer gate TRG is provided on the surface of the semiconductor layer 100S.
  • the side surfaces of this transfer gate TG are covered with sidewalls SW.
  • the sidewall SW contains silicon nitride (SiN), for example.
  • a gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG.
  • the transfer gate TG of each pixel Pix is provided, for example, so as to surround the floating diffusion FD in plan view.
  • the semiconductor layer 100S is provided with a pixel separation section 117 that separates the pixels ix from each other.
  • the pixel separation portion 117 is formed extending in the normal direction of the semiconductor layer 100S (the direction perpendicular to the surface of the semiconductor layer 100S).
  • the pixel separation unit 117 is provided so as to separate the pixels Pix from each other, and has, for example, a grid-like planar shape (see FIG. 4).
  • the pixel separation unit 117 for example, electrically and optically separates the pixels Pix from each other.
  • the pixel separation section 117 includes, for example, a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A.
  • the insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. As shown in FIG.
  • the insulating film 117B is made of, for example, silicon oxide (SiO).
  • the pixel separation section 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation section 117 is not limited to the FTI structure penetrating the semiconductor layer 100S. For example, a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S may be used.
  • the pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.
  • a pinning region 116 is provided in the semiconductor layer 100S.
  • the pinning region 116 is provided on the side surface of the pixel isolation portion 117 , specifically between the pixel isolation portion 117 and the p-well layer 115 or the n-type semiconductor region 114 .
  • the pinning region 116 is composed of, for example, a p-type semiconductor region.
  • FIGS. 12A to 12C are diagrams schematically showing examples of the operation of each photoelectric conversion unit PD of the 3 ⁇ 3 pixel Pix (see FIGS. 6 and 9).
  • the photoelectric conversion units PD and PD33 are part of the photoelectric conversion units PD and PD33 in the 3 ⁇ 3 pixel Pix (see FIGS. 6 and 9).
  • the photoelectric conversion unit PD33 corresponds to the pixel Pix on the third row and third column in FIG. That is, the photoelectric conversion units PD and P33 are electrically connected via the switching element TR1 when horizontally adjacent, and electrically connected via the switching element TR2 when vertically adjacent. .
  • one end of the photoelectric conversion unit PD is connected to the other end of the switching element TR3, the other end of the switching element TR1, and one end of the switching element TR2.
  • the switching element TR3 is turned on, that is, the gate signal is set to high, a predetermined positive potential VDD is applied, the accumulated charges are discharged, and the initial reset is performed.
  • the photoelectric conversion unit may use materials such as silicon (Si), indium gallium arsenide (InGaAs), germanium (Ge) organic, and the like.
  • Silicon (Si), an oxide semiconductor, an organic semiconductor, or the like may be used as materials for elements such as the switching elements TR1 to TR3, the switching elements TRG, RST, AMP, SEL, and FG.
  • the switching element TR3 is turned off, that is, the gate signal is set to low, the photoelectric conversion portion PD starts accumulating charges by photoelectric conversion.
  • FIG. 12A is a diagram schematically showing the completion of charge accumulation in the photoelectric conversion units PD 33.
  • the switching elements TR1, TR2 and TRG are rendered non-conductive, ie the gate signal is low.
  • the light transmitted through all the photoelectric conversion units PD of the 3 ⁇ 3 pixels Pix generates photocharges. This photocharge is accumulated by a well-shaped positive potential.
  • the accumulation time of the 3 ⁇ 3 pixels Pix is set based on the weight value w ij in equation (1) and based on the control signal from the arithmetic processing unit 142 . That is, as the weight value wij increases, the accumulated charge amount increases.
  • FIG. 12B is a diagram schematically showing the case where the switching elements TR1 and TR2 are connected.
  • the switching elements TR1 and TR are made conductive, that is, the gate signals of the switching elements TR1 and TR are made high.
  • the charges accumulated in the 3 ⁇ 3 pixels Pix are averaged, and become, for example, a value proportional to the image luminance signal Sigij of the formula (1) described later.
  • FIG. 12C is a diagram schematically showing the state before charges are transferred to the floating diffusion FD.
  • the switching elements TR1 and TR2 connected to the photoelectric conversion section PD33 are made non-conductive, that is, the gate signals of the switching elements TR1 and TR2 are set to low.
  • the charge accumulated in the photoelectric conversion unit PD33 becomes a value proportional to, for example, the image luminance signal Sigij in equation (1) described later.
  • the gate signal of the switching element TRG is made low.
  • the charges accumulated in the photoelectric conversion unit PD33 are transferred to the loading diffusion FD.
  • the photoelectric conversion section PD33 is separated by the switching elements TR1 and TR which are made non-conductive, the charge limited to 1/9 is transferred to the floating diffusion FD. This prevents the floating diffusion FD from overflowing.
  • the switching elements TR1 and TR connected to the photoelectric conversion unit PD33 are rendered non-conductive as the state before the charge is transferred to the floating diffusion FD, but the present invention is not limited to this.
  • the switching elements switching elements TR1 and TR2 connected to the photoelectric conversion unit PD33 may be maintained in a conductive state. In this case, all accumulated charges can be transferred to the floating diffusion FD.
  • FIG. 13 to 15 are diagrams exemplifying the range of calculation processing of weighting calculation.
  • FIG. 13 is a diagram showing addition ranges A11 to A22 at timings t1 to t3 and corresponding floating diffusions FD11 to FD22.
  • FIG. 14 shows addition ranges at timings t4 to t6
  • FIG. 15 shows addition ranges at timings t7 to t9. 13 to 15, the addition ranges A11 to A22 and the corresponding floating diffusions FD11 to FD22 relatively indicate arbitrary regions of the pixel array section 30.
  • FIG. 13 to 15 are diagrams exemplifying the range of calculation processing of weighting calculation.
  • FIG. 13 is a diagram showing addition ranges A11 to A22 at timings t1 to t3 and corresponding floating diffusions FD11 to FD22.
  • FIG. 14 shows addition ranges at timings t4 to t6
  • FIG. 15 shows addition ranges at timings t7 to t9. 13 to 15, the addition ranges
  • the addition range of the floating diffusion FD11 is the addition range A11
  • the addition range of the floating diffusion FD12 is the addition range A12
  • the addition range of the floating diffusion FD21 is the addition range A21
  • the addition range of the floating diffusion FD22 is the addition range A22.
  • Other floating diffusions FDn also have addition ranges An. That is, in the addition range A11 to A22 of 3 ⁇ 3, the addition range overlaps as shown in equation (1), so nine addition processes are performed in the imaging element 200 at timings t1 to t9. That is, nine images are captured at timings t1 to t9.
  • FIG. 16 is a diagram showing an example of 3 ⁇ 3 weight values w ij in equation (1).
  • equation (1) is an example of addition processing used in the processing of the arithmetic processing unit 142 (see FIG. 1).
  • the arithmetic processing unit 142 supplies, for example, the weight value wij information of the equation (1) to the accumulation control circuit 210 (see FIG. 3) via the control unit 130 .
  • the weight value wij may be referred to as a filter value, and the addition range may be referred to as a filter.
  • the image luminance signal Sigij is calculated by adding the weight value wij to the luminance value pij .
  • i, j indicate the position of the pixel Pix in the pixel array. That is, i indicates the position in the horizontal direction in the pixel array section 30, and j indicates the position in the vertical direction.
  • the luminance value p ij corresponds to the charge accumulated in the photoelectric conversion unit PD in the pixel range Pix at positions i and j.
  • the addition range A11 in FIGS. 13 to 15 shows an example of the addition range in which the brightness value p ij of the equation (1) is included in the addition process.
  • the charge proportional to the charge accumulated in the 3 ⁇ 3 photoelectric conversion units PD in the addition range A11 is finally accumulated in the floating diffusion FD11.
  • the charges proportional to the charges accumulated in the 3 ⁇ 3 photoelectric conversion units PD in the addition range A12 are finally accumulated in the floating diffusion FD12.
  • the charge proportional to the charge accumulated in the 3 ⁇ 3 photoelectric conversion units PD in the addition range A21 is finally accumulated in the floating diffusion FD11.
  • the charge proportional to the charge accumulated in the 3 ⁇ 3 photoelectric conversion units PD in the addition range A22 is finally accumulated in the floating diffusion FD22.
  • the addition range A11 to A22 shifts to the right by one pixel range
  • the addition range A11 to A22 further shifts to the right by one pixel range.
  • the addition range A11 to A22 shifts downward by one pixel range from the position at timing t1, and at timing t5, the addition range A11 to A22 further shifts to the right by one pixel.
  • the addition range A11 to A22 is further shifted to the right by one pixel range. As shown in FIG.
  • the addition range A11 to A22 shifts downward by one pixel range from timing t4, and at timing t5, the addition range A11 to A22 further shifts to the right by one pixel.
  • the addition range A11 to A22 is further shifted to the right by one pixel range. In this way, in the calculation process of the weighting calculation shown in the formula (1), for example, the addition process is performed while changing the addition range A11 to A22 nine times.
  • the accumulation control circuit 210 supplies signals Ofg1 to OfgH*V having time information proportional to the weight value wij to each pixel Pix. Then, the photoelectric conversion unit PD of each pixel Pix performs photoelectric conversion based on the signals Ofg1 to OfgH*V for a time proportional to the weight value wij to accumulate electric charge. That is, in the present embodiment, a calculation corresponding to the weight value wij is performed by performing photoelectric conversion for a time proportional to the weight value wij . Then, finally, one-ninth of the charge accumulated in each pixel Pix is transferred to the floating diffusion FD.
  • FIG. 17 is a timing chart showing a processing example of the addition range A11 at timing t1 in FIG. A processing example of the addition range A11 will be described based on FIG. 17 while referring to FIGS.
  • the vertical axis indicates any two signals Ofg * , signals Vsw1, Vsw2, Hsw1, Hsw2, Rst, and Trg in order from the top.
  • the horizontal axis indicates time.
  • a high level signal of the signal Ofg * renders the switching element TR3 of the pixel Pix * conductive, discharging the charge in the photoelectric conversion unit PD to the power supply VDD for initialization.
  • the photoelectric conversion unit PD accumulates charges according to the amount of received light for a time proportional to the weight value wij .
  • the other pixels Pix * accumulate charges according to the amount of received light for a period of time proportional to the weight value wij .
  • the switching element TR2 between the pixels Pix in the first row and the second row becomes conductive.
  • the switching element TR2 between the pixels Pix on the second and third rows becomes conductive.
  • the switching element TR1 between the pixels Pix on the first and second columns becomes conductive.
  • the switching element TR1 between the pixels Pix on the second and third columns becomes conductive.
  • the switching element RST becomes conductive, and the charges in the floating diffusion FD are discharged.
  • the switching element RST becomes non-conductive.
  • the switching element TRG becomes conductive, and at the same time, the switching element TR2 of the pixel Pix on the third row and third column becomes conductive.
  • all the charges accumulated in the photoelectric conversion unit PD on the third row and the third column are transferred to the floating diffusion FD.
  • Similar driving is simultaneously performed in the other addition ranges A12 to An, and charges corresponding to the addition ranges A12 to An are accumulated in each floating diffusion FD.
  • the charges of the floating diffusion FD connected to the same VSl line are sequentially amplified and converted into digital luminance signals in a time-division manner.
  • FIG. 18 is a timing chart showing a processing example of the addition range A11 at timing t5 in FIG.
  • the example of timing t5 differs from the example of processing of addition range A11 at timing t1 due to the difference in the relative position of floating diffusion FD within addition range A11. That is, at the timing when the signals Vsw2, Vsw3, Hsw2, and Hsw3 become high, the switching element TR2 between the pixels Pix in the second row and the third row becomes conductive. Similarly, the switching element TR2 between the pixels Pix on the third and fourth rows is turned on. Similarly, the switching element TR1 between the pixels Pix on the second and third columns becomes conductive. Similarly, the switching element TR1 between the pixels Pix in the third and fourth columns becomes conductive.
  • the arithmetic processing unit 142 acquires the image luminance signal Sigij of, for example, equation (1) calculated in the entire pixel range of the pixel array unit 30, and can perform subsequent image processing. Repeated calculations, such as weighted addition, which require a relatively large calculation load, are performed by the solid-state imaging device 200 in the process of transferring accumulated charges, so that the processing speed of the calculation processing unit 142 can be increased. .
  • the photoelectric conversion unit PD of each pixel Pix can A charge is accumulated by photoelectric conversion.
  • a weighting operation for example, equation (1)
  • the accumulated charges can be transferred between the pixels Pix, it is possible to change the position of the addition range A11 without providing only one floating diffusion FD corresponding to the addition range A11.
  • the floating diffusion FD It becomes possible to cope without increasing the number. As a result, an increase in the size of the arithmetic element 200 can be suppressed.
  • the imaging device 100 according to the modification of the first embodiment differs from the imaging device 100 according to the first embodiment in that the pixel circuit AFD further includes a floating diffusion FD2 and the capacitance of the floating diffusion FD can be switched. Differences from the imaging apparatus 100 according to the first embodiment will be described below.
  • FIG. 19 is a circuit diagram showing a configuration example of a pixel circuit AFD according to a modification of the first embodiment.
  • the pixel circuit AFD further has a floating diffusion FD2, a control line FGL, and a switching element FG.
  • One end of the control line FGL is connected to the third access control circuit 211c (see FIG. 3).
  • a control signal Fg is supplied to the control line TRGL from the third access control circuit 211c.
  • the switching element FG is, for example, an N-type MOS (Metal Oxide Semiconductor) transistor.
  • One end of the switching element RST is connected to the floating diffusion FD2, and the other end is connected to the power supply voltage VDD.
  • One end of the switching element FG is connected to the floating diffusion FD, and the other end is connected to the floating diffusion FD2. Also, the gate of the switching element FG is connected to the control line FGL.
  • the switching element FG and the switching element RST are brought into conduction based on the control signals Fg and Rst. Thereby, the charges accumulated in the floating diffusion FD and the floating diffusion FD2 are discharged. Next, based on the control signal Rst, the switching element RST is turned off. As a result, after the exposure period T ends, the switching element TRG becomes conductive based on the control signal Trg. Accumulate the transferred charge.
  • the pixel circuit AFD is electrically connected to the signal line VSL by turning on the switching element SEL based on the control signal Sel.
  • the switching element AMP is connected to the constant current source 220 (see FIG. 5) of the reading section 212 and operates as a so-called source follower.
  • a voltage corresponding to the voltages of the floating diffusion FD and the floating diffusion FD2 at that time is output to the ADC 230 as the image luminance signal Sig as described above.
  • the switching element FG and the switching element RST are brought into conduction based on the control signals Fg and Rst. Thereby, the charges accumulated in the floating diffusion FD and the floating diffusion FD2 are discharged. Next, the switching element FG is turned off based on the control signal Fgt. As a result, after the exposure period T ends, the switching element TRG becomes conductive based on the control signal Trg. accumulate. After that, the same processing as described above is performed.
  • the pixel circuit AFD further includes the floating diffusion FD2.
  • the capacity of the floating diffusion FD can be changed according to the amount of light received by the solid-state imaging device 200, and the imaging sensitivity and the storage charge capacity can be adjusted.
  • the image pickup apparatus 100 according to the second embodiment differs from the image pickup apparatus 100 according to the first embodiment in that the pixel circuits AFD perform initialization processing of the pixels Pix connected to the pixel circuits AFD. Differences from the imaging apparatus 100 according to the first embodiment will be described below.
  • FIG. 20 is a diagram showing a configuration example of the pixel array section 30 according to the second embodiment. As shown in FIG. 19, the third-row, third-column photoelectric conversion unit PD33 does not have a reset switching element TR3, which is different from the configuration example of the pixel array unit 30 shown in FIG.
  • FIG. 21 is a timing chart showing an addition processing example in the pixel array section 30 of FIG. Accumulation of the photoelectric conversion unit PD and charge transfer are performed in the same manner as in FIGS. In this case, the reset driving of the photoelectric conversion unit PD33 is different from the processing in FIGS. 17, 17, and the like.
  • the switching element TR2 of the pixel Pix on the third row and the third column is turned on, and at the same time, the control signals Rst and Trg are set to high level to turn on the switching elements RST and TRG.
  • the charge accumulated in the photoelectric conversion unit PD33 is discharged via the switching elements RST and TRG.
  • the switching elements RST and TRG are rendered non-conductive, and the switching element TR2 is rendered non-conductive.
  • the pixel circuit AFD discharges the charge of the photoelectric conversion unit PD33 on the third row and the third column, thereby enabling initialization.
  • FIG. 22 is a plan view of the detection chip 202 of the pixel array section 30 shown in FIG. As shown in FIG. 22, since the photoelectric conversion unit PD33 on the third row and third column does not have the switching element TR3 for resetting, the switching element TRG of the pixel circuit AFD and the floating diffusion FD are arranged on the switching element TR3 side. It becomes possible. This makes it possible to further widen the aperture of the photoelectric conversion unit PD33 on the third row and third column.
  • the pixel circuit AFD performs initialization processing of the pixel Pix connected to the pixel circuit AFD.
  • the pixel array section 30 can be configured without providing the switching element TR3 of the pixel Pix, the imaging element 200 can be made more compact, and the aperture of the photoelectric conversion section PD33 on the third row and third column can be further widened.
  • the switching elements TR1 and TR2 are connected, and the charges accumulated in the 3 ⁇ 3 pixels Pix are averaged and transferred to the floating diffusion FD.
  • the imaging device 100 is different in that charges accumulated in 3 ⁇ 3 pixels Pix are sequentially added for each row or column. Differences from the imaging apparatus 100 according to the first embodiment will be described below.
  • FIG. 23 is a diagram schematically showing a processing example of transferring accumulated charges for each pixel Pix to the floating diffusion FD according to the third embodiment.
  • FIG. 23 shows an imaging example of the addition range H*V at timing tn.
  • the accumulation control circuit 210 supplies signals Ofg1 to OfgH*V having time information proportional to the weight value wij to each pixel Pix.
  • the photoelectric conversion unit PD of each pixel Pix performs photoelectric conversion based on the signals Ofg1 to OfgH*V for a time proportional to the weight value wij to accumulate electric charge.
  • a calculation corresponding to the weight value wij is performed by performing photoelectric conversion for a time proportional to the weight value wij . Then, according to the control of the accumulation control circuit 210, the first access control circuit 211a, the second access control circuit 211b, and the third access control circuit 211c, the accumulated charge is transferred between the photoelectric conversion units PD of each pixel Pix. Transfer in order. As a result, the accumulated charge for each pixel Pix is finally transferred to the floating diffusion FD.
  • FIG. 24 is a diagram showing a configuration example of the pixel array section 30 according to the third embodiment. For example, it is a configuration example of 3 ⁇ 3 pixels Pix on the upper left of the FD in FIG.
  • FIG. 25 is a diagram showing a configuration example of a pixel Pix according to the third embodiment. As shown in FIG. 25, the pixel Pix has switching elements TR1 to TR3 and a photoelectric converter PD. A potential control line CONT (hereinafter sometimes referred to as COT) is connected to the photoelectric conversion unit PD.
  • CONT potential control line CONT
  • the accumulation control lines OFG1-9 connect between each pixel Pix and the accumulation control circuit 210 (see FIG. 3).
  • potential control lines COT1-COT3 connect between each pixel Pix and the accumulation control circuit 210 (see FIG. 3). Since the subsequent connection relationship is the same as in FIG. 6, the explanation is omitted.
  • 26A to 26C are diagrams schematically showing a configuration example and an operation example of the photoelectric conversion unit PD in chronological order.
  • the photoelectric conversion unit PD according to this embodiment is a photoelectric conversion unit capable of changing the positive potential shape.
  • FIG. 26A is a diagram showing a charge accumulation state.
  • FIG. 26A schematically shows adjacent pixels PD11 and PD12.
  • the switching elements TR1 and TR2 are made non-conductive, that is, the gate signal is made low.
  • a voltage corresponding to, for example, the transfer order is applied in advance to the terminal PDT from the potential control line COT. This forms a step in the well-shaped positive potential.
  • control is performed to transfer charges from the pixel PD11 side to the pixel PD12 side, so the potential on the pixel PD12 side is deeper toward the positive potential side than on the pixel PD11 side.
  • the light transmitted through the photoelectric conversion part PD generates photocharges. This photocharge is accumulated by a well-shaped positive potential.
  • FIG. 26B is a diagram schematically showing the case where the switching elements TR1 and TR2 are brought into a conducting state. As shown in FIG. 26B, the switching elements TR1 and TR2 are made conductive, ie the gate signal is made high. As a result, the charge accumulated in the photoelectric conversion unit PD11 is transferred to the photoelectric conversion unit PD12 on the deeper side (larger side) of the positive potential potential.
  • FIG. 26C is a diagram schematically showing the case where the switching elements TR1 and TR2 are brought into a non-conducting state. Next, as shown in FIG. 26C, the switching elements TR1 and TR2 are rendered non-conductive to end charge transfer. Charges are transferred between pixels by repeating the process as shown in FIGS. 26B and 26C.
  • FIG. 27 is a timing chart showing a processing example of the addition range A11 at timing t1 in FIG. A processing example of the addition range A11 will be described based on FIG. 27 while referring to FIGS.
  • the vertical axis indicates any two signals Ofg * , signals Vsw1, Vsw2, Hsw1, Hsw2, Rst, and Trg in order from the top.
  • the horizontal axis indicates time.
  • a high level signal of the signal Ofg * renders the switching element TR3 of the pixel Pix * conductive, discharging the charge in the photoelectric conversion unit PD to the power supply VDD for initialization.
  • a predetermined bias voltage is applied to the photoelectric conversion unit PD via the signal line CONT, and a charge corresponding to the amount of received light is generated for a time proportional to the weight value wij .
  • the other pixels Pix * accumulate charges according to the amount of received light for a period of time proportional to the weight value wij .
  • the switching element TR2 between the pixels Pix on the first and second rows is turned on.
  • the bias voltage of the photoelectric conversion units PD in the second row is set higher than the bias voltage of the photoelectric conversion units PD in the first row.
  • the charges accumulated in the photoelectric conversion units PD in the pixels Pix on the first row are transferred to the photoelectric conversion units PD in the pixels Pix on the second row.
  • the switching element TR2 becomes non-conductive again.
  • the switching element TR2 between the pixels Pix on the second and third rows becomes conductive.
  • the bias voltage of the photoelectric conversion unit PD in the third row is set higher than the bias voltage of the photoelectric conversion unit PD in the second row.
  • the charges accumulated in the photoelectric conversion units PD in the pixels Pix on the second row are transferred to the photoelectric conversion units PD in the pixels Pix on the third row.
  • the switching element TR2 becomes non-conductive again.
  • the switching element TR1 between the pixels Pix on the first and second columns is turned on.
  • the bias voltage of the photoelectric conversion units PD in the second column is set higher than the bias voltage of the photoelectric conversion units PD in the first column.
  • the charges accumulated in the photoelectric conversion units PD in the pixels Pix in the first column are transferred to the photoelectric conversion units PD in the pixels Pix in the second column.
  • the switching element TR1 becomes non-conductive again.
  • the switching element TR1 between the pixels Pix on the second and third columns is turned on.
  • the bias voltage of the photoelectric conversion units PD in the third column is set higher than the bias voltage of the photoelectric conversion units PD in the second column.
  • the charges accumulated in the photoelectric conversion units PD in the pixels Pix on the second column are transferred to the photoelectric conversion units PD in the pixels Pix on the third column.
  • the switching element TR1 becomes non-conductive again.
  • the switching element RST becomes conductive, and the charges in the floating diffusion FD are discharged.
  • the switching element RST becomes non-conductive.
  • the switching element TRG becomes conductive, and at the same time, the switching element TR2 of the pixel Pix on the third row and third column becomes conductive.
  • the bias voltage of the floating diffusion FD is made higher than the bias voltage of the photoelectric conversion unit PD in the pixel Pix on the third row and the third column.
  • the charge of the photoelectric conversion unit PD in the pixel Pix on the third row and column is transferred to the floating diffusion FD.
  • Similar driving is simultaneously performed in the other addition ranges A12 to An, and charges corresponding to the addition ranges A12 to An are accumulated in each floating diffusion FD.
  • the charges of the floating diffusion FD connected to the same VSl line are sequentially amplified and converted into digital luminance signals in a time-division manner.
  • FIG. 28 is a timing chart showing a processing example of the addition range A11 at timing t5 in FIG.
  • the example of timing t5 is different from the example of processing of addition range A11 at timing t1 due to the difference in the relative position of floating diffusion FD in addition range A11. That is, the accumulated charges of the photoelectric conversion units PD in the pixels Pix on the second row in the addition range A11 are transferred to the photoelectric conversion units PD in the pixels Pix on the third row, and then the pixels Pix on the third row in the addition range A11 is transferred to the photoelectric conversion unit PD in the pixel Pix on the second row.
  • the accumulated charges of the photoelectric conversion units PD in the pixels Pix on the second column in the addition range A11 are transferred to the photoelectric conversion units PD in the pixels Pix on the third column, and then the pixels Pix on the third column in the addition range A11. is transferred to the photoelectric conversion unit PD in the pixel Pix on the second column.
  • the rest is the same as the processing example of the addition range A11 at timing t1.
  • the arithmetic processing unit 142 acquires the image luminance signal Sigij of, for example, equation (1) calculated in the entire pixel range of the pixel array unit 30, and can perform subsequent image processing. Repeated calculations, such as weighted addition, which require a relatively large calculation load, are performed by the solid-state imaging device 200 in the process of transferring accumulated charges, so that the processing speed of the calculation processing unit 142 can be increased. .
  • FIG. 29A is a diagram schematically showing charge transfer operations of adjacent photoelectric conversion units PD11 and PD12.
  • a photo gate 11 (Photo Gate 11) and a photo gate 12 (Photo Gate 12) are arranged in the photoelectric conversion units PD11 and PD12.
  • a signal potential is supplied to the photogate 11 (Photo Gate11) and the photogate 12 (Photo Gate11) by a potential control line CONT.
  • the switching element TR3 is brought into a conductive state to discharge the charges accumulated in the photoelectric conversion units PD1 and PD2, thereby performing an initial reset.
  • the switching elements TR1, TR2, and TR3 are turned off, and charges corresponding to the amount of received light are accumulated one by one.
  • the potentials applied to the photogate 11 (Photo Gate11) and the photogate 12 (Photo Gate12) are the same.
  • FIG. 29B is a diagram schematically showing a case where the switching elements TR1 and TR2 are brought into a conducting state.
  • the switching elements TR1 and TR2 are made conductive, that is, the gate signal is made high.
  • the signal potential of the photogate 11 is made lower than the signal potential of the photogate 12 by the potential control line CONT.
  • the charge accumulated in the photoelectric conversion unit PD11 is transferred to the photoelectric conversion unit PD12 on the deeper side (larger side) of the positive potential potential.
  • FIG. 29C is a diagram schematically showing the case where the switching elements TR1 and TR2 are brought into a non-conducting state. Next, as shown in FIG. 29C, the switching elements TR1 and TR2 are rendered non-conductive to end charge transfer. At the end of accumulation, the potentials applied to the photogate 11 (PhotoGate11) and the photogate 12 (PhotoGate12) are the same. Charges are transferred between pixels by repeating the process as shown in FIGS. 29B and 29C. Subsequent processing and the like are the same as those of the imaging apparatus 100 according to the third embodiment.
  • the photogate 11 (Photo Gate 11) and the photo gate 12 (Photo Gate 11) enable charge transfer. Become. This makes it possible to control the bias potential of the photoelectric conversion unit PD more accurately, and to perform transfer control more accurately.
  • Imaging device 100 according to the third embodiment directly controls the potential of the photoelectric conversion unit PD by the potential control line CONT
  • the imaging device 100 according to the modification 2 of the third embodiment has a switching element The difference is that SW-11 and SW-12 are controlled by the potential control line CONT. Differences from the imaging apparatus 100 according to the third embodiment will be described below.
  • FIG. 30A is a diagram schematically showing charge transfer operations of adjacent photoelectric conversion units PD11 and PD12.
  • a switching element SW-11 and a switching element SW-12 are arranged adjacent to the switching elements TR1 and TR2.
  • the switching element SW-11 and the switching element SW-12 are transistors, for example. That is, potential potentials equivalent to those of the switching elements TR1 and TR2 can be formed.
  • a signal potential is supplied to the switching element SW-11 and the switching element SW-12 through a potential control line CONT.
  • the switching element TR3 is brought into a conductive state to discharge the charges accumulated in the photoelectric conversion units PD1 and PD2, thereby performing an initial reset.
  • the switching elements SW-11, SW-12, TR1, TR2, and TR3 are made non-conductive, and charges corresponding to the amount of received light are accumulated.
  • FIG. 30B is a diagram schematically showing the case where the switching elements SW-11, SW-12, TR1, and TR2 are brought into a conducting state.
  • the switching elements SW-11, SW-12, TR1 and TR2 are turned on, that is, the gate signal is turned high.
  • the electric charges accumulated in the photoelectric conversion units PD11 and PD12 are transferred to the switching elements SW-11, SW-12, TR1 and TR2, which are on the deep side (large side) of the positive potential potential.
  • FIG. 30C is a diagram schematically showing the case where the switching element SW-11 is brought into a non-conducting state. Next, as shown in FIG. 30C, when the switching element SW-11 is turned off, electric charges are collected on the switching elements SW-12, TR1 and TR2.
  • FIG. 30D is a diagram schematically showing a case where switching elements SW-11, SW-12, TR1, TR2, and TR3 are brought into a non-conducting state.
  • the switching elements SW-11, SW-12, TR1, TR2, and TR are turned off, the electric charges collected on the switching elements SW-12, TR1, and TR2 are transferred to the photoelectric conversion unit PD12. , terminates the charge transfer. Charge is transferred between pixels by repeating the process as in Figures 30B, 30C, and 30D. Subsequent processing and the like are the same as those of the imaging apparatus 100 according to the third embodiment.
  • the switching element SW-11 and the switching element SW-12 enable charge transfer. This makes it possible to control the bias potential of the photoelectric conversion unit PD more accurately, and to perform transfer control more accurately.
  • the image pickup apparatus 100 according to the fourth embodiment differs from the image pickup apparatus 100 according to the first embodiment in that the pixel array section 30 is composed of color pixels and can also be driven for color pixels. Differences from the imaging apparatus 100 according to the first embodiment will be described below.
  • FIG. 31 is a diagram showing a configuration example of the pixel array section 30 according to the fourth embodiment.
  • each pixel Pix has, for example, a Bayesian arrangement of color filters, red (R), green (G), and blue (B). Accordingly, each pixel Pix receives light through one of the plurality of color filters red (R), green (G), and blue (B).
  • FIG. 32 is a timing chart showing an addition processing example in the pixel array section 30 of FIG. In this case, red (R) pixel accumulation driving, green (G) pixel accumulation driving, and blue (B) pixel accumulation driving are performed in different time zones. It differs from the driving of FIGS.
  • red (R) pixel In accumulation driving, the accumulation of each pixel Pix is started with a length proportional to the weight value wij . Then, the green (G) pixel and the blue (B) pixel are reset by reset signals Gr2 and Br2 before charge transfer between the photoelectric conversion units PD of each pixel Pix. The subsequent transfer processing is the same as in FIGS. In this way, in the red (R) pixel accumulation drive, the accumulated charges of the green (G) and blue (B) pixels are reset and discharged before the accumulated charges are transferred. As a result, the red (R) pixel accumulated charge is transferred to the floating diffusion FD.
  • the accumulation drive for green (G) color pixels the accumulation of each pixel Pix starts with a length proportional to the weight value wij . Then, the red (R) pixel and the blue (B) pixel are reset by reset signals Rr2 and Br2 before charge is transferred between the photoelectric conversion units PD of each pixel Pix. The subsequent transfer processing is the same as in FIGS. In this way, in the green (G) pixel accumulation drive, the accumulated charges of the red (R) and blue (B) pixels are reset and discharged before the accumulated charges are transferred. As a result, accumulated charges for green (G) pixels are transferred to the floating diffusion FD.
  • the accumulation drive for blue (B) color pixels the accumulation of each pixel Pix is started with a length proportional to the weight value wij .
  • Red (R) pixels and green (G) pixels are reset by reset signals Rr2 and Gr2 before charges are transferred between the photoelectric conversion units PD of each pixel Pix.
  • the subsequent transfer processing is the same as in FIGS.
  • the blue (B) pixel accumulation drive the accumulated charges of the red (R) and green (G) pixels are reset and discharged before the accumulated charges are transferred.
  • accumulated charges for blue (B) pixels are transferred to the floating diffusion FD.
  • the pixel array section 30 is composed of color pixels and has a drive for color pixels.
  • the red (R) pixel accumulated charge, the green (G) pixel accumulated charge, and the blue (B) pixel accumulated charge can be transferred to the floating diffusion FD, thereby suppressing color mixture.
  • the image pickup apparatus 100 according to the fifth embodiment differs from the image pickup apparatus 100 according to the first embodiment in that it can be driven when the weight value w ij (F104) in equation (1) has a negative value. do. Differences from the imaging apparatus 100 according to the first embodiment will be described below.
  • FIG. 33 is a diagram schematically showing a processing example for the weight value w ijj (F104) of the formula (1) according to the fourth embodiment.
  • the positive Accumulation of each photoelectric conversion element PD is performed for an accumulation time length corresponding to the weight value wij having a value.
  • the charge between the photoelectric conversion units PD of each pixel Pix is transferred to the floating diffusion FD. After that, it is converted into a first digital signal by the AD conversion section ADC230 (see FIG. 5) and recorded in the recording section 120 (see FIG. 1). It should be noted that the accumulated time corresponding to the weight value wij having a negative value is zero.
  • the weight value w ij having a negative value is controlled by the accumulation control circuit 210, the first access control circuit 211a, the second access control circuit 211b, and the third access control circuit 211c .
  • Accumulation of each photoelectric conversion element PD is performed for an accumulation time length corresponding to the absolute value of (F104). Then, the charge between the photoelectric conversion units PD of each pixel Pix is transferred to the floating diffusion FD. After that, it is converted into a second digital signal by the AD conversion section ADC 230 (see FIG. 5) and recorded in the recording section 120 (see FIG. 1). It should be noted that the accumulation time of the length corresponding to the weight value wij having a positive value is set to zero.
  • the arithmetic processing unit 142 calculates the difference between the first digital signal in the first frame F100 and the second digital signal in the second frame F102 recorded in the recording unit 120 (see FIG. 1), generates a digital signal corresponding to the weight value w ij (F104) of .
  • the calculation result corresponding to the weight value w ij (F104) of the equation (1) is generated as a numerical value.
  • the imaging apparatus 100 performs accumulation in each photoelectric conversion element PD for an accumulation time length corresponding to the weight value wij having a positive value, and obtains the first digital signal. Convert. Subsequently, accumulation is performed in each photoelectric conversion element PD for an accumulation time length corresponding to the absolute value of the weight value wij having a negative value, and is converted into a second digital signal. Subsequently, the arithmetic processing unit 142 subtracts the second digital signal from the first digital signal. This makes it possible to drive arithmetic processing when the weight value w ij (F104) in equation (1) has a negative value.
  • This technology can be configured as follows.
  • a plurality of pixel regions composed of a plurality of pixels; a plurality of first charge storage units corresponding to each of the pixel regions; a plurality of first pixels in the pixel region, a photoelectric conversion unit; a photoelectric conversion portion of a pixel adjacent to at least one of the vertical and horizontal directions and a first element that is rendered conductive or non-conductive;
  • a second pixel in the pixel region is a photoelectric conversion unit; a first element that is in a conducting state or a non-conducting state with the photoelectric conversion portion of at least one of vertically and horizontally adjacent pixels;
  • a solid-state imaging device comprising: a first storage element that is brought into a conducting state or a non-conducting state with the first storage section.
  • the first element After being brought into the first conduction state, the first element, which is brought into the conduction state or the non-conduction state with the other photoelectric conversion portions in the pixel region, is further brought into the second non-conduction state, and the first capacitor element is turned into the second non-conduction state.
  • the solid-state imaging device according to (3) which is set to the third conductive state.
  • the pixel has a potential adjustment element connected between the photoelectric conversion unit and the first element, and the stored charge is transferred by the potential adjustment element and the first element; ).
  • the pixel further includes a second element for discharging accumulated charges of the photoelectric conversion unit, The solid-state imaging device according to (10), wherein a non-discharge period of accumulated charges by the second element is controlled according to the weight value.
  • the plurality of pixels are arranged in a matrix,
  • the first element makes the connection between the photoelectric conversion units adjacent in the first direction conductive or non-conductive, or makes the connection between the photoelectric conversion units adjacent in the second direction different from the first direction conductive.
  • the solid-state imaging device according to (1) which is either in a state or in a non-conducting state.
  • each of the pixels constituting the pixel region receives light through one of a plurality of color filters; Before transferring the accumulated charges corresponding to a predetermined color filter out of the plurality of color filters to the first storage unit, the accumulated charges corresponding to other color filters out of the plurality of color filters are discharged. , (20).
  • (24) further comprising an accumulation control circuit for controlling at least one of resetting of accumulated charges in each of the photoelectric conversion units, generation of accumulated charges according to the weight value, the pixel region, and potential shape, according to the arithmetic processing; ).
  • (25) (24) the solid-state imaging device, and and an arithmetic processing unit capable of performing a convolution operation,
  • the imaging device wherein the weight value and the information of the pixel area corresponding to the calculation range are supplied from the calculation processing unit.
  • first digital data generated by the analog-to-digital converter after the photoelectric conversion period of the photoelectric converter is controlled according to the positive weight value of the arithmetic processing and transferred to the first electricity storage unit;
  • the photoelectric conversion period of the photoelectric conversion unit is controlled according to the absolute value of the negative weight value of the arithmetic processing, and the second digital signal generated by the analog-to-digital conversion unit after being transferred to the first storage unit.
  • 100 imaging device, 142: arithmetic processing unit, 200: image sensor, 210: Accumulation control circuit, A11 to A22: addition range (pixel range), AMP: switching element (fourth element), FD: Floating diffusion (first power storage unit), FD2 floating diffusion (second power storage unit), FG: switching element (seventh element), PD: photoelectric conversion unit, PD11: photoelectric conversion unit, PD12: photoelectric conversion unit, PD13: photoelectric conversion unit of the second pixel, PD33: photoelectric conversion unit of the second pixel, Photo Gate 11: photo gate 11, Photo Gate 12: Photo Gate 12, RST: switching element (sixth element), SEL: switching element (fifth element), SW-11: switching element, SW-12: switching element, TR1: switching element (first element), TR2: switching element (first element), TR3: switching element (second element), TRG: switching element (third element).

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
PCT/JP2022/023223 2021-09-17 2022-06-09 固体撮像素子、及び撮像装置 Ceased WO2023042498A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2023548126A JPWO2023042498A1 (https=) 2021-09-17 2022-06-09
US18/690,390 US20240380998A1 (en) 2021-09-17 2022-06-09 Solid-state imaging element and imaging device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-152305 2021-09-17
JP2021152305 2021-09-17

Publications (1)

Publication Number Publication Date
WO2023042498A1 true WO2023042498A1 (ja) 2023-03-23

Family

ID=85602701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/023223 Ceased WO2023042498A1 (ja) 2021-09-17 2022-06-09 固体撮像素子、及び撮像装置

Country Status (3)

Country Link
US (1) US20240380998A1 (https=)
JP (1) JPWO2023042498A1 (https=)
WO (1) WO2023042498A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533018A (en) * 1976-06-30 1978-01-12 Hitachi Ltd Solid pickup element
JP2011139350A (ja) * 2009-12-28 2011-07-14 Canon Inc 固体撮像装置及びその駆動方法
JP2014232900A (ja) * 2013-05-28 2014-12-11 株式会社ニコン 固体撮像素子及び撮像装置
JP2015023250A (ja) * 2013-07-23 2015-02-02 ソニー株式会社 固体撮像素子及びその駆動方法、並びに電子機器
WO2017169216A1 (ja) * 2016-03-31 2017-10-05 ソニー株式会社 固体撮像素子、固体撮像素子の駆動方法、及び、電子機器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018019191A (ja) * 2016-07-27 2018-02-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
CN110832844B (zh) * 2017-07-07 2021-11-09 普里露尼库斯新加坡私人有限公司 固态摄像装置、固态摄像装置的驱动方法、以及电子设备
JP2020072316A (ja) * 2018-10-30 2020-05-07 ソニーセミコンダクタソリューションズ株式会社 電子回路、固体撮像素子、および、電子回路の制御方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533018A (en) * 1976-06-30 1978-01-12 Hitachi Ltd Solid pickup element
JP2011139350A (ja) * 2009-12-28 2011-07-14 Canon Inc 固体撮像装置及びその駆動方法
JP2014232900A (ja) * 2013-05-28 2014-12-11 株式会社ニコン 固体撮像素子及び撮像装置
JP2015023250A (ja) * 2013-07-23 2015-02-02 ソニー株式会社 固体撮像素子及びその駆動方法、並びに電子機器
WO2017169216A1 (ja) * 2016-03-31 2017-10-05 ソニー株式会社 固体撮像素子、固体撮像素子の駆動方法、及び、電子機器

Also Published As

Publication number Publication date
JPWO2023042498A1 (https=) 2023-03-23
US20240380998A1 (en) 2024-11-14

Similar Documents

Publication Publication Date Title
US10756129B2 (en) Image sensors having imaging pixels with ring-shaped gates
CN101656820B (zh) 固体摄像装置及其制造方法
JP6075646B2 (ja) 固体撮像装置およびその駆動方法、並びに電子機器
US10014333B2 (en) Back-side illuminated pixels with interconnect layers
US10186535B2 (en) Image sensors with stacked photodiodes
US10192919B2 (en) Imaging systems with backside isolation trenches
US9117728B2 (en) Solid-state imaging device, method of manufacturing same, and electronic apparatus
CN118450274A (zh) 具有高动态范围成像像素的图像传感器
TW202205652A (zh) 固體攝像裝置、固體攝像裝置的製造方法、以及電子機器
US10566375B2 (en) Stacked-die image sensors with shielding
JP2008041689A (ja) 光電変換装置および光電変換装置を用いた撮像システム
JP7497396B2 (ja) 撮像素子及び撮像装置
JP2011066241A (ja) 固体撮像装置とその製造方法、及び電子機器
CN116057953A (zh) 固态摄像元件和电子设备
JP2017076872A (ja) 撮像素子
US20210152771A1 (en) Backside illuminated global shutter image sensor with an analog memory charge coupled device
JP2025172012A (ja) イメージセンサー及びその動作方法並びに電子装置
JP6813971B2 (ja) 光電変換装置及び撮像システム
JP2005198001A (ja) 固体撮像装置
WO2023042498A1 (ja) 固体撮像素子、及び撮像装置
JP7156330B2 (ja) 撮像素子及び撮像装置
WO2023105965A1 (ja) 固体撮像素子、及び撮像装置
JP2018049855A (ja) 固体撮像装置及び電子機器
US12256162B2 (en) Reference pixel column readout
JP2020014255A (ja) 撮像素子及び撮像装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2023548126

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22869647

Country of ref document: EP

Kind code of ref document: A1