WO2023039849A1

WO2023039849A1 - Storage device and driving method therefor

Info

Publication number: WO2023039849A1
Application number: PCT/CN2021/119130
Authority: WO
Inventors: 朱治宇; 雷张伟; 聂瑞杰
Original assignee: 华为技术有限公司
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2023-03-23

Abstract

A storage device and a driving method therefor, which relate to the field of circuits, and which solve the problem of the relatively high memory bandwidth and capacity requirements of existing memories. Specifically: customizing a storage device, the storage device comprising a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector. The storage array is used to store image frame data and compensation parameters. On the basis of a read request, the read decoder gates bit-plane data and compensation parameters corresponding to the bit-plane data. On the basis of the compensation parameters corresponding to the bit-plane data, the compensation circuit compensates the bit-plane data. The encoding circuit encodes the bit-plane data compensated by the compensation circuit. On the basis of the read request, the selector selects and outputs the bit-plane data encoded by the encoding circuit.

Description

A storage device and its driving method

technical field

The embodiments of the present application relate to the circuit field, and in particular, to a storage device and a driving method thereof.

Background technique

At present, liquid crystal on silicon (LCOS), as a micro-display technology, is widely used in projectors, virtual reality (virtual reality, VR) display, augmented reality (augmented reality, AR) display, laser TV and other fields. . In order to improve the display effect of LCOS, when LCOS is driven, the original data can be compensated and corrected through the compensation circuit and compensation parameters, and the compensated data can be encoded and output to the LCOS panel.

FIG. 1 is a digital LCOS driver chip. As shown in FIG. 1 , the driver chip includes a compensation circuit, a parameter memory, an encoding circuit, a row buffer, a memory, and a storage controller. The input data is compensated and corrected through the compensation circuit and the compensation parameters. The input data may be original image data, and the compensated data is input into the encoding circuit for encoding. The storage controller cooperates with the line buffer to cache and transpose the encoded data. The storage controller writes the coded data into the memory through the write pointer, and reads the data from the memory through the read pointer.

However, after the input data is compensated, corrected and encoded, the amount of data will increase dramatically (for example, the amount of data can usually be expanded by 3 to 6 times). For example, as shown in Figure 2, each pixel in the input data is 8 bits, and each pixel in the output data after compensation encoding is expanded to 32 bits, and the output data after compensation encoding is in the form of a bit-plane Output to LCOS panel. It can be seen from Fig. 1 that since the data written into the memory and the data read from the memory are compensated and coded data, the amount of data written into the memory and the amount of data read from the memory are relatively large, which affects the bandwidth of the memory and the data read from the memory. The capacity requirement is higher and the cost is higher.

Contents of the invention

Embodiments of the present application provide a storage device and a driving method thereof, which can reduce capacity and bandwidth requirements of the storage device and reduce costs.

The embodiment of the present application adopts the following technical solutions:

According to the first aspect of the embodiments of the present application, there is provided a storage device, which includes: a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector; the storage array is used for storing the first image frame data and compensating parameter, the storage array is coupled to the input end of the compensation circuit, the read decoder is connected to the row gate line or the column gate line of the memory array, and the output end of the compensation circuit is coupled to the input end of the selector through the encoding circuit. Wherein, the read decoder is used to gate the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on the read request; the first image frame includes a plurality of bit planes, and the first bit plane is multiple Any one of the bit-planes. The compensation circuit is configured to compensate the data of the first bit plane based on the compensation parameter corresponding to the data of the first bit plane. An encoding circuit, configured to encode the data of the first bit plane compensated by the compensation circuit. The selector is used to select and output the data of the first bit plane encoded by the encoding circuit.

Based on this scheme, by building the compensation circuit and the encoding circuit into the storage device, the read decoder can select part or all of the data of the first bit plane based on the read request, and the compensation parameters corresponding to the data of the bit plane, and pass The compensation circuit and the encoding circuit perform compensation and encoding on the data of the bit plane, and then output the compensated encoded data to the storage device. It can be understood that since the compensation circuit and the encoding circuit are built into the storage device in this solution, the data of the first bit plane can be gated, and the data of the first bit plane can be compensated and encoded inside the storage device. Data of the compensated-encoded first bit-plane may be directly output. Compared with when the memory is independent of the compensation circuit and the encoding circuit, it is necessary to sequentially read all the bit data of each pixel from the memory. Addressing the data of one bit plane, instead of addressing the data of all bits of a pixel, can reduce the read bandwidth requirement of the storage device. Moreover, in this solution, the first image frame data stored in the storage array is data without compensation encoding, so the amount of data written into the storage array is small, which can reduce the write bandwidth and capacity of the storage device.

Optionally, when the read decoder is connected to the row gate line of the memory array, the selector is used for column gate. When the read decoder is connected to the column gate line of the memory array, the selector is used for row gate.

With reference to the first aspect, in an implementation manner, the data of the first bit plane gated by the read decoder based on the read request is part or all of the data of the first bit plane.

Based on this scheme, the read decoder can select 1-bit data of some pixels located in the same bit plane in the first image frame based on the read request, and can also select all pixels located in the same bit plane in the first image frame The 1-bit data is compensated and coded inside the storage device, and the compensated coded data of one bit plane is directly output. It is not necessary to read all the bit data of each pixel in the first image frame, and then perform compensation encoding on the read data outside the memory, thus reducing the bandwidth requirement of the storage device.

With reference to the first aspect, in an implementation manner, the above-mentioned read request includes a first address, and a read decoder is specifically configured to gate the data of the first bit plane based on the first address in the read request, and the first bit The compensation parameters corresponding to the data of the plane.

Optionally, the first address may be an upper address in the read request.

Based on this solution, the read decoder can directly address the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on the high address (first address) in the read request, and can simultaneously select the first bit The compensation parameters corresponding to the data of the plane and the data of the first bit plane are compensated and corrected based on the compensation parameters. Compared with the prior art of sequentially reading the data of each pixel in the first image frame in the memory, this solution can directly select the data of the bit plane, and the reading efficiency is higher. Compared with storing the compensation parameters and image data in different memories in the prior art, this solution can not only reduce the cost, but also improve read efficiency.

With reference to the first aspect, in an implementation manner, the read request further includes a second address; the read decoder determines a selection signal based on the second address in the read request, and the selection signal is used to enable the selector.

Optionally, the second address may be a lower address in the read request.

Based on this solution, the read decoder can select the selector based on the lower address (second address) in the read request, so as to output data of a certain bit plane after compensation encoding. That is to say, in this scheme, the data of the bit plane is gated through the high-order address, and the selector is gated through the low-order address to output the data of the bit-plane after compensation and encoding of the bit-plane, and the compensation and encoding of the bit-plane are equal It is performed inside the storage device, so the read bandwidth of the storage device can be reduced.

In combination with the first aspect, in an implementation manner, the above selection signal is also used to select a target bit plane, and the target bit plane is a bit plane encoded by an encoding circuit; the selector is specifically used to select based on the selection signal Output the data of the target bit-plane.

Based on this scheme, after the data of the first bit plane is compensated and encoded, the amount of data will expand, and the first bit plane may expand into multiple bit planes. This scheme can determine the output data based on the low address in the read request. the target bit plane, and output the compensated encoded data of the target bit plane through the selector. When the memory is independent of the compensation circuit and the encoding circuit, if you want to output the data of a bit plane, you need to read the data of all pixels in the image frame in sequence, and perform compensation encoding on the data of each pixel to complete a bit Compared with the data output of two planes, this solution can realize compensation and encoding of a bit plane inside the storage device, and output the data of one of the bit planes after compensation and encoding from the storage device, which can significantly reduce the read bandwidth of the storage device .

With reference to the first aspect, in an implementation manner, the first image frame data stored in the storage array is original data.

Based on this scheme, by writing the original data without compensation and encoding into the storage array, compared with the image data stored in the memory as compensated and encoded data, since the first image frame data stored in the storage array in this scheme is not After compensation and encoding processing, the amount of data is small, which can reduce the write bandwidth and capacity of the storage device.

With reference to the first aspect, in an implementation manner, the storage device further includes an image compression circuit configured to compress the first image frame before the first image frame is written into the storage array.

Based on this solution, the data written into the storage array can be data processed by the image compression circuit, and the first image frame data written into the storage array has not been compensated and encoded, so the write bandwidth of the storage device can be further reduced and capacity.

With reference to the first aspect, in an implementation manner, the above-mentioned storage device may further include a write decoder, configured to sequentially write the data of each pixel in the first image frame into the storage array. Optionally, when the write decoder writes the data of each pixel in the first image frame into the memory array, it can write the data of the same bit in each pixel into the memory with the same row address or column address. In the unit, so that multiple storage units with the same row address or column address in the storage array store the data of the same bit plane.

The second aspect of the embodiment of the present application provides a method for driving a storage device, the storage device includes: a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector; the storage array is used to store the first image frame data As well as compensation parameters, the storage array is coupled to the input end of the compensation circuit, the read decoder is connected to the row gate line or the column gate line of the memory array, and the output end of the compensation circuit is coupled to the input end of the selector through the encoding circuit. The driving method includes: the read decoder gates the data of the first bit plane based on the read request, and the compensation parameters corresponding to the data of the first bit plane; the first image frame includes a plurality of bit planes, and the first bit plane is multiple Any one of the bit-planes. The compensation circuit compensates the data of the first bit plane based on the compensation parameter corresponding to the data of the first bit plane. The encoding circuit encodes the data of the first bit plane compensated by the compensation circuit. The selector selects and outputs the data of the first bit-plane encoded by the encoding circuit.

With reference to the second aspect, in an implementation manner, the data of the first bit plane gated by the read decoder based on the read request is part or all of the data of the first bit plane.

With reference to the second aspect, in an implementation manner, the read request includes the first address; the read decoder gates the data of the first bit plane based on the read request, and the compensation parameters corresponding to the data of the first bit plane include:

The read decoding is based on the first address, strobes the data of the first bit plane, and the compensation parameter corresponding to the data of the first bit plane.

With reference to the second aspect, in an implementation manner, the read request further includes a second address; the method further includes:

The read decoder determines a selection signal based on the second address; the selection signal is used to gate the selector.

In combination with the second aspect, in an implementation manner, the selection signal is also used to select the target bit plane, and the target bit plane is a bit plane encoded by the encoding circuit; the selector selects and outputs the bit plane encoded by the encoding circuit based on the read request. The data of the first bit plane, including:

The selector selects an output target bit plane based on the selection signal.

With reference to the second aspect, in an implementation manner, the first image frame data stored in the storage array is original data.

With reference to the second aspect, in an implementation manner, the storage device further includes an image compression circuit, and the method further includes:

The image compression circuit compresses the first image frame before the first image frame is written into the memory array.

With reference to the second aspect, in an implementation manner, the first image frame data stored in the storage array is data compressed by an image compression circuit.

For descriptions of effects of various implementations of the second aspect above, reference may be made to descriptions of effects of corresponding implementations of the first aspect, and details are not repeated here.

The third aspect of the embodiments of the present application provides a driver chip, the driver chip includes an interface circuit, and the storage device as described in the above first aspect and various implementations of the first aspect, the storage device is used to The circuit receives the above-mentioned first image frame data.

The fourth aspect of the embodiments of the present application provides a drive system, the drive system includes the storage device, the interface circuit, and the LCOS panel as described in the first aspect and various implementations of the first aspect, and the storage device uses After receiving the above-mentioned first image frame data through the interface circuit, the LCOS panel is used to display the compensated and coded data output by the storage device.

Description of drawings

Fig. 1 is the structural representation of the driver chip of a kind of digital LCOS that the embodiment of the application provides;

FIG. 2 is a schematic diagram of compensating the amount of data before and after encoding provided by the embodiment of the present application;

Fig. 3 is the structural representation of another kind of digital LCOS driver chip that the embodiment of the present application provides;

FIG. 4 is a system architecture diagram of an application scenario of a storage device provided in an embodiment of the present application;

FIG. 5 is a system architecture diagram of an application scenario of another storage device provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a storage device provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another storage device provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of a driver chip provided by an embodiment of the present application;

FIG. 9 is a schematic flowchart of a method for driving a storage device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can represent: a, b, c, a and b, a and c, b and c, or, a and b and c, wherein a, b and c can be single or multiple. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect, Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order. For example, "first" in the first bit-plane and "second" in the second bit-plane in the embodiment of the present application are only used to distinguish different bit-planes. The first, second, etc. descriptions that appear in the embodiments of this application are only for illustration and to distinguish the description objects. Any limitations of the examples.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

First, the bit plane in the embodiment of the present application is explained with reference to FIG. 2 .

As shown in (a) in FIG. 2 , take the resolution of input data as 2K*4K and each pixel as 8 bits as an example. The input data shown in (a) in FIG. 2 includes 8 bit planes, and data of the same bit in all pixels form a bit plane. For example, the values of the first bits of all pixels in the input data may form the first bit plane.

Figure 1 is a digital LCOS driver chip. As shown in Figure 1, since the data written into the memory and the data read from the memory are all compensated and encoded data, the amount of data written into the memory and the amount of data read from the memory are relatively large, which affects the bandwidth of the memory. The requirements for capacity and capacity are higher, and the cost is higher.

A method to improve memory bandwidth and capacity, which can expand bandwidth by using a large number of double data rate (DDR) particles, or use high bandwidth memory (high bandwidth memory, HBM) technology to improve memory bandwidth and capacity. However, since the amount of image data is relatively small compared to the capacity of DDR, if a large number of DDR particles are used to expand the bandwidth, more DDR capacity will be wasted and the cost will be higher. Moreover, when a large number of DDR particles are used to expand the bandwidth, due to the excessive number of chip pins, the size of the chip is larger and the cost is higher. If HBM technology is used to expand bandwidth, advanced packaging technology is required, and the chip cost is relatively high.

Figure 3 is another digital LCOS driver chip. Take for example that each pixel is 8bit when uncompensated encoding, and each pixel is 32bit after compensation encoding. In conjunction with Fig. 2, as shown in Fig. 3, the storage controller writes the input data (raw image data) shown in (a) in Fig. 2 into memory (for example, static random-access memory (static random-access memory, SRAM) ))middle. The 8-bit data of each pixel is sequentially read from the memory, and the 8-bit data is compensated and encoded sequentially through the compensation circuit and the encoding circuit. Since the output data is output to the LCOS panel in the form of a bit-plane (bit-plane) shown in (c) in Figure 2, therefore, when outputting the first bit-plane, first, sequentially read from the memory The 8bit data of each pixel point is compensated and encoded, and only the 1bit data corresponding to the first bit plane is reserved in the 32bit data of each pixel point after compensation encoding, which is sequentially output to The LCOS panel discards the remaining 31bit data. Then, read the 8-bit data of each pixel from the memory in turn, and perform compensation and encoding on the 8-bit data of each pixel in turn. When outputting the second bit plane, each pixel after compensation and encoding In the 32bit data, only the 1bit data corresponding to the second bit plane is reserved, and it is output to the LCOS panel in turn, and the remaining 31bit data are discarded. And so on until all output data shown in (b) in FIG. 2 is output.

In the driver chip shown in FIG. 3 , since the input data written into the memory is original image data without compensation and encoding, compared with the solution shown in FIG. 1 , the write bandwidth and capacity of the memory can be reduced. However, since in the scheme shown in Figure 3, every time a bit plane shown in (c) in Figure 2 is output, the 8bit data of all pixels will be read from the memory once, combined with (b) in Figure 2 As shown, if all 32-bit planes after compensation encoding are to be output, it is necessary to read 8-bit data of all pixels from the memory 32 times. This will result in 32 times the read bandwidth of the memory and higher power consumption.

In order to solve the problem of high cost caused by the large read bandwidth and write bandwidth of the memory when the LCOS is driven. The embodiment of the present application provides a storage device. By building a compensation circuit and an encoding circuit in the storage device, the read decoder can gate part or all of the data of a bit plane, and The data of the bit plane is compensated and encoded, and the storage device can directly output the data of a bit plane after compensation and encoding. Compared with the scheme shown in Figure 3, when the memory is independent of the compensation circuit and the encoding circuit, it is necessary to sequentially read all the bit data of each pixel from the memory. Array) setting, can gate the data of a bit plane, and perform compensation encoding on the data of a bit plane, can significantly reduce the read bandwidth of the storage device, and the cost is low. Moreover, in the embodiment of the present application, by storing the image frame data without compensation encoding in the storage array, the amount of data is small. Therefore, the capacity requirement of the storage array is small, and the write bandwidth and capacity of the storage device can be reduced.

The storage device provided in the embodiments of the present application can be applied to display devices such as projectors, VR/AR displays, and laser TVs. The embodiment of the present application does not limit the type of the display device used by the storage device, and this is only an exemplary description.

FIG. 4 is a system architecture diagram of an application scenario of a storage device. As shown in Figure 4, the driver chip receives the original image data from the video source through the interface circuit, and inputs the original image data into the storage device provided by the embodiment of the present application after image preprocessing, and the storage device is used to process the original image data Compensation and coding. Output the image data compensated and encoded by the storage device to the LCOS panel, control the liquid crystal material in the area corresponding to the pixel of the LCOS panel, and adjust the reflectivity of the control light, so as to control the intensity of the reflected light after the light source passes through the LCOS panel, forming different gray levels The image is finally projected to the human eye or the screen by the optical components.

Optionally, the interface circuits in the driver chip shown in Figure 4 include but are not limited to high definition multimedia interface (high definition multimedia interface, HDMI), low-voltage differential signaling (low-voltage differential signaling, LVDS), mobile industry processor interface (mobile industry processor interface, MIPI) and other data interfaces.

The storage device provided in the embodiment of the present application may also be applied in the communication field, for example, the storage device may be used to drive an all-optical switching LCOS optical processor.

FIG. 5 is a system architecture diagram of another application scenario of a storage device. As shown in Figure 5, the LCOS drive chip includes the storage device provided by the embodiment of the present application. The optical signal is input by the optical fiber and incident on the mirror through the optical prism. The storage device in the LCOS drive chip outputs the driving voltage to the LCOS panel to control the deflection of the liquid crystal. Angle, in order to control the angle of light signal reflection. The reflected optical signal passes through the optical prism, the compensation optical unit to the grating for filtering. After filtering, it passes through the compensation optics and the optical prism unit and enters the mirror again. The storage device in the LCOS driver chip outputs the driving voltage to the LCOS panel to control the liquid crystal again. Deflection and reflection signals pass through the prism of the optical imaging and polarization unit to the output optical fiber to complete all-optical switching. When the storage device provided by the embodiment of the present application is applied to the LCOS driver chip shown in FIG. 5 , the LCOS driver chip can realize optical switching by controlling the liquid crystal deflection of the LCOS panel, which can reduce the bandwidth and capacity requirements of the LCOS driver chip.

An embodiment of the present application provides a storage device. As shown in FIG. 6 , the storage device includes a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector. The storage array is used to store the first image frame data and compensation parameters, the storage array is coupled to the input end of the compensation circuit, the read decoder is connected to the row gate line or the column gate line of the storage array, and the output end of the compensation circuit passes through the encoding The circuit is coupled and connected to the input end of the selector. The read decoder is configured to gate the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on the read request.

Optionally, the first image frame data may be original image data. For example, the first image frame data may be raw image data received from a video source. As shown in (a) in FIG. 2 , the first image frame data may be 2K*4K*8 data, and each pixel in the first image frame data may be represented by 8bit data.

The first image frame may include a plurality of bit-planes. The first bit plane is any one of the multiple bit planes. The number of bit planes included in the first image frame is related to the number of bits of each pixel in the first image frame. For example, as shown in (a) in FIG. 2, when the bit of each pixel in the first image frame is 8 bits, the first image frame includes 8 bit planes, and the first bit plane is 2K*4K bit.

The data of the first bit plane gated by the read decoder based on the read request may be part of the data of the first bit plane, or may be all of the data of the first bit plane, which is not limited in this embodiment of the present application. It can be understood that, compared with the prior art, the embodiment of the present application can directly address the data of a bit plane instead of addressing the data of all bits of a pixel, thus reducing the read bandwidth requirement of the storage device.

For example, taking the first image frame data as the data of 2K*4K*8 shown in (a) in FIG. 2 as an example, the first image frame data includes 8 bit planes, if the first bit plane is 8 bits In the first bit plane in the plane, the read decoder can select the 1-bit data of the first bit of a pixel based on the read request, or select the 1-bit data of the first bit of multiple pixels. It is also possible to strobe the 1-bit data of the first bit of all pixels. The embodiment of the present application does not limit the amount of data that the read decoder strobes based on the read request. The size of the data is related to the storage method of the first image frame data in the storage array, the bit width of the selector and other parameters. For example, taking the first bit plane includes 2K*4K bit data, and the bit width of the selector is M as an example, the read decoder can select N bit data of the first bit plane based on a read request, where N is less than or equal to M. That is, the amount of data gated by the read decoder based on the read request does not exceed the bit width of the selector.

Optionally, the data of the same bit plane in the first image frame can be stored in the same row of the storage array, can also be stored in the same column of the storage array, and can also be stored in multiple rows and/or multiple columns of the storage array. The embodiment of the application does not limit the specific storage manner of the first image frame data in the storage array.

Exemplarily, the compensation parameters corresponding to different data of the same bit plane in the first image frame may be the same or different. Compensation parameters corresponding to data of different bit planes may be the same or different, which is not limited in this embodiment of the present application. It can be understood that, in the case that the compensation parameters corresponding to the data of multiple bit planes in the first image frame are the same, when the decoder selects the data of any one of the multiple bit planes, the compensation parameter will be selected. In the case that the compensation parameters corresponding to the data of different bit planes in the first image frame are different, when the decoder selects the data of a bit plane, the compensation parameters corresponding to the data of the bit plane will also be selected.

Optionally, there may be one or more compensation parameters corresponding to 1-bit data of the first bit-plane. The embodiment of the present application does not limit the number of compensation parameters corresponding to 1-bit data of the first bit-plane. Figure 6 uses one There are two compensation parameters corresponding to 1-bit data of the bit plane, parameter 1 and parameter 2 respectively, for illustration. The compensation parameters in the storage array can be preset in the storage array (for example, preset in the storage device when leaving the factory), and can also be written into the storage array by software. In the embodiment of the present application, the writing method of the compensation parameters in the storage array is Not limited.

The above read request is used to read the data of the first bit plane, and the read request may include the first address and the second address. The first address can be a high address or a low address. When the first address is a high address, the second address is a low address. When the first address is a low address, the second address is a high address. The first address in the read request is used to select the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane. The second address in the read request is used to assert the select signal to enable the selector. For example, as shown in Figure 6, taking the compensation parameters corresponding to 1 bit data of each bit plane including parameter 1 and parameter 2 as an example, when the read request is used to read the data of the first bit plane, the read decoder based on The first address in the read request strobes the data of the first bit plane, and parameter 1 and parameter 2 corresponding to the data of the first bit plane.

Optionally, the read decoder is further configured to determine a selection signal based on the second address in the read request, and the selection signal is used to enable the selector.

When the read decoder is connected to the row gate line of the memory array, the selector is used for column gate. When the read decoder is connected to the column gate line of the memory array, the selector is used for row gate. The embodiment of the present application does not limit whether the read decoder is connected to the row gate line or the column gate line of the storage array. Figure 6, Figure 7 and Figure 8 take the read decoder connected to the column gate line of the storage array as an example. hint.

The compensation circuit is configured to compensate the data of the first bit plane based on the compensation parameter corresponding to the data of the first bit plane.

Exemplarily, as shown in FIG. 6, after the read decoder strobes the data of the first bit plane and the parameter 1 and parameter 2 corresponding to the data of the first bit plane, the data of the first bit plane and the first The parameter 1 and parameter 2 corresponding to the data of the bit plane are output to the compensation circuit, and the data of the first bit plane are compensated and corrected through multiplication and addition operations in the compensation circuit to adjust the gain and offset of each pixel gray scale. The embodiment of the present application does not limit the specific circuit structure of the compensation circuit. Figures 6 to 8 illustrate the compensation circuit including an adder and a multiplier as an example. In practical applications, other compensation methods can be used to correct the data of each bit plane Make compensation corrections.

An encoding circuit, configured to encode the data of the first bit plane compensated by the compensation circuit.

Exemplarily, as shown in FIG. 6 , the encoding circuit can use a look-up table (look-up-table, LUT) to realize the encoding function, and the amount of data encoded by the LUT can be expanded to 4 times of the original data. For example, taking the data of the first bit plane as 2K*4K as an example, the data after compensation correction and LUT encoding can be expanded to 4*2K*4K. That is, data of one bit plane can be expanded into data of multiple bit planes after being compensated and encoded. The embodiment of the present application does not limit the specific encoding manner of the encoding circuit, and FIG. 6 to FIG. 8 are illustrated by taking the encoding circuit using LUT encoding as an example.

The selector is used to select and output the data of one bit plane encoded by the encoding circuit.

Exemplarily, the selector may be a MUX (multiplexer), or may be other selection circuits, and the embodiment of the present application does not limit the specific type of the selector.

Optionally, the selector may be coupled to the read decoder, or directly connected to the read pointer, and the present application does not limit the specific connection manner of the selector. FIG. 6 and FIG. 7 illustrate an example by taking the coupled connection between the selector and the read decoder as an example.

The selector may determine a select signal for enabling the selector based on the second address in the read request. This selector can be used for row gating as well as for column gating. For example, when the read decoder is connected to the row gate line, the selector is used for column gate. For another example, when the read decoder is connected to the column gate line, the selector is used to pass the column.

Optionally, the selection signal is also used to select a target bit plane, where the target bit plane is a bit plane encoded by the encoding circuit. The selector is specifically configured to select and output the target bit plane based on the selection signal.

Exemplarily, taking the example where the read decoder is used for column gating and the selector is used for row gating as an example, the read decoder can determine a selection signal according to the low address in the read request, the selection signal is used for row gating, and Selecting and outputting the data of the target bit-plane, the selector outputs the data corresponding to the target bit-plane among the plurality of bit-planes encoded by the encoding circuit based on the selection signal.

For example, as shown in Figure 6, take the first bit plane expanded to four 2K*4K bit planes after compensation and LUT encoding, and the target bit plane is the second bit plane in the four bit planes as an example. The coder determines to select and output the data of the second bit plane according to the low address in the read request, and the selector sequentially selects a plurality of row gate lines, and sequentially outputs a plurality of data corresponding to the second bit plane, so that The data of the second bit plane is output to the LCOS panel.

Exemplarily, in combination with the scheme shown in FIG. 2, the scheme shown in FIG. 3 is used to read 8-bit data of one pixel from the memory at a time, and perform compensation coding on the 8-bit data of each pixel. If the data in FIG. 2 is to be All the data of one bit plane after the compensation coding shown in (c) is output, and the 8-bit data of all pixels needs to be read from the memory once, that is, the data shown in (a) in Figure 2 needs to be read once. All data is read out, the amount of data read is 2K*4K*8, and the power consumption is high. With the storage device provided by the embodiment of the present application, by building the compensation circuit and the encoding circuit into the storage device, all the data of a bit plane is gated based on one or more read requests, and the data of the bit plane is selected inside the storage device. Compensation encoding is performed on the data. If one bit plane after compensation encoding shown in (c) in FIG. The data of one bit plane shown in (c) in FIG. 2 is read, and the amount of read data is 2K*4K*1.

Exemplarily, the first image frame data is the input data of 2K*4K*8 shown in (a) in FIG. Take the output data of 2K*4K*32 as an example, use the scheme shown in Figure 3 to output the data of 2K*4K*32 shown in (b) in Figure 2 to the LCOS panel, you need to ( The input data shown in a) 2K*4K*8 is read 32 times, that is, the size of the read data is 2K*4K*8*32. With the storage device provided by the embodiment of the present application, since the compensation circuit and the encoding circuit are arranged near the memory (storage array), if the data of 2K*4K*32 shown in (b) in FIG. 2 is to be output to the LCOS panel , it is only necessary to read the compensated coded 32-bit planes shown in (b) in FIG. Obviously, using the storage device provided by the embodiment of the present application, compared with the solution shown in FIG. 3 , the amount of read data is reduced to 1/8. It can be understood that the bandwidth can be regarded as the speed of data transmission, and the larger the bandwidth in the same time, the more the amount of data transmitted. Similarly, from the perspective of data volume, the less data transmitted within the same time period, the lower the bandwidth requirement. Therefore, this solution provides a storage device that reduces the data volume to 1/8, so the read bandwidth requirement of the storage device can be Reduced to 1/8.

Optionally, as shown in FIG. 7 , the storage device provided by the embodiment of the present application may further include an image compression circuit, where the image compression circuit is configured to compress the first image frame before the first image frame is written into the storage array. When the storage device includes an image compression circuit, the first image frame data stored in the storage array may be image data compressed by the image compression circuit. It can be understood that since the image data compressed by the image compression circuit has a smaller data volume than the uncompressed original data, by storing the compressed image data in the storage array, the write bandwidth and capacity of the storage array can be further reduced , saving storage resources.

Optionally, as shown in FIG. 7 , the storage device may further include a write decoder for writing the first image frame data into the storage array. The first image frame data written into the storage array by the write decoder may be original image data, or image data compressed by an image compression circuit.

For example, as shown in FIG. 2 and FIG. 7 , the write decoder can sequentially write the 8-bit data of each pixel in the first image frame into the storage array. After the write decoder writes the 8bit data of each pixel in the first image frame into the storage array, the data of the same bit plane in the first image frame can be stored in the same row of the storage array, or can be stored in the storage array The same column can also be stored in multiple rows and/or columns of the storage array.

In the storage device provided by the embodiment of the present application, the compensation circuit and the encoding circuit are built into the storage device, so that the compensation circuit and the encoding circuit are arranged near the storage array, so that part or all of the data of a bit plane can be gated and stored in the storage device. The data of the bit plane is compensated and encoded internally, and the storage device can directly output the data of a bit plane after compensation and encoding. Compared with the scheme shown in Figure 3, which sequentially reads the data of all bits of each pixel from the memory, this scheme can gate the data of one bit plane by setting the compensation circuit and the encoding circuit close to the storage array, and can Reduce read bandwidth to 1/8. Therefore, the storage device provided by the embodiment of the present application can significantly reduce the read bandwidth, and the cost is low. And by writing the original image data or the first image frame data compressed by the compression circuit into the storage array, compared with the scheme shown in Figure 1, since the first image frame data written in the storage array has not been compensated and encoded , therefore, the amount of data written into the storage array is small, and the write bandwidth and capacity of the storage device can be reduced.

The embodiment of the present application also provides a driver chip, as shown in Figure 8, the driver chip may include the storage device shown in Figure 6 or Figure 7, and an interface circuit, the storage device is used to receive the first image through the interface circuit frame data.

Optionally, the driver chip can also include an image processing module, which can convert, adjust, and enhance the original image data to obtain the final video information stream in the RGB or YUV domain.

Optionally, as shown in Figure 8, the driver chip may also include an interface format conversion circuit and an output interface, and the interface format conversion circuit is used to perform data and frame format conversion on the data output by the storage device shown in Figure 6 or Figure 7 . The output interface is used to output the converted data to the LCOS panel to drive the liquid crystal of the LCOS panel. The output interface may include, but is not limited to, an LVDS interface. FIG. 8 only illustrates an example where the output interface is an LVDS interface. In practical applications, the type of the output interface may be related to the type of the panel, which is not limited in this embodiment of the present application.

The present application provides a method for driving a storage device. The storage device may be the storage device shown in FIG. 6 or 7. As shown in FIG. 9, the method may include the following steps:

S901. The read decoder selects the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on the read request.

The first image frame includes multiple bit planes, and the first bit plane is any one of the multiple bit planes. Compensation parameters corresponding to different data of the same bit plane in the first image frame may be the same or different. Compensation parameters corresponding to data of multiple bit planes included in the first image frame may be the same or different, which is not limited in this embodiment of the present application. For related descriptions about the first image frame data and compensation parameters, reference may be made to the foregoing embodiments, and details are not repeated here.

Optionally, the read request may include a high-order address and a low-order address, and the high-order address may be used to gate the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane. The lower bits of the address can be used to assert the select signal to enable the selector.

The read decoder in the above step S901, based on the read request, selects the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane, which may include: the read decoder selects the data based on the upper address in the read request Through the data of the first bit plane, and the compensation parameters corresponding to the data of the first bit plane.

S902. The compensation circuit compensates the data of the first bit plane based on the compensation parameter corresponding to the data of the first bit plane.

For example, as shown in FIG. 6, the multiplier and the adder in the compensation circuit can compensate and correct the data of the first bit plane based on the compensation parameters corresponding to the data of the first bit plane, so as to adjust the gain and sum of the gray levels of each pixel. Offset.

S903. The encoding circuit encodes the data of the first bit plane compensated by the compensation circuit.

For example, as shown in FIG. 6 , the encoding circuit can use a look-up table LUT to implement the encoding function, and the amount of data encoded by the LUT can be expanded to four times the original data.

S904. The selector selects and outputs the data of the first bit plane encoded by the encoding circuit.

Optionally, the selector may determine a selection signal based on the lower address in the read request, and the selection signal is used to gate the selector.

The selection signal can also be used to select the target bit-plane encoded by the encoding circuit.

For example, as shown in Figure 6, if the read decoder determines to select and output the data of the second bit plane according to the low address in the read request, the selector sequentially selects multiple rows corresponding to the data of the second bit plane The selector sequentially outputs a plurality of data corresponding to the second bit plane, so that the data of the second bit plane can be output to the LCOS panel.

Optionally, the above method may further include writing the first image frame data into the storage array based on the write request by the write decoder. The first image frame data written into the storage array by the write decoder may be original image data, or image data compressed by an image compression circuit.

In the driving method of the storage device provided by the embodiment of the present application, the compensation circuit and the encoding circuit are built in the storage device, so that the compensation circuit and the encoding circuit are arranged close to the storage array, so that part or all of the data of a bit plane can be selected, and Compensation and coding are performed on the data of the bit plane inside the storage device, and the storage device can directly output the data of a bit plane after compensation and coding. Compared with the scheme shown in FIG. 3 , which sequentially reads all the bits of data of each pixel from the memory, this scheme can reduce the read bandwidth to 1/8 by gating the data of one bit plane. Therefore, the storage device provided by the embodiment of the present application can significantly reduce the read bandwidth, and the cost is low. And by writing the original image data or the first image frame data compressed by the compression circuit into the storage array, compared with the scheme shown in Figure 1, since the first image frame data written in the storage array has not been compensated and encoded , therefore, the amount of data written into the storage array is small, and the write bandwidth and capacity of the storage device can be reduced.

The embodiment of the present application also provides a computer-readable storage medium, in which computer program code is stored. When the above-mentioned processor executes the computer program code, the electronic device executes the driving method shown in FIG. 9 .

The embodiment of the present application also provides a computer program product, which causes the computer to execute the driving method shown in FIG. 9 when the computer program product is run on the computer.

The steps of the methods or algorithms described in connection with the disclosure of this application can be implemented in the form of hardware, or can be implemented in the form of a processor executing software instructions. Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable Programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium can be located in the ASIC. In addition, the ASIC may be located in the core network interface device. Certainly, the processor and the storage medium may also exist in the core network interface device as discrete components.

Those skilled in the art should be aware that, in the above one or more examples, the functions described in the present invention may be implemented by hardware, software, firmware or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of the present invention shall be included in the protection scope of the present invention.

Claims

A storage device, characterized in that the storage device includes a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector; the storage array is used to store the first image frame data and compensation parameters, and the storage The array is coupled to the input end of the compensation circuit, the read decoder is connected to the row gate line or column gate line of the memory array, and the output end of the compensation circuit is connected to the selector through the encoding circuit The input end coupling connection;

The read decoder is configured to gate the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on a read request; the first image frame includes a plurality of bit planes, the The first bit-plane is any one of the plurality of bit-planes;

The compensation circuit is configured to compensate the data of the first bit plane based on a compensation parameter corresponding to the data of the first bit plane;

The encoding circuit is configured to encode the data of the first bit plane compensated by the compensation circuit;

The selector is configured to select and output the data of the first bit plane encoded by the encoding circuit.
The storage device according to claim 1, wherein the data of the first bit plane gated by the read decoder based on the read request is part or all of the data of the first bit plane.
The storage device according to claim 1 or 2, wherein the read request includes a first address;

The read decoder is specifically configured to select the data of the first bit plane and the compensation parameter corresponding to the data of the first bit plane based on the first address.
The storage device according to claim 3, wherein the read request further includes a second address;

The read decoder is specifically further configured to determine a selection signal based on the second address; the selection signal is used to gate the selector.
The storage device according to claim 4, wherein the selection signal is also used to select a target bit plane, and the target bit plane is a bit plane encoded by the encoding circuit;

The selector is specifically configured to select and output the target bit plane based on the selection signal.
The storage device according to any one of claims 1-5, wherein the first image frame data stored in the storage array is original data.
The storage device according to any one of claims 1-5, wherein the storage device further comprises an image compression circuit, and the image compression circuit is used to write the memory array in the first image frame Before, the first image frame is compressed.
The storage device according to claim 7, wherein the first image frame data stored in the storage array is data compressed by the image compression circuit.
A method for driving a storage device, wherein the storage device includes a storage array, a read decoder, a compensation circuit, an encoding circuit, and a selector; the storage array is used to store first image frame data and compensation parameters, The memory array is coupled to the input end of the compensation circuit, the read decoder is connected to the row gate line or the column gate line of the memory array, and the read decoder is connected to the selection end of the selector Coupling connection, the output terminal of the compensation circuit is coupled and connected with the input terminal of the selector through the encoding circuit; the method includes:

The read decoder gates the data of the first bit plane and the compensation parameters corresponding to the data of the first bit plane based on the read request; the first image frame includes a plurality of bit planes, and the first bit The plane is any bit plane in the plurality of bit planes;

The compensation circuit compensates the data of the first bit plane based on a compensation parameter corresponding to the data of the first bit plane;

The encoding circuit encodes the data of the first bit plane compensated by the compensation circuit;

The selector selects and outputs the data of the first bit plane encoded by the encoding circuit.
The method according to claim 9, wherein the data of the first bit plane gated by the read decoder based on the read request is part or all of the data of the first bit plane.
The method according to claim 9 or 10, wherein the read request includes a first address; the read decoder gates the data of the first bit plane based on the read request, and the first bit plane The corresponding compensation parameters of the data include:

The read decoding is based on the first address, gating the data of the first bit plane, and the compensation parameter corresponding to the data of the first bit plane.
The method according to claim 11, wherein the read request further comprises a second address; the method further comprises:

The read decoder determines a selection signal based on the second address; the selection signal is used to gate the selector.
The method according to claim 12, wherein the selection signal is also used to select a target bit plane, and the target bit plane is a bit plane encoded by the encoding circuit; the selector is based on the A reading request, selecting and outputting the data of the first bit plane encoded by the encoding circuit, including:

The selector selects and outputs the target bit-plane based on the selection signal.
The method according to any one of claims 9-13, wherein the first image frame data stored in the storage array is original data.
The method according to any one of claims 9-13, wherein the storage device further comprises an image compression circuit, and the method further comprises:

The image compression circuit compresses the first image frame before the first image frame is written into the storage array.
The method according to claim 15, wherein the first image frame data stored in the storage array is data compressed by the image compression circuit.
A driver chip, characterized in that the driver chip includes an interface circuit, and the storage device according to any one of claims 1-8, the storage device is used to receive the first Image frame data.