WO2023035850A1 - 一种高速串行链路测试方法及装置 - Google Patents

一种高速串行链路测试方法及装置 Download PDF

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Publication number
WO2023035850A1
WO2023035850A1 PCT/CN2022/111882 CN2022111882W WO2023035850A1 WO 2023035850 A1 WO2023035850 A1 WO 2023035850A1 CN 2022111882 W CN2022111882 W CN 2022111882W WO 2023035850 A1 WO2023035850 A1 WO 2023035850A1
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test
code stream
device under
test code
under test
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PCT/CN2022/111882
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English (en)
French (fr)
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罗军平
潘伟
虞澜
李建康
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华为技术有限公司
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Publication of WO2023035850A1 publication Critical patent/WO2023035850A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Definitions

  • the present application relates to the technical field of communications, and in particular to a high-speed serial link testing method and device.
  • the receiving compliance test is used to test the receiving performance of the interface in the device and the transmission performance of the communication link connected to the interface. By analyzing whether the bit error rate of the bit stream received by the device meets the requirements, the receiving performance of the interface in the device is determined. Performance and the transmission performance of the communication link connected to the interface (especially the channel in the communication link that transmits data to the interface).
  • the bit error tester can send the test code stream to the device under test. After the device under test receives the test code stream through the receiver of the interface, it will feed back the test code stream through the transmitter of the interface. To the bit error tester, the bit error tester obtains the test result of the receiving compliance test by comparing the sent test bit stream with the received test bit stream. It can be seen that the reception compliance test relies on the loop between the device under test and the bit error tester. Since the test bit stream needs to be transmitted back from the device under test to the bit error tester, it is easy to introduce bit errors during this process, which makes the test results obtained by the bit error tester wrong, and the accuracy of the receiving compliance test is poor.
  • the present application provides a high-speed serial link testing method and device for improving the accuracy of receiving compliance testing.
  • the embodiment of the present application provides a high-speed serial link testing method, which can be used to test the receiver of the high-speed serial interface in the device under test.
  • the device under test can pass The receiver receives the first test code stream sent by the test equipment. After the device under test receives the first test code stream, it can obtain test results by analyzing the first test code stream and the reference test code stream. The test results can characterize the receiving performance of the high-speed serial interface and the connection with the high-speed serial interface The transmission performance of the communication link, the reference test stream is pre-configured.
  • the device under test can analyze the first test code stream and the reference test code stream by itself to obtain test results. It is no longer necessary to feed back the received first test code stream to the test equipment, and the test equipment obtains the test results.
  • the first test code stream does not need to be fed back to the test equipment through a loop, which reduces the error caused by the first test code stream. Probability, to ensure the accuracy of the test.
  • the device under test also has a display function, capable of displaying the determined test results.
  • the user can know the test result in time and improve the user experience.
  • the device under test may also send the test result to the test device through a transmitter of a high-speed serial interface.
  • the test equipment can accurately obtain the test result without performing analysis.
  • the test result may be the number of difference bits in the first test code stream, and the number of difference bits indicates the number of bits that differ between the first test code stream and the reference test code stream.
  • the test result may also be the bit error rate of the first test code stream, and the bit error rate may be equal to the ratio of the number of difference bits to the total number of bits in the first test code stream.
  • the expression form of the test result is more flexible and applicable to different scenarios.
  • the reference test code stream may be pre-configured for the device under test.
  • the reference test stream is the default and is already configured on the device under test.
  • the reference test code stream may also be notified by the test device to the test device.
  • the device under test may store a set of reference test code streams, and the reference test code stream set may include multiple different reference test code streams. Each reference test stream corresponds to an identifier. The identifiers corresponding to different reference test code streams are different.
  • the test device can send the identifier of the reference test code stream to the test device, and after the device under test obtains the identifier of the reference test code stream from the test device, it can determine the ID corresponding to the reference test code stream from the set of reference test code streams according to the identifier of the reference test code stream. Refer to the test stream.
  • the reference test code stream can be pre-configured in the device under test in different ways, which effectively expands the application scenarios.
  • the device under test before the device under test receives the first test code stream sent by the test device through the receiver, it can also perform a self-test on the device under test to determine whether the device under test has a code error detection function, or That is, whether the difference bits of the code stream can be accurately identified.
  • the test device may send a second test code stream (also referred to as a self-test code stream in an embodiment) to the device under test, and the second test code stream may include a target number of difference bits. After the device under test receives the second test code stream through the receiver, it can determine the number of difference bits in the second test code stream.
  • the test device may not send the first test code stream to the device under test.
  • the self-inspection of the device under test can ensure that the subsequent test results are relatively reliable and accurate.
  • the test device when the test device sends the first test code stream to the device under test, it may use different transmission rates to send the first test code stream. That is, the device under test may receive the first test code stream test sent by the test device at different transmission rates through the receiver. In this way, the receiving performance of the high-speed serial interface of the device under test and the transmission performance of the communication link connected with the high-speed serial interface can be tested under different transmission rates.
  • test results under different transmission rates can be obtained to ensure the integrity of the test.
  • the test device may also notify the transmission rate of the first test code stream. For example, the test device may send a notification message to the device under test, and the notification message may indicate the transmission rate of the first test code stream.
  • the device under test may receive the notification message, and determine the transmission rate of the first test code stream according to the notification message.
  • the transmission rate may also be displayed to indicate that the test result is a test result at the transmission rate.
  • the device under test can receive the first test code stream at a corresponding rate by determining the transmission rate of the first test code stream, so as to accurately analyze the first test code stream and the reference test code stream, and obtain Test Results.
  • the embodiment of the present application also provides a link test device, which has the function of realizing the behavior in the method example of the first aspect above, and for the beneficial effect, please refer to the description of the first aspect here No longer.
  • the functions described above may be implemented by hardware, or may be implemented by executing corresponding software on the hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the structure of the link test device includes a receiving module, an analyzing module, and optionally a display module and a sending module, and these modules can perform corresponding functions in the method example of the first aspect above, For details, refer to the detailed description in the method example, and details are not repeated here.
  • the embodiment of the present application also provides a computing device, the computing device has the function of implementing the behavior in the method example of the first aspect above, and the beneficial effects can be referred to the description of the first aspect, which will not be repeated here.
  • the structure of the computing device includes a processor and a memory, and the processor is configured to support the computing device to perform corresponding functions in the method of the first aspect above.
  • the memory coupled to the processor, holds program instructions and data necessary for the computing device.
  • the structure of the computing device also includes a communication interface for communicating with other devices, such as sending the first test code stream and the second test code stream, and receiving test results.
  • the present application also provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes the above-mentioned first aspect and each possibility of the first aspect.
  • the present application further provides a computer program product including instructions, which, when run on a computer, cause the computer to execute the method described in the above first aspect and each possible implementation manner of the first aspect.
  • the present application also provides a computer chip, the chip is connected to the memory, and the chip is used to read and execute the software program stored in the memory, and implement the above first aspect and each possibility of the first aspect.
  • FIG. 1 is a schematic diagram of an eye diagram
  • Fig. 2 is a test schematic diagram of a compliance test
  • FIG. 3 is a schematic structural diagram of a system provided by the present application.
  • Fig. 4 is a schematic diagram of a high-speed serial link testing method provided by the present application.
  • FIG. 5 is a schematic structural diagram of a link test device provided by the present application.
  • FIG. 6 is a schematic structural diagram of a computing device provided by the present application.
  • the code stream can be a signal stream composed of a series of analog signals (such as high and low levels), or a signal stream composed of a series of digital signals (such as 0, 1).
  • the acceptance compliance test is one of the high-speed link signal quality certification tests.
  • the reception compliance test tests the reception performance of the interface under test in the device under test and the transmission performance of the communication link connected to the interface under test.
  • the communication link connected to the interface under test may include two types of channels, one is a channel for transmitting code streams to the interface under test. The other is a channel used to transmit data sent by the interface under test.
  • the transmission performance of the communication link tested by the compliance test mainly focuses on the transmission performance of the channel used to transmit data to the interface under test in the communication link.
  • the acceptance compliance test by judging whether the bit stream received by the tested interface meets the requirements of the bit error rate, such as determining whether the number of different bits in the received bit stream or the bit error rate is lower than the threshold, to evaluate the interface under test Whether the receiver can accurately receive the bit stream and whether the communication link can introduce fewer bit errors and accurately transmit the bit stream to the interface under test.
  • the test equipment such as a bit error tester
  • the communication link such as the signal can form the smallest eye diagram.
  • the code stream received by the interface determines whether the code stream meets the requirements of the signal error rate.
  • the eye diagram is to superimpose a series of signals together to form an eye-like image.
  • the eye diagram can usually be displayed on an oscilloscope to analyze whether the signal meets the standard.
  • FIG. 1 it is a schematic diagram of an eye diagram.
  • the part of the black line is the eye diagram displayed on the oscilloscope. Shaded areas may be referred to as non-standard areas.
  • the non-standard area is the area that the eye diagram cannot touch. If the eye diagram touches the shaded area, it means that the signal forming the eye diagram is not up to standard.
  • the eye diagram formed by the signal sent by the test equipment needs to meet the standard. For different types of communication links and different transmission rates, the standards that the eye diagram needs to meet may be different.
  • the transmission code stream compliance test (Tx Compliance test) at different transmission rates
  • PCIe peripheral component interconnect express
  • SATA serial advanced technology attachment
  • Tx Compliance test the transmission code stream compliance test
  • the eye diagram formed by the signal sent by the test equipment can be the minimum eye diagram.
  • the so-called minimum eye diagram refers to the eye diagram that does not touch the shadow area and is adjacent to the shadow area.
  • FIG. 2 it is a schematic structural diagram of a test system for receiving a compliance test, and the test system includes a bit error tester and a device under test.
  • the device under test can be mounted on the test board.
  • the bit error tester can send out the test code stream, and can also compare the code stream fed back by the device under test with the sent test code stream to determine the number of differences between the feedback code stream and the sent test code stream.
  • the difference bits refer to bits that are different between the fed-back code stream and the sent code stream. Then determine whether the interface of the device under test and the communication link connected to the interface pass the receiving compliance test based on the number of difference bits, and also display the test results, such as displaying the number of difference bits, or whether it passes the receiving compliance test.
  • the device under test can be any device with a high-speed serial interface.
  • the bit error tester can establish a communication channel with the device under test.
  • Calibration is required before the interface of the device under test is subjected to receive compliance testing.
  • This calibration includes the following operations:
  • Operation 1 Establish channel 1 between the bit error tester and the receiver of the interface of the device under test.
  • the length of the channel 1 is the maximum length allowed by the standard.
  • the bit error tester can send the test code stream that can form the smallest eye diagram at the test point through the channel 1, that is, at the interface of the device under test.
  • the formal testing process can be entered.
  • the receiver and transmitter of the interface of the device under test may form an internal loop during the test.
  • the bit error tester can also be connected to the transmitter of the interface through another channel 2 (the length of the channel 2 may be shorter than the channel 1 between the bit error tester and the receiver of the interface of the device under test).
  • the bit error tester can send the test bit stream to the device under test through the channel 1 between the receiver of the interface.
  • the test code stream received by the interface port in the interface can be transmitted to the transmitter through the internal loop, and then the test code stream received by the interface is sent to the bit error tester through the transmitter.
  • the bit error tester can compare the test code stream fed back by the device under test with the test code stream sent out to obtain the test result, that is, to display the number of different bits in the test code stream fed back by the device under test.
  • the receiving compliance test is currently implemented through the loop between the device under test and the bit error tester.
  • the detection result of the bit error tester is not only related to channel 1, but also related to the internal loop of the device under test and the channel 2 related.
  • the internal loop or channel 2 may introduce bit errors, resulting in inaccurate test results of the bit error tester and affecting the accuracy of the reception compliance test.
  • the receiving compliance test is a test mentioned in some high-speed serial link standards (such as PCIe or SATA).
  • the test used to evaluate the reception performance of the interface and the transmission performance of the communication link connected to the interface in other communication link standards may also be called by other names.
  • This application only provides a test idea for evaluating the receiving performance of the interface and the transmission performance of the communication link connected to the interface. This test idea can be used in the receiving compliance test, and can also be used in other tests .
  • the acceptance compliance test is taken as an example for illustration.
  • FIG. 3 is a schematic structural diagram of a system provided by the embodiment of the present application.
  • the system includes The test device 200 and the device under test 100 .
  • the device under test 100 has a test interface 110 , the test interface 110 may be a high-speed serial interface, and the test interface 110 includes a receiver 111 and a transmitter 112 .
  • the device under test 100 has a bit error detection function, and can determine the bit error status of the bit stream by analyzing the bit stream obtained by the receiver 111 of the interface under test 110 (such as a test bit stream and a self-check bit stream), such as Determine the number of difference bits or bit error rate in the received code stream, where the number of difference bits refers to the number of bits that differ between the received code stream and the code stream sent by the actual testing device 200 .
  • the bit error rate is equal to the ratio of the number of difference bits to the total number of bits of the received code stream.
  • the reception performance of the interface under test 110 and the transmission performance of the communication link connected to the interface under test 110 are evaluated through the bit error status of the code stream.
  • the device under test 100 may also display the determined bit error status of the code stream, and the embodiment of the present application does not limit the manner in which the device under test 100 displays the determined bit error status of the code stream.
  • the device under test 100 may also have a display function.
  • the device under test 100 may include a display component 120, such as a display screen, and the display component 120 can display the bit error status determined by the device under test 100, such as displaying the number of different bits or the bit error rate in the received code stream.
  • the device under test 100 may also have a voice broadcast function.
  • the device under test 100 may include a voice playback component 130, such as a loudspeaker, and the voice playback component 130 can voice prompt the bit error status determined by the device under test 100, such as the number of different bits or the error rate in the received test code stream. code rate.
  • the device under test 100 may also have a file printing function.
  • the device under test 100 may include a printing component 140, and the printing component 140 can print the bit error status determined by the device under test 100 on paper, such as printing the number of different bits or the bit error rate in the received code stream on the On the paper, the user can determine the bit error status determined by the device under test 100 through the paper.
  • the device under test 100 may also feed back the bit error status of the determined code stream to the test device 200, for example, a feedback channel is established between the transmitter 112 of the interface under test 110 and the test device 200, through which the The determined bit error status of the bit stream is fed back to the testing device 200 .
  • the test device 200 is a device that can send a specific test code stream.
  • the embodiment of the present application does not limit the type of the test device 200.
  • the test device 200 may be a bit error tester or a pattern generator. Any equipment that can send code streams can be used as the test equipment 200.
  • Three kinds of channels can be established between the device under test 100 and the testing device 200 , which are a self-test channel for self-test, a test channel and a feedback channel. Wherein, the length of the test channel may be greater than that of the self-test channel.
  • the self-test channel communicates with the test device 200 and the receiver 111 of the interface under test 110 .
  • the test device 200 may send a self-test code stream to the device under test 100 through the self-test channel.
  • the test channel communicates with the test device 200 and the receiver 111 of the interface under test 110 .
  • the test device 200 may send a test code stream to the device under test 100 through the test channel.
  • the self-test channel can be released first.
  • the self-test channel and the test channel can be two channels with different lengths.
  • the self-test channel can be a channel with a smaller length, so as to ensure that the self-test code stream will not introduce bit errors during transmission.
  • the test channel can be a long channel to ensure the accuracy of the compliance test.
  • the length of the test channel may be the maximum length specified by the standard. The embodiment of the present application does not limit the specific value of the maximum length. In some standards, the maximum length of the channel can be specified by the transmission loss of the signal. For example, it is required to transmit at 16 giga transmission per second (GT/s ), the transmission loss of the signal shall not exceed 20 decibels.
  • the self-test channel and the test channel may also be the same channel, that is, the channel is usually used to transmit both the self-test code stream and the test code stream.
  • the feedback channel connects the testing device 200 with the transmitter 112 of the interface under test 110 .
  • the device under test 100 may send the bit error status of the code stream to the test device 200 through the feedback channel, such as the number of different bits in the code stream (such as the self-test code stream or the test code stream).
  • the device under test 100 can analyze the test code stream received from the test device 200 and the pre-configured reference test code stream by itself, and obtain the test results to further determine
  • the receiving performance of the interface under test 110 and the transmission performance of the communication link connected to the interface under test 110, that is, the device under test 100 can implement the receiving compliance test and obtain the test results by itself, without feeding back the received test code stream
  • the testing equipment 200 analyzes and obtains the test results. It effectively reduces the bit errors that may be introduced during the test process and ensures the accuracy of the test results.
  • the high-speed serial link test method provided by the embodiment of the present application will be described below in conjunction with accompanying drawing 4.
  • the method includes two parts, one part is the self-test process of the device under test 100, and the device under test 100 is determined through the self-test process. Whether it has a bit error detection function, and whether it can accurately analyze the bit error state of the received code stream (see step 401 to step 403).
  • the other part is the testing process of the device under test 100 (see step 404 to step 407).
  • Step 401 Build a self-test channel between the test device 200 and the interface 110 of the device under test 100 , the self-test channel can connect the device under test 100 and the receiver 111 of the device under test 100 .
  • the length of the self-inspection channel can be as small as possible, and the self-inspection channel with a smaller length can effectively avoid bit errors that may be introduced later when transmitting the self-inspection code stream.
  • Step 402 the test device 200 sends a self-test code stream to the interface under test 110 of the device under test 100 through the self-test channel.
  • the self-check code stream includes a target number of difference bits. These difference bits may be randomly added by the test device 200 into the original code stream, and the original code stream may be a code stream known by the device under test 100 and the test device 200 . If the original code stream can be pre-configured in the device under test 100 .
  • Step 403 The device under test 100 obtains the self-test code stream from the interface under test 110, and determines the number of difference bits in the self-test code stream.
  • the device under test 100 can compare the self-test code stream with the original code stream, and determine the number of difference bits in the self-test code stream.
  • the device under test 100 may exhibit the determined number of difference bits.
  • step 404 can be executed.
  • the number of difference bits is taken as an example.
  • the device under test 100 can also determine the bit error rate of the self-test bit stream, that is, the bit error rate is obtained by the ratio of the difference bit number to the total number of bits of the self-test bit stream, Determine whether the bit error rate is equal to the ratio of the target number to the total number of bits in the self-test bitstream.
  • Step 404 Build a test channel before the test device 200 and the interface 110 of the device under test 100, the test channel can connect the device under test 100 and the receiver 111 of the device under test 100, and ensure that the transmitted signal passes through the The test channel is capable of forming a minimum eye diagram at the device under test 100 .
  • the length of the test channel can be as long as possible, and the test channel with a longer length increases the transmission path of the test code stream to a certain extent, which can greatly increase the probability of introducing bit errors in the test code stream. , the test code stream received by the interface under test 110 in the device under test 100 can still meet the bit error rate requirement, indicating that the receiving performance of the interface under test 110 is better, effectively ensuring the accuracy of the test results.
  • the length of the test channel can be the maximum length allowed by the standard.
  • test code stream received by the interface under test 110 in the device under test 100 can still meet the bit error rate requirement when sending a signal capable of forming the smallest eye diagram, then in the case of sending other standards-compliant signals In this case, the test code stream received by the interface under test 110 can also meet the bit error rate requirement.
  • Step 405 the test device 200 sends a test code stream to the interface under test 110 of the device under test 100 through the test channel.
  • test device 200 When the test device 200 sends the test code stream to the device under test 100, it can add a code stream start flag before the test code stream.
  • the code stream after the start flag of the code stream is the test code stream.
  • the first value may be pre-agreed.
  • the device under test 100 After the device under test 100 detects the start flag of the code stream through the interface under test 110 , it receives the test code stream. After the test code stream is sent, the test device 200 may also add a code stream end mark after the test code stream. Similar to the code stream start flag, the code stream end flag can be a bit with a second value. The code stream end flag marks the end of the test code stream, and there is no subsequent test code stream.
  • Step 406 The device under test 100 obtains the test code stream from the interface under test 110, analyzes the test code stream and the reference test code stream to obtain test results, such as determining the number of different bits in the test code stream or the error of the test code stream code rate.
  • the device under test 100 can compare the test code stream and the reference test code stream to determine the number of different bits in the test code stream or the bit error rate of the test code stream.
  • the reference test code stream can be Pre-configured, for example, the test device 200 may notify the device under test 100 in advance, or it may be a default setting.
  • the embodiment of the present application does not limit the manner in which the test device 200 notifies the device under test 100 of the reference test code stream in advance.
  • a set of reference test code streams may be stored in the device under test 100, and the reference test code streams include multiple different reference test code streams.
  • Each reference test code stream is provided with an identifier, and different reference test code streams have different identifiers, and one identifier corresponds to one reference test code stream.
  • the test device 200 may first send the identifier of the reference test code stream to the device under test 100 .
  • the device under test 100 obtains the reference test code stream corresponding to the identifier from the set of reference test code streams by referring to the identifier of the test code stream, for comparison with the received test code stream.
  • test device 200 can also send the reference test code stream to the test device 200 in advance, such as the test device 200 can send the reference test code stream to the test device 200 through the self-test channel established before, so as to avoid Unnecessary bit errors are introduced into the stream.
  • the reference test code stream is default and has been configured in the test device 200 .
  • Step 407 The device under test 100 displays the test results, such as the number of different bits or the bit error rate, or feeds back the test results to the test device 200 .
  • the test result is the number of difference bits as an example.
  • the display and feedback method of the bit error rate are similar to the display and feedback method of the number of difference bits, and will not be repeated here.
  • the device under test 100 may also store the test result.
  • the device under test 100 can display the difference bit number through the display component 120, can also play the difference bit number through the voice playback component 130, or can print the difference bit number on paper through the printing component 140, so that the user can know the test result .
  • a feedback channel is set up between the test device 200 and the transmitter 112 of the interface under test 110, and the device under test 100 can feed back the determined difference bit number to the test device 200 through the feedback channel, and the test device 200 receives the difference bit number After that, the number of difference bits received can be displayed.
  • the transmission rate of the code stream will also be a factor for introducing bit errors into the code stream.
  • the transmission rate of the bit stream is too high, the intervals between the signals in the bit stream are small, and there is likely to be interference with each other, and bit errors are likely to occur.
  • tests can be performed at different transmission rates.
  • test code streams may be sent at different transmission rates to obtain detection results at different transmission rates, that is, to determine the number of different bits in the test code streams at different transmission rates.
  • the initial transmission rate and the switching manner of the transmission rate may be pre-agreed between the device under test 100 and the test device 200 .
  • the transmission rate can be the lowest transmission rate, such as 4GT/s, and then the transmission rate can be gradually increased.
  • the transmission rate can be the highest transmission rate, such as 64GT/s, and then the transmission rate can be gradually reduced.
  • the test device 200 may notify the device under test 100 of the need to switch the transmission rate by sending a notification message, and may also notify the device under test 100 of a specific value of the transmission rate after switching.
  • the test device 200 and the device under test 100 may also agree on the duration of the compliance test at each transmission rate, and switch to the next transmission rate after reaching the agreed time period, and send the test code stream at this transmission rate.
  • the device under test 100 may also mark the transmission rate to indicate that the test result is the test result at the transmission rate.
  • the device under test 100 presents the test result to the test device 200 , it may also mark the transmission rate to indicate that the test result is the test result at the transmission rate.
  • the embodiment of the present application also provides a link test device, which is used to execute the method performed by the device under test described in the method embodiment shown in Figure 4
  • a link test device which is used to execute the method performed by the device under test described in the method embodiment shown in Figure 4
  • the link test device 500 can test the receiver of the high-speed serial interface in the device under test, and the link test device 500 is deployed on the device under test 100 .
  • the link testing device 500 includes a receiving module 501 and an analyzing module 502 .
  • the receiving module 501 is configured to receive the first test code stream sent by the test equipment through a receiver.
  • the analysis module 502 is configured to obtain test results by analyzing the first test code stream and the reference test code stream, and the test results are used to characterize the receiving performance of the high-speed serial interface and the transmission performance of the communication link connected to the high-speed serial interface, Reference test streams are pre-configured.
  • the link test device 500 further includes a display module 503 .
  • the display module 503 can display test results.
  • the link testing device 500 further includes a sending module 504 .
  • the sending module 504 can send the test result to the test equipment through the sender of the high-speed serial interface.
  • the test result is the number of different bits existing in the first test code stream or the bit error rate of the first test code stream.
  • the reference test code stream is pre-configured for the link test device 500 .
  • the parameter test stream is default and has been configured in the link test device 500 .
  • the reference test code stream may be notified by the test equipment to the link test apparatus 500 .
  • the receiving module 501 can obtain the identification of the reference test code stream from the test device; afterward, the analysis module 502 determines the corresponding reference test code stream from the set of reference test code streams according to the identification of the reference test code stream, and the reference test code stream includes multiple Different reference test code streams, each reference test code stream corresponds to an identifier.
  • the receiving module 501 may also receive the second test code stream sent by the test device through the receiver, and the second test code stream A target number of difference bits are included in the stream.
  • the analysis module 502 can determine the number of difference bits in the second test code stream, wherein the number of difference bits in the second test code stream is equal to the target number.
  • the receiving module 501 when the receiving module 501 receives the first test code stream sent by the test device through the receiver, it may receive the first test code stream sent by the test device at different transmission rates through the receiver.
  • the receiving module 501 may also acquire a notification message sent by the test device, where the notification message is used to indicate the transmission rate of the first test code stream.
  • each functional module in the embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the above-mentioned embodiments may be implemented in whole or in part by software, hardware, firmware or other arbitrary combinations.
  • the above-described embodiments may be implemented in whole or in part in the form of computer program products.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on the computer, the processes or functions according to the embodiments of the present invention will be generated in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state drive (SSD).
  • the management device 600 shown in FIG. 6 includes at least one processor 601, a memory 602, and optionally, a communication interface 603.
  • the communication interface 603 may also be called a high-speed serial interface or interface.
  • the memory 602 can be a volatile memory, such as a random access memory; the memory can also be a nonvolatile memory, such as a read-only memory, a flash memory, a hard disk (hard disk drive, HDD) or a solid-state drive (solid-state drive, SSD), or memory 602 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.
  • the memory 602 may be a combination of the above-mentioned memories.
  • connection medium between the processor 601 and the memory 602 is not limited in this embodiment of the present application.
  • Processor 601 can be central processing unit (central processing unit, CPU), and this processor 601 can also be other general processors, digital signal processor (digital signal processor, DSP), application specific integrated circuit (application specific integrated circuit, ASIC) ), field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, artificial intelligence chips, chip-on-chip, etc.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the processor 601 in FIG. 6 may execute the method performed by the device under test in any one of the above method embodiments.
  • the function/implementation process of the analysis module 502 and the display module 503 in FIG. 5 can be implemented by calling the computer execution instructions stored in the memory 602 by the processor 601 in FIG.
  • the function/implementation process can be realized through the communication interface 603 in FIG. 6 .
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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Abstract

一种高速串行链路测试方法及装置，本申请中，被测设备可以通过接收器接收测试设备发送的第一测试码流。在接收到第一测试码流后，被测设备通过分析第一测试码流和参考测试码流获取测试结果，该测试结果能够表征高速串行接口的接收性能、以及与高速串行接口连接的通信链路的传输性能，参考测试码流是预先配置的。被测设备能够自行分析第一测试码流和参考测试码流，获得测试结果。不再需要将接收到的第一测试码流反馈至测试设备，由测试设备获得测试结果，第一测试码流不需要再通过回路反馈给测试设备，减少了第一测试码流引入误码的概率，保证了测试的准确性。

Description

一种高速串行链路测试方法及装置
相关申请的交叉引用
本申请要求在2021年09月09日提交中国专利局、申请号为202111056149.8、申请名称为“一种高速串行链路测试方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种高速串行链路测试方法及装置。
背景技术
接收遵从性测试用于对设备中接口的接收性能以及与该接口连接的通信链路的传输性能进行测试，通过分析设备所接收的码流误码率是否满足要求，来判定设备中接口的接收性能以及与该接口连接的通信链路(尤其是通信链路中向该接口传输数据的通道)的传输性能。
目前，在进行接收遵从性测试时，误码测试仪可以向被测设备发送测试码流，被测设备通过接口的接收器接收到测试码流后，再通过接口的发送器将测试码流反馈至误码测试仪，误码测试仪通过比较发送的测试码流以及接收到的测试码流获得接收遵从性测试的测试结果。可见，接收遵从性测试依赖于被测设备与误码测试仪之间的回路。由于测试码流需要从被测设备再传回至误码测试仪，在这个过程中容易引入误码，使得误码测试仪所获得的测试结果存在错误，接收遵从性测试的准确性较差。
发明内容
本申请提供一种高速串行链路测试方法及装置，用以提高接收遵从性测试的准确性。
第一方面，本申请实施例提供了一种高速串行链路测试方法，该方法可以用于对被测设备中高速串行接口的接收器进行测试，在该方法中，被测设备可以通过接收器接收测试设备发送的第一测试码流。被测设备在接收到第一测试码流后，可以通过分析第一测试码流和参考测试码流获取测试结果，该测试结果能够表征高速串行接口的接收性能、以及与高速串行接口连接的通信链路的传输性能，参考测试码流是预先配置的。
通过上述方法，被测设备能够自行分析第一测试码流和参考测试码流，获得测试结果。不再需要将接收到的第一测试码流反馈至测试设备，由测试设备获得测试结果，第一测试码流不需要再通过回路反馈给测试设备，减少了第一测试码流引入误码的概率，保证了测试的准确性。
在一种可能的实施方式中，被测设备还具备展示功能，能够展示所确定测试结果。
通过上述方法，通过展示该测试结果，能够使得用户能够及时了解测试结果，提升用户体验。
在一种可能的实施方式中，被测设备还可以通过高速串行接口的发送器向测试设备发送测试结果。
通过上述方法，通过将测试结果反馈给测试设备，测试设备不需进行分析就可以准确地获知该测试结果。
在一种可能的实施方式中，测试结果的表现形式有很多种。测试结果可以为第一测试码流中存在的差异比特数，差异比特数指示第一测试码流中与参考测试码流中存在差异的比特的数量。测试结果还可以为第一测试码流的误码率，该误码率可以等于差异比特数与第一测试码流中总比特数的比值。
通过上述方法，测试结果的表现形式较为灵活，适用于不同的场景。
在一种可能的实施方式中，该参考测试码流可以是预先配置给被测设备的。例如，该参考测试码流是默认的，并且已配置在被测设备上了。又例如，该参考测试码流也可以是测试设备通知给测试设备的。被测设备中可以保存有参考测试码流集合，该参考测试码流集合中可以包括多个不同的参考测试码流。每个参考测试码流对应一个标识。不同参考测试码流所对应的标识不同。测试设备可以向测试设备发送该参考测试码流的标识，被测设备在从测试设备获取参考测试码流的标识后，可以根据参考测试码流的标识从参考测试码流集合中确定标识对应的参考测试码流。
通过上述方法，该参考测试码流可以采用不同的方式预先配置到被测设备中，有效地拓展了应用场景。
在一种可能的实施方式中，被测设备在通过接收器接收测试设备发送的第一测试码流之前，还可以对被测设备进行自检，确定被测设备是否具备误码检测功能，也即是否能够准确识别出码流的差异比特。在自检时，测试设备可以向被测设备发送第二测试码流(在实施例中也可以称为自检码流)，该第二测试码流中可以包括目标数量的差异比特。被测设备通过接收器接收到该第二测试码流后，可以确定第二测试码流中差异比特数，若第二测试码流中差异比特数等于目标数量，则说明自检通过，测试设备可以向被测设备发送第一测试码流。若第二测试码流中差异比特数不等于目标数量，则说明自检失败，测试设备可以不向被测设备发送第一测试码流。
通过上述方法，对被测设备进行自检，能够保证后续测试结果较为可靠、准确。
在一种可能的实施方式中，测试设备在向被测设备发送第一测试码流时，可以采用不同的传输速率发送第一测试码流。也即，被测设备可以通过接收器接收测试设备以不同传输速率发送的第一测试码流测试。这样能够测试不同传输速率下，被测设备的高速串行接口的接收性能以及与高速串行接口连接的通信链路的传输性能。
通过上述方法，可以获得不同传输速率下的测试结果，保证测试的完整性。
在一种可能的实施方式中，测试设备在向被测设备发送第一测试码流之前，还可以通知该第一测试码流的传输速率。例如测试设备可以向被测设备发送通知消息，该通知消息可以指示第一测试码流的传输速率。被测设备可以接收该通知消息，根据该通知消息确定该第一测试码流的传输速率。当后续展示测试结果时，还可以展示该传输速率，以指示该测试结果为该传输速率下的测试结果。
通过上述方法，被测设备通过确定第一测试码流的传输速率，能够以相应的速率接收该第一测试码流，以便能够准确的对第一测试码流和参考测试码流进行分析，获得测试结果。
第二方面，本申请实施例还提供了一种链路测试装置，该链路测试装置具有实现上述第以第一方面的方法实例中行为的功能，有益效果可以参见第一方面的描述此处不再赘述。 所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。在一个可能的设计中，所述链路测试装置的结构中包括接收模块、分析模块，可选的，还包括展示模块、发送模块，这些模块可以执行上述第一方面方法示例中的相应功能，具体参见方法示例中的详细描述，此处不做赘述。
第三方面，本申请实施例还提供了一种计算设备，该计算设备具有实现上述第一方面的方法实例中行为的功能，有益效果可以参见第一方面的描述此处不再赘述。所述计算设备的结构中包括处理器和存储器，所述处理器被配置为支持所述计算设备执行上述第一方面方法中相应的功能。所述存储器与所述处理器耦合，其保存所述计算设备必要的程序指令和数据。所述计算设备的结构中还包括通信接口，用于与其他设备进行通信，如可以发送第一测试码流、第二测试码流，接收测试结果。
第四方面，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
第五方面，本申请还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
第六方面，本申请还提供一种计算机芯片，所述芯片与存储器相连，所述芯片用于读取并执行所述存储器中存储的软件程序，执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
附图说明
图1为一种眼图的示意图；
图2为一种接受遵从性测试的测试示意图；
图3为本申请提供的一种系统结构示意图；
图4为本申请提供的一种高速串行链路测试方法示意图；
图5为本申请提供的一种链路测试装置的结构示意图；
图6为本申请提供的一种计算设备的结构示意图。
具体实施方式
在对本申请实施例所提供的一种高速串行链路测试方法以及设备说明之前，先对本申请实施例所涉及的概念进行说明：
1、码流。
连续发送的多个信号可以形成码流。码流可以是有一连串模拟信号(如高低电平)组成的信号流，也可以为一连数字信号(如0、1)组成的信号流。
2、接受遵从性测试(Rx Compliance Test)。
接受遵从性测试是高速链路信号质量认证测试中的一种，接收遵从性测试所测试的是被测设备中被测接口的接收性能以及与该被测接口连接的通信链路的传输性能。
需要说明的，与该被测接口连接的通信链路可以包括两种类型的通道，一种为用于向该被测接口传输码流的通道。另一种为用于将该被测接口发送的数据传输出去的通道。接受遵从性测试所测试的通信链路的传输性能，主要侧重在该通信链路中用于向该被测接口 传输数据的通道的传输性能。
在接受遵从性测试中通过判断被测接口所接收的码流是否满足误码率的要求，如确定所接收的码流中差异比特数或误码率是否低于阈值，来评估被测接口中接收器是否能够准确接收码流以及通信链路是否能够较少引入误码、准确的将码流传输至被测接口。在接收遵从性测试中测试设备(如误码测试仪)可以通过通信链路向被测设备的接口发送符合规范要求的码流(如该信号能够形成最小眼图)，通过分析被测设备的接口所接收的码流确定该码流是否满足信号误码率的要求。
3、眼图。
眼图是把一连串信号叠加在一起，形成一个类似眼睛的图像，眼图通常可以被展示在示波器中，用来分析信号是否满足标准。
参见图1，为一种眼图的示意图。其中黑色线条的部分即为在示波器上所展示的眼图。阴影区域可以称为非标准区。非标准区是眼图不能接触的区域。若眼图接触到该阴影区域则说明形成该眼图的信号是不符合标准的。在接受遵从性测试中，测试设备发送的信号所形成的眼图需要满足标准。对于不同类型的通信链路以及不同的传输速率，眼图所需满足的标准可以不同。例如，对于高速串行计算机扩展总线(peripheral component interconnect express，PCIe)、以及串行高级技术附件(serial advanced technology attachment，SATA)总线中不同传输速率下的发送码流遵从性测试(Tx Compliance test)中会规定眼图需要满足的标准，如不同传输速率下眼图的高度以及宽度。
另外，为了保证接受遵从性测试的准确性，测试设备发送的信号所形成的眼图可以为最小眼图，所谓最小眼图是指未接触该阴影区域，且与该阴影区域临近的眼图。
下面对接收遵从性测试的过程进行说明：
如图2所示，为接收遵从性测试的测试系统结构示意图，该测试系统中包括误码测试仪以及被测设备。被测设备可以安装在测试板上。
误码测试仪能够发出测试码流，还能够通过对被测设备反馈的码流以及所发出的测试码流进行比对，确定反馈的码流相对于所发出的测试码流的差异比特数，其中，差异比特是指反馈的码流以及所发出的码流之间存在差异的比特。进而通过该差异比特数确定被测设备的接口以及该接口连接的通信链路是否通过接收遵从性测试，还可以展示测试结果，如展示差异比特数、或是否通过接收遵从性测试。
被测设备可以是任意具备高速串行接口的设备。误码测试仪可以与被测设备建立用于通信的通道。
在被测设备的接口进行接收遵从性测试之前，需要先进行校准。
该校准包括如下操作：
操作一、在误码测试仪与被测设备接口的接收器之间建立通道1。该通道1的长度为标准允许范围内的最大长度。
操作二、误码测试仪通过该通道1在测试点处，也即被测设备接口处，可以发送能够形成最小眼图的测试码流。
在校准之后，可以进入正式的测试过程。在测试时被测设备的接口的接收器和发送器可以构成内部回路。误码测试仪还可以通过另外一条通道2(该通道2的长度可以小于误码测试仪与被测设备接口的接收器之间的通道1)连接接口的发送器。在测试的过程中，误码测试仪可以通过与接口的接收器之间的通道1向被测设备发送测试码流。该接口中通 过接口端口接收的测试码流可以经过内部回路传输到发送器，之后再通过发送器将接口器所接收的测试码流发送到误码测试仪。
误码测试仪可以通过对被测设备反馈的测试码流以及所发出的测试码流进行比对，获得测试结果，也即展示被测设备反馈的测试码流中的差异比特数。
从上述描述可知，目前接收遵从性测试是通过被测设备与误码测试仪之间的回路实现的，误码测试仪的检测结果不仅与通道1有关，还与被测设备的内部回路以及通道2有关。在实际测试过程中，内部回路或通道2可能会引入误码，导致误码测试仪的测试结果不准确，影响接收遵从性测试的准确性。
需要说明的是，接收遵从性测试是在一些高速串行链路标准(如PCIe或SATA)中提及的一种测试。在其他通信链路标准中用于评估接口的接收性能、以及与接口连接的通信链路的传输性能的测试也可以为其他名称。本申请仅是提供了一种评估接口的接收性能、以及与接口连接的通信链路的传输性能的一种测试思路，该测试思路可以用于接收遵从性测试中，也可以用于其他测试中。在本申请实施例仅是以接收遵从性测试为例进行说明。
为了能够保证接收遵从性测试的准确性，本申请实施例提供了一种高速串行链路测试方法，如图3所示，为本申请实施例提供的一种系统结构示意图，该系统中包括测试设备200和被测设备100。
被测设备100上有被测接口110，该被测接口110可以为高速串行接口，被测接口110包括接收器111和发送器112。在本申请中，被测设备100具备误码检测功能，能够通过分析被测接口110的接收器111获得码流(如测试码流和自检码流)确定该码流的误码状态，如确定所接收到的码流中的差异比特数或误码率，其中，差异比特数是指所接收的码流与实际测试设备200所发送的码流之间存在差异的比特的数量。误码率等于差异比特数与所接收的码流的总比特数的比值。进而，通过该码流的误码状态来评估被测接口110的接收性能、以及与被测接口110连接的通信链路的传输性能。
该被测设备100还可以展示所确定的码流的误码状态，本申请实施例并不限定该被测设备100展示所确定的码流的误码状态的方式。
例如，该被测设备100还可以具备显示功能。例如，被测设备100中可以包括显示组件120，如显示屏，显示组件120能够显示被测设备100所确定误码状态，如显示所接收的码流中的差异比特数或误码率。
又例如，该被测设备100还可以具备语音播报功能。例如，被测设备100中可以包括语音播放组件130，如喇叭，语音播放组件130能够语音提示被测设备100所确定误码状态，如语音提示所接收的测试码流中的差异比特数或误码率。
又例如，该被测设备100还可以具备文件打印功能。例如，被测设备100中可以包括打印组件140，打印组件140能够将被测设备100所确定误码状态打印在纸张上，如将所接收的码流中的差异比特数或误码率打印在纸张上，用户可以通过纸张确定被测设备100所确定误码状态。
该被测设备100也可以将所确定的码流的误码状态反馈至测试设备200，例如，在被测接口110的发送器112与测试设备200之间建立反馈通道，通过该反馈通道将所确定的码流的误码状态反馈至测试设备200。
测试设备200为可以发出特定的测试码流的设备，本申请实施例并不限定测试设备200的类型，该测试设备200可以是误码测试仪，还可以是码型生成器。凡是能够发出码流的 设备均可以作为测试设备200。
被测设备100与测试设备200之间可以建立三种通道，分别为用于进行自检的自检通道、测试通道以及反馈通道。其中，测试通道的长度可以大于自检通道。
该自检通道联通测试设备200与被测接口110的接收器111。测试设备200可以通过自检通道向被测设备100发送自检码流。
该测试通道联通测试设备200与被测接口110的接收器111。测试设备200可以通过测试通道向被测设备100发送测试码流。
通常，在被测设备100和测试设备200之间在同一时间只能存在测试通道或自检通道中的一种，例如当需要构建测试通道时，可以先解除自检通道。自检通道和测试通道可以为长度不同的两个通道，例如自检通道可以为长度较小的通道，以保证自检码流在传输过程中不会引入误码。测试通道可以为长度较长的通道，以保证接受遵从性测试的准确程度。例如，该测试通道的长度可以为标准所规定的最大长度。本申请实施例并不限定该最大长度的具体值，在一些标准中可以通过信号的传输损耗来规定通道的最大长度，例如，要求在16千兆传输/秒(giga transmission per second，GT/s)下，信号的传输损耗不能超过20分贝。
在一些情况下，自检通道和测试通道也可以为同一个通道，也即该通常既用于传输自检码流，又用于传输测试码流。
该反馈通道联通测试设备200与被测接口110的发送器112。被测设备100可以通过反馈通道向测试设备200发送码流的误码状态，如该码流(如自检码流或测试码流)中存在的差异比特数等。
在本申请实施例提供的高速串行链路测试方法中，被测设备100能够自行对从测试设备200接收的测试码流和预先配置的参考测试码流进行分析，获取测试结果，以进一步确定被测接口110的接收性能、以及与被测接口110连接的通信链路的传输性能，也即被测设备100能够自行实现接收遵从性测试获得测试结果，不需要将接收到的测试码流反馈至测试设备200，由测试设备200分析、获得测试结果。有效的降低了测试过程中可能引入的误码，保证测试结果的准确性。
下面结合附图4对本申请实施例提供的高速串行链路测试方法进行说明，在该方法中包括两部分，一部分为被测设备100的自检过程，通过该自检过程确定被测设备100是否具备误码检测功能，是否能够准确地分析出所接收码流的误码状态(参见步骤401～步骤403)。另一部分为被测设备100进行测试的过程(参见步骤404～步骤407)。
步骤401：在测试设备200和被测设备100的被测接口110之间构建自检通道，该自检通道可以连接该被测设备100与被测设备100的接收器111。该自检通道的长度可以尽量小，长度较小的自检通道能够有效避免后续在传输自检码流时可能引入的误码。
步骤402：测试设备200通过该自检通道向被测设备100的被测接口110发送自检码流。该自检码流中包括有目标数量的差异比特。这些差异比特可以是测试设备200在原始码流中随机加入的，该原始码流可以是被测设备100和测试设备200已知的码流。若该原始码流可以是在被测设备100中预先配置好的。
步骤403：被测设备100从被测接口110中获得自检码流，确定该自检码流中差异比特数。
被测设备100可以对自检码流与原始码流进行比对，确定该自检码流中存在的差异比 特数。被测设备100可以展示所确定的差异比特数。
若被测设备100所确定的自检码流中的差异比特数与该目标数量不一致，说明该被测设备100无法准确分析码流，不具备误码检测功能，无法执行后续步骤。若被测设备100所确定的自检码流中的差异比特数与该目标数量不一致，说明该被测设备100具备误码检测功能，能够准确分析码流，可以执行步骤404。
步骤403中以差异比特数为例进行说明，被测设备100也可以确定自检码流的误码率，也即通过差异比特数与自检码流的总比特数的比值获得误码率，确定该误码率是否等于目标数量与自检码流的总比特数的比值。
步骤404：在测试设备200和被测设备100的被测接口110之前构建测试通道，该测试通道可以连接该被测设备100与被测设备100的接收器111，并且确保所发送的信号通过该测试通道能够在被测设备100处形成最小眼图。
该测试通道的长度可以尽量长，长度较长的测试通道在一定程度上增加了测试码流的传输路径，这样能够使得在测试码流中引入误码的概率大大增加，若在这种情况下，被测设备100中被测接口110所接收的测试码流依然能够满足误码率要求，则说明该被测接口110的接收性能较佳，有效确保了测试结果准确性。该测试通道的长度可以标准所允许的最大长度。
通过发送能够形成最小眼图的信号进行接收遵从性测试，也可以确保测试结果的准确性。这是因为如果在发送能够形成最小眼图的信号的情况下，被测设备100中被测接口110所接收的测试码流依然能够满足误码率要求，那么在发送其他符合标准的信号的情况下，被测接口110所接收的测试码流同样能够满足误码率要求。
步骤405：测试设备200通过该测试通道向被测设备100的被测接口110发送测试码流。
测试设备200在向被测设备100发送测试码流时，可以在测试码流之前添加码流起始标志，该码流起始标志可以为具备第一值的比特位，码流起始标志标注了该码流起始标志之后的码流为测试码流。该第一值可以是预先约定的。
当被测设备100通过被测接口110检测到该码流起始标志后，接收测试码流。在测试码流发送完成后，测试设备200还可以在测试码流之后添加码流结束标志。与码流起始标志类似，该码流结束标志可以为具备第二值的比特位，码流结束标志标注了测试码流已结束，后续已不存在测试码流。
步骤406：被测设备100从被测接口110中获得测试码流，分析测试码流和参考测试码流获取测试结果，如确定该测试码流中存在的差异比特数或该测试码流的误码率。
在执行步骤406时，被测设备100可以对测试码流和参考测试码流进行比对，确定测试码流中存在的差异比特数或该测试码流的误码率，该参考测试码流可以预先配置的，如可以是测试设备200预先通知给被测设备100的，也可以是默认设置的。
本申请实施例并不限定测试设备200预先通知给被测设备100参考测试码流的方式。
例如，在被测设备100中可以保存有参考测试码流集合，该参考测试码流中包括多个不同的参考测试码流。每个参考测试码流设置有标识，不同的参考测试码流的标识不同，一个标识与一个参考测试码流对应。测试设备200在发送测试码流之前，可以先将参考测试码流的标识发送给被测设备100。被测设备100通过参考测试码流的标识从该参考测试码流集合中获取该标识所对应的参考测试码流，以用于与所接收的测试码流的比对。
又例如，测试设备200也可以预先将该参考测试码流发送给测试设备200，如测试设备200可以通过之前建立的自检通道将参考测试码流发送至测试设备200，以避免在参考测试码流中引入不必要的误码。
又例如，该参考测试码流是默认的，已配置在该测试设备200中。
步骤407：被测设备100展示测试结果，如展示差异比特数或误码率，或向测试设备200反馈测试结果。在下面的说明中以测试结果为差异比特数为例进行说明，误码率的展示以及反馈方式与差异比特数的展示以及反馈方式类似，此处不再赘述。被测设备100也可以存储该测试结果。
被测设备100可以通过显示组件120展示该差异比特数，也可以通过语音播放组件130语音播放该差异比特数，也可以通过打印组件140将差异比特数打印在纸张上，以便用户能够获知检测结果。
测试设备200与被测接口110的发送器112之间建立反馈通道，被测设备100可以将所确定的差异比特数通过该反馈通道反馈至测试设备200，测试设备200在接收到该差异比特数后，可以展示所接收的差异比特数。
需要说明的是，码流的传输速率也会是码流中引入误码的一个因素。举例来说，当码流的传输速率过大，码流中各个信号的间隔较小，相互之间容易存在干扰，容易产生误码。在进行接收遵从性测试时，可以在不同的传输速率下进行测试。例如，可以以不同的传输速率发送测试码流，获得在不同传输速率下的检测结果，也即确定不同传输速率下测试码流中存在的差异比特数。
在进行不同传输速率下的接收遵从性测试时，被测设备100与测试设备200之间可以预先约定起始的传输速率以及传输速率的切换方式。
在开始测试时，传输速率可以为最低的传输速率，如4GT/s，之后，传输速率可以逐渐提升。在开始测试时，传输速率可以为最高的传输速率，如64GT/s，之后，传输速率可以逐渐降低。
测试设备200可以通过发送通知消息的方式告知被测设备100需要进行传输速率的切换，还可以告知被测设备100切换后的传输速率的具体值。测试设备200与被测设备100之间也可以约定每种传输速率下接收遵从性测试的时长，在达到约定的时长后，切换到下一个传输速率，以该传输速率发送测试码流。
由于引入了不同传输速率下的接收遵从性测试，被测设备100在展示测试结果时，也可以标注传输速率，以指示在该测试结果为在该传输速率下的测试结果。同样的，被测设备100在向测试设备200展示测试结果时，也可以标注传输速率，以指示在该测试结果为在该传输速率下的测试结果。
基于与方法实施例同一发明构思，本申请实施例还提供了一种链路测试装置，该链路测试装置用于执行上述如图4所示的方法实施例中所述被测设备执行的方法，相关特征可参见上述方法实施例，此处不再赘述。如图5所示，该链路测试装置500能够对被测设备中高速串行接口的接收器进行测试，该链路测试装置500部署在被测设备100上。所述链路测试装置500包括接收模块501、分析模块502。
接收模块501，用于通过接收器接收测试设备发送的第一测试码流。
分析模块502，用于通过分析第一测试码流和参考测试码流获取测试结果，测试结果用于表征高速串行接口的接收性能、以及与高速串行接口连接的通信链路的传输性能，参 考测试码流是预先配置的。
在一种可能的实施方式中，链路测试装置500还包括展示模块503。该展示模块503可以展示测试结果。
在一种可能的实施方式中，链路测试装置500还包括发送模块504。发送模块504可以通过高速串行接口的发送器向测试设备发送测试结果。
在一种可能的实施方式中，测试结果为第一测试码流中存在的差异比特数或第一测试码流的误码率。
在一种可能的实施方式中，参考测试码流是预先配置给链路测试装置500的。例如，该参数测试码流是默认的，已配置在链路测试装置500中。又例如，该参考测试码流可以测试设备通知给链路测试装置500的。接收模块501可以从测试设备获取参考测试码流的标识；之后，分析模块502根据参考测试码流的标识从参考测试码流集合中确定标识对应的参考测试码流，参考测试码流包括多个不同的参考测试码流，每个参考测试码流与一个标识对应。
在一种可能的实施方式中，接收模块501在通过接收器接收误码测试仪发送的第一测试码流之前，还可以通过接收器接收测试设备发送的第二测试码流，第二测试码流中包括目标数量的差异比特。分析模块502可以确定第二测试码流中差异比特数，其中，第二测试码流中差异比特数等于目标数量。
在一种可能的实施方式中，接收模块501在通过接收器接收测试设备发送的第一测试码流时，可以通过接收器接收测试设备以不同传输速率发送的第一测试码流。
在一种可能的实施方式中，接收模块501还可以获取测试设备发送的通知消息，通知消息用于指示第一测试码流的传输速率。
需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在本申请的实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
在一个简单的实施例中，本领域的技术人员可以想到如图2所示的实施例中被测设备可采用图6所示的形式。
如图6所示的管理设备600，包括至少一个处理器601、存储器602，可选的，还可以 包括通信接口603，该通信接口603也可以称为高速串行接口或接口。
存储器602可以是易失性存储器，例如随机存取存储器；存储器也可以是非易失性存储器，例如只读存储器，快闪存储器，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)、或者存储器602是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器602可以是上述存储器的组合。
本申请实施例中不限定上述处理器601以及存储器602之间的具体连接介质。
处理器601可以为中央处理器(central processing unit，CPU)，该处理器601还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件、人工智能芯片、片上芯片等。通用处理器可以是微处理器或者是任何常规的处理器等。
当所述链路测试装置500或被测设备采用图6所示的形式时，图6中的处理器601可以通过调用存储器602中存储的计算机执行指令，使得所述链路测试装置500或被测设备可以执行上述任一方法实施例中的所述被测设备执行的方法。
具体的，图5的接收模块501、分析模块502、展示模块503以及发送模块504的功能/实现过程均可以通过图6中的处理器601调用存储器602中存储的计算机执行指令来实现。或者，图5中的分析模块502、展示模块503的功能/实现过程可以通过图6中的处理器601调用存储器602中存储的计算机执行指令来实现，图5的接收模块501或发送模块504的功能/实现过程可以通过图6中的通信接口603来实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请范围。这 样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (18)

  1. 一种高速串行链路测试方法，其特征在于，所述方法用于对被测设备中高速接口的接收器进行测试，所述方法包括：
    所述被测设备通过所述接收器接收测试设备发送的第一测试码流；
    所述被测设备通过分析所述第一测试码流和参考测试码流获取测试结果，所述测试结果用于表征所述高速串行接口的接收性能、以及与所述高速串行接口连接的通信链路的传输性能，所述参考测试码流是预先配置的。
  2. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    所述被测设备展示所述测试结果。
  3. 如权利要求1或2所述的方法，其特征在于，所述方法还包括：
    所述被测设备通过所述高速串行接口的发送器向所述测试设备发送所述测试结果。
  4. 如权利要求1-3任一项所述的方法，其特征在于，所述测试结果为所述第一测试码流中存在的差异比特数或所述第一测试码流的误码率。
  5. 如权利要求1-4任一项所述的方法，其特征在于，所述参考测试码流是预先配置的，包括：
    所述被测设备从所述测试设备获取所述参考测试码流的标识；
    所述被测设备根据参考测试码流的标识从参考测试码流集合中确定所述标识对应的参考测试码流，所述参考测试码流包括多个不同的参考测试码流，每个参考测试码流与一个标识对应。
  6. 如权利要求1-5任一项所述的方法，其特征在于，所述被测设备通过所述接收器接收测试设备发送的第一测试码流之前，包括：
    所述被测设备通过所述接收器接收所述测试设备发送的第二测试码流，所述第二测试码流中包括目标数量的差异比特；
    所述被测设备确定所述第二测试码流中差异比特数，其中，所述第二测试码流中差异比特数等于所述目标数量。
  7. 如权利要求1-6任一项所述的方法，其特征在于，所述被测设备通过所述接收器接收测试设备发送的第一测试码流，包括：
    所述被测设备通过所述接收器接收所述测试设备以不同传输速率发送的第一测试码流。
  8. 如权利要求1-7任一项所述的方法，其特征在于，所述被测设备通过所述接收器接收测试设备发送的第一测试码流之前，还包括：
    所述被测设备获取所述测试设备发送的通知消息，所述通知消息用于指示所述第一测试码流的传输速率。
  9. 一种链路测试装置，其特征在于，所述链路测试装置用于对被测设备中高速串行接口的接收器进行测试，所述链路测试装置包括接收模块、分析模块；
    所述接收模块，用于通过所述接收器接收测试设备发送的第一测试码流；
    所述分析模块，用于通过分析所述第一测试码流和参考测试码流获取测试结果，所述测试结果用于表征所述高速串行接口的接收性能、以及与所述高速串行接口连接的通信链路的传输性能，所述参考测试码流是预先配置的。
  10. 如权利要求9所述的装置，其特征在于，所述链路测试装置还包括展示模块；
    所述展示模块，用于展示所述测试结果。
  11. 如权利要求9或10所述的装置，其特征在于，所述链路测试装置还包括发送模块：
    所述发送模块，用于通过所述高速串行接口的发送器向所述测试设备发送所述测试结果。
  12. 如权利要求9-11任一项所述的装置，其特征在于，所述测试结果为所述第一测试码流中存在的差异比特数或所述第一测试码流的误码率。
  13. 如权利要求9-12任一项所述的装置，其特征在于，
    所述接收模块，还用于从所述测试设备获取所述参考测试码流的标识；
    所述分析模块，还用于根据参考测试码流的标识从参考测试码流集合中确定所述标识对应的参考测试码流，所述参考测试码流包括多个不同的参考测试码流，每个参考测试码流与一个标识对应。
  14. 如权利要求9-13任一项所述的装置，其特征在于，所述接收模块在通过所述接收器接收误码测试仪发送的第一测试码流之前，还用于：
    通过所述接收器接收所述测试设备发送的第二测试码流，所述第二测试码流中包括目标数量的差异比特；
    所述分析模块，还用于确定所述第二测试码流中差异比特数，其中，所述第二测试码流中差异比特数等于所述目标数量。
  15. 如权利要求9-14任一项所述的装置，其特征在于，所述接收模块在通过所述接收器接收测试设备发送的第一测试码流，具体用于：
    通过所述接收器接收所述测试设备以不同传输速率发送的第一测试码流。
  16. 如权利要求9-15任一项所述的装置，其特征在于，所述接收模块，还用于：
    获取所述测试设备发送的通知消息，所述通知消息用于指示所述第一测试码流的传输速率。
  17. 一种训练装置，其特征在于，包括存储器和处理器；所述存储器存储有程序指令，所述处理器运行所述程序指令以执行权利要求1～8任一所述的方法。
  18. 一种计算机可读存储介质，其特征在于，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行如权利要求1～8任一所述的方法。
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