WO2023033914A1

WO2023033914A1 - Display with high voltage capacitive elements array and controller

Info

Publication number: WO2023033914A1
Application number: PCT/US2022/035851
Authority: WO
Inventors: Matthew APREA; Samuel SHIAN; Ioannis Kymissis
Original assignee: Solchroma Technologies, Inc.
Priority date: 2021-08-31
Filing date: 2022-06-30
Publication date: 2023-03-09
Also published as: WO2023033914A8

Abstract

An electric circuit can be used to control the operation of an array of high voltage capacitive elements (HVCEs) used in displays. The electric circuit can include a m x n array of actuation circuits for the m x n HVCEs. Each actuation circuit can include an actuation switch coupled with a first terminal of the HVCE, a data capacitor coupled with the control terminal of the actuation switch, a data switch coupled with the capacitor, the data switch configured to charge or discharge the data capacitor based on a voltage on a n-th column interconnect and responsive to activation of a first activation signal on a m-th row interconnect. The circuit also includes an actuation time limiting switch configured to charge/discharge the capacitor based on a target voltage and activation of a second activation signal, which is activated after an activation and de-activation of the first activation signal.

Description

DISPLAY WITH HIGH VOLTAGE CAPACITIVE ELEMENTS ARRAY AND

CONTROLLER

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/239,232, entitled “Display with High Voltage Capacitive Elements Array and Controller,” filed August 31, 2021, which is incorporated herein by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Grant No. 1660204 awarded by the National Science Foundation. The government has certain rights in the invention.

TECHNICAL FIELD

[0003] This disclosure relates to display devices, and in particular to high voltage capacitive elements used in display devices.

BACKGROUND

[0004] Numerous electrical devices require large numbers of individual electrical elements forming 2D arrays. These electrical elements can include primary elements, or combinations of primary elements, such as semiconductive, resistive, inductive, or capacitive elements. When these elements form an array, precise control of individual elements through independent addressing with minimal cross talk can be crucial to proper device operation. As a particular example, thin-film transistor (TFT) arrays have been extensively used as active matrix backplanes for displays including LCD, electrophoretic, OLED and electro-wetting displays (Design of Organic TFT Pixel Electrode Circuit for Active-Matrix OLED Displays, JOURNAL OF COMPUTERS, VOL. 3, NO. 3, MARCH 2008). However, most TFT arrays are limited to low voltage applications (less than about 100V). While these low-voltage TFT arrays may work for some displays, there remains a class of electrical devices that require significantly higher voltages (e.g., greater than about 200V) to provide the driving force for operation, even when consuming relatively small amounts of current.

[0005] As an example, some high-voltage, low-current electrical devices use capacitive elements, in which electrical charges placed on the electrodes provide the driving force for a physical change such as mechanical actuation or state change. These high voltage capacitive elements (HVCEs) include, but are not limited to, dielectric elastomer actuators (DEAs), electrostrictive actuators, electrostatic actuators, and electret or ferroelectric polymers. DEAs can be arranged in an array and controlled individually independent of other elements of the array. A common design of DEAs is to sandwich a soft insulating elastomer membrane between two compliant electrodes. Dielectric elastomer technologies typically require high voltages to affect mechanical actuations, and while many companies and organizations have developed high voltage transistors, these have not been formed into usable arrays. Examples of HVCE actuators for display devices are discussed in US 17/046,904, entitled “Display Techniques Incorporating Fluidic Actuators and Relate Systems and Methods,” which is incorporated herein in its entirety.

SUMMARY

[0006] In one aspect, an electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, includes m x n actuation circuits, wherein each actuation circuit of the m x n actuation circuits corresponds to a HVCE of the array of HVCEs, where each m x //-th actuation circuit includes: an actuation switch coupled with a first terminal of a corresponding HVCE, a capacitor coupled with the control terminal of the actuation switch, another terminal of the capacitor coupled with a ground terminal, a data switch coupled with the capacitor, the data switch configured to charge or discharge the capacitor based on a voltage on a //-th column interconnect coupled with one of the terminals of the data switch responsive to activation of a first activation signal on a m-th row interconnect coupled with the control terminal of the data switch, an actuation time limiting switch coupled with the capacitor, the actuation time limiting switch configured to charge or discharge the capacitor based on a target voltage at one of its terminals responsive to activation of a second activation signal, which is activated after an activation and de-activation of the first activation signal.

[0007] In another aspect, An electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, including m x n actuation circuits, wherein each actuation circuit of the m x n actuation circuits includes: a first actuation switch coupled with a first terminal of a corresponding HVCE; a second actuation switch coupled with a second terminal of the corresponding HVCE; a first capacitor coupled with the control terminal of the first actuation switch, another terminal of the first capacitor coupled with a ground terminal; a second capacitor coupled with the control terminal of the second actuation switch, another terminal of the second capacitor coupled with the ground terminal; a first data switch coupled with the first capacitor, the first data switch configured to charge or discharge the first capacitor based on a voltage on a first //-th column interconnect coupled with one of the terminals of the first data switch responsive to activation of a first m-th row activation signal on a first m-th row interconnect coupled with the control terminal of the first data switch; a second data switch coupled with the second capacitor, the second data switch configured to charge or discharge the second capacitor based on a voltage on a second //-th column interconnect coupled with one of the terminals of the second data switch responsive to activation of the first m-th row activation signal on the first m-th row interconnect coupled with the control terminal of the second data switch; a first actuation time limiting switch coupled with the first capacitor, the first actuation time limiting switch configured to charge or discharge the first capacitor based on a first target voltage on a third //-th column interconnect coupled with one of the terminals of the first actuation time limiting switch responsive to activation of a second ///-th row activation signal on a second ///-th row interconnect coupled with the control terminal of the first actuation time limiting switch; a second actuation time limiting switch coupled with the second capacitor, the second actuation time limiting switch configured to charge or discharge the second capacitor based on a second target voltage on a fourth //-th column interconnect coupled with one of the terminals of the second actuation time limiting switch responsive to activation of the second ///-th row activation signal on the second m-th row interconnect coupled with the control terminal of the second actuation time limiting switch; a first drive interconnect providing a first drive voltage coupled with the first terminal of the HVCE; and a second drive interconnect providing a second drive voltage coupled with the second terminal of the HVCE.

[0008] In yet another aspect, An electric circuit for controlling an m x n array of high voltage capacitive elements (HVCEs), the electric circuit including an m x n array of actuation circuits, wherein each of the m x n actuation circuits includes: a coupling circuit configured to selectively charge or discharge the corresponding HVCE from at least one power supply terminal based on at least one data voltage; a data loading circuit coupled with the m x n array of actuation circuits, the data loading circuit configured to load at least one data voltage in each of the m x n actuation circuits; a controller coupled with the m x n actuation circuits, the data loading circuit, and a power supply providing the at least one power supply terminal, the controller configured to: for a set of charging frame durations, control the power supply to provide a charging voltage at the at least one power supply terminal, for a set of discharging frame durations, control the power supply to provide a discharging voltage at the at least one power supply terminal, and for each frame duration of the set of charging frame durations and the set of discharging frame durations, control the data loading circuit to load a data voltage in each of the m x n actuation circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

[0010] Figure 1 shows an example N x M array of HVCEs.

[0011] Figure 2 shows an example first electric circuit for controlling the operation of a plurality of HVCEs.

[0012] Figure 3 shows an example first timing diagram depicting the operation of the first electrical circuit shown in Figure 2.

[0013] Figure 4 shows an example second electric circuit for controlling the operation of a plurality of HVCEs.

[0014] Figure 5 shows an example second timing diagram depicting the operation of the second electrical circuit shown in Figure 4.

[0015] Figure 6 shows an example third electric circuit for controlling the operation of a plurality of HVCEs.

[0016] Figure 7 shows an example fourth electric circuit for controlling the operation of a plurality of HVCEs.

[0017] Figure 8 shows an example timing diagram depicting the operation of the fourth electrical circuit 700 shown in Figure 7.

[0018] Figure 9 shows an equivalent circuit of an HVCE.

[0019] Figure 10 illustrates an example set of sequence of frames for charging the HVCE to its desired target voltage.

[0020] Figure 11 shows an example pseudocode that can be executed by a controller to control the actuation circuits during various designated frame.

[0021] Figure 12 shows an example sequence of power supply voltages for mitigating ion migration effects on HVCEs.

[0022] Figure 13 shows an example pseudocode that can be executed by a controller to control the charge accumulation in the HVCE.

[0023] Figure 14 shows an example charge accumulation table that can be maintained by the controller to monitor charge accumulation.

[0024] Figure 15 shows a block diagram of an example system including an array of HVCEs and an array of actuators. [0025] Additional advantages of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or can be learned by practice of the disclosure. The advantages of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed.

[0026] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0027] Many modifications and other embodiments disclosed herein will come to mind to one skilled in the art to which the disclosed compositions and methods pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the disclosures are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. The skilled artisan will recognize many variants and adaptations of the aspects described herein. These variants and adaptations are intended to be included in the teachings of this disclosure and to be encompassed by the claims herein.

[0028] Figure 1 illustrates an M X N array 100 of high-voltage capacitive elements (HVCE) 102. The M x N array 100 of HVCEs 102 can represent, for example, actuators for actuating display elements. The M X N array 100 includes M rows and N columns of HVCEs 102. The HVCEs 102 may be controlled by a printed circuit board (PCB) or a high-voltage thin-film- transistor (TFT) backplane. These arrays will have the ability to charge individual elements of the array to a high-voltage state by applying a high-voltage to one of the HVCE terminals, while the other end is grounded. It may also have the ability to float the HVCEs (place into a high-impedance state) by placing one or both of the HVCE terminals into a high-impedance state. Lastly it may have the ability to discharge the HVCE by connecting the high-side of the HVCE to ground while the other terminal is also connected to ground. In an array it may be necessary to command individual HVCEs to different states, including moving from a low- voltage charged state to a high-voltage charged state, moving from a high-voltage charged state to a low-voltage charged state, and maintaining the present state.

[0029] The M x N array 100 of HVCEs may be organized into electrically connected rows and columns, whereby the rows may be optionally switched between positive-voltage, ground or negative-voltage states, and the columns may be optionally switched between positive-voltage, ground or negative-voltage states. In such an arrangement, the array 100 may be “scanned” by “selecting” a row (placing the row into a positive-voltage), and selectively driving the column electrodes individually to ground/negative- voltage or positive-voltage states. Furthermore, a power supply voltage (e.g., VDrive) can be applied globally to all elements in the array and may be placed optionally into a high-voltage positive, high-voltage negative, or ground state. By doing so each HVCE may be placed into one of three states: charging, discharging or floating. The present row is “selected” for a finite period of time (row scan time) before it is un-selected and the next row in the sequence is selected, and the column signals are changed to accommodate the desired states of the next rows HVCEs. All non-selected rows cab be in a ground or negative voltage state. This continues until the entire array is scanned. One pass through the array can be referred to as a frame duration, and rate at which the frame is scanned can be referred to as the frame rate. The array may be scanned for a finite number of frames or continuously scanned.

[0030] Figure 2 shows an example first electric circuit 200 for controlling the operation of a plurality of HVCEs. The first electric circuit 200 includes 16 first actuation circuits 250 arranged in four rows and four columns and can be utilized to control the operation of a 4 x 4 array of HVCEs 102. The first electrical circuit 200 shown in Figure 2 is only an example, and it can be appreciated that the first electrical circuit 200 can be readily modified to include fewer or more actuation circuits 250 for controlling a desired number of HVCEs 120. As mentioned above, the first electrical circuit 200 includes the actuation circuits 250 arranged in rows and columns. The rows include a first row 202, a second row 204, a third row 206 and a fourth row 208. The columns include a first column 212, a second column 214, a third column 216, and a fourth column 218. The first electrical circuit 200 includes two row interconnects per row of actuation circuits 250. For example, row interconnects R0W1 1 and R0W1 2 are associated with the first row 202 of actuation circuits 250, row interconnects R0W2 1 and ROW2 2 are associated with the second row 204 of actuation circuits 250, row interconnects R0W3 1 and ROW3 2 are associated with the third row 206 of actuation circuits 250, and row interconnects R0W4 1 and ROW4 2 are associated with the fourth row 208 of the actuation circuits 250. The first electrical circuit 200 also includes one column interconnect per column. For example, column interconnects COL1, COL2, COL3, and COL4 are associated with actuation circuits 250 in the first column 212, the second column 214, the third column 216, and the fourth column 218, respectively. The row interconnects and the column interconnects can be coupled with a controller that controls the voltage and durations of the voltages on the row and column interconnects. As discussed further below, the row interconnects are utilized to enable actuation circuits 250 within their respective rows to accept data voltages, and the column interconnects are utilized to provide the data voltages to their respective ones of enabled actuation circuits 250.

[0031] Turning to the actuation circuits 250, each actuation circuit 250 includes an actuation switch 220, a data capacitor 222, a data switch 224, and an actuation time limiting switch 226. Referring to the actuation circuit 250 in the first row 202 and the first column 212, the actuation switch 220 (also referred to as “a coupling circuit”) is positioned between the HVCE 102 and the ground terminal. In some aspects, the actuation switch 200 can include a thin film transistor with an offset gate structure, meaning the gate electrode is offset from either the source or drain structure of the transistor yielding increased isolation between the low-voltage gate and the high-voltage source or drain. This arrangement can provide the gate terminal electrical isolation from the high voltage source or drain terminals. The gate terminal (also referred to as “a control terminal”) of the actuation switch 220 is coupled with one terminal of the data capacitor 222, the other terminal of which is coupled with the ground terminal. One terminal of the data switch 224 is coupled with the respective column interconnect (COL1) while the other terminal of the data switch 224 is coupled with the gate terminal of the actuation switch 220 and with the data capacitor 222. The gate terminal of the data switch 224 is coupled with the respective first row interconnect (R0W1 1). One terminal of the actuation time limiting switch 226 is coupled with one terminal of the data capacitor 222 that is also coupled with the data switch 224, while the other terminal of the actuation time limiting switch 226 is coupled with the other terminal of the data capacitor 222 and with the ground terminal. The gate terminal of the actuation time limiting switch 226 is coupled with the respective second row interconnect (ROW 1 2).

[0032] Figure 3 shows an example first timing diagram 300 depicting the operation of the first electrical circuit 200 shown in Figure 2. The first timing diagram 300 shows the operation over two frames Fl and F2. Each frame can represent a duration that allows the enabling all the actuation circuits 250 in the electrical circuit. For example, in some instances, the actuation circuits 250 are enabled row-by-row. When the actuation circuits in one row are enabled, the actuation circuits in other rows are disabled. The actuation circuits are enabled by enabling the respective row interconnects. When the actuation circuits within a row are enabled, the column interconnects are loaded with the desired data voltage, which in turn is loaded into the data capacitors 222 of the respective actuation circuits 250. The HVCE corresponding to an actuation circuit is actuated based on the data in the column interconnects. The row can then be disabled by disabling the corresponding row interconnects, and the row interconnects associated with the next row are enabled. Thus, each row can be sequentially enabled to load data and selectively actuate the HVCEs corresponding to that row. The frame duration can be the time period during which all the rows have been enabled once. This sequence can be repeated in the subsequent frame durations to repeatedly and selectively actuate the HVCEs 102. A controller (discussed below) can be programmed to control the activation of the appropriate row and column interconnects as well as the voltage provided to the HVCEs 102. [0033] The frame Fl begins at time tO. At this time, the controller can control the voltage on the first column interconnect COL1 to be at the desired voltage. For example, the controller can set this voltage to a high voltage if the HVCE 102 is to be activated during frame Fl. If the HVCE 102 is to be deactivated, the controller can set the voltage on the first column interconnect COL1 to a low voltage. At time tl, the controller activates the voltage (“the first activation signal”) on the first row interconnect R0W1 1. It should be noted that while in Figure 3 the first row 202 is activated first, the controller can activate any one of the four rows (202-208) first. Activating the first activation signal on the R0W1 1 row interconnect causes the voltage at the gate terminal of the data switch 224 to go high, and for the data switch 224 to switch ON. This creates a current path between the first column interconnect COL1 and the ground terminal through the data switch 224 and the data capacitor 222. As a result, the data capacitor 222 charges to a voltage proportional to the voltage on the first column interconnect COLE The charging of the data capacitor 222 causes the voltage at the gate terminal of the actuation switch 220 to rise. When this voltage increases above the threshold voltage of the actuation switch 220, the actuation switch 220 switches ON. This opens a current path from a HVCE global power supply 252, through the HVCE 102 and the actuation switch 220 to the ground terminal. The current flow through the HVCE 102 causes the voltage across the HVCE 102 to increase towards a desired target voltage.

[0034] The HVCE 102 continues to be actuated while first activation signal on the first row interconnect ROW 1 1 is active. At time t2, the controller deactivates the first activation signal on the first row interconnect R0W1 1. Upon deactivation of the first activation signal, the data switch 224 switches OFF, cutting off the current path between the first column interconnect COL1 and the data capacitor 222. The actuation switch 220 may still remain switched ON due to the charge stored in the data capacitor 222. As a result, despite the data switch 224 switching OFF, the current path through the HVCE 102 may still be maintained.

[0035] At time t3, the controller can activate a second activation signal on the second row interconnect ROW 1 2, which switches ON the actuation time limiting switch 226. As a result, the actuation time limiting switch 226 discharges the data capacitor 222, causing the voltage at the gate terminal of the actuation switch 220 to go below the threshold voltage, and cause the actuation switch 220 to switch OFF. This disconnects the current path through the HVCE 102. As a result, the voltage across the HVCE 102 ceases to increase. The amount of time for which the current path is maintained through the HVCE 102 is equal to the duration between time tl and t3. During this time, the voltage across the HVCE 102 increases.

[0036] At time t4 the controller can deactivate the second activation signal on the second row interconnect R0W1 2. The controller can also subsequently reduce the voltage on the first column interconnect COLE The deactivating of the second activation signal on the second row interconnect ROW 1 2 can end a row time allocated to the first row. During the remainder of the first frame Fl, the controller can activate and deactivate the first and second row interconnects of the remaining rows in the first electrical circuit 200. The second frame F2 begins at time tO. However, unlike the first frame Fl, where the voltage on the first column interconnect COL1 was maintained at a high voltage, in the second frame F2 the controller maintains a low voltage on the first column interconnect COLL The controller can determine whether to provide a high or a low voltage on the first column interconnect COL1 based on the current voltage across the HVCE 102 and the target voltage. As an example, if the current voltage of the HVCE 102 has reached its desired target voltage, the controller can determine to not charge the HVCE in subsequent frames. To that end, the controller can maintain a low voltage at the first column interconnect COLL

[0037] At time tl , the controller activates the first activation signal on the first row interconnect ROW1_1, which switches ON the data switch 224. As the voltage on the first column interconnect COL1 is low, any charge on the data capacitor 222 will be discharged through the data switch 224. As a result, the actuation switch 220 will remain open, impeding current flow through the HVCE 102. The controller can deactivate the first activation signal on the first row interconnect R0W1 1 at time t3, and activate the second activation signal on the second row interconnect ROW 1 2 at time t4. However, unlike the first frame F 1 , where the data capacitor 222 was charged at time t3, in the second frame F2 the data capacitor 222 is already discharged. As a result, the switching ON of the actuation time limiting switch 226 will cause no change in the switching state of the actuation switch 220.

[0038] In the first electrical circuit 200, the controller can select whether to charge or discharge the HVCE based on a target voltage for the HVCE. If the current voltage across the HVCE is below the target voltage, the controller can implement the signals shown in the first frame Fl in Figure 3. If, however, the current voltage of the HVCE 102 is above the target voltage, the controller can implement the signals in the second frame F2, such that the voltage across the HVCE 102 is allowed to decay over time and converge to the desired lower target voltage. [0039] Figure 4 shows an example second electric circuit 400 for controlling the operation of a plurality of HVCEs. The second electric circuit 400 is substantially similar to the first electric circuit 200, however, unlike the first electric circuit 200, which includes only one column interconnect per column, the second electric circuit 400 in contrast includes two column interconnects per column. In particular, the first column 212 includes a first column interconnect COLl l and a second column interconnect COL1 2, the second column 214 includes a first column interconnect COL2 1 and a second column interconnect COL2 2, the third column 216 includes a first column interconnect COL3 1 and a second column interconnect COL3 2, and the fourth column 218 includes a first column interconnect COL4 1 and a second column interconnect COL4 2. Each second column interconnect is coupled with a second terminal of the actuation time limiting switches 226 of the actuation circuits 250 in that column. As discussed below, the second column interconnect enables altering the amount of time that the actuation switch 220 can be switched ON to allow the charging of the HVCE 102.

[0040] Figure 5 shows an example second timing diagram 500 depicting the operation of the second electrical circuit 400 shown in Figure 4. The second timing diagram 500 shows the timing diagram of the second column interconnect COL 1 2 in addition to that of the first column interconnect COL 1 1. At the start of the first frame Fl at time tO, the controller provides a high voltage on the first column interconnect COLl l while providing a low voltage on the second column interconnect COL1 2. In the first frame Fl from time tl to time t3 the operation of the second electrical circuit is similar to that of the first electrical circuit 200. At time t3, the controller activates the second activation signal on the second row interconnect R0W1 2. This causes the actuation time limiting switch 226 to switch ON. Unlike the first electric circuit 200, where the switching ON of the actuation timing switch 226 caused the discharge of the capacitor through the ground terminal, in the second electrical circuit 400, the switching ON of the actuation timing switch 226 causes the capacitor to charge or discharge based on the voltage on the second column interconnect COL1 2. In the first frame, the controller sets the second column interconnect COL 1 2 to a low voltage. Therefore, the data capacitor 222 will be discharged through the actuation time limiting switch 226 to the second column interconnect COL 1 2. Thus, the total time for which the actuation switch 220 remains ON is equal to the duration between tl and t3.

[0041] At the beginning of the second frame F2 however, the controller pulls the voltage on the second column interconnect COL1 2 high. Thus, at time t3, when the controller activates the second activation signal on the second row interconnect R0W1 2, the actuation time limiting transistor switches ON and keeps the data capacitor 222 charged because of the high voltage on the second column interconnect COL 1 2. Thus, unlike the first electrical circuit 200 where the actuation switch 220 switches OFF at time t3, in the second electrical circuit 400 the actuation switch 220 remains ON at time t3 by virtue of a high voltage on the second column interconnect COL1 2. At time t4, the controller deactivates the second activation signal on the second row interconnect R0W1 2, which switches OFF the actuation time limiting switch 226. However, as the data capacitor 222 remains charged, the actuation switch 220 has a high voltage at its control terminal. Thus, the actuation switch 220 remains ON, maintaining a current path through the HVCE 102. The actuation switch 220 remains ON through the entire second frame duration F2. In the third frame F3, the controller lowers the voltage on the second column interconnect COL1 2. Thus, at time t3, when the controller activates the second activation signal on the second row interconnect R0W1 2, the actuation time limiting switch 226 switches ON and discharges the data capacitor 222 through the second column interconnect COL1 2. As a result, the actuation switch 220 switches OFF and terminates the current path through the HVCE 102. The second electrical circuit 400 provides an option to extend the charging time of the HVCE by a full frame duration. For example, in the first electrical circuit 200, the actuation time of the HVCE is t3 -t 1. However, in the second electrical circuit 400, the actuation time (with COL1 2 at high voltage) is tF+t3-tl, where tF is the frame duration.

[0042] Figure 6 shows an example third electric circuit 600 for controlling the operation of a plurality of HVCEs. The third electrical circuit 600 is similar to the second electrical circuit 400 shown in Figure 4. However, unlike the second electrical circuit 400, which includes two row interconnects for each row, the third electrical circuit 600 includes two row interconnects for only a single row. All other rows have only one row interconnect. For example, the first row 202, the second row 204, and the third row 206 include one row interconnect each (R0W1 1, R0W2 1, and R0W3 1, respectively). The fourth row 208 includes two row interconnects R0W4 1 and ROW4 2. The control terminals of the actuation time limiting switches 226, which in the second electrical circuit 400 were connected to the second row interconnect, are instead connected to the row interconnect of the adjacent row. For example, the control terminals of the actuation time limiting switches 226 in the first row 202 are connected to the row interconnect R0W2 1 of the second row 204. Similarly, the control terminals of the actuation time limiting switches 226 in the second row 204 are connected to the row interconnect R0W3 1 of the third row 206, and the control terminals of the actuation time limiting switches 226 in the third row 206 are connected to the row interconnect R0W4 1 of the fourth row 208. In some examples, the control terminals of the actuation time limiting switches 226 in the fourth row 202 can be connected to the row interconnect R0W1 1 of the first row 202. In this manner, all the rows have only a single row interconnect. The third electrical circuit 600 reduces the number of interconnects needed to operate the circuit. This reduction in the number of interconnects reduces power dissipation in the circuit and frees up valuable chip real estate that could be used to accommodate other circuitry. The operation of the third electrical circuit however is similar to the operation of the second electrical circuit 400. For example, referring to the timing diagram 500 in Figure 5, the R0W1 2 can be replaced with the row interconnect R0W2 1 of the second row 204.

[0043] Figure 7 shows an example fourth electric circuit 700 for controlling the operation of a plurality of HVCEs. In particular, Figure 7 shows one of M x N actuation circuits 750. The remainder of the actuation circuits in the fourth electrical circuit 700 can be identical to the actuation circuit 750. The fourth electrical circuit 750, like the first electrical circuit 200 and the second electrical circuit 400 includes two row interconnects R0W1 1 and R0W1 2 per row. However, unlike the first electrical circuit 200, which included one column interconnect per column and the second and third electrical circuits, each of which included two column interconnects per column, the fourth electrical circuit 750 includes four column interconnects per column (COLl l, COL1 2, COL1 3, and COL1 4). Additionally, the actuation circuit 750 includes two power supply terminals DRIVE A and DRIVE B, coupled with the two terminals of the HVCE 102. The voltage provided by the two power supply terminals can be individually controlled by the controller. In particular, the controller can control the power supply to provide a positive drive voltage, a negative drive voltage, a ground voltage, and a high impedance state (HI-Z) at each of the two power supply terminals.

[0044] The actuation circuit 750 essentially includes two actuation circuits — one associated with each power supply terminal. For example, the actuation circuit 750 includes a first actuation switch 706, one terminal of which is coupled with a first terminal of the HVCE 102 and the first power supply terminal (DRIVE A), and a second actuation switch 710, one terminal of which is coupled with the second terminal of the HVCE 102 and the second power supply terminal (DRIVE B). The second terminal of each of the first actuation switch 706 and the second actuation switch 710 is coupled with the ground terminal. A first data capacitor 708 is coupled with the control terminal of the first actuation switch 706, while a second data capacitor 712 is coupled with the control terminal of the second actuation switch 710. A first data switch 704 has one terminal that is coupled with the first data capacitor 708 and the control terminal of the first actuation switch 706. The other terminal of the first data switch 704 is coupled with the first column interconnect COLl l. The control terminal of the first data switch 704 is coupled with the first row interconnect ROW 1 1. A first actuation time limiting switch 702 has one terminal that is coupled with the control terminal of the first actuation switch 706 and the first data capacitor 708. The second terminal of the first actuation time limiting switch 702 is coupled with a second column interconnect COL1 2. The control terminal of the first actuation time limiting switch 702 is coupled with the second row interconnect ROW 1 2.

[0045] Further, a second data switch 716 has one terminal that is coupled with the second data capacitor 712 and the control terminal of the second actuation switch 710. The other terminal of the second data switch 716 is coupled with the third column interconnect COL 1 3. The control terminal of the second data switch 716 is coupled with the first row interconnect R0W1 1. A second actuation time limiting switch 714 has one terminal that is coupled with the control terminal of the second actuation switch 710 and the second data capacitor 712. The second terminal of the second actuation time limiting switch 714 is coupled with a fourth column interconnect COL1 4. The control terminal of the second actuation time limiting switch 714 is coupled with the second row interconnect R0W1 2.

[0046] Figure 8 shows an example timing diagram 800 depicting the operation of the fourth electrical circuit 700 shown in Figure 7. The first frame Fl begins at time tO. The controller controls the state of the two power supply terminals DRIVE A and DRIVE B such at they are not simultaneous providing a voltage at their output. For example, the controller can control the power supply terminals such that if one power supply terminal is providing a voltage, the other power supply terminal is at a high impedance state. In the first frame Fl, the controller controls the first power supply terminal DRIVE A to provide a high voltage, while controls the second power supply terminal DRIVE B into a high impedance state. Further, the controller controls the first and the second column interconnects to provide a low voltage such that the first actuation switch 706 remains in the OFF state for the duration that the DRIVE A is providing a high voltage. This ensures that there is no short circuit of the high voltage provided by the DRIVE A to the ground terminal. At time tl, the controller activates the first activation signal on the first row interconnect R0W1 1. As a result, the second data switch 716 switches ON and provides the voltage on the third column interconnect COL1 3 to the second data capacitor 712. As the voltage on the third column interconnect COL 1 3 is high, the second data capacitor 712 will be charged through the second data switch 716. Note that because the voltage on the first column interconnect COL 1 1 is at a low voltage, the first data switch 704, which is also connected to the first row interconnect R0W1 1, discharges any charge on the first data capacitor 708, thereby ensuring that the first actuation switch 706 is in the OFF state.

[0047] The charging of the second data capacitor 712 can result in the second actuation switch 710 to switch ON, thereby coupling the second terminal of the HVCE 102 to ground. As the first terminal of the HVCE 102 is coupled to DRIVE A, which is providing a high voltage, a current path from the first terminal of the HVCE 102 to the second terminal of the HVCE 102 is formed. This is also indicated by the current waveform I HVCE, which shows a positive value when flowing from the first terminal to the second terminal of the HVCE 102.

[0048] At time t2, the controller deactivates the first activation signal on the first row interconnect R0W1 1. However, because the second data capacitor 712 is still charged, the second actuation switch 710 can remain in the ON state, thereby maintaining the current through the HVCE. At time t3, the controller activates the second activation signal on the second row interconnect R0W1 2. This causes the second actuation time limiting switch 714 to switch ON. As the voltage on the fourth column interconnect COL 4 is a low voltage, the second actuation time limiting switch 714 discharges the second data capacitor 712, thereby causing the second actuation switch 710 to switch OFF. This causes the current I HVCE through the HVCE to cease. Thus, similar to the operation of the second electrical circuit 400 discussed above, the total time for which the current flows through the HVCE is equal to t3 -t 1. [0049] In the following second frame F2, the controller switches the states of the power supply terminal. For example, the controller controls the first power supply terminal DRIVE A to be in a high impedance state and controls the second power supply terminal DRIVE B to provide a high voltage. The controller also pulls the voltages on the third column interconnect COL1 3 and the fourth column interconnect COL 1 4 to a low voltage. This ensures that the second actuation switch 710 is maintained in the OFF state. At time tl, the controller activates the first activation signal on the first row interconnect ROW 1 1. This causes the first data switch 704 to switch ON. As the voltage on the first column interconnect COLl l is high, the first data capacitor 708 is charged through the first data switch 704. The charging of the first data capacitor 708 can cause the first actuation switch 706 to switch ON, which in turn creates a current path between the first terminal of the HVCE 102 and the ground terminal. As the second terminal of the HVCE is coupled to the second power supply terminal DRIVE B, which is at a high voltage state, current flows through the HVCE 102. However, the direction of the current in the HVCE 102 is reversed. That is, the current flows from the second terminal of the HVCE 102 to the first terminal of the HVCE 102, as indicated by the negative current I HVCE. [0050] Figure 9 shows an equivalent circuit of an HVCE 900. In particular, the equivalent circuit 900 can represent the HVCE 102 discussed above in relation to Figures 1-8. The HVCE 102 can be represented as a series connection between a first resistor R1 and a capacitor Cl, and a second resistor R2 in parallel with the capacitor Cl. When a current flows between the two terminals of the HVCE 102, the current flows through the first resistor R1 and the capacitor Cl . As a result, the voltage across the HVCE rises at a rate determined by the time R1C1 time constant. When one of the terminals of the HVCE is coupled to ground, the voltage across the HVCE begins to decay. The decay in the voltage across the HVCE also occurs at a rate determined by the R1C1 time constant. In instances where the one or both terminals of the HVCE are held at a high impedance state, the charge in the HVCE is dissipated internally and the decay occurs at a rate determined by the R2C1 time constant. In some examples, the R2C1 time constant can be substantially larger than the R1C1 time constant. Typically, these time constants are substantially larger than the actuation time of the actuation switches discussed above (e.g., t3 -t 1 ). Thus, it can take several frames of activating the actuation switch associated with an HVCE to charge or discharge the HVCE to its target voltage.

[0051] In one approach, the R1C1 time constant can represent the amount of time needed to charge the HVCE to about 62% of its target voltage, and three R1C1 time constants can represent the amount of time needed to charge the HVCE to about 95% of the target voltage. With the actuation time being substantially smaller than the R1C1 time constant, the charging of the HVCE using the activation circuits discussed above can be precisely controlled to achieve the desired target voltage across the HVCE by charging, discharging, or floating the HVCE. As an example, assume that the HVCE target voltage is 1130V, the power supply voltage is 1200V, an actuation time (e.g., t3-tl, or the average duration per frame that the HVCE is charged through the power supply) is equal to 17 ps, and the RC time constant is 0.0002. Dividing the RC time constant by the actuation time indicates that about 11 frames would be needed to charge the HVCE to the equivalent of one RC time constant. To achieve the target voltage 1130 V, which is about 95% of 1200, approximately 33 frames would be needed. That is, to charge the HVCE from zero volts to the target voltage of 1130, the corresponding actuation circuit would have to be enabled to charge the HVCE for 33 frames. Once the voltage of the HVCE reaches the target voltage, the HVCE can be maintained in a floating state until the voltage across the HVCE drops by a threshold level that can be recovered by charging during a single frame. Similar techniques can be utilized to discharge the HVCE from a higher voltage to a lower target voltage. For example, discharging the HVCE from 1300 V to a target voltage of 950 V could be accomplished by discharging the HVCE for three frames and then charging the HVCE for three charge frames. After the three charge frames, the HVCE can be maintained in a floating state, only to be charged if the voltage across the HVCE drops below a threshold voltage.

[0052] The HVCE can therefore be charged or discharged to the target voltage by selectively charging, discharging, or floating the HVCE for a number of frames, where the number of frames can be based, in part, on the current voltage of the HVCE and the target voltage of the HVCE. Of course, other factors such as the power supply voltage and the RC time constants associated with the HVCE would have to be taken into account to determine the number or frames.

[0053] Because each HVCE can be at different voltages at any time, and can have different target voltages, the number of frames needed to bring the HVCEs to their respective target voltages can vary. Moreover, typically all the HVCEs in a row are connected to a single global power supply terminal. As a result, one HVCE in the row cannot be charged, while the other HVCE in the same row is being discharged.

[0054] Figure 10 illustrates an example set of sequence of frames for charging the HVCE to its desired target voltage. In particular, Figure 10 shows a fist frame sequence 1002, a second frame sequence 1004, a third frame sequence 1006 and a fourth frame sequence 1008. Each frame sequence in Figure 10 is merely an example, and non-limiting. The frames begin from frame F0 and continue to frame FN. In the first frame sequence 1002, the frame F0 is designated as charge frame (denoted by the letter “C”). When a frame is designated as a charge frame, the controller controls the power supply voltage (e.g., the HVCE global power supply 252 in Figures 2, 4 and 6, or the DRIVE A and DRIVE B power terminals in Figure 7) to provide a positive voltage. For example, the controller can control the power supply to provide 1300 V at the power supply terminal. During the frame F0, the controller can determine which of the M x N HVCEs need charging, which need discharging, and which need to be floated. Because the frame F0 is a charging frame, the controller can activate the actuation circuits corresponding to those HVCEs that need to be charged. The controller can deactivate the actuation circuits of those HVCEs that need to be discharged or floated. The controller can similarly continue in the subsequent frames that are also designated as charging frames. The controller can monitor the current voltages of each HVCE before the start of each frame and determine whether the current voltage has reached the target voltage. If a HVCE has reached its target voltage, the controller can float the HVCE by deactivating the corresponding actuation circuit during the charge frame. In instances where all the HVCEs have reached their target voltages, the controller can float all those HVCEs by deactivating their corresponding actuation circuits and changing the state of the power supply to high impedance during floating frames (denoted by the letter “F”).

[0055] The first frame sequence 1002 also includes discharge frames (denoted by the letter “D”). When in a frame that is designated as a discharge frame, the controller can control the power supply to provide a negative voltage. For all the HVCEs that need to be discharged, i.e., whose current voltage is greater than their target voltage, the controller can activate the actuation circuits corresponding to those HVCEs. The controller can deactivate the actuation circuits of the remaining HVCEs.

[0056] The number of consecutive charge frames C, the discharge frames D, and the floating frames F, can vary based on the implementation. In some instances, the floating frames are positioned between the charge frames and the discharge frames. In some instances, the charging frames can be immediately followed by discharging frames. In some other instances, the controller can alternate between charging and discharging frames. In some other instances, the controller may randomly determine whether a current frame is a charging frame, a discharging frame or a floating frame.

[0057] Figure 11 shows an example pseudocode 1100 that can be executed by a controller to control the actuation circuits during various designated frame. At the first step, the controller loops though a first of M rows. For each row, the controller loops through each column, i.e., each HVCE in the selected row. For each column, the controller determines whether the designation of the current frame is a charge frame or a discharge frame. If the current frame is designated as a charge frame, the controller, for each HVCE, determines whether the target voltage of the HVCE is greater than the present voltage of the HVCE. If the target voltage is greater, the controller can determine that the HVCE needs to be charged. As a result, the controller can control the corresponding actuation circuit, as discussed above in relation to Figures 1-8, to charge the HVCE for the activation duration. If the target voltage is not greater than the present voltage, i.e., the HVCE has perhaps reached its target voltage, the controller can determine that the HVCE does not need to be charged in this frame, and therefore can deactivate the corresponding actuation circuit. If the current frame is designated as a discharge frame, the controller can determine, for each HVCE in the column, whether the target voltage is less than the present voltage. If this condition is true, the controller can control the power supply to provide a negative power supply voltage to the HVCEs and to activate the corresponding actuation circuits. In the discharge frame, if the controller determines that the target voltage is not less than the present voltage, the controller can float the HVCE by deactivating the corresponding actuation circuit. [0058] In some examples, HVCEs that have been exposed to the same voltage for prolonged period of time can experience ion migration. Ion migration can degrade the performance of the HVCEs. One approach to mitigating ion migration buildup can include reversing the polarity of the power supply provided to the HVCEs. Figure 12 shows an example sequence of power supply voltages for mitigating ion migration effects on HVCEs. In particular, Figure 12 shows the power supply voltage provided to the HVCEs over time. During a first polarity duration (tpl), the controller can provide a positive voltage to the HVCEs. In the second polarity duration (tp2), the controller can reverse the polarity of the power supply voltage provided to the HVCEs. The reversal of the polarity of the power supply voltage across the HVCE can result in the reversal of the direction of current flow within the HVCE. The reversal of direction of current flow can help in mitigating the degrading effects of ion migration in the HVCE. Specifically, the reversal of the polarity of the supply voltage can be used to balance the accumulation of charge over a period of time. For example, referring to Figure 12, charge accumulation can occur during the first polarity duration tpl. If the magnitude of the second polarity duration tp2 is equal to the first polarity duration, then the net charge accumulation at the end of the second polarity period tp2 can be equal to zero. Achieving zero charge accumulation in the HVCE can reduce the degradation of the HVCE.

[0059] Zero charge accumulation over time may be difficult to implement because the HVCEs are exposed to different voltages at different times. In one approach, the controller can track the net charge applied to a HVCE, where the net charge can be determined based on the voltage level at the HVCE and the number of frames the HVCE is exposed to that voltage level. The controller can maintain a cumulative product of the voltage and the number of frames (voltageframes) for each HVCE. For example, for a first polarity duration if a HVCE is maintained at 400 V for 6 frames, the controller can determine the voltage-frame product as 400 x 6 = 2400. If the HVCE is then exposed to a 1000 V for 8 frames, the controller can add the product 1000 x 8 = 8000 to 2400 to determine a new voltage-frame value of 10400. The controller can add the voltage-frame value for every subsequent frame during the first polarity duration to a running sum of voltage-frame values. In this manner, the controller can track the total charge accumulation on the HVCE. When the polarity is reversed, the controller can subtract the voltage-frame product values from the running sum for each subsequent frame. For example, if the HVCE, during the second polarity duration, is exposed to - 400 V for one frame, the controller can subtract 400 from the value 10400 to result in the value 10000. The controller can continue operating the HVCE with second polarity until the net value is within a +/- threshold range from zero. The controller can similarly monitor the cumulative voltage-frame values for other HVCEs. Over time, and with random HVCE states, the net voltage would likely hover around zero. The controller may in addition, or alternately, can maintain a cumulative current-time product instead of voltage-frame. In some other examples, the controller may in addition, or alternatively, maintain a cumulative electric field value. Generally, the controller can maintain a cumulative value of any parameter that is representative of charge accumulation in the HVCE.

[0060] One example of polarity reversal has been discussed above in relation to the fourth electrical circuit 700 as show in Figures 7 and 8. In the fourth electrical circuit 700, the controller can control the two power supply terminals DRIVE A and DRIVE _B to provide the desired voltage levels, and also control the actuation circuits to control the charging or discharging of the HVCEs.

[0061] Figure 13 shows an example pseudocode 1300 that can be executed by a controller to control the charge accumulation in the HVCE. The pseudocode 1300 shows the steps for a first polarity duration only, however, the steps for the second polarity duration can be similar to the first polarity duration but with the polarity reversed. At the first step, the controller determines the current polarity (polarity A) of the frame and sets the polarity of the power supply terminals to that polarity. The controller can then loop through each row in the M rows of the HVCEs. Within each row, the controller can loop through the N columns of HVCEs. At each column, i.e., at each HVCE, the controller can determine whether the current frame is a charge frame or a discharge frame. If the frame is a charge frame, the controller can determine whether the target voltage is greater than the present voltage. If the target voltage is greater than the present voltage, the controller can charge the HVCE, and calculate the new present voltage based on the RC time constant of the HVCE. If the target voltage is not greater than the present voltage, the controller can float the HVCE. If on the other hand the current frame is a discharge frame, the controller can determine whether the target voltage is less than the present voltage. If the target voltage is less than the present voltage, the controller can discharge the HVCE and determine an updated present voltage based on the RC time constant. If the target voltage is not less than the present voltage, the controller can allow the HVCE to float. The controller can then determine the accumulated voltage-frame product by adding the present voltage to the accumulated voltage stored in memory.

[0062] Figure 14 shows an example charge accumulation table that can be maintained by the controller to monitor charge accumulation. The charge accumulation table can include a first column including the identity of one or more HVCEs, and a second column indicating the current charge accumulation value. The controller can monitor these values to perform polarity reversals at various intervals of time such that the charge accumulation values are maintained within a +/- threshold from zero.

[0063] In reference to the electrical circuits discussed above, a “coupling circuit” can refer to the actuation switch (e.g., 220) that is positioned between the HVCE and the ground terminal. Also, in reference to the electrical circuits discussed above, a data loading circuit can refer to the circuitry other than the coupling circuit that facilitates the loading of the data voltage into the data capacitor. For example, the data loading circuit can include row interconnects, column interconnects, and the remainder of the circuitry (other than the coupling circuit) in the actuation circuit.

[0064] Figure 15 shows a block diagram of an example system 1500. The example system 1500 can include a controller 1502, an M x N array of HVCEs 1504, an actuation circuit 1506 (also referred to as an m x n array of actuation circuits), a power supply 1508, and memory 1510. The controller 1502 can include one or more of a microcontroller, a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or other circuitry for controlling the operation of the system 1500. The controller 1502 can perform the function of the controllers discussed above in relation to Figures 1-14. The M x N array of HVCEs 1504 can be similar to the M x N array of HVCEs discussed above in relation to Figures 1-14, and in particular in reference to Figure 1. The actuation circuit 1506 can be any one of the actuation circuits discussed above, and in particular the actuation circuits discussed in reference to Figures 2-8. The power supply 1508 can provide the desired voltages to the M x N array of HVCEs 1504 and the actuation circuit 1506, and can be controlled by the controller 1502 to provide voltages such as, for example, the charging voltage and the discharging voltage to one or more power supply terminals, or provide an HVCE global power supply. The memory 1510 can store data and instructions for the controller 1502 to access for controlling the operation of the M x N array of HVCEs 1504, the actuation circuit 1506, and the power supply 1508, as discussed above in relation to Figures 1-14.

[0065] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any of the other several embodiments without departing from the scope or spirit of the present disclosure.

[0066] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0067] When a range is expressed, a further aspect includes from the one particular value and/or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g., the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’ . Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0068] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the subranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0069] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0070] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms may be defined elsewhere in the present disclosure.

[0071] As used herein, “comprising” is to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more features, integers, steps, or components, or groups thereof. Moreover, each of the terms “by”, “comprising,” “comprises”, “comprised of,” “including,” “includes,” “included,” “involving,” “involves,” “involved,” and “such as” are used in their open, nonlimiting sense and may be used interchangeably. Further, the term “comprising” is intended to include examples and aspects encompassed by the terms “consisting essentially of’ and “consisting of.” Similarly, the term “consisting essentially of’ is intended to include examples encompassed by the term “consisting of.

[0072] As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise.

[0073] The various concepts introduced above may be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0074] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0075] From the foregoing, it will be seen that aspects herein are well adapted to attain all the ends and objects hereinabove set forth together with other advantages which are obvious and which are inherent to the structure.

[0076] While specific elements and steps are discussed in connection to one another, it is understood that any element and/or steps provided herein is contemplated as being combinable with any other elements and/or steps regardless of explicit provision of the same while still being within the scope provided herein.

[0077] It will be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims.

[0078] Since many possible aspects may be made without departing from the scope thereof, it is to be understood that all matter herein set forth or shown in the accompanying drawings and detailed description is to be interpreted as illustrative and not in a limiting sense.

[0079] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. The skilled artisan will recognize many variants and adaptations of the aspects described herein. These variants and adaptations are intended to be included in the teachings of this disclosure and to be encompassed by the claims herein.

[0080] The present disclosure will be better understood upon reading the following aspects, which should not be confused with the claims. Each of the number aspects described below can in some instances be combined with one or more additional aspects described below as well as with one or more aforementioned aspects of the disclosure.

[0081] Aspect 1. An electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, comprising m x n actuation circuits , wherein each actuation circuit of the m x n actuation circuits corresponds to a HVCE of the array of HVCEs, wherein each m x n-th actuation circuit includes an actuation switch coupled with a first terminal of a corresponding HVCE, a capacitor coupled with the control terminal of the actuation switch, another terminal of the capacitor coupled with a ground terminal, a data switch coupled with the capacitor, the data switch configured to charge or discharge the capacitor based on a voltage on a n-th column interconnect coupled with one of the terminals of the data switch responsive to activation of a first activation signal on a m-th row interconnect coupled with the control terminal of the data switch, an actuation time limiting switch coupled with the capacitor, the actuation time limiting switch configured to charge or discharge the capacitor based on a target voltage at one of its terminals responsive to activation of a second activation signal, which is activated after an activation and de-activation of the first activation signal.

[0082] Aspect 2. The electric circuit of any one of aspects 1-6, wherein the m-th row interconnect is a first m-th row interconnect coupled with the control terminal of the data switch of each actuation circuit in the m-th row on the m x n actuation circuits, wherein the electric circuit comprise a second m-th row interconnect providing the second activation signal and coupled with the control terminal of the actuation time limiting switch of each actuation circuit in the m-th row on the m x n actuation circuits.

[0083] Aspect 3. The electric circuit of any one of aspects 1-6, wherein the target voltage is a ground voltage

[0084] Aspect 4. The electric circuit of any one of aspects 1-6, wherein the n-th column interconnect is a first n-th column interconnect, wherein the electric circuit further comprises a second n-th column interconnect, and wherein the target voltage is provided by the second n- th column interconnect.

[0085] Aspect 5. The electric circuit of any one of aspects 1-6, wherein the second activation signal is provided by a row interconnect in a row adjacent to the row in which the m x n-th actuation circuit is included.

[0086] Aspect 6. The electric circuit of any one of aspects 1-6, wherein the actuation switch has a offset gate structure.

[0087] Aspect 7. An electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, comprising: m x n actuation circuits, wherein each actuation circuit of the m x n actuation circuits includes: a first actuation switch coupled with a first terminal of a corresponding HVCE; a second actuation switch coupled with a second terminal of the corresponding HVCE; a first capacitor coupled with the control terminal of the first actuation switch, another terminal of the first capacitor coupled with a ground terminal; a second capacitor coupled with the control terminal of the second actuation switch, another terminal of the second capacitor coupled with the ground terminal; a first data switch coupled with the first capacitor, the first data switch configured to charge or discharge the first capacitor based on a voltage on a first n-th column interconnect coupled with one of the terminals of the first data switch responsive to activation of a first m-th row activation signal on a first m-th row interconnect coupled with the control terminal of the first data switch; a second data switch coupled with the second capacitor, the second data switch configured to charge or discharge the second capacitor based on a voltage on a second n-th column interconnect coupled with one of the terminals of the second data switch responsive to activation of the first m-th row activation signal on the first m-th row interconnect coupled with the control terminal of the second data switch; a first actuation time limiting switch coupled with the first capacitor, the first actuation time limiting switch configured to charge or discharge the first capacitor based on a first target voltage on a third n-th column interconnect coupled with one of the terminals of the first actuation time limiting switch responsive to activation of a second m-th row activation signal on a second m-th row interconnect coupled with the control terminal of the first actuation time limiting switch; a second actuation time limiting switch coupled with the second capacitor, the second actuation time limiting switch configured to charge or discharge the second capacitor based on a second target voltage on a fourth n-th column interconnect coupled with one of the terminals of the second actuation time limiting switch responsive to activation of the second m-th row activation signal on the second m-th row interconnect coupled with the control terminal of the second actuation time limiting switch; a first drive interconnect providing a first drive voltage coupled with the first terminal of the HVCE; and a second drive interconnect providing a second drive voltage coupled with the second terminal of the HVCE.

[0088] Aspect 8. The electric circuit of any one of aspects 7-11, wherein at a first instance of time the voltage on the first n-th column interconnect is greater than the voltage on the second n-th column interconnect such that the first capacitor is charged to the voltage on the first n-th column interconnect and the second capacitor is discharged to the voltage on the second n-th column interconnect, and wherein a first current flows from the second drive interconnect and through the corresponding HVCE from the second terminal of the corresponding HVCE to the first terminal of the corresponding HVCE.

[0089] Aspect 9. The electric circuit of any one of aspects 7-11, wherein the first drive interconnect is held at a high impedance state.

[0090] Aspect 10. The electric circuit of any one of aspects 7-11, wherein at a second instance of time after the first instance of time, the voltage on the first n-th column interconnect is less than the voltage on the second n-th column interconnect such that the first capacitor is discharged to the voltage on the first n-th column interconnect and the second capacitor is charge to the voltage on the second n-th column interconnect, and wherein a second current flows from the first drive interconnect and through the corresponding HVCE from the first terminal of the corresponding HVCE to the second terminal of the corresponding HVCE.

[0091] Aspect 11. The electric circuit of any one of aspects 7-11, wherein the second drive interconnect is held at a high impedance state.

[0092] Aspect 12. An electric circuit for controlling an m x n array of high voltage capacitive elements (HVCEs), the electric circuit comprising: an m x n array of actuation circuits, wherein each of the m x n actuation circuits includes: a coupling circuit configured to selectively charge or discharge the corresponding HVCE from at least one power supply terminal based on at least one data voltage; a data loading circuit coupled with the m x n array of actuation circuits, the data loading circuit configured to load at least one data voltage in each of the m x n actuation circuits; a controller coupled with the m x n actuation circuits, the data loading circuit, and a power supply providing the at least one power supply terminal, the controller configured to: for a set of charging frame durations, control the power supply to provide a charging voltage at the at least one power supply terminal, for a set of discharging frame durations, control the power supply to provide a discharging voltage at the at least one power supply terminal, and for each frame duration of the set of charging frame durations and the set of discharging frame durations, control the data loading circuit to load a data voltage in each of the m x n actuation circuits.

[0093] Aspect 13. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: for a first HVCE from the m x n array of HVCEs, determine that a present voltage level is less than a target voltage level, based on the determination, during at least one charging frame duration of the set of charging frame durations, control the data loading circuit to provide the data voltage to the coupling circuit of a first actuation circuit of the m x n array of actuation circuits corresponding to the first HVCE causing the coupling circuit to charge the first HVCE via the at least one power supply terminal.

[0094] Aspect 14. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: determine a number of the at least one charging frame duration based on a RC time constant associated with charging the first HVCE and a time period within each of the at least one charging frame duration for which the HVCE is charged.

[0095] Aspect 15. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: identify an HVCE from the m x n array of HVCEs for which a difference between its present voltage level and its target voltage level is greater than that for all remainder of the m x n array of HVCEs, and select a number of the set of charging frame durations to be at least equal to that needed to charge the HVCE to its target voltage.

[0096] Aspect 16. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: for a second HVCE from the m x n array of HVCEs, determine that a present voltage level is greater than a target voltage level, based on the determination, during at least one discharging frame duration of the set of discharging frame durations, control the data loading circuit to provide the data voltage to the coupling circuit of a second actuation circuit of the m x n array of actuation circuits corresponding to the second HVCE causing the coupling circuit to discharge the second HVCE via the at least one power supply terminal.

[0097] Aspect 17. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: determine a number of the at least one discharging frame duration based on an RC time constant associated with discharging the second HVCE and a time period within each of the at least one discharging frame duration for which the HVCE is discharged.

[0098] Aspect 18. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: identify an HVCE from the m x n array of HVCEs for which a magnitude of a difference between its present voltage level and its target voltage level is greater than that for all remainder of the m x n array of HVCEs, and select a number of the set of discharging frame durations to be at least equal to that needed to discharge the HVCE to its target voltage level.

[0099] Aspect 19. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: for a set of floating frame durations that form a subset of the set of charging frame durations or the set of discharging frame durations, control the data loading circuit to load a data voltage in each of the m x n actuation circuits to cause the respective coupling circuit to disconnect the corresponding HVCE from the at least one power supply terminal.

[0100] Aspect 20. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: temporally position the set of floating frame durations between the set of charging frame durations and the set of discharging frame durations.

[0101] Aspect 21. The electric circuit of any one of aspects 12-22, wherein the power supply provides a first power supply terminal and a second power supply terminal, the power supply configured to selectively enable one of the first power supply terminal and the second power supply terminal to provide the charging voltage or the discharging voltage and selectively disable the other of the first power supply terminal and the second power supply terminal to provide a high impedance state, wherein the first power supply terminal is coupled with a first HVCE terminal of the m x n array of HVCEs and the second power supply terminal is coupled with a second HVCE terminal of the m x n array of HVCEs, wherein the controller is configured to: control the power supply to enable the first power supply terminal and disable the second power supply terminal, control the coupling circuit to selectively charge or discharge the corresponding HVCE from the first power supply terminal by selectively coupling a second HVCE terminal of the corresponding HVCE with a ground terminal, for a second polarity duration temporally separate from the first duration: control the power supply to disable the first power supply terminal and enable the second power supply terminal, control the coupling circuit to selectively charge or discharge the corresponding HVCE from the second power supply terminal by selectively coupling the first terminal of the corresponding HVCE with a ground terminal.

[0102] Aspect 22. The electric circuit of any one of aspects 12-22, wherein the controller is further configured to: for the first polarity duration and for the second polarity duration: for each of the set of charging frame durations and each of the set of discharging frame durations, add a present voltage of each HVCE of the m x n HVCEs to a value in a corresponding entry in a m x n data structure, wherein the present voltage has a positive polarity during the first polarity duration and has a negative polarity during the second polarity duration.

Claims

CLAIMS What is claimed is:

1. An electric circuit for controlling an m x n array of high voltage capacitive elements (HVCEs), the electric circuit comprising: an m x n array of actuation circuits, wherein each of the m x n actuation circuits includes: a coupling circuit configured to selectively charge or discharge the corresponding HVCE from at least one power supply terminal based on at least one data voltage; a data loading circuit coupled with the m x n array of actuation circuits, the data loading circuit configured to load at least one data voltage in each of the m x n actuation circuits; a controller coupled with the m x n actuation circuits, the data loading circuit, and a power supply providing the at least one power supply terminal, the controller configured to: for a set of charging frame durations, control the power supply to provide a charging voltage at the at least one power supply terminal, for a set of discharging frame durations, control the power supply to provide a discharging voltage at the at least one power supply terminal, and for each frame duration of the set of charging frame durations and the set of discharging frame durations, control the data loading circuit to load a data voltage in each of the m x n actuation circuits.

2. The electric circuit of claim 1, wherein the controller is further configured to: for a first HVCE from the m x n array of HVCEs, determine that a present voltage level is less than a target voltage level, based on the determination, during at least one charging frame duration of the set of charging frame durations, control the data loading circuit to provide the data voltage to the coupling circuit of a first actuation circuit of the m x n array of actuation circuits corresponding to the first HVCE causing the coupling circuit to charge the first HVCE via the at least one power supply terminal.

3. The electrical circuit of claim 2, wherein the controller is further configured to:

29 determine a number of the at least one charging frame duration based on a RC time constant associated with charging the first HVCE and a time period within each of the at least one charging frame duration for which the HVCE is charged.

4. The electrical circuit of claim 3, wherein the controller is further configured to: identify an HVCE from the m x n array of HVCEs for which a difference between its present voltage level and its target voltage level is greater than that for all remainder of the m x n array of HVCEs, and select a number of the set of charging frame durations to be at least equal to that needed to charge the HVCE to its target voltage.

5. The electrical circuit of claim 1, wherein the controller is further configured to: for a second HVCE from the m x n array of HVCEs, determine that a present voltage level is greater than a target voltage level, based on the determination, during at least one discharging frame duration of the set of discharging frame durations, control the data loading circuit to provide the data voltage to the coupling circuit of a second actuation circuit of the m x n array of actuation circuits corresponding to the second HVCE causing the coupling circuit to discharge the second HVCE via the at least one power supply terminal.

6. The electrical circuit of claim 5, wherein the controller is further configured to: determine a number of the at least one discharging frame duration based on an RC time constant associated with discharging the second HVCE and a time period within each of the at least one discharging frame duration for which the HVCE is discharged.

7. The electrical circuit of claim 6, wherein the controller is further configured to: identify an HVCE from the m x n array of HVCEs for which a magnitude of a difference between its present voltage level and its target voltage level is greater than that for all remainder of the m x n array of HVCEs, and select a number of the set of discharging frame durations to be at least equal to that needed to discharge the HVCE to its target voltage level.

8. The electrical circuit of any one of claims 1-6, wherein the controller is further configured to:

30 for a set of floating frame durations that form a subset of the set of charging frame durations or the set of discharging frame durations, control the data loading circuit to load a data voltage in each of the m x n actuation circuits to cause the respective coupling circuit to disconnect the corresponding HVCE from the at least one power supply terminal.

9. The electrical circuit of claim 8, wherein the controller is further configured to: temporally position the set of floating frame durations between the set of charging frame durations and the set of discharging frame durations.

10. The electrical circuit of any one of claims 1-9, wherein the power supply provides a first power supply terminal and a second power supply terminal, the power supply configured to selectively enable one of the first power supply terminal and the second power supply terminal to provide the charging voltage or the discharging voltage and selectively disable the other of the first power supply terminal and the second power supply terminal to provide a high impedance state, wherein the first power supply terminal is coupled with a first HVCE terminal of the m x n array of HVCEs and the second power supply terminal is coupled with a second HVCE terminal of the m x n array of HVCEs, wherein the controller is configured to: for a first polarity duration: control the power supply to enable the first power supply terminal and disable the second power supply terminal, control the coupling circuit to selectively charge or discharge the corresponding HVCE from the first power supply terminal by selectively coupling a second HVCE terminal of the corresponding HVCE with a ground terminal, for a second polarity duration temporally separate from the first duration: control the power supply to disable the first power supply terminal and enable the second power supply terminal, control the coupling circuit to selectively charge or discharge the corresponding HVCE from the second power supply terminal by selectively coupling the first terminal of the corresponding HVCE with a ground terminal.

11. The electrical circuit according to claims 10, wherein the controller is further configured to: for the first polarity duration and for the second polarity duration: for each of the set of charging frame durations and each of the set of discharging frame durations, add a present voltage of each HVCE of the m x n HVCEs to a value in a corresponding entry in a m x n data structure, wherein the present voltage has a positive polarity during the first polarity duration and has a negative polarity during the second polarity duration.

12. An electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, comprising: m x n actuation circuits, wherein each actuation circuit of the m x n actuation circuits corresponds to a HVCE of the array of HVCEs, wherein each m x n-th actuation circuit includes: an actuation switch coupled with a first terminal of a corresponding HVCE, a capacitor coupled with the control terminal of the actuation switch, another terminal of the capacitor coupled with a ground terminal, a data switch coupled with the capacitor, the data switch configured to charge or discharge the capacitor based on a voltage on a n-th column interconnect coupled with one of the terminals of the data switch responsive to activation of a first activation signal on a m- th row interconnect coupled with the control terminal of the data switch, an actuation time limiting switch coupled with the capacitor, the actuation time limiting switch configured to charge or discharge the capacitor based on a target voltage at one of its terminals responsive to activation of a second activation signal, which is activated after an activation and de-activation of the first activation signal.

13. The electric circuit of claim 12, wherein the m-th row interconnect is a first m-th row interconnect coupled with the control terminal of the data switch of each actuation circuit in the m-th row on the m x n actuation circuits, wherein the electric circuit comprise a second m-th row interconnect providing the second activation signal and coupled with the control terminal of the actuation time limiting switch of each actuation circuit in the m-th row on the m x n actuation circuits.

14. The electric circuit of claim 13, wherein the target voltage is a ground voltage.

15. The electric circuit of claim 12, wherein the n-th column interconnect is a first n-th column interconnect, wherein the electric circuit further comprises a second n-th column interconnect, and wherein the target voltage is provided by the second n-th column interconnect.

16. The electric circuit of claim 15, wherein the second activation signal is provided by a row interconnect in a row adjacent to the row in which the m x n-th actuation circuit is included.

17. The electric circuit of claim 12, wherein the actuation switch has an offset gate structure.

18. An electric circuit for controlling an array of high voltage capacitive elements (HVCEs) arranged in m rows by n columns, comprising: m x n actuation circuits, wherein each actuation circuit of the m x n actuation circuits includes: a first actuation switch coupled with a first terminal of a corresponding HVCE; a second actuation switch coupled with a second terminal of the corresponding HVCE; a first capacitor coupled with the control terminal of the first actuation switch, another terminal of the first capacitor coupled with a ground terminal; a second capacitor coupled with the control terminal of the second actuation switch, another terminal of the second capacitor coupled with the ground terminal; a first data switch coupled with the first capacitor, the first data switch configured to charge or discharge the first capacitor based on a voltage on a first n-th column interconnect coupled with one of the terminals of the first data switch responsive to activation of a first m-th row activation signal on a first m-th row interconnect coupled with the control terminal of the first data switch; a second data switch coupled with the second capacitor, the second data switch configured to charge or discharge the second capacitor based on a voltage on a second n-th column interconnect coupled with one of the terminals of the second data switch responsive to activation of the first m-th row activation signal on the first m-th row interconnect coupled with the control terminal of the second data switch;

33 a first actuation time limiting switch coupled with the first capacitor, the first actuation time limiting switch configured to charge or discharge the first capacitor based on a first target voltage on a third n-th column interconnect coupled with one of the terminals of the first actuation time limiting switch responsive to activation of a second m-th row activation signal on a second m-th row interconnect coupled with the control terminal of the first actuation time limiting switch; a second actuation time limiting switch coupled with the second capacitor, the second actuation time limiting switch configured to charge or discharge the second capacitor based on a second target voltage on a fourth n-th column interconnect coupled with one of the terminals of the second actuation time limiting switch responsive to activation of the second m-th row activation signal on the second m-th row interconnect coupled with the control terminal of the second actuation time limiting switch; a first drive interconnect providing a first drive voltage coupled with the first terminal of the HVCE; and a second drive interconnect providing a second drive voltage coupled with the second terminal of the HVCE.

19. The electric circuit of claim 18, wherein at a first instance of time the voltage on the first n-th column interconnect is greater than the voltage on the second n-th column interconnect such that the first capacitor is charged to the voltage on the first n-th column interconnect and the second capacitor is discharged to the voltage on the second n-th column interconnect, and wherein a first current flows from the second drive interconnect and through the corresponding HVCE from the second terminal of the corresponding HVCE to the first terminal of the corresponding HVCE.

20. The electric circuit of claim 19, wherein the first drive interconnect is held at a high impedance state.

21. The electric circuit of claim 19, wherein at a second instance of time after the first instance of time, the voltage on the first n-th column interconnect is less than the voltage on the second n-th column interconnect such that the first capacitor is discharged to the voltage on the first n-th column interconnect and the second capacitor is charge to the voltage on the second n-th column interconnect, and wherein a second current flows from the first drive

34 interconnect and through the corresponding HVCE from the first terminal of the corresponding HVCE to the second terminal of the corresponding HVCE.

22. The electric circuit of claim 21, wherein the second drive interconnect is held at a high impedance state.

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