WO2023032407A1 - Rectifier circuit, and semiconductor device and power supply device using same - Google Patents

Rectifier circuit, and semiconductor device and power supply device using same Download PDF

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Publication number
WO2023032407A1
WO2023032407A1 PCT/JP2022/023631 JP2022023631W WO2023032407A1 WO 2023032407 A1 WO2023032407 A1 WO 2023032407A1 JP 2022023631 W JP2022023631 W JP 2022023631W WO 2023032407 A1 WO2023032407 A1 WO 2023032407A1
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Prior art keywords
mosfet
rectifier circuit
voltage
drain
rectifier
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PCT/JP2022/023631
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French (fr)
Japanese (ja)
Inventor
明寛 三輪
浩幸 庄司
順一 坂野
智之 内海
孝裕 樋口
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株式会社日立パワーデバイス
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Publication of WO2023032407A1 publication Critical patent/WO2023032407A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/10Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode arranged for operation in series, e.g. for multiplication of voltage
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a rectifier circuit, and a semiconductor device and a power supply device using the rectifier circuit.
  • Diode rectifier circuits and synchronous rectifier circuits that use MOSFETs are used as rectifier circuits that are used in power supply devices and convert alternating current into direct current.
  • a synchronous rectifier circuit has low power loss because a MOSFET does not have a built-in potential like a diode and a forward current rises from 0V. Therefore, synchronous rectification circuits are used in power supply devices that require low loss, such as front-end power supplies.
  • Patent Document 1 and Patent Document 2 are known as conventional technologies related to synchronous rectification circuits.
  • a rectifier circuit based on the technology described in Patent Document 1 is composed of a control circuit having a comparator and a gate driver, a capacitor for supplying power to the control circuit, and a MOSFET.
  • the control circuit turns the MOSFET on and off by means of the gate driver according to the drain-source voltage of the MOSFET detected by the comparator.
  • the capacitor is charged by the drain-source voltage of the MOSFET when the MOSFET is off.
  • a normally-off enhancement-type low-voltage transistor Q1 and a normally-on depression-type high-voltage transistor Q2 are connected in series between an anode (A) and a cathode (K).
  • a low voltage transistor Q1 is turned on and off by the output of the comparator.
  • the comparator receives the source voltage of Q1 connected to the anode and the source voltage of the depletion type high voltage transistor Q3 connected to the cathode together with Q2.
  • a capacitor serving as a power source for the comparator is connected between the anode and the cathode via a high voltage transistor Q3, and is charged by the voltage between the anode and the cathode when Q1 is turned off.
  • a rectifier circuit according to the technology described in Patent Document 2 operates as a rectifying element having an anode and a cathode, like a diode.
  • JP 2015-116053 A Japanese Unexamined Patent Application Publication No. 2011-151788
  • Patent Document 1 if a high-voltage MOSFET is used to increase the voltage resistance of the rectifier circuit, the control circuit and capacitors also need to be increased in voltage. Further, when using a semiconductor switching element to control the input voltage to the comparator and the charging voltage of the capacitor to the voltage level of the comparator and the capacitor, a high withstand voltage semiconductor switching element is required. Therefore, increasing the withstand voltage of the rectifier circuit increases the power loss of the rectifier circuit.
  • the low withstand voltage transistor Q1 and the high withstand voltage transistor Q2 are connected in series, thereby increasing the withstand voltage of the rectifier circuit.
  • the high voltage transistor Q3 is used to control the input voltage to the comparator and the charging voltage of the capacitor, power loss in the rectifier circuit increases.
  • the present invention provides a rectifier circuit capable of increasing the withstand voltage while suppressing an increase in power loss, as well as a semiconductor device and a power supply device using this rectifier circuit.
  • the rectifier circuit allows a current to flow in one direction, and includes a first enhancement-type MOSFET, and a first MOSFET connected in series to the first MOSFET.
  • an enhancement-type second MOSFET with a low withstand voltage a control circuit that rectifies both the first MOSFET and the second MOSFET, a power supply to the control circuit, and a drain-source voltage in the second MOSFET and a capacitor charged by
  • a semiconductor device includes a rectifier circuit and a semiconductor package containing the rectifier circuit, and the rectifier circuit is the rectifier circuit according to the present invention.
  • a semiconductor device includes a bridge rectifier circuit including a plurality of rectifier circuits, and a semiconductor package containing the bridge rectifier circuits. Each is a rectifier circuit according to the invention as described above.
  • a power supply device has a rectifier circuit section, and the rectifier circuit section includes the rectifier circuit according to the present invention.
  • the present invention it is possible to increase the withstand voltage of the rectifier circuit while suppressing an increase in power loss. As a result, the power loss of a semiconductor device having a rectifier circuit or a power supply device having a rectifier circuit section can be reduced.
  • FIG. 1 is a circuit diagram showing the configuration of a rectifier circuit that is Example 1.
  • FIG. FIG. 10 is a circuit diagram showing the configuration of a rectifier circuit that is Example 2;
  • FIG. 11 is a circuit diagram showing the configuration of a rectifier circuit that is Example 3;
  • FIG. 10 is a current/voltage waveform diagram showing the operation of the rectifier circuit of Example 4;
  • FIG. 11 is a configuration diagram of a semiconductor device that is Example 5;
  • FIG. 11 is a configuration diagram of a semiconductor device that is Example 6;
  • FIG. 11 is a circuit diagram showing the configuration of a power supply device that is Embodiment 7;
  • FIG. 3 is a circuit diagram showing the configuration of a rectifier circuit as a first comparative example;
  • FIG. 5 is a circuit diagram showing the configuration of a rectifier circuit that is a second comparative example;
  • FIG. 1 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 1 of the present invention.
  • the rectifier circuit of the first embodiment includes a MOSFET QH1 with a high withstand voltage (for example, several hundred V or more) connected in series between a first terminal T1 and a second terminal T2, and a MOSFET QH1 It consists of a MOSFET QL1 with a lower withstand voltage, a control circuit 1, a diode D1, and a capacitor C1.
  • the source of the MOSFET QL1 and the drain of the MOSFET QH1 are connected to the first terminal T1 and the second terminal T2, respectively.
  • the drain of QL1 and the source of QH1 are connected together to form a series connection point.
  • the rectified current (I S ) flows in the direction from T1 to T2 in the series connection of QH1 and QL1, and does not flow in the direction from T2 to T1.
  • MOSFET QL1 and MOSFET QH1 are enhancement-type n-channel MOSFETs.
  • the control circuit 1 comprises a comparator COMP1 and a gate driver GD1.
  • Comparator COMP1 compares the drain-source voltage V QL1DS of MOSFET QL1 with a predetermined threshold.
  • the gate driver GD1 generates a control signal for controlling ON/OFF of the MOSFET QL1 and MOSFET QH1 based on the comparison result of the comparator COMP1. That is, MOSFET QL1 and MOSFET QH1 are turned on and off simultaneously by the same gate driver GD1.
  • Capacitor C1 supplies power to comparator COMP1 and gate driver GD1.
  • the MOSFET QL1 When the MOSFET QL1 is off, the positive voltage of the voltage V QL1DS applied across the drain-source of the MOSFET QL1 causes a flow from the drain terminal of the MOSFET QL1 to the source terminal via the capacitor C1 and the anti-backflow diode D1. The current charges the capacitor C1.
  • the drain-source voltage V QL1DS of the MOSFET QL1 is obtained by changing the voltage applied between the first terminal T1 and the second terminal T2 by the circuit section consisting of the MOSFET QL1, the MOSFET QH1 and the capacitor C1 It is the voltage to be divided.
  • the magnitude of V QL1DS is mainly determined by the ratio of the drain-source parasitic capacitance of MOSFET QH1, the drain-source parasitic capacitance of MOSFET QL1, and the capacitance of capacitor C1. Therefore, the voltage applied to the capacitor and the The detection voltage (input voltage) of the comparator can be set to a desired voltage level that is lower than the withstand voltage of the series connection of QH1 and QL1 and suitable for the capacitor and comparator.
  • MOSFETs QH1 and QL1 After MOSFETs QH1 and QL1 turn on, a rectified current (I S ) flows through each channel of MOSFETs QH1 and QL1. At this time, the drain-source voltage (V QL1DS ) of the MOSFET QL1 is expressed by the product of the ON resistance of the MOSFET QL1 and I S . For the same IS , the voltage drop across the on-resistance of the MOSFET is smaller than the on-voltage of the body diode, resulting in a low loss rectifier circuit.
  • V QL1DS negative value
  • V TH1 threshold
  • comparator COMP1 the output of comparator COMP1 transitions from high to low.
  • gate driver GD1 outputs an off-gate signal to each gate of MOSFETs QH1 and QL1. This causes the gate-source voltage of MOSFET QH1 (V QH1GS ) and the gate-source voltage of MOSFET QL1 (V QL1GS ) to decrease, thus turning off MOSFETs QH1 and QL1.
  • MOSFET QH1 and QL1 After MOSFETs QH1 and QL1 turn off, the drain-to-source voltage of MOSFET QL1 (V QL1DS (positive value)) divided by the circuit portion consisting of the respective drain-to-source capacitances of MOSFETs QH1 and QL1 and capacitor C1 , C1 are charged again.
  • V QL1DS positive value
  • Example 1 Synchronous rectification by turning on/off the MOSFET is applied in each of the comparative examples.
  • FIG. 8 is a circuit diagram showing the configuration of a rectifier circuit as a first comparative example.
  • one MOSFET is used in the same manner as the technique of Patent Document 1 described above.
  • the high-voltage MOSFET QH1 is turned on and off, and the rectified current flows through the high-voltage MOSFET QH1.
  • the detection voltage of the capacitor C1 is controlled to a desired level by the high voltage MOSFET QH2, and the detection voltage input to the comparator COMP1 is controlled to a desired level by the high voltage MOSFET QH3. controlled. Note that the detection voltage input to the comparator COMP1 is suppressed below the differential input voltage of the comparator COMP1.
  • a capacitor C2 is connected in series with the high voltage MOSFET QH2, and this capacitor C2 is connected to the input of the comparator COMP1.
  • a series circuit of a Zener diode ZD1 and a resistor R3 is connected between the first terminal T1 and the second terminal T2 in order to generate a gate drive voltage for the high voltage MOSFET QH3.
  • FIG. 9 is a circuit diagram showing the configuration of a rectifier circuit that is a second comparative example.
  • an enhancement-type low-voltage MOSFET QL1 and a depletion-type high-voltage MOSFET QH1 are connected in series, and a rectified current flows through the low-voltage MOSFET QL1 and the high-voltage MOSFET QH1.
  • the low voltage MOSFET QL1 is turned on/off, and the high voltage MOSFET QH1 increases the voltage of the rectifier circuit.
  • the voltage of the capacitor C1 and the detection voltage of the comparator COMP1 are controlled to desired levels by the depletion type high voltage MOSFET QH2.
  • QH1 and QH2 operate as normally-on switching elements.
  • the number of high voltage MOSFETs used in the first comparative example (FIG. 8) and the second comparative example (FIG. 9) is three (QH1, QH2, QH3) and two (QH1, QH2), respectively.
  • the number of high voltage MOSFETs used in the first embodiment (FIG. 1) is one.
  • the high voltage MOSFET QH1 through which a rectified current flows and increases the voltage resistance of the rectifier circuit, is a depletion type MOSFET that operates normally.
  • the high voltage MOSFET QH1 is an enhancement type MOSFET.
  • the enhancement-type high-voltage MOSFET and the enhancement-type low-voltage MOSFET are connected in series, and the high-voltage MOSFET increases the voltage resistance of the rectifier circuit.
  • Both of the withstand voltage MOSFETs are on/off controlled for rectifying operation.
  • the capacitor which is the power supply for the control circuit that rectifies the high-voltage MOSFET and the low-voltage MOSFET, is charged by the drain-source voltage of the low-voltage MOSFET, and the control circuit reduces the drain-source voltage of the low-voltage MOSFET. The voltage is detected, and the high-voltage MOSFET and the low-voltage MOSFET are rectified according to the detected voltage.
  • the power supply for the control circuit and the voltage level of the detection voltage can be set to a desired level without using a control element such as a high-voltage MOSFET while increasing the withstand voltage of the rectifier circuit.
  • a control element such as a high-voltage MOSFET
  • the high voltage MOSFET through which the rectified current flows is an enhancement type, it is possible to reduce the power loss and the cost. Therefore, according to the first embodiment, the withstand voltage of the rectifier circuit can be increased without increasing the power loss and cost.
  • FIG. 2 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 2 of the present invention. Differences from the first embodiment are mainly described below.
  • a Zener diode ZD1 is inserted between the drain and gate of the low-voltage MOSFET QL1.
  • the anode and cathode of Zener diode ZD1 are connected to the gate and drain, respectively.
  • the zener voltage of the zener diode ZD1 should be lower than the withstand voltage of the MOSFET QL1, lower than the rated voltage of the control circuit 1, or lower than the differential input voltage of the comparator COMP1.
  • the drain-source voltage V QL1DS of the MOSFET QL1 can be reliably suppressed below the withstand voltage of the MOSFET QL1, or the voltage of the capacitor C1 can be suppressed below the rated voltage of the control circuit 1, or the voltage of the comparator COMP1
  • the detection voltage can be suppressed below the differential input voltage of COMP1.
  • the magnitude of the voltage between the gate and source of the MOSFET QH1 can be suppressed lower than the withstand voltage between the gate and source of the MOSFET QH1. Therefore, the operational reliability of the rectifier circuit is improved.
  • FIG. 3 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 3 of the present invention. Differences from the first embodiment are mainly described below.
  • resistors R2 and R1 are connected in parallel to MOSFETs QL1 and QH1, respectively.
  • the voltage applied between the first terminal T1 and the second terminal T2 will be the drain-source voltage V QH1DS of MOSFET QH1 and the drain-source voltage of MOSFET QL1.
  • V-- QL1DS and V--QL1DS Thereby, the value of VQL1DS can be reliably set to a desired voltage value.
  • the voltage applied to the capacitor and the detected voltage (input voltage) of the comparator can be reliably set to desired voltage levels suitable for the capacitor and comparator.
  • FIG. 4 is a current/voltage waveform diagram showing the operation of the rectifier circuit that is Example 4 of the present invention. Differences from the first embodiment are mainly described below.
  • FIG. 4 shows the rectified current Is, the drain-source voltage V QL1DS of the MOSFET QL1, the gate-source voltage V QL1GS of the MOSFET QL1, and the gate-source voltage V QH1GS of the MOSFET QH1.
  • the rectified current IS is a sine half-wave current.
  • Example 4 the circuit configuration is similar to Example 1 (FIG. 1), but unlike Example 1, comparator COMP1 has two threshold values (V TH1 , V TH2 ) with different magnitudes.
  • the comparator COMP1 in Example 4 has a first threshold V TH1 and a second threshold V TH2 . Both V TH1 and V TH2 have negative values. V TH1 ⁇ V TH2 and the absolute value of V TH1 is greater than the absolute value of V TH2 .
  • the comparator COMP1 compares the drain-source voltage V QL1DS of the MOSFET QL1 with the first threshold value V TH1 when the MOSFETs QL1 and QH1 are turned on, and compares the drain-source voltage V QL1DS of the MOSFET QL1 with the first threshold value V TH1 when the MOSFETs QL1 and QH1 are turned off.
  • a source-to-source voltage V QL1DS is compared with a second threshold V TH2 .
  • Comparator COMP1 transitions its output from low to high when I S begins to flow and V QL1DS changes from positive to negative and then V QL1DS becomes lower than V TH1 .
  • the gate driver GD1 outputs an on-gate signal, increasing V-- QH1GS and V-- QL1GS . Therefore, QH1 and QL1 are turned on.
  • VQL1DS When QH1 and QL1 are turned on, VQL1DS once increases and then changes in a half-sinusoidal fashion, but does not reach the second threshold VTH2 . Therefore, the output of the comparator COMP1 is maintained at a high level, so QH1 and QL1 are maintained on.
  • comparator COMP1 transitions its output from high to low.
  • the gate driver GD1 outputs an off-gate signal, so that V-- QH1GS and V-- QL1GS decrease. Therefore, QH1 and QL1 are turned off.
  • the threshold with which the comparator COMP1 compares the drain-source voltage V QL1DS of the MOSFET QL1 differs between the turn-on operation and the turn-off operation, so that the output level of the comparator COMP1 switches between high and low in a short period of time. , so-called chattering can be prevented. This prevents an unstable operation in which the turn-on operation and turn-off operation of the rectifier circuit are repeated in a short period of time.
  • the operational stability of the rectifier circuit is improved.
  • V QL1DS of the MOSFET QL1 after turn-on fluctuates greatly
  • setting V TH1 and V TH2 according to the fluctuation range of V QL1DS improves the stability of the operation of the rectifier circuit. definitely improve.
  • a hysteresis comparator for example, can be applied as the comparator in the fourth embodiment.
  • FIG. 5 is a configuration diagram of a semiconductor device that is Embodiment 5 of the present invention.
  • Example 5 a rectifier circuit 2 is built in a semiconductor package 3 as a semiconductor circuit.
  • the rectifier circuit 2 the rectifier circuit of Example 1 (FIG. 1) is applied. Therefore, the high-voltage MOSFET Q1, the low-voltage MOSFET Q2, the capacitor C1, the backflow prevention diode D1, and the control circuit 1 (comparator COMP1, gate driver GD1), which constitute the rectifier circuit 2, are incorporated in the semiconductor package 3.
  • the rectifier circuit 2 is resin-sealed with molding resin or a resin case, and the first terminal T1 and the second terminal T2 are exposed on the outer surface of the resin that seals the rectifier circuit 2.
  • the synchronous rectification circuit can be easily applied as a substitute for the rectifier diode, and the electrical/electronic device provided with the rectifier circuit section can be reduced in loss.
  • the semiconductor device of Example 5 uses synchronous rectification, it operates as a two-terminal rectifying element like a diode. Therefore, it is possible to reduce man-hours for designing and mounting the electric/electronic device including the rectifier circuit section.
  • any one of the rectifier circuits of Examples 2 to 4 may be applied.
  • FIG. 6 is a configuration diagram of a semiconductor device that is Embodiment 6 of the present invention.
  • rectifier circuits 2, 5, 6, and 7 are incorporated in a semiconductor package 4 as semiconductor circuits.
  • a circuit similar to that of the first embodiment (FIG. 1) is applied to the rectifier circuit 2 .
  • a circuit similar to that of the first embodiment (FIG. 1) is applied to each of the rectifier circuits 5, 6, and 7 as well.
  • These rectifier circuits 2, 5, 6 and 7 form a single-phase bridge rectifier circuit.
  • the rectifier circuits 2, 5, 6, and 7 are resin-sealed with molding resin or a resin case, and a pair of AC terminals T4, T5 and a pair of DC terminals T3, T6 of the single-phase bridge rectifier circuit are connected. , are exposed to the outer surface of the resin that seals the rectifier circuits 2, 5, 6, 7.
  • the synchronous rectifier circuit can be easily applied to the single-phase bridge rectifier circuit as a substitute for the rectifier diode, and the loss of the single-phase bridge rectifier circuit and the electric/electronic device equipped with the single-phase bridge rectifier circuit can be reduced. can do.
  • the semiconductor device of Example 6 can have compatibility with the diode bridge by matching the arrangement of the AC terminals T4, T5 and the DC terminals T3, T6 in the semiconductor package 4 with the packaged diode bridge. .
  • the semiconductor device of Example 6 operates as a four-terminal rectifying element like a single-phase diode bridge while using synchronous rectification. Therefore, it is possible to reduce man-hours for designing and mounting an electric/electronic device including a full-wave rectifier circuit.
  • a three-phase bridge rectifier circuit can be configured by using six rectifier circuits of any one of Examples 1 to 4. In this case, three AC terminals and a pair of DC terminals for three phases are exposed on the outer surface of the resin that seals the six rectifier circuits.
  • FIG. 7 is a circuit diagram showing the configuration of a power supply device that is Embodiment 7 of the present invention.
  • the power supply device in FIG. 7 converts AC power from a commercial AC power supply into DC power with a desired voltage and outputs the DC power.
  • rectifying elements CRD1 to CRD4 constituting a bridge rectifying circuit for rectifying the AC voltage of the commercial AC voltage, a rectifying element FWD1 for freewheeling in the chopper circuit section, At least one of the rectifying elements SSD1 and SSD2 constituting the rectifying circuit section that receives the AC output power of the inverter circuit section via a transformer and converts it to a desired DC voltage, and the rectifying element ORD1 for preventing backflow.
  • the rectifier circuit of any one of Examples 1 to 4, or the semiconductor device of Example 5 is applied.
  • the single-phase bridge rectifier circuit of Example 6 may be used for the rectifying elements CRD1 to CRD4.
  • the rectifying element connected in parallel with the MOSFET is a parasitic diode (body diode) of the MOSFET.
  • the circuit configuration of the power supply device in FIG. 7 is a known circuit configuration.
  • the seventh embodiment it is possible to reduce the power loss of the power supply device. It should be noted that the power supply device according to the seventh embodiment is suitable for a front-end power supply that requires high efficiency.
  • the rectifier circuits of Examples 1 to 4 and the semiconductor devices of Examples 5 and 6 can be applied not only to the front power supply but also to various power supply apparatuses having a rectifier circuit section.
  • the present invention is not limited to the above-described embodiments, and includes various modifications.
  • the above embodiments have been described in detail to facilitate understanding of the present invention, and are not necessarily limited to those having all the described configurations.
  • it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.
  • the MOSFET is not limited to an n-channel type, and may be a p-channel type.
  • the semiconductor material forming the MOSFET is not limited to silicon (Si), but may be a wide bandgap semiconductor such as silicon carbide (SiC).

Abstract

Disclosed is a rectifier circuit that makes it possible to achieve a high breakdown voltage while suppressing an increase in power loss, and a semiconductor device and a power supply device using this rectifier circuit. This rectifier circuit supplies a current in one direction, said rectifier circuit comprising: a first enhancement type MOSFET (QH1); a second enhancement type MOSFET (QL1) that is connected in series to the first MOSFET and that has a lower breakdown voltage than the first MOSFET; a control circuit (1) that causes the first MOSFET and the second MOSFET to perform a rectification operation; and a capacitor (C1) that supplies power to the control circuit and that is charged by the voltage between the drain and the source of the second MOSFET.

Description

整流回路、並びに、それを用いる半導体装置および電源装置Rectifier circuit, semiconductor device and power supply device using the same
 本発明は、整流回路、並びに整流回路を用いる半導体装置および電源装置に関する。 The present invention relates to a rectifier circuit, and a semiconductor device and a power supply device using the rectifier circuit.
 電源装置に用いられ、交流を直流に変換する整流回路としては、ダイオード整流回路や、MOSFETを用いる同期整流回路が使用されている。同期整流回路は、MOSFETがダイオードのような内蔵ポテンシャルを有さず0Vから順方向電流が立ち上がるため、電力損失が低い。したがって、フロントエンド電源などのように低損失化を要する電源装置においては、同期整流回路が用いられている。 Diode rectifier circuits and synchronous rectifier circuits that use MOSFETs are used as rectifier circuits that are used in power supply devices and convert alternating current into direct current. A synchronous rectifier circuit has low power loss because a MOSFET does not have a built-in potential like a diode and a forward current rises from 0V. Therefore, synchronous rectification circuits are used in power supply devices that require low loss, such as front-end power supplies.
 同期整流回路に関する従来技術として、特許文献1および特許文献2に記載される技術が知られている。 The techniques described in Patent Document 1 and Patent Document 2 are known as conventional technologies related to synchronous rectification circuits.
 特許文献1に記載の技術では、オルタネータに用いられる低損失な整流回路として、制御回路とMOSFETが1つのパッケージに搭載される。この整流回路は、ダイオードのように、電流を一方向に流す機能(整流機能)を有する2端子の半導体装置として動作する。 In the technology described in Patent Document 1, a control circuit and a MOSFET are mounted in one package as a low-loss rectifier circuit used in an alternator. Like a diode, this rectifier circuit operates as a two-terminal semiconductor device having a function of flowing current in one direction (rectifying function).
 特許文献1に記載の技術による整流回路は、比較器およびゲートドライバを有する制御回路と、制御回路に電源を供給するコンデンサと、MOSFETとから構成されている。制御回路は、比較器によって検出されるMOSFETのドレイン-ソース間電圧に応じて、ゲートドライバによってMOSFETをオン・オフする。コンデンサは、MOSFETがオフしているときに、MOSFETのドレイン-ソース間電圧によって充電される。 A rectifier circuit based on the technology described in Patent Document 1 is composed of a control circuit having a comparator and a gate driver, a capacitor for supplying power to the control circuit, and a MOSFET. The control circuit turns the MOSFET on and off by means of the gate driver according to the drain-source voltage of the MOSFET detected by the comparator. The capacitor is charged by the drain-source voltage of the MOSFET when the MOSFET is off.
 特許文献2に記載の技術では、アノード(A)とカソード(K)の間に、ノーマリオフのエンハンスメント型の低耐圧トランジスタQ1と、ノーマリオンのデプレッション型の高耐圧トランジスタQ2とが直列接続される。低耐圧トランジスタQ1が、比較器の出力によってオン・オフされる。比較器は、アノードに接続されるQ1のソース電圧と、Q2とともにカソードに接続されるデプレッション型の高耐圧トランジスタQ3のソース電圧を入力とする。比較器の電源となるコンデンサは、高耐圧トランジスタQ3を介して、アノード・カソード間に接続され、Q1のオフ時に、アノード・カソード間電圧によって充電される。 In the technique described in Patent Document 2, a normally-off enhancement-type low-voltage transistor Q1 and a normally-on depression-type high-voltage transistor Q2 are connected in series between an anode (A) and a cathode (K). A low voltage transistor Q1 is turned on and off by the output of the comparator. The comparator receives the source voltage of Q1 connected to the anode and the source voltage of the depletion type high voltage transistor Q3 connected to the cathode together with Q2. A capacitor serving as a power source for the comparator is connected between the anode and the cathode via a high voltage transistor Q3, and is charged by the voltage between the anode and the cathode when Q1 is turned off.
 特許文献2に記載の技術による整流回路は、ダイオードのように、アノードおよびカソードを備える整流素子として動作する。 A rectifier circuit according to the technology described in Patent Document 2 operates as a rectifying element having an anode and a cathode, like a diode.
特開2015-116053号公報JP 2015-116053 A 特開2011-151788号公報Japanese Unexamined Patent Application Publication No. 2011-151788
 特許文献1の技術では、整流回路を高耐圧化するために高耐圧MOSFETを用いると、制御回路やコンデンサも高電圧化を必要とする。また、半導体スイッチング素子を用いて、比較器への入力電圧やコンデンサの充電電圧を、比較器やコンデンサの電圧レベルに制御する手段を用いる場合には、高耐圧の半導体スイッチング素子が必要となる。したがって、整流回路を高耐圧化すると、整流回路の電力損失が増大する。 With the technology of Patent Document 1, if a high-voltage MOSFET is used to increase the voltage resistance of the rectifier circuit, the control circuit and capacitors also need to be increased in voltage. Further, when using a semiconductor switching element to control the input voltage to the comparator and the charging voltage of the capacitor to the voltage level of the comparator and the capacitor, a high withstand voltage semiconductor switching element is required. Therefore, increasing the withstand voltage of the rectifier circuit increases the power loss of the rectifier circuit.
 特許文献2の技術では、低耐圧トランジスタQ1と、高耐圧トランジスタQ2とが直列接続されることにより、整流回路を高耐圧化することができる。しかしながら、比較器への入力電圧やコンデンサの充電電圧を制御するために高耐圧トランジスタQ3が用いられるので、整流回路の電力損失が増大する。 In the technique of Patent Document 2, the low withstand voltage transistor Q1 and the high withstand voltage transistor Q2 are connected in series, thereby increasing the withstand voltage of the rectifier circuit. However, since the high voltage transistor Q3 is used to control the input voltage to the comparator and the charging voltage of the capacitor, power loss in the rectifier circuit increases.
 そこで、本発明は、電力損失の増大を抑制しながら高耐圧化することができる整流回路、並びに、この整流回路を用いる半導体装置および電源装置を提供する。 Accordingly, the present invention provides a rectifier circuit capable of increasing the withstand voltage while suppressing an increase in power loss, as well as a semiconductor device and a power supply device using this rectifier circuit.
 上記課題を解決するために、本発明による整流回路は、電流を一方向に流すものであって、エンハンスメント型の第1のMOSFETと、第1のMOSFETに直列に接続され、第1のMOSFETよりも低耐圧のエンハンスメント型の第2のMOSFETと、第1のMOSFETと第2のMOSFETとを共に整流動作させる制御回路と、制御回路に電源を供給し、第2のMOSFETにおけるドレイン-ソース間電圧によって充電されるコンデンサと、を備える。 In order to solve the above-mentioned problems, the rectifier circuit according to the present invention allows a current to flow in one direction, and includes a first enhancement-type MOSFET, and a first MOSFET connected in series to the first MOSFET. an enhancement-type second MOSFET with a low withstand voltage, a control circuit that rectifies both the first MOSFET and the second MOSFET, a power supply to the control circuit, and a drain-source voltage in the second MOSFET and a capacitor charged by
 上記課題を解決するために、本発明による半導体装置は、整流回路と、整流回路を内蔵する半導体パッケージと、を備えるものであって、整流回路が、上記の本発明による整流回路である。 In order to solve the above problems, a semiconductor device according to the present invention includes a rectifier circuit and a semiconductor package containing the rectifier circuit, and the rectifier circuit is the rectifier circuit according to the present invention.
 上記課題を解決するために、本発明による半導体装置は、複数の整流回路から構成されるブリッジ整流回路と、ブリッジ整流回路を内蔵する半導体パッケージと、を備えるものであって、複数の整流回路の各々が、上記の本発明による整流回路である。 In order to solve the above-described problems, a semiconductor device according to the present invention includes a bridge rectifier circuit including a plurality of rectifier circuits, and a semiconductor package containing the bridge rectifier circuits. Each is a rectifier circuit according to the invention as described above.
 上記課題を解決するために、本発明による電源装置は、整流回路部を有するものであって、整流回路部が、上記の本発明による整流回路を備える。 In order to solve the above problems, a power supply device according to the present invention has a rectifier circuit section, and the rectifier circuit section includes the rectifier circuit according to the present invention.
 本発明によれば、整流回路を電力損失の増大を抑制しながら高耐圧化することができる。これにより、整流回路を有する半導体装置や、整流回路部を有する電源装置の電力損失を低減できる。 According to the present invention, it is possible to increase the withstand voltage of the rectifier circuit while suppressing an increase in power loss. As a result, the power loss of a semiconductor device having a rectifier circuit or a power supply device having a rectifier circuit section can be reduced.
 上記した以外の課題、構成および効果は、以下の実施形態の説明により明らかにされる。 Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.
実施例1である整流回路の構成を示す回路図である。1 is a circuit diagram showing the configuration of a rectifier circuit that is Example 1. FIG. 実施例2である整流回路の構成を示す回路図である。FIG. 10 is a circuit diagram showing the configuration of a rectifier circuit that is Example 2; 実施例3である整流回路の構成を示す回路図である。FIG. 11 is a circuit diagram showing the configuration of a rectifier circuit that is Example 3; 実施例4である整流回路の動作を示す電流・電圧波形図である。FIG. 10 is a current/voltage waveform diagram showing the operation of the rectifier circuit of Example 4; 実施例5である半導体装置の構成図である。FIG. 11 is a configuration diagram of a semiconductor device that is Example 5; 実施例6である半導体装置の構成図である。FIG. 11 is a configuration diagram of a semiconductor device that is Example 6; 実施例7である電源装置の構成を示す回路図である。FIG. 11 is a circuit diagram showing the configuration of a power supply device that is Embodiment 7; 第1の比較例である整流回路の構成を示す回路図である。FIG. 3 is a circuit diagram showing the configuration of a rectifier circuit as a first comparative example; 第2の比較例である整流回路の構成を示す回路図である。FIG. 5 is a circuit diagram showing the configuration of a rectifier circuit that is a second comparative example;
 以下、本発明の実施形態について、下記の実施例1~7により、図面を用いながら説明する。各図において、参照番号が同一のものは同一の構成要件あるいは類似の機能を備えた構成要件を示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings in Examples 1 to 7 below. In each figure, the same reference numbers denote the same components or components with similar functions.
 図1は、本発明の実施例1である整流回路の構成を示す回路図である。 FIG. 1 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 1 of the present invention.
 実施例1の整流回路は、図1に示すように、第1の端子T1と第2の端子T2との間に直列接続される高耐圧(例えば、数100V以上)のMOSFET QH1と、MOSFET QH1よりも低耐圧のMOSFET QL1と、制御回路1と、ダイオードD1と、コンデンサC1から構成される。 As shown in FIG. 1, the rectifier circuit of the first embodiment includes a MOSFET QH1 with a high withstand voltage (for example, several hundred V or more) connected in series between a first terminal T1 and a second terminal T2, and a MOSFET QH1 It consists of a MOSFET QL1 with a lower withstand voltage, a control circuit 1, a diode D1, and a capacitor C1.
 第1の端子T1および第2の端子T2には、それぞれ、MOSFET QL1のソースおよびMOSFET QH1のドレインが接続される。QL1のドレインとQH1のソースとが互いに接続され、直列接続点となる。なお、実施例1では、整流電流(I)は、QH1とQL1の直列接続において、T1からT2へ向かう方向へ流れ、T2からT1に向かう方向へは流れない。 The source of the MOSFET QL1 and the drain of the MOSFET QH1 are connected to the first terminal T1 and the second terminal T2, respectively. The drain of QL1 and the source of QH1 are connected together to form a series connection point. In Example 1, the rectified current (I S ) flows in the direction from T1 to T2 in the series connection of QH1 and QL1, and does not flow in the direction from T2 to T1.
 なお、実施例1において、MOSFET QL1およびMOSFET QH1は、エンハンスメント型のnチャネルMOSFETである。 In addition, in Example 1, MOSFET QL1 and MOSFET QH1 are enhancement-type n-channel MOSFETs.
 制御回路1は、比較器COMP1とゲートドライバGD1から構成される。比較器COMP1は、MOSFET QL1のドレイン-ソース間電圧VQL1DSと所定の閾値を比較する。ゲートドライバGD1は比較器COMP1の比較結果に基づき、MOSFET QL1およびMOSFET QH1のオン・オフを制御する制御信号を生成する。すなわち、MOSFET QL1およびMOSFET QH1は同じゲートドライバGD1によって、同時にターンオンされるとともに、同時にターンオフされる。 The control circuit 1 comprises a comparator COMP1 and a gate driver GD1. Comparator COMP1 compares the drain-source voltage V QL1DS of MOSFET QL1 with a predetermined threshold. The gate driver GD1 generates a control signal for controlling ON/OFF of the MOSFET QL1 and MOSFET QH1 based on the comparison result of the comparator COMP1. That is, MOSFET QL1 and MOSFET QH1 are turned on and off simultaneously by the same gate driver GD1.
 コンデンサC1は、比較器COMP1とゲートドライバGD1に電源を供給する。MOSFET QL1がオフの時に、MOSFET QL1のドレイン-ソース間に印加される電圧VQL1DSの正の電圧によって、コンデンサC1と逆流防止用ダイオードD1とを経由してMOSFET QL1のドレイン端子からソース端子へ流れる電流によってコンデンサC1は充電される。 Capacitor C1 supplies power to comparator COMP1 and gate driver GD1. When the MOSFET QL1 is off, the positive voltage of the voltage V QL1DS applied across the drain-source of the MOSFET QL1 causes a flow from the drain terminal of the MOSFET QL1 to the source terminal via the capacitor C1 and the anti-backflow diode D1. The current charges the capacitor C1.
 このとき、MOSFET QL1のドレイン-ソース間電圧VQL1DSは、第1の端子T1と第2の端子T2との間に印加される電圧を、MOSFET QL1とMOSFET QH1およびコンデンサC1とからなる回路部によって分圧される電圧である。なお、VQL1DSの大きさは、主に、MOSFET QH1のドレイン-ソース間寄生容量と、MOSFET QL1のドレイン-ソース間寄生容量と、コンデンサC1の容量の比で決まる。したがって、MOSFET QH1のドレイン-ソース間寄生容量と、MOSFET QL1のドレイン-ソース間寄生容量と、コンデンサの容量を考慮して、QH1,QL1,C1を選定することで、コンデンサに印加される電圧と比較器の検出電圧(入力電圧)とを、QH1およびQL1の直列接続の耐圧よりも低く、コンデンサおよび比較器に適する所望の電圧レベルに設定することができる。 At this time, the drain-source voltage V QL1DS of the MOSFET QL1 is obtained by changing the voltage applied between the first terminal T1 and the second terminal T2 by the circuit section consisting of the MOSFET QL1, the MOSFET QH1 and the capacitor C1 It is the voltage to be divided. The magnitude of V QL1DS is mainly determined by the ratio of the drain-source parasitic capacitance of MOSFET QH1, the drain-source parasitic capacitance of MOSFET QL1, and the capacitance of capacitor C1. Therefore, the voltage applied to the capacitor and the The detection voltage (input voltage) of the comparator can be set to a desired voltage level that is lower than the withstand voltage of the series connection of QH1 and QL1 and suitable for the capacitor and comparator.
 以下、図1の整流回路の同期整流動作について説明する。 The synchronous rectification operation of the rectifier circuit in FIG. 1 will be described below.
 まず、ターンオン動作について説明する。 First, the turn-on operation will be explained.
 第1の端子T1から第2の端子T2に整流電流(I)が流れ始めるとき、Iは、MOSFET QH1,QL1の各ボディダイオード(寄生ダイオード)を流れる。このとき、ボディダイオードの順方向電圧により、MOSFET QL1のドレイン-ソース間電圧(VQL1DS)は負の値となる。VQL1DSの値が、比較器COMP1の閾値(VTH1)よりも小さくなると、比較器COMP1の出力が低レベルから高レベルに遷移する。比較器COMP1の出力が高レベルになると、ゲートドライバGD1は、MOSFET QH1,QL1の各ゲートにオンゲート信号を出力する。これにより、MOSFET QH1のゲート-ソース電圧(VQH1GS)とMOSFET QL1のゲート-ソース電圧(VQL1GS)が増大するので、MOSFET QH1,QL1はターンオンする。 When the rectified current (I S ) starts to flow from the first terminal T1 to the second terminal T2, the I S flows through each body diode (parasitic diode) of the MOSFETs QH1 and QL1. At this time, the drain-source voltage (V QL1DS ) of MOSFET QL1 becomes a negative value due to the forward voltage of the body diode. When the value of V QL1DS becomes less than the threshold (V TH1 ) of comparator COMP1, the output of comparator COMP1 transitions from low to high. When the output of the comparator COMP1 becomes high level, the gate driver GD1 outputs an on-gate signal to each gate of the MOSFETs QH1 and QL1. This increases the gate-source voltage of MOSFET QH1 (V QH1GS ) and the gate-source voltage of MOSFET QL1 (V QL1GS ), thus turning on MOSFETs QH1 and QL1.
 MOSFET QH1,QL1のターンオン後、整流電流(I)は、MOSFET QH1,QL1の各チャネルを流れる。このとき、MOSFET QL1のドレイン-ソース間電圧(VQL1DS)は、MOSFET QL1のオン抵抗とIとの積で表される。同じIに対して、MOSFETのオン抵抗による電圧降下は、ボディダイオードのオン電圧より小さいので、整流回路が低損失化される。 After MOSFETs QH1 and QL1 turn on, a rectified current (I S ) flows through each channel of MOSFETs QH1 and QL1. At this time, the drain-source voltage (V QL1DS ) of the MOSFET QL1 is expressed by the product of the ON resistance of the MOSFET QL1 and I S . For the same IS , the voltage drop across the on-resistance of the MOSFET is smaller than the on-voltage of the body diode, resulting in a low loss rectifier circuit.
 次に、ターンオフ動作について説明する。 Next, the turn-off operation will be explained.
 整流電流(I)が減少すると、MOSFET QL1のドレイン-ソース間電圧(VQL1DS(負の値))は増加する。VQL1DSの値が、比較器COMP1の閾値(VTH1)よりも大きくなると、比較器COMP1の出力が高レベルから低レベルに遷移する。比較器COMP1の出力が低レベルになると、ゲートドライバGD1は、MOSFET QH1,QL1の各ゲートにオフゲート信号を出力する。これにより、MOSFET QH1のゲート-ソース電圧(VQH1GS)とMOSFET QL1のゲート-ソース電圧(VQL1GS)が減少するので、MOSFET QH1,QL1はターンオフする。 As the rectified current (I S ) decreases, the drain-source voltage (V QL1DS (negative value)) of MOSFET QL1 increases. When the value of V QL1DS becomes greater than the threshold (V TH1 ) of comparator COMP1, the output of comparator COMP1 transitions from high to low. When the output of comparator COMP1 goes low, gate driver GD1 outputs an off-gate signal to each gate of MOSFETs QH1 and QL1. This causes the gate-source voltage of MOSFET QH1 (V QH1GS ) and the gate-source voltage of MOSFET QL1 (V QL1GS ) to decrease, thus turning off MOSFETs QH1 and QL1.
 MOSFET QH1,QL1のターンオフ後、MOSFET QH1,QL1の各ドレイン-ソース間容量およびコンデンサC1からなる回路部によって分圧される、MOSFET QL1のドレイン-ソース間電圧(VQL1DS(正の値))によって、C1は再び充電される。 After MOSFETs QH1 and QL1 turn off, the drain-to-source voltage of MOSFET QL1 (V QL1DS (positive value)) divided by the circuit portion consisting of the respective drain-to-source capacitances of MOSFETs QH1 and QL1 and capacitor C1 , C1 are charged again.
 なお、MOSFET QH1,QL1がオフ状態の場合、MOSFET QH1のゲート-ソース電圧VQH1GSはゲートドライバの出力電圧(=0)からMOSFET QL1のドレイン-ソース間電圧VQL1DSを引いた電圧に等しい。したがって、オフ状態におけるVQL1DSは、MOSFET QH1のゲート-ソース間耐圧よりも低く設定されることが好ましい。もしくは、MOSFET QH1のゲート-ソース間耐圧が、オフ状態におけるVQL1DSよりも高いことが好ましい。 When the MOSFETs QH1 and QL1 are off, the gate-source voltage V QH1GS of the MOSFET QH1 is equal to the output voltage of the gate driver (=0) minus the drain-source voltage V QL1DS of the MOSFET QL1. Therefore, V QL1DS in the off state is preferably set lower than the breakdown voltage between the gate and source of MOSFET QH1. Alternatively, the gate-source breakdown voltage of MOSFET QH1 is preferably higher than V QL1DS in the off state.
 ここで、実施例1の比較例について説明する。いずれの比較例においても、MOSFETのオン・オフによる同期整流が適用されている。 Here, a comparative example of Example 1 will be described. Synchronous rectification by turning on/off the MOSFET is applied in each of the comparative examples.
 図8は、第1の比較例である整流回路の構成を示す回路図である。 FIG. 8 is a circuit diagram showing the configuration of a rectifier circuit as a first comparative example.
 第1の比較例では、上述の特許文献1の技術と同様に、一個のMOSFETが用いられ、図8では高耐圧MOSFET QH1がオン・オフされ、整流電流は高耐圧MOSFET QH1に流れる。さらに、図8に示すように、コンデンサC1の検出電圧が、高耐圧MOSFET QH2によって所望のレベルに制御されるとともに、比較器COMP1に入力される検出電圧が、高耐圧MOSFET QH3によって所望のレベルに制御される。なお、比較器COMP1に入力される検出電圧は、比較器COMP1の差動入力電圧以下に抑えられる。 In the first comparative example, one MOSFET is used in the same manner as the technique of Patent Document 1 described above. In FIG. 8, the high-voltage MOSFET QH1 is turned on and off, and the rectified current flows through the high-voltage MOSFET QH1. Furthermore, as shown in FIG. 8, the detection voltage of the capacitor C1 is controlled to a desired level by the high voltage MOSFET QH2, and the detection voltage input to the comparator COMP1 is controlled to a desired level by the high voltage MOSFET QH3. controlled. Note that the detection voltage input to the comparator COMP1 is suppressed below the differential input voltage of the comparator COMP1.
 なお、第1の比較例では、高耐圧MOSFET QH2に直列にコンデンサC2が接続され、このコンデンサC2が比較器COMP1の入力に接続される。また、高耐圧MOSFET QH3のゲート駆動電圧を生成するために、ツェナーダイオードZD1と抵抗R3の直列回路が、第1の端子T1と第2の端子T2の間に接続される。このように、第1の比較例では、部品点数が増加する。 In addition, in the first comparative example, a capacitor C2 is connected in series with the high voltage MOSFET QH2, and this capacitor C2 is connected to the input of the comparator COMP1. A series circuit of a Zener diode ZD1 and a resistor R3 is connected between the first terminal T1 and the second terminal T2 in order to generate a gate drive voltage for the high voltage MOSFET QH3. Thus, the number of parts increases in the first comparative example.
 図9は、第2の比較例である整流回路の構成を示す回路図である。 FIG. 9 is a circuit diagram showing the configuration of a rectifier circuit that is a second comparative example.
 第2の比較例では、エンハンスメント型の低耐圧MOSFET QL1とデプレッション型の高耐圧MOSFET QH1とが直列に接続され、整流電流は低耐圧MOSFET QL1および高耐圧MOSFET QH1に流れる。低耐圧MOSFET QL1がオン・オフされるとともに、高耐圧MOSFET QH1によって整流回路が高耐圧化される。さらに、図9に示すように、デプレッション型の高耐圧MOSFET QH2によって、コンデンサC1の電圧と、比較器COMP1の検出電圧とが、所望のレベルに制御される。なお、本比較例では、QH1およびQH2は、ノーマリオン型のスイッチング素子として動作する。 In the second comparative example, an enhancement-type low-voltage MOSFET QL1 and a depletion-type high-voltage MOSFET QH1 are connected in series, and a rectified current flows through the low-voltage MOSFET QL1 and the high-voltage MOSFET QH1. The low voltage MOSFET QL1 is turned on/off, and the high voltage MOSFET QH1 increases the voltage of the rectifier circuit. Further, as shown in FIG. 9, the voltage of the capacitor C1 and the detection voltage of the comparator COMP1 are controlled to desired levels by the depletion type high voltage MOSFET QH2. In this comparative example, QH1 and QH2 operate as normally-on switching elements.
 第1の比較例(図8)および第2の比較例(図9)において用いられる高耐圧MOSFETの個数は、それぞれ3個(QH1,QH2,QH3)および2個(QH1,QH2)である。これに対し、実施例1(図1)において用いられる高耐圧MOSFETの個数は、1個である。これにより、実施例1によれば、整流回路の電力損失が低減できるとともに、整流回路のサイズやコストが低減できる。 The number of high voltage MOSFETs used in the first comparative example (FIG. 8) and the second comparative example (FIG. 9) is three (QH1, QH2, QH3) and two (QH1, QH2), respectively. In contrast, the number of high voltage MOSFETs used in the first embodiment (FIG. 1) is one. Thus, according to the first embodiment, the power loss of the rectifier circuit can be reduced, and the size and cost of the rectifier circuit can be reduced.
 また、第2の比較例(図9)において、整流電流が流れ、整流回路を高耐圧化する高耐圧MOSFET QH1が、ノーマリオンで動作するデプレッション型MOSFETである。これに対し、実施例1(図1)では、高耐圧MOSFET QH1がエンハンスメント型MOSFETである。これにより、実施例1によれば、電力損失が低減できたり、コストが低減できたりする。 In addition, in the second comparative example (FIG. 9), the high voltage MOSFET QH1, through which a rectified current flows and increases the voltage resistance of the rectifier circuit, is a depletion type MOSFET that operates normally. On the other hand, in Example 1 (FIG. 1), the high voltage MOSFET QH1 is an enhancement type MOSFET. Thus, according to the first embodiment, power loss can be reduced and costs can be reduced.
 上述のように、実施例1によれば、エンハンスメント型の高耐圧MOSFETとエンハンスメント型の低耐圧MOSFETとを直列接続して、高耐圧MOSFETにより整流回路を高耐圧化するとともに、高耐圧MOSFETと低耐圧MOSFETをともにオン・オフ制御して整流動作させる。さらに、高耐圧MOSFETと低耐圧MOSFETを整流動作させる制御回路の電源となるコンデンサが、低耐圧MOSFETのドレイン-ソース間電圧によって充電されるとともに、制御回路は低耐圧MOSFETのドレイン-ソース間電圧を検出して、検出電圧に応じて高耐圧MOSFETと低耐圧MOSFETを整流動作させる。 As described above, according to the first embodiment, the enhancement-type high-voltage MOSFET and the enhancement-type low-voltage MOSFET are connected in series, and the high-voltage MOSFET increases the voltage resistance of the rectifier circuit. Both of the withstand voltage MOSFETs are on/off controlled for rectifying operation. Furthermore, the capacitor, which is the power supply for the control circuit that rectifies the high-voltage MOSFET and the low-voltage MOSFET, is charged by the drain-source voltage of the low-voltage MOSFET, and the control circuit reduces the drain-source voltage of the low-voltage MOSFET. The voltage is detected, and the high-voltage MOSFET and the low-voltage MOSFET are rectified according to the detected voltage.
 これにより、整流回路を高耐圧化しながらも、高耐圧MOSFETなどの制御用素子を用いることなく、制御回路用の電源や検出電圧の電圧レベルを所望の大きさに設定することができる。さらに、整流電流が流れる高耐圧MOSFETが、エンハンスメント型であるため、電力損失が低減できたり、コストが低減できたりする。したがって、実施例1によれば、電力損失やコストを増大することなく、整流回路を高耐圧化できる。 As a result, the power supply for the control circuit and the voltage level of the detection voltage can be set to a desired level without using a control element such as a high-voltage MOSFET while increasing the withstand voltage of the rectifier circuit. Furthermore, since the high voltage MOSFET through which the rectified current flows is an enhancement type, it is possible to reduce the power loss and the cost. Therefore, according to the first embodiment, the withstand voltage of the rectifier circuit can be increased without increasing the power loss and cost.
 図2は、本発明の実施例2である整流回路の構成を示す回路図である。以下、主に、実施例1と異なる点について説明する。 FIG. 2 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 2 of the present invention. Differences from the first embodiment are mainly described below.
 図2に示すように、実施例2においては、低耐圧のMOSFET QL1のドレイン-ゲート間にツェナーダイオードZD1が挿入される。なお、ツェナーダイオードZD1のアノードおよびカソードが、それぞれ、ゲートおよびドレインに接続される。ツェナーダイオードZD1のツェナー電圧は、MOSFET QL1の耐圧以下、または制御回路1の定格電圧以下、または比較器COMP1の差動入力電圧以下とする。 As shown in FIG. 2, in Example 2, a Zener diode ZD1 is inserted between the drain and gate of the low-voltage MOSFET QL1. The anode and cathode of Zener diode ZD1 are connected to the gate and drain, respectively. The zener voltage of the zener diode ZD1 should be lower than the withstand voltage of the MOSFET QL1, lower than the rated voltage of the control circuit 1, or lower than the differential input voltage of the comparator COMP1.
 MOSFET QL1のドレイン-ソース間電圧VQL1DSがツェナーダイオードZD1のツェナー電圧以上になるとき、ZD1が降伏して、VQL1DSがツェナー電圧によって設定される所望の値にクランプされる。 When the drain-to-source voltage V QL1DS of MOSFET QL1 rises above the Zener voltage of Zener diode ZD1, ZD1 breaks down and V QL1DS is clamped to the desired value set by the Zener voltage.
 これにより、MOSFET QL1のドレイン-ソース間電圧VQL1DSを、確実に、MOSFET QL1の耐圧以下に抑えたり、あるいはコンデンサC1の電圧を制御回路1の定格電圧以下に抑えたり、または、比較器COMP1の検出電圧をCOMP1の差動入力電圧以下に抑えたりすることができる。また、MOSFET QH1のゲート-ソース間電圧の大きさを、MOSFET QH1のゲート-ソース間耐圧よりも低く抑えることができる。したがって、整流回路の動作の信頼性が向上する。 As a result, the drain-source voltage V QL1DS of the MOSFET QL1 can be reliably suppressed below the withstand voltage of the MOSFET QL1, or the voltage of the capacitor C1 can be suppressed below the rated voltage of the control circuit 1, or the voltage of the comparator COMP1 The detection voltage can be suppressed below the differential input voltage of COMP1. Also, the magnitude of the voltage between the gate and source of the MOSFET QH1 can be suppressed lower than the withstand voltage between the gate and source of the MOSFET QH1. Therefore, the operational reliability of the rectifier circuit is improved.
 図3は、本発明の実施例3である整流回路の構成を示す回路図である。以下、主に、実施例1と異なる点について説明する。 FIG. 3 is a circuit diagram showing the configuration of a rectifier circuit that is Embodiment 3 of the present invention. Differences from the first embodiment are mainly described below.
 図3に示すように、実施例3においては、MOSFET QL1,QH1に、それぞれ抵抗R2,R1が並列接続される。 As shown in FIG. 3, in Example 3, resistors R2 and R1 are connected in parallel to MOSFETs QL1 and QH1, respectively.
 第1の端子T1と第2の端子T2との間に印加される電圧が、抵抗R1とR2の比に応じて、MOSFET QH1のドレイン-ソース間電圧VQH1DSとMOSFET QL1のドレイン-ソース間電圧VQL1DSとに分圧される。これにより、VQL1DSの値が、確実に所望の電圧値に設定することができる。 Depending on the ratio of resistors R1 and R2, the voltage applied between the first terminal T1 and the second terminal T2 will be the drain-source voltage V QH1DS of MOSFET QH1 and the drain-source voltage of MOSFET QL1. V-- QL1DS and V--QL1DS. Thereby, the value of VQL1DS can be reliably set to a desired voltage value.
 したがって、実施例3によれば、コンデンサに印加される電圧と比較器の検出電圧(入力電圧)とを、確実にコンデンサおよび比較器に適する所望の電圧レベルに設定することができる。 Therefore, according to the third embodiment, the voltage applied to the capacitor and the detected voltage (input voltage) of the comparator can be reliably set to desired voltage levels suitable for the capacitor and comparator.
 図4は、本発明の実施例4である整流回路の動作を示す電流・電圧波形図である。以下、主に、実施例1と異なる点について説明する。 FIG. 4 is a current/voltage waveform diagram showing the operation of the rectifier circuit that is Example 4 of the present invention. Differences from the first embodiment are mainly described below.
 図4においては、整流電流Is、MOSFET QL1のドレイン-ソース間電圧VQL1DS、MOSFET QL1のゲート-ソース間電圧VQL1GS、MOSFET QH1のゲート-ソース間電圧VQH1GSを示す。なお、図4においては、整流電流Iは、正弦半波電流としている。 FIG. 4 shows the rectified current Is, the drain-source voltage V QL1DS of the MOSFET QL1, the gate-source voltage V QL1GS of the MOSFET QL1, and the gate-source voltage V QH1GS of the MOSFET QH1. In addition, in FIG. 4, the rectified current IS is a sine half-wave current.
 実施例4では、回路構成は実施例1(図1)と同様であるが、実施例1と異なり、比較器COMP1が大きさの異なる二つの閾値(VTH1,VTH2)を有する。 In Example 4, the circuit configuration is similar to Example 1 (FIG. 1), but unlike Example 1, comparator COMP1 has two threshold values (V TH1 , V TH2 ) with different magnitudes.
 図4に示すように、実施例4における比較器COMP1は、第1の閾値VTH1および第2の閾値VTH2を有している。VTH1,VTH2は共に負の値を有する。VTH1<VTH2であり、VTH1の絶対値はVTH2の絶対値よりも大きい。 As shown in FIG. 4, the comparator COMP1 in Example 4 has a first threshold V TH1 and a second threshold V TH2 . Both V TH1 and V TH2 have negative values. V TH1 <V TH2 and the absolute value of V TH1 is greater than the absolute value of V TH2 .
 以下、実施例4の整流回路動作について説明するが、電圧の大小および増減については、電圧の正負を考慮して記述する。 The operation of the rectifier circuit of Example 4 will be described below, but the magnitude and increase/decrease of the voltage will be described in consideration of the positive/negative of the voltage.
 比較器COMP1は、MOSFET QL1,QH1のターンオン動作時には、MOSFET QL1のドレイン-ソース間電圧VQL1DSと第1の閾値VTH1とを比較し、MOSFET QL1,QH1のターンオフ動作時には、MOSFET QL1のドレイン-ソース間電圧VQL1DSと第2の閾値VTH2とを比較する。 The comparator COMP1 compares the drain-source voltage V QL1DS of the MOSFET QL1 with the first threshold value V TH1 when the MOSFETs QL1 and QH1 are turned on, and compares the drain-source voltage V QL1DS of the MOSFET QL1 with the first threshold value V TH1 when the MOSFETs QL1 and QH1 are turned off. A source-to-source voltage V QL1DS is compared with a second threshold V TH2 .
 Iが流れ始め、VQL1DSが正から負に変わり、その後、VQL1DSがVTH1よりも低くなると、比較器COMP1は、出力を低レベルから高レベルに遷移する。これにより、ゲートドライバGD1がオンゲート信号を出力するので、VQH1GSおよびVQL1GSが増大する。したがって、QH1,QL1はターンオンする。 Comparator COMP1 transitions its output from low to high when I S begins to flow and V QL1DS changes from positive to negative and then V QL1DS becomes lower than V TH1 . As a result, the gate driver GD1 outputs an on-gate signal, increasing V-- QH1GS and V-- QL1GS . Therefore, QH1 and QL1 are turned on.
 QH1,QL1はターンオンすると、VQL1DSは、一旦増大して、その後、正弦半波状に変化するが、第2の閾値VTH2には到達しない。このため、比較器COMP1は出力を高レベルに維持するので、QH1,QL1はオン状態を維持する。 When QH1 and QL1 are turned on, VQL1DS once increases and then changes in a half-sinusoidal fashion, but does not reach the second threshold VTH2 . Therefore, the output of the comparator COMP1 is maintained at a high level, so QH1 and QL1 are maintained on.
 Iが減少して、VQL1DS(<0)がVTH2(<0)以上に増大すると、比較器COMP1は、出力を高レベルから低レベルに遷移する。これにより、ゲートドライバGD1がオフゲート信号を出力するので、VQH1GSおよびVQL1GSが減少する。したがって、QH1,QL1はターンオフする。 As I S decreases and V QL1DS (<0) increases above V TH2 (<0), comparator COMP1 transitions its output from high to low. As a result, the gate driver GD1 outputs an off-gate signal, so that V-- QH1GS and V-- QL1GS decrease. Therefore, QH1 and QL1 are turned off.
 上述のように、比較器COMP1がMOSFET QL1のドレイン-ソース間電圧VQL1DSと比較する閾値が、ターンオン動作時とターンオフ動作時で異なることにより、比較器COMP1の出力レベルの高低が短時間で切り替わる、いわゆるチャタリングが防止できる。これにより、整流回路のターンオン動作およびターンオフ動作が短時間で繰り返されるような不安定動作が防止される。 As described above, the threshold with which the comparator COMP1 compares the drain-source voltage V QL1DS of the MOSFET QL1 differs between the turn-on operation and the turn-off operation, so that the output level of the comparator COMP1 switches between high and low in a short period of time. , so-called chattering can be prevented. This prevents an unstable operation in which the turn-on operation and turn-off operation of the rectifier circuit are repeated in a short period of time.
 上述のように、実施例4によれば、整流回路の動作の安定性が向上する。特に、ターンオン後におけるMOSFET QL1のドレイン-ソース間電圧VQL1DSの変動が大きな場合に、VQL1DSの変動幅に応じて、VTH1,VTH2を設定することにより、整流回路の動作の安定性が確実に向上する。 As described above, according to the fourth embodiment, the operational stability of the rectifier circuit is improved. In particular, when the drain-source voltage V QL1DS of the MOSFET QL1 after turn-on fluctuates greatly, setting V TH1 and V TH2 according to the fluctuation range of V QL1DS improves the stability of the operation of the rectifier circuit. definitely improve.
 なお、実施例4における比較器としては、例えば、ヒステリシスコンパレータが適用できる。 A hysteresis comparator, for example, can be applied as the comparator in the fourth embodiment.
 図5は、本発明の実施例5である半導体装置の構成図である。 FIG. 5 is a configuration diagram of a semiconductor device that is Embodiment 5 of the present invention.
 図5に示すように、実施例5では、半導体回路として、整流回路2が、半導体パッケージ3に内蔵される。整流回路2としては、実施例1(図1)の整流回路が適用される。したがって、整流回路2を構成する、高耐圧MOSFET Q1、低耐圧MOSFET Q2、コンデンサC1、逆流防止用ダイオードD1、制御回路1(比較器COMP1、ゲートドライバGD1)が半導体パッケージ3に内蔵される。 As shown in FIG. 5, in Example 5, a rectifier circuit 2 is built in a semiconductor package 3 as a semiconductor circuit. As the rectifier circuit 2, the rectifier circuit of Example 1 (FIG. 1) is applied. Therefore, the high-voltage MOSFET Q1, the low-voltage MOSFET Q2, the capacitor C1, the backflow prevention diode D1, and the control circuit 1 (comparator COMP1, gate driver GD1), which constitute the rectifier circuit 2, are incorporated in the semiconductor package 3.
 半導体パッケージ3においては、整流回路2が成形樹脂もしくは樹脂ケースなどによって樹脂封止され、第1の端子T1と第2の端子T2が、整流回路2を封止する樹脂の外表面に露出している。 In the semiconductor package 3, the rectifier circuit 2 is resin-sealed with molding resin or a resin case, and the first terminal T1 and the second terminal T2 are exposed on the outer surface of the resin that seals the rectifier circuit 2. there is
 実施例5によれば、整流ダイオードの代替として同期整流回路を容易に適用して、整流回路部を備える電気・電子装置を低損失化することができる。 According to the fifth embodiment, the synchronous rectification circuit can be easily applied as a substitute for the rectifier diode, and the electrical/electronic device provided with the rectifier circuit section can be reduced in loss.
 実施例5の半導体装置は、同期整流を用いながらも、ダイオードと同様に2端子の整流素子として動作する。このため、整流回路部を備える電気・電子装置の設計および実装の工数を削減することができる。 Although the semiconductor device of Example 5 uses synchronous rectification, it operates as a two-terminal rectifying element like a diode. Therefore, it is possible to reduce man-hours for designing and mounting the electric/electronic device including the rectifier circuit section.
 なお、整流回路2として、実施例2~4のいずれかの整流回路が適用されてもよい。 As the rectifier circuit 2, any one of the rectifier circuits of Examples 2 to 4 may be applied.
 図6は、本発明の実施例6である半導体装置の構成図である。 FIG. 6 is a configuration diagram of a semiconductor device that is Embodiment 6 of the present invention.
 図6に示すように、実施例6では、半導体回路として、整流回路2,5,6,7が、半導体パッケージ4に内蔵される。整流回路2は、実施例1(図1)と同様の回路が適用される。整流回路5,6,7の各々にも、実施例1(図1)と同様の回路が適用される。これらの整流回路2,5,6,7は、単相ブリッジ整流回路を構成している。 As shown in FIG. 6, in the sixth embodiment, rectifier circuits 2, 5, 6, and 7 are incorporated in a semiconductor package 4 as semiconductor circuits. A circuit similar to that of the first embodiment (FIG. 1) is applied to the rectifier circuit 2 . A circuit similar to that of the first embodiment (FIG. 1) is applied to each of the rectifier circuits 5, 6, and 7 as well. These rectifier circuits 2, 5, 6 and 7 form a single-phase bridge rectifier circuit.
 半導体パッケージ4においては、整流回路2,5,6,7が成形樹脂もしくは樹脂ケースなどによって樹脂封止され、単相ブリッジ整流回路の一対の交流端子T4,T5および一対の直流端子T3,T6が、整流回路2,5,6,7を封止する樹脂の外表面に露出している。 In the semiconductor package 4, the rectifier circuits 2, 5, 6, and 7 are resin-sealed with molding resin or a resin case, and a pair of AC terminals T4, T5 and a pair of DC terminals T3, T6 of the single-phase bridge rectifier circuit are connected. , are exposed to the outer surface of the resin that seals the rectifier circuits 2, 5, 6, 7.
 実施例6によれば、整流ダイオードの代替として同期整流回路を単相ブリッジ整流回路に容易に適用して、単相ブリッジ整流回路や、単相ブリッジ整流回路を備える電気・電子装置を低損失化することができる。 According to the sixth embodiment, the synchronous rectifier circuit can be easily applied to the single-phase bridge rectifier circuit as a substitute for the rectifier diode, and the loss of the single-phase bridge rectifier circuit and the electric/electronic device equipped with the single-phase bridge rectifier circuit can be reduced. can do.
 実施例6の半導体装置は、半導体パッケージ4において交流端子T4,T5および直流端子T3,T6の配置を、パッケージングされたダイオードブリッジに合わせることにより、このダイオードブリッジとの互換性を有することができる。また、実施例6の半導体装置は、同期整流を用いながらも、単相ダイオードブリッジと同様に4端子の整流素子として動作する。このため、全波整流回路部を備える電気・電子装置の設計および実装の工数を削減することができる。 The semiconductor device of Example 6 can have compatibility with the diode bridge by matching the arrangement of the AC terminals T4, T5 and the DC terminals T3, T6 in the semiconductor package 4 with the packaged diode bridge. . In addition, the semiconductor device of Example 6 operates as a four-terminal rectifying element like a single-phase diode bridge while using synchronous rectification. Therefore, it is possible to reduce man-hours for designing and mounting an electric/electronic device including a full-wave rectifier circuit.
 なお、整流回路2,5,6,7として、実施例2~4のいずれかの整流回路が適用されてもよい。また、実施例1~4のいずれかの整流回路を6個用いて、三相ブリッジ整流回路を構成することができる。この場合、三相分の3個の交流端子および一対の直流端子が、6個の整流回路を封止する樹脂の外表面に露出する。 As the rectifier circuits 2, 5, 6, and 7, any one of the rectifier circuits of Examples 2 to 4 may be applied. A three-phase bridge rectifier circuit can be configured by using six rectifier circuits of any one of Examples 1 to 4. In this case, three AC terminals and a pair of DC terminals for three phases are exposed on the outer surface of the resin that seals the six rectifier circuits.
 図7は、本発明の実施例7である電源装置の構成を示す回路図である。 FIG. 7 is a circuit diagram showing the configuration of a power supply device that is Embodiment 7 of the present invention.
 図7の電源装置は、商用交流電源からの交流電力を、所望の電圧の直流電力に変換して出力する。 The power supply device in FIG. 7 converts AC power from a commercial AC power supply into DC power with a desired voltage and outputs the DC power.
 図7中に、ダイオードの回路記号で示す整流素子の内、商用交流電圧の交流電圧を整流するブリッジ整流回路を構成する整流素子CRD1~CRD4と、チョッパ回路部における還流用の整流素子FWD1と、インバータ回路部の交流出力電力をトランスを介して入力して、所望の電圧の直流電圧に変換する整流回路部を構成する整流素子SSD1,SSD2と、逆流防止用の整流素子ORD1の少なくともいずれかに、実施例1~4のいずれかの整流回路、もしくは実施例5の半導体装置が適用される。なお、整流素子CRD1~CRD4には、実施例6の単相ブリッジ整流回路を用いてもよい。 In FIG. 7, among the rectifying elements indicated by the circuit symbols of diodes, rectifying elements CRD1 to CRD4 constituting a bridge rectifying circuit for rectifying the AC voltage of the commercial AC voltage, a rectifying element FWD1 for freewheeling in the chopper circuit section, At least one of the rectifying elements SSD1 and SSD2 constituting the rectifying circuit section that receives the AC output power of the inverter circuit section via a transformer and converts it to a desired DC voltage, and the rectifying element ORD1 for preventing backflow. , the rectifier circuit of any one of Examples 1 to 4, or the semiconductor device of Example 5 is applied. The single-phase bridge rectifier circuit of Example 6 may be used for the rectifying elements CRD1 to CRD4.
 なお、図7中で、MOSFETに並列に接続される整流素子は、MOSFETの寄生ダイオード(ボディダイオード)である。また、図7中の整流素子が全てダイオードである場合、図7の電源装置の回路構成は公知の回路構成である。 In addition, in FIG. 7, the rectifying element connected in parallel with the MOSFET is a parasitic diode (body diode) of the MOSFET. Moreover, when all the rectifying elements in FIG. 7 are diodes, the circuit configuration of the power supply device in FIG. 7 is a known circuit configuration.
 実施例7によれば、電源装置の電力損失を低減することができる。なお、実施例7による電源装置は、高い効率が要求されるフロントエンド電源に好適である。 According to the seventh embodiment, it is possible to reduce the power loss of the power supply device. It should be noted that the power supply device according to the seventh embodiment is suitable for a front-end power supply that requires high efficiency.
 なお、実施例1~4の整流回路と実施例5~6の半導体装置は、フロント電源に限らず、整流回路部を備える各種の電源装置に適用できる。 The rectifier circuits of Examples 1 to 4 and the semiconductor devices of Examples 5 and 6 can be applied not only to the front power supply but also to various power supply apparatuses having a rectifier circuit section.
 なお、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記の実施例は本発明に対する理解を助けるために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 It should be noted that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above embodiments have been described in detail to facilitate understanding of the present invention, and are not necessarily limited to those having all the described configurations. In addition, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Moreover, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.
 例えば、MOSFETは、nチャネル型に限らず、pチャネル型でもよい。また、MOSFETを構成する半導体材料は、シリコン(Si)に限らず、炭化ケイ素(SiC)などのワイドバンドギャプ半導体でもよい。 For example, the MOSFET is not limited to an n-channel type, and may be a p-channel type. Moreover, the semiconductor material forming the MOSFET is not limited to silicon (Si), but may be a wide bandgap semiconductor such as silicon carbide (SiC).
1…制御回路、2,5,6,7…整流回路、3,4…半導体パッケージ 1... control circuit, 2, 5, 6, 7... rectifier circuit, 3, 4... semiconductor package

Claims (12)

  1.  電流を一方向に流す整流回路において、
     エンハンスメント型の第1のMOSFETと、
     前記第1のMOSFETに直列に接続され、前記第1のMOSFETよりも低耐圧のエンハンスメント型の第2のMOSFETと、
     前記第1のMOSFETと前記第2のMOSFETとを共に整流動作させる制御回路と、
     前記制御回路に電源を供給し、前記第2のMOSFETにおけるドレイン-ソース間電圧によって充電されるコンデンサと、
    を備えることを特徴とする整流回路。
    In a rectifier circuit that allows current to flow in one direction,
    an enhancement-type first MOSFET;
    a second enhancement-type MOSFET connected in series to the first MOSFET and having a lower breakdown voltage than the first MOSFET;
    a control circuit that rectifies both the first MOSFET and the second MOSFET;
    a capacitor that supplies power to the control circuit and is charged by the drain-to-source voltage on the second MOSFET;
    A rectifier circuit, comprising:
  2.  請求項1に記載の整流回路において、
     前記制御回路は、
     前記第2のMOSFETにおける前記ドレイン-ソース間電圧に基づいて前記第1のMOSFETと前記第2のMOSFETとを共にオン・オフすることにより、前記第1のMOSFETと前記第2のMOSFETとを共に整流動作させることを特徴とする整流回路。
    In the rectifier circuit according to claim 1,
    The control circuit is
    By turning on/off both the first MOSFET and the second MOSFET based on the drain-source voltage in the second MOSFET, both the first MOSFET and the second MOSFET are turned on and off. A rectifier circuit characterized by performing a rectifying operation.
  3.  請求項1に記載の整流回路において、
     前記制御回路は、
     前記第2のMOSFETにおける前記ドレイン-ソース間電圧に応じて、出力レベルを切り換える比較器と、
     前記比較器の前記出力レベルに応じて、前記第1のMOSFETおよび前記第2のMOSFETの各ゲートへ共通のゲート信号を出力するゲートドライバと、
    を有することを特徴とする整流回路。
    In the rectifier circuit according to claim 1,
    The control circuit is
    a comparator that switches an output level according to the drain-source voltage in the second MOSFET;
    a gate driver that outputs a common gate signal to each gate of the first MOSFET and the second MOSFET according to the output level of the comparator;
    A rectifier circuit, comprising:
  4.  請求項3に記載の整流回路において、
     前記第2のMOSFETのドレインおよびソースが、前記比較器の入力に接続されることを特徴とする整流回路。
    In the rectifier circuit according to claim 3,
    A rectifier circuit, wherein the drain and source of said second MOSFET are connected to the input of said comparator.
  5.  請求項4に記載の整流回路において、
     前記第2のMOSFETにおける前記ドレイン-ソース間電圧が前記比較器の差動入力電圧以下であることを特徴とする整流回路。
    In the rectifier circuit according to claim 4,
    A rectifier circuit, wherein the drain-source voltage in the second MOSFET is equal to or less than the differential input voltage of the comparator.
  6.  請求項1に記載の整流回路おいて、前記第1のMOSFETのゲート-ソース間の耐圧が、前記第2のMOSFETがオフのときにおける前記第2のMOSFETの前記ドレイン-ソース間電圧よりも大きいことを特徴とする整流回路。 2. The rectifier circuit according to claim 1, wherein the withstand voltage between the gate and source of said first MOSFET is higher than the voltage between said drain and source of said second MOSFET when said second MOSFET is off. A rectifier circuit characterized by:
  7.  請求項1に記載の整流回路おいて、前記第2のMOSFETのドレインとゲートとの間にツェナーダイオードが接続されることを特徴とする整流回路。 The rectifier circuit according to claim 1, wherein a Zener diode is connected between the drain and gate of said second MOSFET.
  8.  請求項1に記載の整流回路おいて、さらに、
     前記第1のMOSFETと並列に接続される第1の抵抗と、
     前記第2のMOSFETと並列に接続される第2の抵抗と、
    を備えることを特徴とする整流回路。
    The rectifier circuit of claim 1, further comprising:
    a first resistor connected in parallel with the first MOSFET;
    a second resistor connected in parallel with the second MOSFET;
    A rectifier circuit comprising:
  9.  請求項3に記載の整流回路において、
     前記比較器は、値が異なる第1の閾値および第2の閾値と、前記第2のMOSFETにおける前記ドレイン-ソース間電圧とを比較することを特徴とする整流回路。
    In the rectifier circuit according to claim 3,
    The rectifier circuit, wherein the comparator compares a first threshold value and a second threshold value having different values with the drain-source voltage of the second MOSFET.
  10.  整流回路と、
     前記整流回路を内蔵する半導体パッケージと、
    を備える半導体装置において、
     前記整流回路が、請求項1から9の何れかに記載される整流回路であることを特徴とする半導体装置。
    a rectifier circuit;
    a semiconductor package containing the rectifier circuit;
    In a semiconductor device comprising
    A semiconductor device, wherein the rectifier circuit is the rectifier circuit according to any one of claims 1 to 9.
  11.  複数の整流回路から構成されるブリッジ整流回路と、
     前記ブリッジ整流回路を内蔵する半導体パッケージと、
    を備える半導体装置において、
     前記複数の整流回路の各々が、請求項1から9の何れかに記載される整流回路であることを特徴とする半導体装置。
    a bridge rectifier circuit composed of a plurality of rectifier circuits;
    a semiconductor package containing the bridge rectifier circuit;
    In a semiconductor device comprising
    10. A semiconductor device, wherein each of the plurality of rectifier circuits is the rectifier circuit according to claim 1.
  12.  整流回路部を有する電源装置において、
     前記整流回路部が、請求項1から9の何れかに記載される整流回路を備えることを特徴とする電源装置。
    In a power supply device having a rectifier circuit,
    A power supply device, wherein the rectifier circuit section includes the rectifier circuit according to any one of claims 1 to 9.
PCT/JP2022/023631 2021-08-31 2022-06-13 Rectifier circuit, and semiconductor device and power supply device using same WO2023032407A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11146640A (en) * 1997-11-10 1999-05-28 Nec Corp Rectifying circuit for switching power supply and switching power supply using the rectifying circuit
JP2011151788A (en) * 2009-12-22 2011-08-04 Fujitsu Semiconductor Ltd Semiconductor device
JP2019129656A (en) * 2018-01-26 2019-08-01 株式会社デンソー Rectification device and rotary electric machine
JP2021068812A (en) * 2019-10-24 2021-04-30 株式会社 日立パワーデバイス Semiconductor device, rectifier element using the same, and alternator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11146640A (en) * 1997-11-10 1999-05-28 Nec Corp Rectifying circuit for switching power supply and switching power supply using the rectifying circuit
JP2011151788A (en) * 2009-12-22 2011-08-04 Fujitsu Semiconductor Ltd Semiconductor device
JP2019129656A (en) * 2018-01-26 2019-08-01 株式会社デンソー Rectification device and rotary electric machine
JP2021068812A (en) * 2019-10-24 2021-04-30 株式会社 日立パワーデバイス Semiconductor device, rectifier element using the same, and alternator

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