WO2023030857A1 - Optoelectronic semiconductor device and production method - Google Patents

Optoelectronic semiconductor device and production method Download PDF

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Publication number
WO2023030857A1
WO2023030857A1 PCT/EP2022/072576 EP2022072576W WO2023030857A1 WO 2023030857 A1 WO2023030857 A1 WO 2023030857A1 EP 2022072576 W EP2022072576 W EP 2022072576W WO 2023030857 A1 WO2023030857 A1 WO 2023030857A1
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WIPO (PCT)
Prior art keywords
semiconductor fin
active
active semiconductor
semiconductor device
passive
Prior art date
Application number
PCT/EP2022/072576
Other languages
French (fr)
Inventor
Andreas LEX
Adrian Stefan Avramescu
Ali MAHDAVI
Norwin Von Malm
Harald KÖNIG
Original Assignee
Osram Opto Semiconductors Gmbh
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Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2023030857A1 publication Critical patent/WO2023030857A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • An optoelectronic semiconductor device is provided.
  • a method for producing such an optoelectronic semiconductor device is also provided.
  • a problem to be solved is to provide an optoelectronic semiconductor device that has improved optical emission characteristics .
  • the optoelectronic semiconductor device comprises one or a plurality of active semiconductor fins.
  • the at least one active semiconductor fin is configured to emit radiation by electroluminescence. That is, if current is provided as intended, light is produced in the at least one active semiconductor fin.
  • the active semiconductor fin may also be referred to as nanofin.
  • the at least one active semiconductor fin is based on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material such as Al n In]__ n-m Ga m N or a phosphide compound semiconductor material such as Al n In]__ n-m Ga m P or also an arsenide compound semiconductor material such as Al n In]__ n-m Ga m As , wherein in each case 0 ⁇ n ⁇ 1 , 0 ⁇ m ⁇ 1 and n + m ⁇ 1 applies .
  • the semiconductor layer sequence may comprise dopants and additional constituents .
  • the at least one active semiconductor fin is particularly preferably based on the InGaN material system .
  • the at least one active semiconductor fin starts from a base plane .
  • the base plane is , for example , a plane at which a growth of the at least one active semiconductor fin has begun .
  • the base plane may be defined by a common base layer which could be made of GaN, for example , or may also be defined by a common electrode layer or current spreading layer to electrically contact the at least one active semiconductor fin .
  • the base plane may be defined by a carrier at which the at least one active semiconductor fin is placed on . In particular, the base plane is located at an n-side of the at least one active semiconductor fin .
  • the at least one active semiconductor fin runs along at least two di f ferent directions .
  • the directions along which the at least one active semiconductor fin runs may be referred to as directions of main extent .
  • the optoelectronic semiconductor device comprises at least one active semiconductor fin which is configured to emit radiation by electroluminescence , wherein
  • the at least one active semiconductor fin starts from a base plane
  • the at least one active semiconductor fin runs along at least two di f ferent directions ; as an option, the optoelectronic semiconductor device further comprises at least one passive semiconductor fin configured not to emit radiation by electroluminescence , wherein, within a factor of at most 1 . 5 , the at least one passive semiconductor fin and the at least one active semiconductor fin have the same height .
  • red-emitting p-pixel imagers based on linear InGaN-nanof ins exhibit an angle-dependent optical far- field emission pattern .
  • nanofins based on InGaN having a high In-content InGaN can be used while maintaining an azimuth angle-independent emission pattern .
  • nanofins can be grown in parallel lines between lines of a dielectric mask layer all over a wafer .
  • the chip process then defines the multiple pixels .
  • the linear structures remain in the pixels and have strong impact on the optical far- field emission pattern .
  • the optical far field can be tuned by additional patterning a light-emitting surface and/or by mirroring a backside .
  • a dielectric mask layer which defines the geometry and arrangement of the nanofins or of the nanofin array, is lithographically patterned in a way that , for example , parallel nanofin structures with angles of 0 ° , - 60 ° and 60 ° relative to the m-plane of the GaN crystal occur within the area of each pixel .
  • This can be achieved by concentric equilateral triangles , hexagons or circles as pattern in the dielectric growth mask layer .
  • passive nanostructures that is , passive semiconductor fins , meaning structures which are non-conductive and/or not light-emitting can be introduced to improve the homogeneity of the neighboring active nanostructures .
  • the relaxation of the epitaxially grown layer, especially of the active area can be controlled .
  • the replacement of parallel linear nanofin structures by nanofins in multiple orientations randomi zes the nanofin optical ef fect on the outcoupling of light and therewith on the optical far- field pattern .
  • the directionality can be controlled by changing the pitch between two adj acent nanofins .
  • all processes for the chip and pixel definition and contacting can remain the same .
  • the chip process can be simpli fied after tuning the geometry and arrangement of the nanofins , for example , less impact of a chip mesa on light outcoupling and/or less impact of passivation on electro-optical properties can be achieved .
  • the at least one active semiconductor fin comprises an n-doped region, a p-doped region and an active zone located between the n-doped region and the p-doped region . Seen in cross-section, the n-doped region, the active zone and the p-doped region can be stacked on top of each other in a direction away from the base plane so that the at least one active semiconductor fin can be of a vertical design .
  • the active zone can be shaped as a cap at least partially around the n-doped region
  • the p- doped region can be shaped as a cap at least partially around the active zone and the n-doped region, seen in crosssection, so that at least one active semiconductor fin can be of a core-shell design .
  • a length of the at least one active semiconductor fin exceeds a height of the at least one active semiconductor fin above the base plane by at least a factor of three or by at least a factor of five or by at least a factor of ten .
  • the at least one active semiconductor fin is signi ficantly longer than high .
  • a width perpendicular to the length of the at least one active semiconductor fin is at most 120% or is at most 80% or is at most 60% of the height .
  • the at least one active semiconductor fin can be comparably narrow, relative to the height .
  • the height of the at least one active semiconductor fin is at least 0 . 4 pm or at least 0 . 7 pm . Alternatively or additionally, the height is at most 5 pm or at most 2 pm .
  • the at least one active semiconductor fin is of constant height .
  • a top of the at least one active semiconductor fin remote from the base plane is at the same level all along the at least one active semiconductor fin . This applies , for example , with a tolerance of at most 20% or of at most 10% of a maximum height of the respective at least one active semiconductor fin .
  • the optoelectronic semiconductor device further comprises one or a plurality of passive semiconductor fins .
  • the at least one passive semiconductor fin is configured not to emit radiation by electroluminescence .
  • the at least one passive semiconductor fin is preferably neither configured to emit radiation by photoluminescence in the intended use of the device .
  • the at least one passive semiconductor fin can be regarded as a geometric structure which is possibly optically and electrically inactive .
  • the at least one passive semiconductor fin growth conditions for the at least one active semiconductor fin can be improved, in particular when growing the active zone .
  • at opposing sides of the at least one active semiconductor fin or at di f ferent active semiconductor fin there may be di f ferent gas streaming conditions during growth of the active zone , which may influence the emission characteristics of the respective active semiconductor fin .
  • gas streaming conditions at the at least one active semiconductor fin can be homogeni zed during growth leading to a homogeni zed optical emission, too .
  • the at least one passive semiconductor fin comprises the n-doped region, too , but is free of the active zone and/or the p-doped region and/or is free of a first current spreading layer applied on the at least one active semiconductor fin .
  • the at least one passive semiconductor fin could basically be designed like the at least one active semiconductor fin, but misses at least one component essential for generating radiation .
  • that there is no active zone at the at least one passive semiconductor fin may be defined by using a masking .
  • the at least one passive semiconductor fin and the at least one active semiconductor fin have the same height .
  • a height of the active zone and of the p-doped region is far less than a height of the n-doped region, when the active zone or the p-doped region is not present in the at least one passive semiconductor fin, this does not signi ficantly change a height of the at least one passive semiconductor fin compared with the at least one active semiconductor fin .
  • the at least one active semiconductor fin may be only slightly higher than the at least one passive semiconductor fin .
  • the at least one passive semiconductor fin runs along the at least two di f ferent directions .
  • the directions the at least one passive semiconductor fin runs along can be the same directions as the directions the at least one active semiconductor fin runs along, or can otherwise be di f ferent .
  • the at least one passive semiconductor fin, or at least one of the passive semiconductor fins i f there is a plurality of the passive semiconductor fins is arranged around the at least one active semiconductor fin, seen in top view of the base plane .
  • the at least one passive semiconductor fin may form a courtyard in which the at least one active semiconductor fin is placed, seen in top view of the base plane .
  • the at least one passive semiconductor fin, or at least one of the passive semiconductor fins i f there is a plurality of the passive semiconductor fins is surrounded by the at least one active semiconductor fin, seen in top view of the base plane .
  • the at least one active semiconductor fin may form an inner courtyard in which the at least one passive semiconductor fin is placed, seen in top view of the base plane .
  • At least one active semiconductor fin arranged between an exterior at least one passive semiconductor fin and an interior at least one passive semiconductor fin .
  • the optoelectronic semiconductor device comprises a plurality of the active semiconductor fins and one passive semiconductor fin, or comprises one active semiconductor fins and a plurality of the passive semiconductor fin, or comprises a plurality of the active semiconductor fins as well as a plurality of the passive semiconductor fins .
  • the at least one active/passive semiconductor fin runs along exactly three di f ferent directions . I f there is a plurality of the active/passive semiconductor fins , preferably this applies collectively to all the active/passive semiconductor fins .
  • the at least one active semiconductor fin is based on the material Al n In]__ n-m Ga m N .
  • a peak wavelength of the light generated in the intended operation of the semiconductor device is in the near-ultraviolet spectral range or in the visible spectral range or in the near-infrared spectral range .
  • the near-ultraviolet spectral range refers to peak wavelengths from 360 nm to 430 nm
  • the visible spectral range refers to peak wavelengths from 431 nm to 680 nm
  • the near-infrared spectral range refers to peak wavelengths from 681 nm to 1 . 5 pm .
  • the at least one active semiconductor fin is based on the material Inj__ m Ga m N and is configured to emit red light .
  • Red light may refer to peak wavelengths from 600 nm to 680 nm .
  • m is between 0 . 5 and 0 . 97 inclusive .
  • an angle between directions of main extent of the at least one active semiconductor fin and/or of the at least one passive semiconductor fin is in each case N times 60 ° , and
  • the at least one semiconductor fin can be aligned with an m-plane of GaN at the base plane .
  • an angle between directions of main extent of the at least one active semiconductor fin is different from 60° and is also different from 120°.
  • said angle may also be different from 30° and from 90° and from 150°.
  • the at least one active semiconductor fin and/or the at least one passive semiconductor fin is arranged in a trigonal or hexagonal pattern.
  • the respective at least one semiconductor fin runs along at most three different directions. Preferably, there are exactly three different directions at 0°, 60° and at 120°.
  • the at least one active semiconductor fin and/or the at least one passive semiconductor fin from a ring-like structure comprising at least two rings as closed structures.
  • Each one of the rings may be composed of one of the active semiconductor fins or of one of the passive semiconductor fins, or each one of the rings is composed of a chain of passive and/or active semiconductor fins.
  • the at least one active semiconductor fin and/or the at least one passive semiconductor fin is a completely closed structure.
  • the respective semiconductor fin can enclose one or a plurality of courtyards in the manner of a closed frame, seen in top view of the base plane.
  • the at least one active semiconductor fin and/or the at least one passive semiconductor fin is a closed structure with left-open corners.
  • the at least one active semiconductor fin and/or the at least one passive semiconductor fin is present not at all or is present to at most 40% or to at most 20% or to at most 5%, referring to a height of the respective at least one active semiconductor fin and/or the at least one passive semiconductor fin.
  • a length along which the closed structure is opened in each case because one of the left-open corners is at most 0.3 pm or is at most 0.2 pm or is at most 0.1 pm.
  • the left-open corners have each an extent of at most 0.3 pm or of at most 0.2 pm or of at most 0.1 pm, in said extent the respective at least one active semiconductor fin and/or the at least one passive semiconductor fin is not present.
  • the otherwise closed at least one active semiconductor fin and/or the at least one passive semiconductor fin has been opened along a length of at most 0.3 pm or of at most 0.2 pm or of at most 0.1 pm to create the respective left-open corner.
  • the optoelectronic semiconductor device comprises a plurality of pixels .
  • each one of the pixels comprises its own at least one active semiconductor fin and/or its own at least one passive semiconductor fin .
  • All the pixels can have the same configuration and/or design, or there are di f ferent types of pixels , for example , to produce red light , green and blue light .
  • the pixels have si ze of at least 0 . 5 pm or of at least 1 pm and/or of at most 20 pm or of at most 12 pm .
  • the si ze may refer to a diameter of the respective pixel or to a length of a diagonal of the respective pixel , seen in top view of the base plane .
  • the pixels are designed in a point- symmetric manner .
  • the pixels are designed in a mirror-symmetric manner with at least two or with at least four axes of mirror symmetry .
  • a method for producing the optoelectronic semiconductor device is additionally provided .
  • an optoelectronic semiconductor device can be produced as indicated in connection with at least one of the above-stated embodiments .
  • Features of the optoelectronic semiconductor device are therefore also disclosed for the method and vice versa .
  • the method comprises the following steps , preferably in the order provided : A) providing the base plane ,
  • Figure 1 is a schematic top view of an exemplary embodiment of an optoelectronic semiconductor device described herein,
  • Figure 2 is a schematic sectional view of the optoelectronic semiconductor device of Figure 1 .
  • Figure 3 is a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor device described herein,
  • Figures 4 to 29 are schematic top views of exemplary embodiments of optoelectronic semiconductor devices described herein
  • Figure 30 is a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor device described herein, and
  • Figure 31 is a schematic block diagram of an exemplary embodiment of a method to produce optoelectronic semiconductor devices described herein .
  • Figures 1 and 2 illustrate an exemplary embodiment of an optoelectronic semiconductor device 1 .
  • the semiconductor device 1 comprises three active semiconductor fins 2 which are configured to produce light when provided with current , for example , to produce red light .
  • the active semiconductor fins 2 start from a base plane 20 .
  • the base plane 20 is defined by a side of a mask layer 51 facing away from the active semiconductor fins 2 .
  • the mask layer 51 there are openings 55 which may be shaped line-like when seen in top view of the base plane 20 .
  • the mask layer 51 may be configured for selective area growth, SAG for short .
  • locations of the active semiconductor fins 2 are defined by the openings 55 .
  • the active semiconductor fins 2 are based on the material system InGaN .
  • a substrate 24 that can be a growth substrate and that may also constitute a carrier 70 that mechanically bears the semiconductor device 1 .
  • the substrate 24 is , for example , of sapphire or of silicon .
  • a continuous second current spreading layer 42 which can be made of n-doped GaN .
  • the second electric contact structure 82 may be metallic and is made , for example , of at least one of Au, Cu and Sn or includes at least one of these metals .
  • the active semiconductor fins 2 each include a first region 21 which may be made of n-doped GaN and/or of n-doped InGaN .
  • the first region 21 starts at the second current spreading layer 42 where the latter is free of the mask layer 51 .
  • the first region 21 may be composed of a rectangular section followed by a trapezoidal section .
  • an active zone 22 including, for example , a multi-quantum well structure , MQW for short .
  • the active zone 22 is followed by a second region 23 which is , for example , of p-doped GaN .
  • the second region 23 can cover all of the active zone 22 as well as all of the first region 21 protruding from the mask layer 51 .
  • a height H of the active semiconductor fins 2 is at least 0 . 1 pm and/or at most 1 pm .
  • a width W of the active semiconductor fins 2 can be smaller than the height H .
  • the height H is constant all along the active semiconductor fins 2 .
  • the first region 21 amounts for at least 60% or for at least 70% or for at least 80% of the height H .
  • the second region 23 as well as the active zone 22 can be signi ficantly thinner than the first region 21 .
  • the active semiconductor fins 2 are embedded in a passivation layer 71 applied on the mask layer 51 .
  • the passivation layer 71 is made of an oxide like aluminum oxide or of a nitride like silicon nitride .
  • the passivation layer 71 can also be of multilayer fashion .
  • the mask layer 51 is , for example , of an oxide like silicon oxide .
  • the passivation layer 71 may terminate flush with the active semiconductor fins 2 , along a direction away from the mask layer 51 .
  • the first current spreading layer 41 serves as a p-contact and is made , for example , of a metal like Al or Ag or also of a transparent conductive oxide , TCO for short , like indium tin oxide , ITO for short , or like ZnO .
  • TCO transparent conductive oxide
  • ITO indium tin oxide
  • ZnO zinc oxide
  • the first electric contact structure 81 is formed in two strips atop the passivation layer 71 and optionally embedding the first current spreading layer 41 .
  • the second electric contact structure 82 may be arranged in two arcs and may run through the passivation layer 71 down to the second current spreading layer 42 .
  • the three active semiconductor fins 2 are of concentric and regular hexagons , seen in top view .
  • the semiconductor device 1 also comprises two passive semiconductor fins 3 .
  • the passive semiconductor fins 3 may be configured in the same manner as the active semiconductor fins 2 , within the manufacturing tolerances .
  • the passive semiconductor fins 3 may include the first region 21 , the active zone 22 and the second region 23 , but di f fer from the active semiconductor fins 2 in that there is no electric contact structure for the passive semiconductor fins 3 .
  • the passive semiconductor fins 3 cannot produce light .
  • An exterior one of the passive semiconductor fins 3 essentially surrounds the active semiconductor fins 2 , and an interior one of the passive semiconductor fins 3 is surrounded by all of the active semiconductor fins 2 .
  • the passive semiconductor fins 3 are of a regular hexagonal structure , too , wherein the interior passive semiconductor fin 3 can be shaped like a wheel with spokes .
  • the active semiconductor fins 2 as well as the passive semiconductor fins 3 have all along their length the same set-up .
  • the arrangement of the first region 21 , of the active zone 22 and of the second region 23 may not change along the semiconductor fins 2 , 3 .
  • the passive semiconductor fins 3 may be free of the active zone 22 and/or of the second region 23 so that the passive semiconductor fins 3 may not be used for producing radiation even i f provided with a complete electric wiring at a p-side and at an n-side .
  • FIG 3 a further embodiment of the semiconductor device 1 is illustrated .
  • the substrate 24 as present in Figure 2 has been replaced by a carrier 70 .
  • the second current spreading layer 42 made of n-doped GaN may directly be applied with the metallic second electric contact structure 82 .
  • the second electric contact structure 82 is applied as a ring outside the active semiconductor fins 2 .
  • the first current spreading layer 41 is embedded in the first electric contact structure 81 .
  • the first electric contact structure 81 is a metallic bond layer by means of which the carrier 70 is attached to the active semiconductor fins 2 .
  • the carrier 70 is a silicon carrier .
  • the semiconductor device 1 of Figure 3 can of course also include at least one of the passive semiconductor fins 3 .
  • the semiconductor device 1 comprises a plurality of structural units , wherein the structural units each comprise a system of , for example , four concentric active semiconductor fins 2 shaped as regular hexagons . Between adj acent structural units of the active semiconductor fins 2 , and optionally also in center regions of the active semiconductor fins 2 , there are passive semiconductor fins 3 .
  • the semiconductor fins 2 , 3 can be oriented in parallel with the a-plane or the m-plane of a GaN-based base plane 20 , like the second current spreading layer made of n-doped GaN .
  • the passive semiconductor fins 3 in center regions between four adj acent structural units , have the shape of a rhomb, seen in top view .
  • the passive semiconductor fins 3 in the courtyards formed by the active semiconductor fins 2 have a regular hexagonal shape , too , and are also arranged in a concentric manner with the active semiconductor fins 3 .
  • the respective hexagons can be arranged in an equidistant manner .
  • a distance between the active semiconductor fins 2 and adj acent passive or active semiconductor fins 3 can be about the same all across the semiconductor device 1 .
  • a distance between the active semiconductor fins 2 and adj acent passive or active semiconductor fins 3 can be about the same all across the semiconductor device 1 .
  • Figure 5 The arrangement of Figure 5 is essentially the same as in Figure 4 , but the structural units are each assigned to one of a plurality of pixels 6 . It is possible that the pixels 6 are designed identically . Moreover, it is possible that the pixels 6 can electrically addressed independently of one another .
  • the carrier not shown in Figure 5 , can comprise an electric circuitry, or can be attached to an electric circuitry, like an IC chip . Thus , the same as to Figure 4 may also apply to Figure 5 , and vice versa .
  • the interior passive semiconductor fins 3 are shaped like hexagonal wheels with six spokes . There can be further rhombic passive semiconductor fins 3 outside the hexagonal exterior passive semiconductor fins 3 .
  • the semiconductor fins 2 , 3 of Figure 6 are again parted into the pixels 6 .
  • the pixels 6 can be arranged in a rectangular patter or, other than shown, may alternatively by arranged in a hexagonal pattern .
  • the active semiconductor fins 2 are concentric circles , seen in top view .
  • the respective circles can be arranged in an equidistant manner, too .
  • the semiconductor fins 2 , 3 can be parted into pixels . Otherwise , the same as to Figures 1 to 7 may also apply to Figure 8 , and vice versa .
  • FIG. 9 to 23 various examples of the semiconductor fins 2 , 3 are shown in top view, wherein in each case only one structural unit is illustrated . These structural units may serve for pixels .
  • the three active semiconductor fins 2 and the exterior passive semiconductor fin 3 are regular hexagons , possibly arranged in a concentric and/or equidistant manner .
  • the central passive semiconductor fin 3 is of hexagonal shape and has six spokes .
  • the actual number of active semiconductor fins 2 can vary, for example , from one to three .
  • the active semiconductor fins 2 are circles , and there is one or there are two interior circular passive semiconductor fins 3 . All the circles can optionally be arranged concentrically and/or in an equidistant manner .
  • the actual number of active semiconductor fins 2 can vary, for example , from two to four .
  • the active semiconductor fins 2 are circles again, and there is one exterior circular passive semiconductor fins 3 . All the circles can optionally be arranged in a concentric and/or equidistant manner.
  • the actual number of active semiconductor fins 2 can vary, for example, from two to four.
  • Figures 15 to 17 and of Figures 18 to 20 can be combined with each other. That is, analogous to Figures 10 to 12, there can be exterior as well as interior passive semiconductor fins 3.
  • the active semiconductor fins 2 are triangles, in particular equilateral triangles.
  • the triangles can be arranged in a concentric and/or equidistant manner.
  • the actual number of active semiconductor fins 2 can vary, for example, from one to three .
  • the active semiconductor fin 2 span a trigonal grid. That is, effectively there is only one active semiconductor fin 2 including all the trigonal branches. According to Figure 25, there are concentric triangles that form the active semiconductor fins 2. In Figure 26, the active semiconductor fins 2 are realized by concentric hexagons . In Figures 24 to 26, a rectangular box is illustrated for the semiconductor devices 1 and/or for the pixels, wherein the illustrated pattern for the at least one active semiconductor fin 2 protrudes from the box. It is possible that all parts of the at least one active semiconductor fin 2 outside the box are cut away or are not at all grown. Thus, structures with open corners may result, see also Figures 28 and 29.
  • Figure 27 it is illustrated that a combination of structures, that is, of hexagons and lines, may be present, for example, due to really or virtually cutting away parts of the at least one active semiconductor fin 2.
  • all the parts of the active semiconductor fins 2 are arranged with angles of 0°, 60° or 120° relative to one another .
  • the structures of the semiconductor devices 1 of Figures 28 and 29 are based on the structures of Figures 10 and 22, respectively. However, in order to reduce tensions along the semiconductor fins 2, 3, there are left-open corners 25. Thus, in principle the semiconductor fins 2, 3 from closed structures, but the corners are removed. In other words, the semiconductor fins 2, 3 may be regarded as chains of semiconductor fins 2, 3 that form a closed structure like a hexagon or a triangle. For example, a length LC along which the closed structure is opened is at most 0.3 pm or is at most 0.2 pm. Thus, the openings resulting from leaving the corners open can be comparably short.
  • left-open corners 25 are limited to the active semiconductor fins 2 so that the passive semiconductor fins 3 may remain as completely closed structures.
  • such left-open corners 25 in the passive semiconductor fins 3 may serve as locations at which an electrical wiring is led to the active semiconductor fins 2, compare Figure 1.
  • Such left-open corners 25 can also be present in all other embodiments in which the semiconductor fins 2, 3 are of polygonal structure.
  • the circular semiconductor fins 2, 3 can have short openings, for example, with a length LC of at most 0.3 pm or of at most 0.2 pm, such that structures with one or with a plurality of arcs may arise.
  • ends of the semiconductor fins 2, 3 are illustrated with acute angles or with obtuse angles. Contrary to that, preferably the ends of the semiconductor fins 2, 3 are of rectangular fashion or may have rounded corners. That is, the semiconductor fins 2, 3 may end with rounded edges. The same applies to all other embodiments. Otherwise, the same as to Figures 1 to 27 may also apply to Figures 28 and 29, and vice versa.
  • the semiconductor fins 2, 3 are of a core-shell design. Contrary to that, the active semiconductor fins 2 of Figure 30 are of a vertical design so that a layer stack with essentially congruent layers is formed. Such a vertical set-up can also be present in Figure 1 and in the embodiments of Figures 4 to 29 instead of the core-shell set-up of Figures 2 and 3.
  • the substrate 24 there can be a buffer layer 26 which is made, for example, of AlInGaN, in particular of GaN.
  • the substrate 24 may be made from sapphire, for example.
  • the buffer layer 26 is followed by the second current spreading layer 42 made of n-doped GaN, for example.
  • the second current spreading layer 42 is provided with the SAG mask layer 51 having the at least one line-like opening 55 to define the semiconductor fins 2, 3.
  • the semiconductor fins 2, 3 comprise a base region 27 made, for example, from n-doped GaN.
  • the base region 27 is followed by a transition region 28 in which there are first sub-layers 91 and second sub-layers 92 which are arranged in an alternating manner.
  • first sub-layers 91 and second sub-layers 92 are arranged in an alternating manner.
  • first sub-layers 91 and second sub-layers 92 are made of GaN and the second sub-layers 92 are made of InGaN.
  • An In content in the second sub-layers 92 is, for example, from above 0% to 20%.
  • a thickness of the sub-layers 91, 92 is, for example, from 0.25 nm to 25 nm.
  • the In content in the second sub-layers 92 increases from sub-layer to sub-layer, and the thicknesses of the sub-layers 91, 92 may also vary along the direction away from the base plane 20.
  • the first region 21 which is composed of the base region 27 and of the transition region 28, is followed by the active zone 22.
  • the active zone 22 also comprises sub-layers 93, 94 which may be different from the sub-layers 91, 92 in the transition region 28.
  • the sub-layers 93 are barrier layers and the sub-layers 94 are quantum well layers.
  • a thickness and/or material composition of the sub-layers 93, 94 preferably does not vary across different sub-layers 93, 94 so that, for example, all the sub-layers 94 are of equal design, concerning thickness and/or material composition, within the manufacturing tolerances; the same can apply for the sub-layers 93.
  • the quantum well sub-layers 94 are made of InGaN with an In content from above 0% to 20%, and the barrier layers 93 are made of GaN.
  • a thickness of the sub-layers 93, 94 is, for example, between 0.25 nm and 25 nm.
  • the second region 23 which is made, for example, of p-doped InAlGaN.
  • a thickness of the individual layers 27, 28, 22, 23 in the layer stack 27, 28, 22, 23 and/or an overall thickness of the layer stack 27, 28, 22, 23 is, for example, at least 10 nm and at most 0.5 pm or is at least 20 nm and at most 0.3 pm.
  • the set-up shown in Figure 30 can apply both for the active semiconductor fins 2 as well as for the passive semiconductor fins 3 , wherein the passive semiconductor fins 3 are optionally free of the active zone 22 and/or free of the second region 23 .
  • a method to produce the optoelectronic semiconductor devices 1 is illustrated .
  • the base plane 20 is provided . That is , for example , the n-doped second current spreading layer 42 made of GaN is provided .
  • a second method step S2 the mask layer 51 is provided on the base plane 20 , and the at least one line-like opening 55 is formed in the mask layer 51 .
  • a third method step S3 the at least one active semiconductor fin 2 and optionally the at least one passive semiconductor fin 3 are grown starting from the at least one line-like opening 55 .
  • a fourth method step S4 the optional passivation layer 71 as well as the electric wiring 41 , 81 , 82 are provided, and as a further option the growth substrate 24 may be replaced with a carrier 70 .
  • the semiconductor device described here is not restricted by the description on the basis of the exemplary embodiments . Rather, the semiconductor device encompasses any new feature and also any combination of features , which includes in particular any combination of features in the patent claims , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .

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Abstract

In at least one embodiment, the optoelectronic semiconductor device (1) comprises at least one active semiconductor fin (2) which is configured to emit radiation by electroluminescence, wherein the at least one active semiconductor fin (2) starts from a base plane (20), and seen in top view of the base plane (20), the at least one active semiconductor fin (2) runs along at least two different directions (E).

Description

Description
OPTOELECTRONIC SEMICONDUCTOR DEVICE AND PRODUCTION METHOD
An optoelectronic semiconductor device is provided. A method for producing such an optoelectronic semiconductor device is also provided.
Document J. Winnerl et al., "Selectively grown GaN nanowalls and nanogrids for photocatalysis: growth and optical properties", Nanoscale, 2019, 11, 4578, refers to semiconductor fins based on GaN.
A problem to be solved is to provide an optoelectronic semiconductor device that has improved optical emission characteristics .
This object is achieved, inter alia, by an optoelectronic semiconductor device and by a method as defined in the independent patent claims. Exemplary further developments constitute the sub ect-matter of the dependent claims.
According to at least one embodiment, the optoelectronic semiconductor device comprises one or a plurality of active semiconductor fins. The at least one active semiconductor fin is configured to emit radiation by electroluminescence. That is, if current is provided as intended, light is produced in the at least one active semiconductor fin. The active semiconductor fin may also be referred to as nanofin.
According to at least one embodiment, the at least one active semiconductor fin is based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as AlnIn]__n-mGamN or a phosphide compound semiconductor material such as AlnIn]__n-mGamP or also an arsenide compound semiconductor material such as AlnIn]__n-mGamAs , wherein in each case 0 < n < 1 , 0 < m < 1 and n + m < 1 applies . The semiconductor layer sequence may comprise dopants and additional constituents . For simplicity ' s sake , however, only the essential constituents of the crystal lattice of the semiconductor layer sequence are indicated, that is , Al , As , Ga, In, N or P, even i f these may in part be replaced and/or supplemented by small quantities of further substances . The at least one active semiconductor fin is particularly preferably based on the InGaN material system .
According to at least one embodiment , the at least one active semiconductor fin starts from a base plane . The base plane is , for example , a plane at which a growth of the at least one active semiconductor fin has begun . The base plane may be defined by a common base layer which could be made of GaN, for example , or may also be defined by a common electrode layer or current spreading layer to electrically contact the at least one active semiconductor fin . Further, the base plane may be defined by a carrier at which the at least one active semiconductor fin is placed on . In particular, the base plane is located at an n-side of the at least one active semiconductor fin .
According to at least one embodiment , seen in top view of the base plane , the at least one active semiconductor fin runs along at least two di f ferent directions . There can be discrete di f ferent directions , i f the at least one active semiconductor fin is of linear or polygonal structure , seen in top view, or there can be continuous di f ferent directions , i f the at least one active semiconductor fin is of round fashion . In case of discrete di f ferent directions , the directions along which the at least one active semiconductor fin runs may be referred to as directions of main extent .
In at least one embodiment , the optoelectronic semiconductor device comprises at least one active semiconductor fin which is configured to emit radiation by electroluminescence , wherein
- the at least one active semiconductor fin starts from a base plane , and
- seen in top view of the base plane , the at least one active semiconductor fin runs along at least two di f ferent directions ; as an option, the optoelectronic semiconductor device further comprises at least one passive semiconductor fin configured not to emit radiation by electroluminescence , wherein, within a factor of at most 1 . 5 , the at least one passive semiconductor fin and the at least one active semiconductor fin have the same height .
For example , red-emitting p-pixel imagers based on linear InGaN-nanof ins exhibit an angle-dependent optical far- field emission pattern . With the optoelectronic semiconductor device and with the method described herein, nanofins based on InGaN having a high In-content InGaN can be used while maintaining an azimuth angle-independent emission pattern .
For example , nanofins can be grown in parallel lines between lines of a dielectric mask layer all over a wafer . After the growth of n-doped, active and p-doped layers the chip process then defines the multiple pixels . The linear structures remain in the pixels and have strong impact on the optical far- field emission pattern . The optical far field can be tuned by additional patterning a light-emitting surface and/or by mirroring a backside .
In the method, in particular a dielectric mask layer, which defines the geometry and arrangement of the nanofins or of the nanofin array, is lithographically patterned in a way that , for example , parallel nanofin structures with angles of 0 ° , - 60 ° and 60 ° relative to the m-plane of the GaN crystal occur within the area of each pixel . This can be achieved by concentric equilateral triangles , hexagons or circles as pattern in the dielectric growth mask layer . Also passive nanostructures , that is , passive semiconductor fins , meaning structures which are non-conductive and/or not light-emitting can be introduced to improve the homogeneity of the neighboring active nanostructures .
Due to the usage of 3D grown nanostructures , like nanowalls or nanofins , the relaxation of the epitaxially grown layer, especially of the active area, can be controlled . The replacement of parallel linear nanofin structures by nanofins in multiple orientations randomi zes the nanofin optical ef fect on the outcoupling of light and therewith on the optical far- field pattern . Furthermore , the directionality can be controlled by changing the pitch between two adj acent nanofins . At the same time , all processes for the chip and pixel definition and contacting can remain the same . Besides this , the chip process can be simpli fied after tuning the geometry and arrangement of the nanofins , for example , less impact of a chip mesa on light outcoupling and/or less impact of passivation on electro-optical properties can be achieved . According to at least one embodiment , the at least one active semiconductor fin comprises an n-doped region, a p-doped region and an active zone located between the n-doped region and the p-doped region . Seen in cross-section, the n-doped region, the active zone and the p-doped region can be stacked on top of each other in a direction away from the base plane so that the at least one active semiconductor fin can be of a vertical design . Further, the active zone can be shaped as a cap at least partially around the n-doped region, and the p- doped region can be shaped as a cap at least partially around the active zone and the n-doped region, seen in crosssection, so that at least one active semiconductor fin can be of a core-shell design .
According to at least one embodiment , a length of the at least one active semiconductor fin exceeds a height of the at least one active semiconductor fin above the base plane by at least a factor of three or by at least a factor of five or by at least a factor of ten . In other words , the at least one active semiconductor fin is signi ficantly longer than high .
According to at least one embodiment , seen in top view of the base plane , a width perpendicular to the length of the at least one active semiconductor fin is at most 120% or is at most 80% or is at most 60% of the height . Thus , the at least one active semiconductor fin can be comparably narrow, relative to the height .
For example , the height of the at least one active semiconductor fin is at least 0 . 4 pm or at least 0 . 7 pm . Alternatively or additionally, the height is at most 5 pm or at most 2 pm . According to at least one embodiment , the at least one active semiconductor fin is of constant height . Hence , a top of the at least one active semiconductor fin remote from the base plane is at the same level all along the at least one active semiconductor fin . This applies , for example , with a tolerance of at most 20% or of at most 10% of a maximum height of the respective at least one active semiconductor fin .
According to at least one embodiment , the optoelectronic semiconductor device further comprises one or a plurality of passive semiconductor fins . The at least one passive semiconductor fin is configured not to emit radiation by electroluminescence . Moreover, the at least one passive semiconductor fin is preferably neither configured to emit radiation by photoluminescence in the intended use of the device . Thus , the at least one passive semiconductor fin can be regarded as a geometric structure which is possibly optically and electrically inactive .
By means of the at least one passive semiconductor fin, growth conditions for the at least one active semiconductor fin can be improved, in particular when growing the active zone . For example , without the at least one passive semiconductor fin, at opposing sides of the at least one active semiconductor fin or at di f ferent active semiconductor fin there may be di f ferent gas streaming conditions during growth of the active zone , which may influence the emission characteristics of the respective active semiconductor fin . By means of the at least one passive semiconductor fin, gas streaming conditions at the at least one active semiconductor fin can be homogeni zed during growth leading to a homogeni zed optical emission, too . According to at least one embodiment , the at least one passive semiconductor fin comprises the n-doped region, too , but is free of the active zone and/or the p-doped region and/or is free of a first current spreading layer applied on the at least one active semiconductor fin . Thus , the at least one passive semiconductor fin could basically be designed like the at least one active semiconductor fin, but misses at least one component essential for generating radiation . For example , that there is no active zone at the at least one passive semiconductor fin may be defined by using a masking .
According to at least one embodiment , within a factor of at most 1 . 5 or within a factor of at most 1 . 2 , the at least one passive semiconductor fin and the at least one active semiconductor fin have the same height . For example , because a height of the active zone and of the p-doped region is far less than a height of the n-doped region, when the active zone or the p-doped region is not present in the at least one passive semiconductor fin, this does not signi ficantly change a height of the at least one passive semiconductor fin compared with the at least one active semiconductor fin . Thus , the at least one active semiconductor fin may be only slightly higher than the at least one passive semiconductor fin .
According to at least one embodiment , the at least one passive semiconductor fin runs along the at least two di f ferent directions . The directions the at least one passive semiconductor fin runs along can be the same directions as the directions the at least one active semiconductor fin runs along, or can otherwise be di f ferent . According to at least one embodiment , the at least one passive semiconductor fin, or at least one of the passive semiconductor fins i f there is a plurality of the passive semiconductor fins , is arranged around the at least one active semiconductor fin, seen in top view of the base plane . In other words , the at least one passive semiconductor fin may form a courtyard in which the at least one active semiconductor fin is placed, seen in top view of the base plane .
According to at least one embodiment , the at least one passive semiconductor fin, or at least one of the passive semiconductor fins i f there is a plurality of the passive semiconductor fins , is surrounded by the at least one active semiconductor fin, seen in top view of the base plane . In other words , the at least one active semiconductor fin may form an inner courtyard in which the at least one passive semiconductor fin is placed, seen in top view of the base plane .
It is possible that there is at least one active semiconductor fin arranged between an exterior at least one passive semiconductor fin and an interior at least one passive semiconductor fin .
According to at least one embodiment , the optoelectronic semiconductor device comprises a plurality of the active semiconductor fins and one passive semiconductor fin, or comprises one active semiconductor fins and a plurality of the passive semiconductor fin, or comprises a plurality of the active semiconductor fins as well as a plurality of the passive semiconductor fins . According to at least one embodiment , the at least one active/passive semiconductor fin runs along exactly three di f ferent directions . I f there is a plurality of the active/passive semiconductor fins , preferably this applies collectively to all the active/passive semiconductor fins .
According to at least one embodiment , the at least one active semiconductor fin is based on the material AlnIn]__n-mGamN .
For example , a peak wavelength of the light generated in the intended operation of the semiconductor device is in the near-ultraviolet spectral range or in the visible spectral range or in the near-infrared spectral range . For example , the near-ultraviolet spectral range refers to peak wavelengths from 360 nm to 430 nm, the visible spectral range refers to peak wavelengths from 431 nm to 680 nm, and the near-infrared spectral range refers to peak wavelengths from 681 nm to 1 . 5 pm .
According to at least one embodiment , the at least one active semiconductor fin is based on the material Inj__mGamN and is configured to emit red light . Red light may refer to peak wavelengths from 600 nm to 680 nm . For example , in quantum wells of the active zone it applies that m is between 0 . 5 and 0 . 97 inclusive .
According to at least one embodiment , an angle between directions of main extent of the at least one active semiconductor fin and/or of the at least one passive semiconductor fin is in each case N times 60 ° , and
N 6 { 1 ; 2 } . Thus , the at least one semiconductor fin can be aligned with an m-plane of GaN at the base plane . According to at least one embodiment, an angle between directions of main extent of the at least one active semiconductor fin is different from 60° and is also different from 120°. As an option, said angle may also be different from 30° and from 90° and from 150°.
It is noted that in this respect an angle plus 180° is regarded as the same angle, because in the present case there is no differentiation between a direction and the corresponding antiparallel direction.
According to at least one embodiment, seen in top view of the base plane, the at least one active semiconductor fin and/or the at least one passive semiconductor fin is arranged in a trigonal or hexagonal pattern. Thus, the respective at least one semiconductor fin runs along at most three different directions. Preferably, there are exactly three different directions at 0°, 60° and at 120°.
According to at least one embodiment, the at least one active semiconductor fin and/or the at least one passive semiconductor fin from a ring-like structure comprising at least two rings as closed structures. Each one of the rings may be composed of one of the active semiconductor fins or of one of the passive semiconductor fins, or each one of the rings is composed of a chain of passive and/or active semiconductor fins. For example, there are at most ten or at most six of such rings. It is possible that the rings are arranged in a concentric manner. As an alternative, there is only one such ring.
According to at least one embodiment, seen in top view of the base plane, the at least one active semiconductor fin and/or the at least one passive semiconductor fin is a completely closed structure. Thus, the respective semiconductor fin can enclose one or a plurality of courtyards in the manner of a closed frame, seen in top view of the base plane.
According to at least one embodiment, seen in top view of the base plane, the at least one active semiconductor fin and/or the at least one passive semiconductor fin is a closed structure with left-open corners. In the respective left-open corner, the at least one active semiconductor fin and/or the at least one passive semiconductor fin is present not at all or is present to at most 40% or to at most 20% or to at most 5%, referring to a height of the respective at least one active semiconductor fin and/or the at least one passive semiconductor fin.
For example, a length along which the closed structure is opened in each case because one of the left-open corners is at most 0.3 pm or is at most 0.2 pm or is at most 0.1 pm. In other words, the left-open corners have each an extent of at most 0.3 pm or of at most 0.2 pm or of at most 0.1 pm, in said extent the respective at least one active semiconductor fin and/or the at least one passive semiconductor fin is not present. This means, for example, that the otherwise closed at least one active semiconductor fin and/or the at least one passive semiconductor fin has been opened along a length of at most 0.3 pm or of at most 0.2 pm or of at most 0.1 pm to create the respective left-open corner. By means of such left-open corners, it is possible to reduce stress in the at least one active semiconductor fin and/or the at least one passive semiconductor fin. According to at least one embodiment , the optoelectronic semiconductor device comprises a plurality of pixels . Preferably, each one of the pixels comprises its own at least one active semiconductor fin and/or its own at least one passive semiconductor fin . All the pixels can have the same configuration and/or design, or there are di f ferent types of pixels , for example , to produce red light , green and blue light .
According to at least one embodiment , the pixels have si ze of at least 0 . 5 pm or of at least 1 pm and/or of at most 20 pm or of at most 12 pm . The si ze may refer to a diameter of the respective pixel or to a length of a diagonal of the respective pixel , seen in top view of the base plane .
According to at least one embodiment , seen in top view of the base plane and concerning the at least one active semiconductor fin and/or the at least one passive semiconductor fin, the pixels are designed in a point- symmetric manner . Alternatively or additionally, the pixels are designed in a mirror-symmetric manner with at least two or with at least four axes of mirror symmetry .
A method for producing the optoelectronic semiconductor device is additionally provided . By means of the method, an optoelectronic semiconductor device can be produced as indicated in connection with at least one of the above-stated embodiments . Features of the optoelectronic semiconductor device are therefore also disclosed for the method and vice versa .
In at least one embodiment , the method comprises the following steps , preferably in the order provided : A) providing the base plane ,
B ) providing at least one line-like opening in a mask layer at the base plane , and
C ) growing the at least one active semiconductor fin starting from the at least one line-like opening .
An optoelectronic semiconductor device and a method described herein are explained in greater detail below by way of exemplary embodiments with reference to the drawings . Elements which are the same in the individual figures are indicated with the same reference numerals . The relationships between the elements are not shown to scale , however, but rather individual elements may be shown exaggeratedly large to assist in understanding .
In the figures :
Figure 1 is a schematic top view of an exemplary embodiment of an optoelectronic semiconductor device described herein,
Figure 2 is a schematic sectional view of the optoelectronic semiconductor device of Figure 1 ,
Figure 3 is a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor device described herein,
Figures 4 to 29 are schematic top views of exemplary embodiments of optoelectronic semiconductor devices described herein, Figure 30 is a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor device described herein, and
Figure 31 is a schematic block diagram of an exemplary embodiment of a method to produce optoelectronic semiconductor devices described herein .
Figures 1 and 2 illustrate an exemplary embodiment of an optoelectronic semiconductor device 1 . The semiconductor device 1 comprises three active semiconductor fins 2 which are configured to produce light when provided with current , for example , to produce red light . The active semiconductor fins 2 start from a base plane 20 .
For example , the base plane 20 is defined by a side of a mask layer 51 facing away from the active semiconductor fins 2 . In the mask layer 51 , there are openings 55 which may be shaped line-like when seen in top view of the base plane 20 . The mask layer 51 may be configured for selective area growth, SAG for short . Thus , locations of the active semiconductor fins 2 are defined by the openings 55 .
For example , the active semiconductor fins 2 are based on the material system InGaN . Thus , optionally there is a substrate 24 that can be a growth substrate and that may also constitute a carrier 70 that mechanically bears the semiconductor device 1 . The substrate 24 is , for example , of sapphire or of silicon . At the substrate 24 , there can be a continuous second current spreading layer 42 which can be made of n-doped GaN . By means of the second current spreading layer 42 , current can be spread across the semiconductor device 1 starting from a second electric contact structure 82 . The second electric contact structure 82 may be metallic and is made , for example , of at least one of Au, Cu and Sn or includes at least one of these metals .
The active semiconductor fins 2 each include a first region 21 which may be made of n-doped GaN and/or of n-doped InGaN . The first region 21 starts at the second current spreading layer 42 where the latter is free of the mask layer 51 . Seen in cross-section, the first region 21 may be composed of a rectangular section followed by a trapezoidal section . At the trapezoidal section, there is an active zone 22 including, for example , a multi-quantum well structure , MQW for short . Further, the active zone 22 is followed by a second region 23 which is , for example , of p-doped GaN . The second region 23 can cover all of the active zone 22 as well as all of the first region 21 protruding from the mask layer 51 .
For example , a height H of the active semiconductor fins 2 is at least 0 . 1 pm and/or at most 1 pm . A width W of the active semiconductor fins 2 can be smaller than the height H . As an option, the height H is constant all along the active semiconductor fins 2 . Further, it is possible that the first region 21 amounts for at least 60% or for at least 70% or for at least 80% of the height H . Thus , the second region 23 as well as the active zone 22 can be signi ficantly thinner than the first region 21 .
Preferably, the active semiconductor fins 2 are embedded in a passivation layer 71 applied on the mask layer 51 . For example , the passivation layer 71 is made of an oxide like aluminum oxide or of a nitride like silicon nitride . Other than shown, the passivation layer 71 can also be of multilayer fashion . The mask layer 51 is , for example , of an oxide like silicon oxide . The passivation layer 71 may terminate flush with the active semiconductor fins 2 , along a direction away from the mask layer 51 .
To provide the active semiconductor fins 2 with current at the second region 23 , there can be a first current spreading layer 41 . The first current spreading layer 41 thus serves as a p-contact and is made , for example , of a metal like Al or Ag or also of a transparent conductive oxide , TCO for short , like indium tin oxide , ITO for short , or like ZnO . By means of the first current spreading layer 41 it is possible that the active semiconductor fins 2 are only at places provided with a first electric contact structure 81 which is preferably a metallic structure .
For example , seen in top view, the first electric contact structure 81 is formed in two strips atop the passivation layer 71 and optionally embedding the first current spreading layer 41 . The second electric contact structure 82 may be arranged in two arcs and may run through the passivation layer 71 down to the second current spreading layer 42 .
The three active semiconductor fins 2 are of concentric and regular hexagons , seen in top view .
As an option, see Figure 1 , the semiconductor device 1 also comprises two passive semiconductor fins 3 . The passive semiconductor fins 3 may be configured in the same manner as the active semiconductor fins 2 , within the manufacturing tolerances . Hence , the passive semiconductor fins 3 may include the first region 21 , the active zone 22 and the second region 23 , but di f fer from the active semiconductor fins 2 in that there is no electric contact structure for the passive semiconductor fins 3 . Hence , the passive semiconductor fins 3 cannot produce light .
An exterior one of the passive semiconductor fins 3 essentially surrounds the active semiconductor fins 2 , and an interior one of the passive semiconductor fins 3 is surrounded by all of the active semiconductor fins 2 . The passive semiconductor fins 3 are of a regular hexagonal structure , too , wherein the interior passive semiconductor fin 3 can be shaped like a wheel with spokes .
By means of the passive semiconductor fins 3 , growth conditions for the active semiconductor fins 2 can be homogeni zed .
Seen in cross-section, preferably the active semiconductor fins 2 as well as the passive semiconductor fins 3 have all along their length the same set-up . In other words , the arrangement of the first region 21 , of the active zone 22 and of the second region 23 may not change along the semiconductor fins 2 , 3 .
Moreover, according to Figures 1 and 2 the passive semiconductor fins 3 di f fer from the active semiconductor fins 2 by not being provided with a complete electric wiring . Alternatively or additionally, the passive semiconductor fins 3 may be free of the active zone 22 and/or of the second region 23 so that the passive semiconductor fins 3 may not be used for producing radiation even i f provided with a complete electric wiring at a p-side and at an n-side .
In Figure 3 , a further embodiment of the semiconductor device 1 is illustrated . The substrate 24 as present in Figure 2 has been replaced by a carrier 70 . Thus , the second current spreading layer 42 made of n-doped GaN may directly be applied with the metallic second electric contact structure 82 . For example , the second electric contact structure 82 is applied as a ring outside the active semiconductor fins 2 .
Moreover, the first current spreading layer 41 is embedded in the first electric contact structure 81 . For example , the first electric contact structure 81 is a metallic bond layer by means of which the carrier 70 is attached to the active semiconductor fins 2 . For example , the carrier 70 is a silicon carrier .
Otherwise , the same as to Figures 1 and 2 may also apply to Figure 3 , and vice versa . In particular, the semiconductor device 1 of Figure 3 can of course also include at least one of the passive semiconductor fins 3 .
In Figure 4 it is shown that the semiconductor device 1 comprises a plurality of structural units , wherein the structural units each comprise a system of , for example , four concentric active semiconductor fins 2 shaped as regular hexagons . Between adj acent structural units of the active semiconductor fins 2 , and optionally also in center regions of the active semiconductor fins 2 , there are passive semiconductor fins 3 .
Because of the hexagonal structure of the active semiconductor fins 2 , there are three di f ferent directions E along which the active semiconductor fins 2 as well as the passive semiconductor fins 3 extent . An angle A between adj acent directions E is 60 ° or 120 ° . Thus , the semiconductor fins 2 , 3 can be oriented in parallel with the a-plane or the m-plane of a GaN-based base plane 20 , like the second current spreading layer made of n-doped GaN .
For example , in center regions between four adj acent structural units , the passive semiconductor fins 3 have the shape of a rhomb, seen in top view . The passive semiconductor fins 3 in the courtyards formed by the active semiconductor fins 2 have a regular hexagonal shape , too , and are also arranged in a concentric manner with the active semiconductor fins 3 . The respective hexagons can be arranged in an equidistant manner .
Thus , a distance between the active semiconductor fins 2 and adj acent passive or active semiconductor fins 3 can be about the same all across the semiconductor device 1 . Thus , along each one of the active semiconductor fins 2 there is about the same space towards the next semiconductor fin 2 , 3 , for example , with a tolerance of at most 10% or of at most 20% of a minimum distance between adj acent active semiconductor fins 2 .
Otherwise , the same as to Figures 1 to 3 may also apply to Figure 4 , and vice versa .
The arrangement of Figure 5 is essentially the same as in Figure 4 , but the structural units are each assigned to one of a plurality of pixels 6 . It is possible that the pixels 6 are designed identically . Moreover, it is possible that the pixels 6 can electrically addressed independently of one another . For this purpose the carrier, not shown in Figure 5 , can comprise an electric circuitry, or can be attached to an electric circuitry, like an IC chip . Thus , the same as to Figure 4 may also apply to Figure 5 , and vice versa .
According to Figure 6 , there are exterior passive semiconductor fins 3 completely surrounding the active semiconductor fins 2 . Further, like in Figure 1 , the interior passive semiconductor fins 3 are shaped like hexagonal wheels with six spokes . There can be further rhombic passive semiconductor fins 3 outside the hexagonal exterior passive semiconductor fins 3 .
According to Figure 7 , the semiconductor fins 2 , 3 of Figure 6 are again parted into the pixels 6 . Like in all other embodiments , the pixels 6 can be arranged in a rectangular patter or, other than shown, may alternatively by arranged in a hexagonal pattern .
Otherwise , the same as to Figures 1 to 5 may also apply to Figures 6 and 7 , and vice versa .
According to Figure 8 , the active semiconductor fins 2 are concentric circles , seen in top view . The respective circles can be arranged in an equidistant manner, too . Optionally, there are also circular passive semiconductor fins 3 . Preferably, there is at least one circular passive semiconductor fin 3 surrounding the assigned active semiconductor fins 2 . As an option, outside said passive semiconductor fins 3 , there can be further passive semiconductor fins 3 composed of merged circles .
Not shown in Figure 8 , as in all other exemplary embodiments , the semiconductor fins 2 , 3 can be parted into pixels . Otherwise , the same as to Figures 1 to 7 may also apply to Figure 8 , and vice versa .
In Figures 9 to 23 , various examples of the semiconductor fins 2 , 3 are shown in top view, wherein in each case only one structural unit is illustrated . These structural units may serve for pixels .
According to Figures 9 to 11 , the three active semiconductor fins 2 and the exterior passive semiconductor fin 3 are regular hexagons , possibly arranged in a concentric and/or equidistant manner . The central passive semiconductor fin 3 is of hexagonal shape and has six spokes . The actual number of active semiconductor fins 2 can vary, for example , from one to three .
In Figures 12 to 14 it is shown that there is only one passive semiconductor fin 3 all around the active semiconductor fins 2 . Thus , there is no inner passive semiconductor fin . Again, the actual number of active semiconductor fins 2 may vary, for example , from one to three .
According to Figures 15 to 17 , the active semiconductor fins 2 are circles , and there is one or there are two interior circular passive semiconductor fins 3 . All the circles can optionally be arranged concentrically and/or in an equidistant manner . The actual number of active semiconductor fins 2 can vary, for example , from two to four .
According to Figures 18 to 20 , the active semiconductor fins 2 are circles again, and there is one exterior circular passive semiconductor fins 3 . All the circles can optionally be arranged in a concentric and/or equidistant manner. The actual number of active semiconductor fins 2 can vary, for example, from two to four.
Of course, the embodiments of Figures 15 to 17 and of Figures 18 to 20 can be combined with each other. That is, analogous to Figures 10 to 12, there can be exterior as well as interior passive semiconductor fins 3.
In Figures 21 to 23 it is illustrated that the active semiconductor fins 2 are triangles, in particular equilateral triangles. The triangles can be arranged in a concentric and/or equidistant manner. The actual number of active semiconductor fins 2 can vary, for example, from one to three .
Not shown in Figures 21 to 23, there can also be exterior and/or interior passive semiconductor fins 3, analogous to Figures 9 to 11 and 15 to 20.
Otherwise, the same as to Figures 1 to 8 may also apply to Figures 9 to 23, and vice versa.
In Figures 24 to 27, further embodiments of the semiconductor device 1 are shown.
According to Figure 24, the active semiconductor fin 2 span a trigonal grid. That is, effectively there is only one active semiconductor fin 2 including all the trigonal branches. According to Figure 25, there are concentric triangles that form the active semiconductor fins 2. In Figure 26, the active semiconductor fins 2 are realized by concentric hexagons . In Figures 24 to 26, a rectangular box is illustrated for the semiconductor devices 1 and/or for the pixels, wherein the illustrated pattern for the at least one active semiconductor fin 2 protrudes from the box. It is possible that all parts of the at least one active semiconductor fin 2 outside the box are cut away or are not at all grown. Thus, structures with open corners may result, see also Figures 28 and 29.
Moreover, in Figure 27 it is illustrated that a combination of structures, that is, of hexagons and lines, may be present, for example, due to really or virtually cutting away parts of the at least one active semiconductor fin 2. In Figure 27, all the parts of the active semiconductor fins 2 are arranged with angles of 0°, 60° or 120° relative to one another .
Although not shown in Figures 24 to 27, again there can be at least one passive semiconductor fin, too, analogously to Figures 9 to 23.
Otherwise, the same as to Figures 1 to 23 may also apply to Figures 24 to 27, and vice versa.
The structures of the semiconductor devices 1 of Figures 28 and 29 are based on the structures of Figures 10 and 22, respectively. However, in order to reduce tensions along the semiconductor fins 2, 3, there are left-open corners 25. Thus, in principle the semiconductor fins 2, 3 from closed structures, but the corners are removed. In other words, the semiconductor fins 2, 3 may be regarded as chains of semiconductor fins 2, 3 that form a closed structure like a hexagon or a triangle. For example, a length LC along which the closed structure is opened is at most 0.3 pm or is at most 0.2 pm. Thus, the openings resulting from leaving the corners open can be comparably short.
Contrary to what is shown in Figures 28 and 29 it is not necessary that all the corners are left open so that there can be a mixture of left-open corners 25 and intact corners. For example, only each second or each third corner is a leftopen corner 25.
Other than shown in Figure 28, it is also possible that the left-open corners 25 are limited to the active semiconductor fins 2 so that the passive semiconductor fins 3 may remain as completely closed structures. However, such left-open corners 25 in the passive semiconductor fins 3 may serve as locations at which an electrical wiring is led to the active semiconductor fins 2, compare Figure 1.
Such left-open corners 25 can also be present in all other embodiments in which the semiconductor fins 2, 3 are of polygonal structure. Analogously, the circular semiconductor fins 2, 3 can have short openings, for example, with a length LC of at most 0.3 pm or of at most 0.2 pm, such that structures with one or with a plurality of arcs may arise.
To simplify the drawings, ends of the semiconductor fins 2, 3 are illustrated with acute angles or with obtuse angles. Contrary to that, preferably the ends of the semiconductor fins 2, 3 are of rectangular fashion or may have rounded corners. That is, the semiconductor fins 2, 3 may end with rounded edges. The same applies to all other embodiments. Otherwise, the same as to Figures 1 to 27 may also apply to Figures 28 and 29, and vice versa.
According to Figures 2 and 3, the semiconductor fins 2, 3 are of a core-shell design. Contrary to that, the active semiconductor fins 2 of Figure 30 are of a vertical design so that a layer stack with essentially congruent layers is formed. Such a vertical set-up can also be present in Figure 1 and in the embodiments of Figures 4 to 29 instead of the core-shell set-up of Figures 2 and 3.
Thus, see Figure 30, at the substrate 24 there can be a buffer layer 26 which is made, for example, of AlInGaN, in particular of GaN. The substrate 24 may be made from sapphire, for example, The buffer layer 26 is followed by the second current spreading layer 42 made of n-doped GaN, for example. The second current spreading layer 42 is provided with the SAG mask layer 51 having the at least one line-like opening 55 to define the semiconductor fins 2, 3. Starting from the line-like opening 55, the semiconductor fins 2, 3 comprise a base region 27 made, for example, from n-doped GaN.
Optionally, the base region 27 is followed by a transition region 28 in which there are first sub-layers 91 and second sub-layers 92 which are arranged in an alternating manner. For simplicity, only one first sub-layer 91 and only one second sub-layer 92 is illustrated for the transition region 28, but preferably there are multiple first and second sublayers 91, 92. For example, the first sub-layers 91 are made of GaN and the second sub-layers 92 are made of InGaN. An In content in the second sub-layers 92 is, for example, from above 0% to 20%. A thickness of the sub-layers 91, 92 is, for example, from 0.25 nm to 25 nm. Preferably, in the direction away from the base plane 20, the In content in the second sub-layers 92 increases from sub-layer to sub-layer, and the thicknesses of the sub-layers 91, 92 may also vary along the direction away from the base plane 20.
The first region 21 which is composed of the base region 27 and of the transition region 28, is followed by the active zone 22. The active zone 22 also comprises sub-layers 93, 94 which may be different from the sub-layers 91, 92 in the transition region 28. For example, the sub-layers 93 are barrier layers and the sub-layers 94 are quantum well layers. A thickness and/or material composition of the sub-layers 93, 94 preferably does not vary across different sub-layers 93, 94 so that, for example, all the sub-layers 94 are of equal design, concerning thickness and/or material composition, within the manufacturing tolerances; the same can apply for the sub-layers 93. For example, the quantum well sub-layers 94 are made of InGaN with an In content from above 0% to 20%, and the barrier layers 93 are made of GaN. A thickness of the sub-layers 93, 94 is, for example, between 0.25 nm and 25 nm.
Atop the active zone 22, there is the second region 23 which is made, for example, of p-doped InAlGaN.
A thickness of the individual layers 27, 28, 22, 23 in the layer stack 27, 28, 22, 23 and/or an overall thickness of the layer stack 27, 28, 22, 23 is, for example, at least 10 nm and at most 0.5 pm or is at least 20 nm and at most 0.3 pm.
The set-up shown in Figure 30 can apply both for the active semiconductor fins 2 as well as for the passive semiconductor fins 3 , wherein the passive semiconductor fins 3 are optionally free of the active zone 22 and/or free of the second region 23 .
Otherwise , the same as to Figures 1 to 29 may also apply to Figure 30 , and vice versa .
In Figure 31 , a method to produce the optoelectronic semiconductor devices 1 is illustrated . In a first method step S I , the base plane 20 is provided . That is , for example , the n-doped second current spreading layer 42 made of GaN is provided .
In a second method step S2 , the mask layer 51 is provided on the base plane 20 , and the at least one line-like opening 55 is formed in the mask layer 51 .
Then, in a third method step S3 the at least one active semiconductor fin 2 and optionally the at least one passive semiconductor fin 3 are grown starting from the at least one line-like opening 55 .
Finally, in a fourth method step S4 the optional passivation layer 71 as well as the electric wiring 41 , 81 , 82 are provided, and as a further option the growth substrate 24 may be replaced with a carrier 70 .
Otherwise , the same as to Figures 1 to 30 may also apply to Figure 31 , and vice versa .
The components shown in the figures follow, unless indicated otherwise , exemplarily in the speci fied sequence directly one on top of the other . Components which are not in contact in the figures are exemplarily spaced apart from one another . I f lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another . Likewise , unless indicated otherwise , the positions of the drawn components relative to one another are correctly reproduced in the figures .
The semiconductor device described here is not restricted by the description on the basis of the exemplary embodiments . Rather, the semiconductor device encompasses any new feature and also any combination of features , which includes in particular any combination of features in the patent claims , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .
This patent application claims the priority of German patent application 10 2021 122 343 . 1 , the disclosure content of which is hereby incorporated by reference .
List of Reference Signs
1 optoelectronic semiconductor device
2 active semiconductor fin
20 base plane
21 n-doped region
22 active zone
23 p-doped region
24 substrate
25 left-open corner
26 buf fer layer
27 base region
28 transition region
3 passive semiconductor fin
41 first current spreading layer
42 second current spreading layer
51 mask layer
52 cover layer
55 line-like opening
6 pixel
70 carrier
71 passivation layer
81 first electric contact structure
82 second electric contact structure
91 , 93 sub-layer ( GaN)
92 , 94 sub-layer ( InGaN)
A angle between adj acent directions of main extent
E direction of extent
H height of the active semiconductor fin
LG length along which the closed structure is opened
S . . method step
W width of the active semiconductor fin

Claims

Patent Claims
1. An optoelectronic semiconductor device (1) comprising at least one active semiconductor fin (2) which is configured to emit radiation by electroluminescence and further comprising at least one passive semiconductor fin (3) configured not to emit radiation by electroluminescence, wherein
- the at least one active semiconductor fin (2) starts from a base plane (20) ,
- seen in top view of the base plane (20) , the at least one active semiconductor fin (2) runs along at least two different directions (E) , and
- within a factor of at most 1.5, the at least one passive semiconductor fin (3) and the at least one active semiconductor fin (2) have the same height.
2. The optoelectronic semiconductor device (1) according to the preceding claim, wherein
- the at least one active semiconductor fin (2) comprises an n-doped region (21) , a p-doped region (23) and an active zone (22) located between the n-doped region (21) and the p-doped region (23) ,
- a length of the at least one active semiconductor fin (2) exceeds a height (H) of the at least one active semiconductor fin (2) above the base plane (20) by at least a factor of five, and
- seen in top view of the base plane (20) , a width (W) perpendicular to the length of the at least one active semiconductor fin (2) is at most 80% of the height (H) .
3. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one active semiconductor fin (2) is of constant height.
4. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one passive semiconductor fin (3) comprises the n-doped region (21) , too, but is free of the active zone (22) and/or the p-doped region (23) and/or is free of a first current spreading layer (41) applied on the at least one active semiconductor fin (2) .
5. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one passive semiconductor fin (3) runs along the at least two different directions (E) .
6. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one passive semiconductor fin (3) , or at least one of the passive semiconductor fins (3) , is arranged around the at least one active semiconductor fin (2) , seen in top view of the base plane (20) .
7. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one passive semiconductor fin (3) , or at least one of the passive semiconductor fins (3) , is surrounded by the at least one active semiconductor fin (2) , seen in top view of the base plane (20) .
8. The optoelectronic semiconductor device (1) according to any one of the preceding claims, comprising a plurality of the active semiconductor fins (2) as well as a plurality of the passive semiconductor fins (3) , wherein the semiconductor fins (2, 3) run along exactly three different directions (E) .
9. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein the at least one active semiconductor fin is based on the material Inj__mGamN and is configured to emit red light.
10. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein an angle (A) between directions (E) of main extent of the at least one active semiconductor fin (2) is in each case N times 60° and N E {1; 2} .
11. The optoelectronic semiconductor device (1) according to any one of claims 1 to 10, wherein an angle (A) between directions (E) of main extent of the at least one active semiconductor fin (2) is different from 60° and is also different from 120°.
12. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein, seen in top view of the base plane (20) , the at least one active semiconductor fin (2) is arranged in a trigonal or hexagonal pattern.
13. The optoelectronic semiconductor device (1) according to any one of the preceding claims, wherein, seen in top view of the base plane (20) , the at least one active semiconductor fin (2) is a completely closed structure .
14. The optoelectronic semiconductor device (1) according to any one of claims 1 to 12, wherein, seen in top view of the base plane (20) , the at least one active semiconductor fin (2) is a closed structure with left-open corners (25) , the left-open corners (25) have an extent of at most 0.3 pm.
15. The optoelectronic semiconductor device (1) according to any one of the preceding claims, comprising a plurality of pixels (6) , wherein each one of the pixels (6) comprises its own at least one active semiconductor fin (2) .
16. The optoelectronic semiconductor device (1) according to the preceding claims wherein, seen in top view of the base plane (20) and concerning the at least one active semiconductor fin (2) , the pixels (6) are designed in a point-symmetric manner and/or in a mirror-symmetric manner with at least two axes of mirror symmetry .
17. A method to produce the optoelectronic semiconductor device (1) according to any one of the preceding claims, comprising the steps of:
A) providing the base plane (20) ,
B) providing at least one line-like opening (55) in a mask layer (51) at the base plane (20) , and
C) growing the at least one active semiconductor fin (2) starting from the at least one line-like opening (55) .
PCT/EP2022/072576 2021-08-30 2022-08-11 Optoelectronic semiconductor device and production method WO2023030857A1 (en)

Applications Claiming Priority (2)

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DE102021122343 2021-08-30
DE102021122343.1 2021-08-30

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190058002A1 (en) * 2017-08-18 2019-02-21 Globalfoundries Inc. Finfets for light emitting diode displays
US20200028029A1 (en) * 2017-03-20 2020-01-23 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip and Method of Manufacturing the Same
FR3087581A1 (en) * 2018-10-22 2020-04-24 Aledia OPTOELECTRONIC DEVICE, RELATED DISPLAY SCREEN AND METHOD FOR MANUFACTURING SUCH AN OPTOELECTRONIC DEVICE

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200028029A1 (en) * 2017-03-20 2020-01-23 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip and Method of Manufacturing the Same
US20190058002A1 (en) * 2017-08-18 2019-02-21 Globalfoundries Inc. Finfets for light emitting diode displays
FR3087581A1 (en) * 2018-10-22 2020-04-24 Aledia OPTOELECTRONIC DEVICE, RELATED DISPLAY SCREEN AND METHOD FOR MANUFACTURING SUCH AN OPTOELECTRONIC DEVICE
US20210391500A1 (en) * 2018-10-22 2021-12-16 Aledia Optoelectronic device, associated display screen and method for fabricating such an optoelectronic device

Non-Patent Citations (1)

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Title
J. WINNERL ET AL.: "Selectively grown GaN nanowalls and nanogrids for photocatalysis: growth and optical properties", NANOSCALE, vol. 11, 2019, pages 4578

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