WO2023030530A1 - 功率放大器和电路板 - Google Patents

功率放大器和电路板 Download PDF

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Publication number
WO2023030530A1
WO2023030530A1 PCT/CN2022/117175 CN2022117175W WO2023030530A1 WO 2023030530 A1 WO2023030530 A1 WO 2023030530A1 CN 2022117175 W CN2022117175 W CN 2022117175W WO 2023030530 A1 WO2023030530 A1 WO 2023030530A1
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Prior art keywords
power
power amplifier
input
divider
output
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PCT/CN2022/117175
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English (en)
French (fr)
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丁冲
秦天银
魏伟伟
张晓毅
余敏德
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中兴通讯股份有限公司
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Publication of WO2023030530A1 publication Critical patent/WO2023030530A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This disclosure relates to the field of amplifier circuits.
  • the power amplifier module in the base station generally adopts the Doherty power amplifier architecture mode.
  • the Doherty combining method is generally used, but the introduction of the Doherty combining structure will limit the working bandwidth to a certain extent.
  • the main purpose of the embodiments of the present disclosure is to provide a power amplifier and a circuit board. Therefore, on the basis of ensuring a certain bandwidth, the power of the broadband is effectively improved, and a wider application of the broadband is realized.
  • an embodiment of the present disclosure provides a power amplifier, which includes a first transmission path, the first transmission path includes and controls a power amplifier and a first power divider, and the output end of the control power amplifier is connected to the first power amplifier.
  • the input ends of the second power divider are respectively correspondingly connected to the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively connected to the first input end and the second input end of the third power divider;
  • N second power divider The third input terminals of the N third power dividers in the transmission path are respectively connected to the N output terminals of the first power divider; wherein, N is an integer greater than or equal to 1 and a combiner with N input terminals, The N input terminals of the combiner are respectively connected to the output terminals of the N third power divider
  • an embodiment of the present disclosure further provides a power amplifier, which includes a first transmission path, the first transmission path includes and controls the power amplifier and the first power divider, and the output terminal of the control power amplifier is connected to the first power amplifier.
  • input end of the splitter N second transmission paths, each second transmission path includes two balanced power amplifiers, a second power splitter and a third power splitter; the input ends of the two balanced power amplifiers are connected to the second power splitter
  • the two output ends of the divider are respectively connected correspondingly, and the output ends of the two balanced power amplifiers are connected with the first input end and the second input end of the third power divider respectively; the third power in the N second transmission paths
  • the N third input terminals of the divider are respectively connected to the N output terminals of the first power divider; wherein, N is an integer greater than or equal to 1 and has a combiner with N input terminals, and the N input terminals of the combiner
  • the output terminals of the N third power dividers in the N second transmission paths are respectively connected
  • an embodiment of the present disclosure further provides a power amplifier, which includes a first transmission path, the first transmission path includes and controls the power amplifier and the first power divider, and the output terminal of the control power amplifier is connected to the first power amplifier.
  • input end of the splitter N second transmission paths, each second transmission path includes two balanced power amplifiers, a second power splitter and a third power splitter; the input ends of the two balanced power amplifiers are connected to the second power splitter
  • the two output ends of the divider are respectively connected correspondingly, and the output ends of the two balanced power amplifiers are respectively connected with the first input end and the second input end of the third power divider;
  • the third input terminal of the three-power divider is respectively connected to the N output terminals of the first power divider; wherein, N is an integer greater than or equal to 1 and has a combiner with N input terminals, and the N inputs of the combiner
  • the output terminals of the N third power dividers in the N second transmission paths are respectively connected correspondingly; wherein, the power
  • an embodiment of the present disclosure further provides a circuit board, which includes at least one of the above power amplifiers.
  • FIG. 1 is an architecture diagram of a power amplifier according to an embodiment of the present disclosure
  • FIG. 2 is a current diagram of a CPA output port and a BPA output port in a power amplifier according to an embodiment of the present disclosure
  • FIG. 3 is a voltage diagram of a CPA output port and a BPA output port in a power amplifier according to an embodiment of the present disclosure
  • FIG. 4 is a CPA and BPA impedance pulling diagram in a power amplifier according to an embodiment of the present disclosure
  • FIG. 5 is a CPA and BPA power diagram in a power amplifier according to an embodiment of the present disclosure
  • FIG. 6 is a graph of CPA and BPA efficiency in a power amplifier according to an embodiment of the present disclosure
  • FIG. 7 is an architecture diagram of a dual-input power amplifier according to an embodiment of the present disclosure.
  • FIG. 8 is an architectural diagram of a three-input power amplifier according to an embodiment of the disclosure.
  • the present disclosure relates to a power amplifier, which is mainly used in a high-power broadband RRU base station.
  • the power amplifier includes: a first transmission path, the first transmission path includes a control power amplifier and a first power divider, the output end of the control power amplifier is connected to the input end of the first power divider; N second transmission paths, each A second transmission path includes a balanced power amplifier, a second power divider, and a third power divider; the input ends of the two balanced power amplifiers are respectively connected to the two output ends of the second power divider, and the two balanced power amplifiers
  • the output end of the third power divider is connected to the first input end and the second input end of the third power divider respectively;
  • the output terminals are respectively connected correspondingly; wherein, N is an integer greater than or equal to 1; a combiner with N input terminals, the N input terminals of the combiner and the output of the third power divider in the N second transmission paths The terminals are respectively connected correspondingly; the fourth power divider with N output
  • FIG. 1 is a structural diagram of a power amplifier according to an embodiment of the present disclosure.
  • the power amplifier shown in FIG. 1 has two second transmission paths (ie, N is 2).
  • the first transmission path is the branch where the control power amplifier (control power amplifier, CPA) is located, the first transmission path can be referred to as the control path, and the control power amplifier can be a class AB power amplifier;
  • the transmission path is a branch where a balanced power amplifier (BPA) is located, the second transmission path may be called a balanced path, and the balanced power amplifier may be a class-C power amplifier.
  • BPA balanced power amplifier
  • the power divider is the power divider, which can be a quadrature hybrid bridge coupler (uadrature Hybrid Bridge Coupler, QHBC) or other forms of power divider.
  • the first power divider can be QHBC1, and the second power divider can be QHBC2 (QHBC2-1 and QHBC2-2), the third power divider can be QHBC3 (QHBC3-1 and QHBC3-2), the fourth power divider can be QHBC4, the fifth power divider can be QHBC5, combiner It may be QHBC6, wherein, the input terminal of QHBC5 is the input terminal of the power amplifier, and the output terminal of the combiner QHBC6 is the output terminal of the power amplifier.
  • the power amplifier includes a set of control circuits and two groups of balance circuits.
  • the signal is input to QHBC5 through the RF input port Pin.
  • QHBC5 divides the signal into two circuits, one feeds into the control circuit and the other feeds into the balance circuit.
  • the control circuit includes: CPA, QHBC1, a limiter (Ampli-limiter), a phase regulator (which can be a phase compensation line (Offset line)) and load resistors Load, where the Offset line is used to modulate the input signal Phase, Ampli-limiter is used to modulate the amplitude of the input signal.
  • the input terminal of CPA is connected to the Ampli-limiter, and the output terminal of CPA is connected to the input terminal of QHBC1.
  • the signal is output from the first output terminal of QHBC5, modulated by phase and amplitude, amplified by CPA working in class AB state, and output by QHBC1.
  • the first group of balanced circuits includes 2 BPAs, the second power divider QHBC2-1, the third power divider QHBC3-1 and several load circuits Load.
  • the signal is output from the second output terminal of QHBC5 to QHBC4, and QHBC4 divides the signal into two channels, one of which is input to QHBC2-1, the signal is distributed by QHBC2-1 and enters BPA, and then output by QHBC3-1; the other is input to QHBC2-2, After the signal is distributed by QHBC2-2, it enters another group of BPA, and then it is output by QHBC3-2.
  • the first output terminal of QHBC1 of the control circuit is connected with the third input terminal of QHBC3-2 of the second group of balanced circuits, and the second output terminal of QHBC1 is connected with the third input terminal of the first group of balanced circuits QHBC3-1 Terminal connection, so that the control circuit CPA can control the BPA in the two groups of balanced circuits, and finally output from the combined circuit QHBC6.
  • a phase adjuster for example, a phase compensation line (Offset line)
  • the limiter Ampli-limiter is connected between the first output terminal of the fifth power divider QHBC5 and the input terminal of the control power amplifier CPA, that is to say, the phase regulator Offset line and/or the limiter (Ampli-limiter) can be arranged in any combination ( Figure 1 only shows the way of series connection) In the control circuit, it is located between the output terminal of QHBC5 and the input terminal of CPA.
  • the phase regulator Offset line is used to modulate the phase of the signal
  • the limiter Ampli-limiter is used to control the signal amplitude. .
  • the second output terminal of the fifth power divider QHBC5 may be connected to the input terminal of the fourth power divider QHBC4 through a phase regulator (not shown). That is to say, the phase regulator can also be placed at the second output terminal of QHBC5 and the input terminal of QHBC4 to adjust the phase to achieve the same effect.
  • each output terminal of the fourth power divider QHBC4 can be connected to the second power divider QHBC2-1 or QHBC2-2 in the corresponding second transmission path through a phase regulator (not shown). input terminal. That is, one phase regulator (not shown) can be placed between the output terminal of QHBC4 and the input terminal of QHBC2-1, and another phase regulator (not shown) can be placed between the other output terminal of QHBC4 and the input terminal of QHBC2-1. Between the input terminals of QHBC2-2, adjust the phases of the two groups of BPA respectively to achieve the same effect.
  • the phase regulator can also be placed between the four output terminals of the second power divider QHBC2-1 and QHBC2-2 and the input terminal of the corresponding BPA, that is, a group of phase regulators can be placed between Between the two output terminals of QHBC2-1 and the corresponding BPA, another group of phase regulators can be placed between the two output terminals of QHBC2-2 and the corresponding BPA to adjust the phases of the four BPAs to achieve the same effect.
  • the power divider in the control circuit and the balance circuit decouples the two power amplifiers well, so that the impedance of the control power amplifier in the control circuit is basically not pulled by the balance power amplifier in the balance circuit, thus No matter how the input signal changes, the control power amplifier CPA can always match well with the impedance matching network in the circuit, avoiding the limitation of the working bandwidth due to the poor matching between the control power amplifier CPA and the impedance matching network, and one control circuit can control multiple In the balanced circuit, the control power amplifier CPA in the control circuit forms an impedance pull to the balanced power amplifier BPA in the balanced circuit, so as to meet the high power demand.
  • the signal is divided into two paths by the QHBC5 through the RF input port Pin.
  • the control circuit starts to work, the voltage and current of the CPA are in the AB state, the signal is amplified after passing through the CPA working in the AB state, and then output through the QHBC1.
  • the voltage and current of the two groups of balanced power amplifiers BPA are in the class C state, the impedance of the two groups of balanced power amplifiers BPA is infinite, and the four BPAs are in the off state, so the two groups of balanced power amplifiers are equivalent to no work.
  • the control circuit and the two sets of balance circuits start working together.
  • the limiter Ampli-limiter starts to work to limit the amplitude of the signal input to the CPA to ensure that the signal input to the control circuit CPA is lower than a certain preset value to avoid
  • the CPA works in an oversaturated state, improving the reliability and stability of the CPA.
  • two groups of balanced power amplifiers BPA start to work, that is, 4 BPAs are turned on.
  • the signal of BPA is divided into two paths by QHBC4, and then fed into two groups of balanced power amplifiers BPA respectively, and then output to two groups of power splitters QHBC3-1 and QHBC3-2 through BPA.
  • the two output terminals of QHBC1 of the control circuit respectively act on the input terminals of the two groups of balanced circuits QHBC3-1 and QHBC3-2.
  • the ratio of the output current of the CPA and BPA power amplifier tubes can be calculated to be 2:1.06, so as to balance the ports of the power splitter connected to any group of BPA output terminals on the road Perform ideal current source model analysis.
  • the power divider connected to the output port is QHBC3-1, and the current diagram shown in Figure 2 is obtained.
  • the horizontal axis represents the voltage and the value on the horizontal axis is after the voltage value is normalized.
  • the vertical axis represents the current.
  • the control circuit changes the length of the offset line, thereby changing the slope of the phase of the S parameter in the working frequency band, and realizes the load pulling of the four BPAs. .
  • the impedance value of CPA is constant at 50 ohms, and the impedance of CPA forms a traction on the impedance of BPA, and the impedance of BPA gradually decreases with the increase of normalized voltage.
  • the signal is acted on by the power amplifiers in the control circuit and the balance circuit, it is output in the combined circuit.
  • the power diagram of CPA and BPA is shown in Figure 5.
  • the output power continues to increase.
  • the efficiency diagram of CPA and BPA is shown in Figure 6.
  • the control power amplifier CAP in the control path forms impedance traction to the balanced power amplifier BPA in the balance path, so as to meet the high power requirement on the basis of ensuring the bandwidth.
  • the present disclosure also relates to a multi-input power amplifier.
  • the implementation details of the multi-input power amplifier are described in detail below by taking a dual-input power amplifier as an example. The following contents are only implementation details provided for easy understanding, and are not necessary for implementing this solution.
  • the dual-input power amplifier includes: a first transmission path, the first transmission path includes a control power amplifier and a first power divider, the output end of the control power amplifier is connected to the input end of the first power divider; N second transmission paths, Each second transmission path includes a balanced power amplifier, a second power divider, and a third power divider; the input ends of the two balanced power amplifiers are respectively connected to the two output ends of the second power divider, and the two balanced power The output terminal of the amplifier is respectively connected to the first input terminal and the second input terminal of the third power divider; the third input terminal of the third power divider in the N second transmission paths is connected to the N of the first power divider.
  • the output terminals are respectively connected correspondingly; wherein, N is an integer greater than or equal to 1; a combiner with N input terminals, the N input terminals of the combiner and the third power divider in the N second transmission paths The output terminals are respectively connected correspondingly; the fourth power divider has N output terminals, and the N output terminals of the fourth power divider are respectively connected to the input terminals of the second power divider in the N second transmission paths; wherein, The power amplifier has two input ends, the input end of the control power amplifier is one of the two input ends of the power amplifier, and the input end of the fourth power divider is the other input end of the two input ends of the power amplifier ; The output end of the combiner is the output end of the power amplifier.
  • FIG. 7 is a structural diagram of a dual-input power amplifier according to an embodiment of the present disclosure.
  • the dual-input power amplifier shown in FIG. 7 has two second transmission paths (ie, N is 2).
  • the dual-input power amplifier includes a control circuit and two sets of balance circuits, and the control power amplifier CPA in the control circuit controls the balance power amplifier BPA in the balance circuit.
  • the architecture similar to that of the power amplifier described with reference to FIG. 1 will not be repeated here.
  • the dual-input power amplifier shown in Figure 7 has two input terminals, wherein the first part of the signal is fed into the control circuit through a radio frequency input port Pin1, and passes through the CPA working in the AB state.
  • QHBC4 divides the signal into two channels, one channel acts on QHBC2-1, BPA, QHBC3-1, and the other channel acts on QHBC2- 2.
  • the control circuit in the dual-input power amplifier removes the phase regulator and the limiter, and the functions of these two modules can be realized by performing amplitude modulation and phase modulation in the digital domain, which can control the power amplifier more precisely.
  • a power divider at the input end is omitted, that is, QHBC5 is omitted, which simplifies the structure and reduces the circuit cost.
  • the gain of the power amplifier is improved, thereby further improving the performance of the power amplifier.
  • the three-input power amplifier specifically includes: a first transmission path, the first transmission path includes a control power amplifier and a first power divider, the output end of the control power amplifier is connected to the input end of the first power divider; N second transmission Each second transmission path includes two balanced power amplifiers, a second power divider, and a third power divider; the input ends of the two balanced power amplifiers are respectively connected to the two output ends of the second power divider, The output terminals of the two balanced power amplifiers are respectively connected to the first input terminal and the second input terminal of the third power divider; the third input terminal of the third power divider in the N second transmission paths is connected to the first power divider.
  • the N output terminals of the divider are respectively connected correspondingly; wherein, N is an integer greater than or equal to 1; a combiner with N input terminals, the N input terminals of the combiner are connected to the third in the N second transmission paths
  • the output terminals of the power divider are respectively connected correspondingly; wherein, the power amplifier has N+1 input terminals, the input terminal of the control power amplifier is one of the N+1 input terminals of the power amplifier, and the N second power dividers
  • the input terminals of the combiner are respectively the remaining N input terminals among the N+1 input terminals of the power amplifier; the output terminals of the combiner are the output terminals of the power amplifier.
  • FIG. 8 is a structural diagram of a three-input power amplifier according to an embodiment of the present disclosure.
  • the three-input power amplifier shown in FIG. 8 has two second transmission paths (ie, N is 2).
  • the power amplifier includes a control circuit and two sets of balance circuits, and the control power amplifier CPA in the control circuit controls the balance circuit and balances the power amplifier BPA.
  • the architecture similar to the architecture of the power amplifier described with reference to FIG. 1 will not be described in detail.
  • the three-input power amplifier shown in Figure 8 has three input terminals, in which the signal is fed into the control circuit through the first RF input port Pin1, amplified after passing through the CPA working in the AB state, and output through QHBC1; the signal is passed through The second RF input port Pin2 feeds into a group of balanced circuits, acting on QHBC2-1, BPA, QHBC3-1, and the signal is fed into another group of balanced circuits through the third RF input port Pin3, acting on QHBC2-2, BPA, QHBC2-2, BPA, QHBC3-1 QHBC3-2.
  • the signals of the control circuit and the balance circuit are finally output from the combining circuit QHBC6.
  • Three-input power amplifier simplifies architecture layout and reduces circuit cost. At the same time, two sets of power dividers are further omitted, that is, QHBC4 and QHBC5 are omitted. Compared with single-input power amplifiers and dual-input power amplifiers, the three-input power amplifier further improves the gain of the power amplifier and improves the performance of the power amplifier.
  • the present disclosure also relates to a circuit board, including a power amplifier; the power amplifier includes at least one of the above-mentioned single-input power amplifier, dual-input power amplifier and triple-input power amplifier.

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Abstract

公开了一种功率放大器和电路板。该功率放大器包括：第一传输路径，其包括控制功率放大器和第一功分器，控制功率放大器的输出端连接第一功分器的输入端；N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器，其中，N个第二传输路径中的N个第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；功率放大器还包括具有N个输入端的合路器、具有N个输出端的第四功分器以及第五功分器，其中，第五功分器的输入端为功率放大器的输入端，合路器的输出端为功率放大器的输出端。

Description

功率放大器和电路板
相关申请的交叉引用
该专利申请要求于2021年9月6日在中国国家知识产权局提交的中国专利申请202111040170.9的优先权，该中国专利申请的公开以引用方式全文并入本文中。
技术领域
本公开涉及放大器电路领域。
背景技术
随着5G商用持续推进，加上3G和4G通信的各个频带，各通信运营商可用无线通信频带越来越多。为满足单个小区覆盖需求，单一站点的基站数量越来越多，运营成本持续增加。为降低运营成本，简化部署过程，降低部署难度，各运营商积极推动无线基站的共建共享，因此，基站中的宽带功放架构受到越来越多的重视。为保证基站的覆盖范围，一般需要保证每1MHz通信频谱具有2W左右的发射功率。因此，宽带需求同时伴随着大功率需求。
目前，基站中的功放模块一般采用的是Doherty功放架构模式，为了满足高发射功率需求，一般还会采用Doherty合路的方式，但引入Doherty的合路结构会一定程度上限制工作带宽。
发明内容
本公开实施例的主要目的在于提出一种功率放大器和电路板。从而在保证带宽一定的基础上使得宽带功率有效提升，实现宽带更为广泛的应用。
为实现上述目的，本公开实施例提供了一种功率放大器，其包括第一传输路径，第一传输路径包括和控制功率放大器和第一功分器， 控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括平衡功率放大器、第二功分器及第三功分器；在每个第二传输路径中，两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的N个第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的N个第三功分器的输出端分别对应连接；具有N个输出端的第四功分器，第四功分器的N个输出端与N个第二传输路径中的N个第二功分器的输入端分别对应连接；第五功分器，第五功分器的第一输出端与控制功率放大器的输入端连接，第五功分器的第二输出端与第四功分器的输入端连接；其中，功率放大器具有一个输入端，第五功分器的输入端为功率放大器的输入端；合路器的输出端为功率放大器的输出端。
为实现上述目的，本公开实施例还提供一种功率放大器，其包括第一传输路径，第一传输路径包括和控制功率放大器和第一功分器，控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的第三功分器的N个第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的N个第三功分器的输出端分别对应连接；具有N个输出端的第四功分器，第四功分器的N个输出端与N个第二传输路径中的第二功分器的输入端分别对应连接；其中，功率放大器具有两个输入端，控制功率放大器的输入端为功率放大器的两个输入端中的一个输入端，第四功分器的输入端为功率放大器的两个输入端中的另一个输入端；所合路器的输出端为功率放大器的输出端。
为实现上述目的，本公开实施例还提供一种功率放大器，其包 括第一传输路径，第一传输路径包括和控制功率放大器和第一功分器，控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的N个第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的N个第三功分器的输出端分别对应连接；其中，功率放大器具有N+1个输入端，控制功率放大器的输入端为功率放大器的N+1个输入端中的一个输入端，N个第二传输路径中的N个第二功分器的输入端分别为功率放大器的N+1个输入端中的其余N个输入端；合路器的输出端为功率放大器的输出端。
为实现上述目的，本公开实施例还提供一种电路板，其包括如上所述的功率放大器中的至少一个。
附图说明
图1是根据本公开的实施例的功率放大器的架构图；
图2是根据本公开的实施例的功率放大器中的CPA输出端口和BPA输出端口电流图；
图3是根据本公开的实施例的功率放大器中的CPA输出端口和BPA输出端口电压图；
图4是根据本公开的实施例的功率放大器中的CPA和BPA阻抗牵引图；
图5是根据本公开的实施例的功率放大器中的CPA和BPA功率图；
图6是根据本公开的实施例的功率放大器中的CPA和BPA效率图；
图7是根据本公开的实施例的双输入功率放大器的架构图；
图8是根据本公开的实施例的三输入功率放大器的架构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
本公开涉及一种功率放大器，主要应用于在大功率宽带RRU基站中。该功率放大器包括：第一传输路径，第一传输路径包括控制功率放大器和第一功分器，控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括平衡功率放大器、第二功分器及第三功分器；两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数；具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的第三功分器的输出端分别对应连接；具有N个输出端的第四功分器，第四功分器的N个输出端与N个第二传输路径中的第二功分器的输入端分别对应连接；第五功分器，第五功分器的第一输出端与控制功率放大器的输入端连接，第五功分器的第二输出端与第四功分器的输入端连接；其中，功率放大器具有一个输入端，第五功分器的输入端为功率放大器的输入端；合路器的输出端为功率放大器的输出端。
图1根据本公开的实施例的功率放大器的架构图，图1所示的功率放大器具有两个第二传输路径(即N为2)。如图1所示，第一传输路径为控制功率放大器(control power amplifier，CPA)所在的支路，第一传输路径可被称之为控制路，控制功率放大器可以是 AB类功率放大器；第二传输路径为平衡功率放大器(balanced power amplifier，BPA)所在的支路，第二传输路径可被称之为平衡路，平衡功率放大器可以是C类功率放大器。功分器即功率分配器，可以是正交混合电桥合路器(uadrature Hybrid Bridge Coupler，QHBC)或其他形式的功率分配器，第一功分器可以是QHBC1，第二功分器可以是QHBC2(QHBC2-1和QHBC2-2)，第三功分器可以是QHBC3(QHBC3-1和QHBC3-2)，第四功分器可以是QHBC4，第五功分器可以是QHBC5，合路器可以是QHBC6，其中，QHBC5输入端为功率放大器的输入端，合路器QHBC6的输出端为功率放大器的输出端。
功率放大器包括一组控制路和两组平衡路，信号经射频输入端口Pin输入到QHBC5，QHBC5将信号分成两路，一路馈入控制路，另一路馈入平衡路。
控制路包括：CPA、QHBC1、一个限幅器(Ampli-limiter),一个相位调节器(其可以是相位补偿线(Offset line))和负载电阻Load若干，其中，Offset line用来调制输入信号的相位，Ampli-limiter用来调制输入信号的幅度。CPA的输入端和Ampli-limiter连接，CPA的输出端连接QHBC1的输入端。信号从QHBC5第一输出端输出，由相位、幅度调制后，经过工作于AB类状态的CPA后放大并经QHBC1输出。
平衡路中第一组平衡路包括2个BPA、第二功分器QHBC2-1、第三功分器QHBC3-1和负载电路Load若干，第二组平衡路具体包括2个BPA、第二功分器QHBC2-2、第三功分器QHBC3-2和负载电阻Load若干。信号从QHBC5第二输出端输出给QHBC4，QHBC4将信号分成两路，一路输入到QHBC2-1，信号经QHBC2-1分配后进入BPA，再由QHBC3-1输出；另一路输入到QHBC2-2，信号经QHBC2-2分配后进入另一组BPA，再由QHBC3-2输出。
需要注意的是，控制路的QHBC1的第一输出端和第二组平衡路的QHBC3-2的第三输入端连接，QHBC1的第二输出端和第一组平衡路QHBC3-1的第三输入端连接，从而使得控制路CPA可以对两组平衡路中的BPA进行控制，最终从合路QHBC6输出。
根据本公开的实施例，相位调节器(例如，相位补偿线(Offset line))连接在第五功分器QHBC5的第一输出端和控制功率放大器CPA的输入端；限幅器Ampli-limiter连接在第五功分器QHBC5的第一输出端和控制功率放大器CPA的输入端之间，也就是说，相位调节器Offset line和/或限幅器(Ampli-limiter)可以以任意排列组合方式(图1仅示出了串联连接的方式)在控制路中位于QHBC5的输出端和CPA输入端之间，相位调节器Offset line用来调制信号的相位，限幅器Ampli-limiter用来控制信号幅度。
根据本公开的实施例，第五功分器QHBC5的第二输出端可通过相位调节器(未示出)连接于第四功分器QHBC4的输入端。也就是说，相位调节器还可以置于QHBC5的第二输出端与QHBC4的输入端调节相位，实现相同的效果。
根据本公开的实施例，第四功分器QHBC4的每个输出端可通过相位调节器(未示出)连接于对应的第二传输路径中的第二功分器QHBC2-1或QHBC2-2的输入端。也就是说，一个相位调节器(未示出)可放置在QHBC4的输出端和QHBC2-1的输入端之间，另一个相位调节器(未示出)可放置在QHBC4的另一输出端和QHBC2-2的输入端之间，分别调节两组BPA的相位，实现相同的效果。
根据本公开的实施例，相位调节器还可以置于第二功分器QHBC2-1和QHBC2-2的四个输出端与对应的BPA的输入端之间，即一组相位调节器可置于QHBC2-1的两个输出端和对应的BPA之间，另一组相位调节器可置于QHBC2-2的两个输出端和对应的BPA之间，调节四个BPA的相位，实现相同效果。
本公开提出的功率放大器，控制路和平衡路中的功分器将两路功率放大器较好地解耦，使得控制路中控制功率放大器的阻抗基本不受平衡路中平衡功率放大器的牵引，从而不管输入信号如何变化，控制功率放大器CPA始终能跟电路中的阻抗匹配网络良好匹配，避免由于控制功率放大器CPA与阻抗匹配网络的不良匹配导致对工作带宽造成限制，并且，一路控制路能够控制多路平衡路，控制路中的控制功率放大器CPA对平衡路中的平衡功率放大器BPA形成阻抗牵引，从 而能够满足高功率需求。
上述功率放大器在具体实施中，如图1所示，信号经射频输入端口Pin由QHBC5将信号分成两路。当输入为小信号时，控制路开始工作，CPA的电压电流处于AB类状态下，信号经过工作于AB类状态的CPA后放大并经QHBC1后输出。同时，在小信号情况下，两组平衡功率放大器BPA电压电流处于C类状态，两组平衡功率放大器BPA的阻抗无穷大，四个BPA处于关断状态，因此两组平衡路相当于没有工作。
当输入信号持续增大到功率状态，控制路和两组平衡路共同开始工作。控制路CPA随着输入功率的进一步增大，电流达到最大值，CPA进入饱和状态，工作效率降低。为避免CPA输入功率的进一步增大而进入过饱和状态，限幅器Ampli-limiter开始工作，对输入至CPA的信号进行幅度限制，保证输入到控制路CPA的信号低于一定预设值，避免CPA工作在过饱和状态，提升CPA的可靠性和稳定性。
在大功率状态下两组平衡功率放大器BPA开始工作，即4个BPA开启。BPA的信号经过QHBC4分成两路后分别馈入两组平衡功率放大器BPA中，经BPA输出到两组功分器QHBC3-1和QHBC3-2。控制路的QHBC1的两个输出端分别作用于两组平衡路QHBC3-1和QHBC3-2的输入端，通过改变控制路offset line的长度，从而改变工作频段内的S参数的相位的斜率，实现对两组平衡路中4个BPA的负载牵引。
例如，若实现一个8dB回退的宽带大功率功放，计算可得CPA和BPA功放管需要输出的电流的比值为2:1.06，以平衡路上任意一组BPA输出端连接的功分器的各个端口进行理想电流源模型分析，比如说输出端口所连接的功分器为QHBC3-1，得到如图2所示的电流图，横轴表示电压且横轴上的数值是将电压值归一化后的结果，纵轴表示电流。如图2中，归一化电压在0.4之前，CPA电流逐步增大，控制路开始工作；BPA电流为0，阻抗无穷大，四个BPA处于关断状态。归一化电压在0.4，CPA电流到最大值0.6，4个BPA开启，两组平衡功率放大器BPA开始工作。功率放大器中的CPA输出端口和BPA输出端口电压图如图3所示，归一化电压达在0.4之前，BPA和CPA电压 逐步增大，在归一化电压达到0.4后，CPA电压稳定不变，BPA电压逐步增大。CPA和BPA的阻抗牵引图如图4所示，在CPA电流到0.6后，控制路通过改变offset line的长度，从而改变工作频段内的S参数的相位的斜率，实现对4个BPA的负载牵引。在8dB回退的宽带大功率功放下，CPA的阻抗值恒定为50欧，CPA阻抗对BPA阻抗形成牵引，BPA的阻抗随归一化电压的增大而逐步降低。信号经控制路和平衡路中各功率放大器作用后在合路输出，CPA和BPA的功率图如图5所示，在CPA对BPA形成阻抗牵引后，输出功率持续提升。CPA和BPA效率图如图6所示，在归一化电压达到0.4时候，效率最高达到近80％，CPA和BPA同时工作，CPA对BPA形成阻抗牵引，使得效率回升再一次达到近80％。本公开的功率放大器在大功率状态下，控制路中控制功率放大器CAP对平衡路中平衡功率放大器BPA形成阻抗牵引，保证带宽基础上满足高功率需求。
本公开还涉及一种多输入功率放大器。下面以双输入功率放大器为例，对多输入功率放大器的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。双输入功率放大器包括：第一传输路径，第一传输路径包括控制功率放大器和第一功分器，控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括平衡功率放大器、第二功分器及第三功分器；两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数；具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的第三功分器的输出端分别对应连接；具有N个输出端的第四功分器，第四功分器的N个输出端与N个第二传输路径中的第二功分器的输入端分别对应连接；其中，功率放大器具有两个输入端，控制功率放大器的输入端为功率放大器的两个输入端中的一个输入端，第四功分器的输入端为功率放大器的两个输入端中的另一个输入端；合路器的输出端为功率放大器的输出端。
图7是根据本公开的实施例的双输入功率放大器的架构图，图7示出的双输入功率放大器具有两个第二传输路径(即N为2)。参考图7，双输入功率放大器包括控制路和两组平衡路，控制路中的控制功率放大器CPA控制平衡路中的平衡功率放大器BPA。为了避免重复，与参照图1描述的功率放大器的架构类似的架构不在赘述。区别于图1所示的功率放大器，图7所示的双输入功率放大器具有两个输入端，其中，第一部分信号经一个射频输入端口Pin1馈入到控制路，经过工作于AB类状态的CPA后放大并经QHBC1输出；第二部分信号经另一个射频输入端口Pin2馈入到平衡路，QHBC4将信号分成两路，一路作用于QHBC2-1、BPA、QHBC3-1，另一路作用于QHBC2-2、BPA、QHBC3-2。
双输入功率放大器中的控制路去除了相位调节器和限幅器，这两个模块的功能可以通过在数字域进行调幅和调相实现，可以进行更为精确的控制功率放大器。采用双输入后，省略了输入端的一个功分器即省略了QHBC5，简化架构，降低电路成本，同时，相对于单输入功率放大器，提升了功率放大器的增益，从而进一步提升功率放大器的性能。
下面以三输入功率放大器为例，对多输入功率放大器的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。三输入功率放大器，具体包括：第一传输路径，第一传输路径包括控制功率放大器和第一功分器，控制功率放大器的输出端连接于第一功分器的输入端；N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；两个平衡功率放大器的输入端与第二功分器的两个输出端分别对应连接，两个平衡功率放大器的输出端与第三功分器的第一输入端、第二输入端分别对应连接；N个第二传输路径中的第三功分器的第三输入端与第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数；具有N个输入端的合路器，合路器的N个输入端与N个第二传输路径中的第三功分器的输出端分别对应连接；其中，功率放大器具有N+1个输入端，控制功率放大器的输入端为功率放大器的N+1个输入端中 的一个输入端，N个第二功分器的输入端分别为功率放大器的N+1个输入端中的其余N个输入端；合路器的输出端为功率放大器的输出端。
图8是根据本公开的实施例的三输入功率放大器的架构图，图8示出的三输入功率放大器具有两个第二传输路径(即N为2)。参考图8，功率放大器包括控制路和两组平衡路，控制路中的控制功率放大器CPA控制平衡路平衡功率放大器BPA。为了避免重复，与参照图1描述的功率放大器的架构类似的架构不在赘述。如图8所示的三输入功率放大器具有三个输入端，其中，信号经第一个射频输入端口Pin1馈入到控制路，经过工作于AB类状态的CPA后放大并经QHBC1输出；信号经第二个射频输入端口Pin2馈入一组平衡路，作用于QHBC2-1、BPA、QHBC3-1，信号经第三个射频输入端口Pin3馈入另一组平衡路作用于QHBC2-2、BPA、QHBC3-2。控制路和平衡路信号最终从合路QHBC6输出。
三输入功率放大器，简化架构布局，降低电路成本。同时进一步省略两组功分器，即省略了QHBC4和QHBC5，相比于单输入功率放大器和双输入功率放大器，三输入功率放大器更进一步提升了功率放大器的增益，提升了功率放大器的性能。
本公开还涉及一种电路板，包括功率放大器；功率放大器包括如上所述的单输入功率放大器，双输入功率放大器以及三输入功率放大器中的至少一个。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 一种功率放大器，包括：
    第一传输路径，所述第一传输路径包括控制功率放大器和第一功分器，所述控制功率放大器的输出端连接于所述第一功分器的输入端；
    N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；在每个第二传输路径中，所述两个平衡功率放大器的输入端与所述第二功分器的两个输出端分别对应连接，所述两个平衡功率放大器的输出端与所述第三功分器的第一输入端、第二输入端分别对应连接；所述N个所述第二传输路径中的N个第三功分器的第三输入端与所述第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数；
    具有N个输入端的合路器，所述合路器的N个输入端与所述N个第二传输路径中的所述N个第三功分器的输出端分别对应连接；
    具有N个输出端的第四功分器，所述第四功分器的N个输出端与所述N个第二传输路径中的N个第二功分器的输入端分别对应连接；
    第五功分器，所述第五功分器的第一输出端与所述控制功率放大器的输入端连接，所述第五功分器的第二输出端与所述第四功分器的输入端连接；
    其中，所述功率放大器具有一个输入端，所述第五功分器的输入端为所述功率放大器的输入端，所述合路器的输出端为所述功率放大器的输出端。
  2. 根据权利要求1所述的功率放大器，其中，所述第一传输路径还包括：相位调节器，所述相位调节器连接在所述第五功分器的第一输出端和所述控制功率放大器的输入端之间。
  3. 根据权利要求1所述的功率放大器，其中，所述第一传输路径还包括：限幅器，所述限幅器连接在所述第五功分器的第一输出端 和所述控制功率放大器的输入端之间。
  4. 根据权利要求1所述的功率放大器，其中，所述第一传输路径包括相位补偿线和限幅器，所述相位补偿线连接在所述第五功分器的第一输出端和所述限幅器的输入端之间，所述限幅器的输出端连接于所述控制功率放大器的输入端。
  5. 根据权利要求1所述的功率放大器，其中，所述控制功率放大器为AB类功率放大器，所述平衡功率放大器为C类功率放大器。
  6. 根据权利要求1所述的功率放大器，其中，所述第五功分器的第二输出端通过相位调节器连接于所述第四功分器的输入端。
  7. 根据权利要求1所述的功率放大器，其中，所述第四功分器的每个输出端通过相位调节器连接于对应的第二传输路径中的第二功分器的输入端。
  8. 根据权利要求1至7中任一项所述的功率放大器，其特征在于，所述N的值为2。
  9. 一种功率放大器，包括：
    第一传输路径，所述第一传输路径包括控制功率放大器和第一功分器，所述控制功率放大器的输出端连接于所述第一功分器的输入端；
    N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；在每个第二传输路径中，所述两个平衡功率放大器的输入端与所述第二功分器的两个输出端分别对应连接，所述两个平衡功率放大器的输出端与所述第三功分器的第一输入端、第二输入端分别对应连接；所述N个第二传输路径中的N个第三功分器的第三输入端与所述第一功分器的N个输出端分别对应连接；其中， N为大于或等于1的整数；
    具有N个输入端的合路器，所述合路器的N个输入端与所述N个第二传输路径中的所述N个第三功分器的输出端分别对应连接；
    具有N个输出端的第四功分器，所述第四功分器的N个输出端与所述N个第二传输路径中的所述第二功分器的输入端分别对应连接；
    其中，所述功率放大器具有两个输入端，所述控制功率放大器的输入端为所述功率放大器的所述两个输入端中的一个输入端，所述第四功分器的输入端为所述功率放大器的所述两个输入端中的另一个输入端，所述合路器的输出端为所述功率放大器的输出端。
  10. 根据权利要求9所述的功率放大器，其中，所述控制功率放大器为AB类功率放大器，所述控制功率放大器为平衡功率放大器为C类功率放大器。
  11. 根据权利要求9或10所述的功率放大器，其中，所述N的值为2。
  12. 一种功率放大器，包括：
    第一传输路径，所述第一传输路径包括控制功率放大器和第一功分器，所述控制功率放大器的输出端连接于所述第一功分器的输入端；
    N个第二传输路径，每个第二传输路径包括两个平衡功率放大器、第二功分器及第三功分器；在每个第二传输路径中，所述两个平衡功率放大器的输入端与所述第二功分器的两个输出端分别对应连接，所述两个平衡功率放大器的输出端与所述第三功分器的第一输入端、第二输入端分别对应连接；所述N个第二传输路径中的N个第三功分器的第三输入端与所述第一功分器的N个输出端分别对应连接；其中，N为大于或等于1的整数；
    具有N个输入端的合路器，所述合路器的N个输入端与所述N 个第二传输路径中的所述N个第三功分器的输出端分别对应连接；
    其中，所述功率放大器具有N+1个输入端，所述控制功率放大器的输入端为所述功率放大器的所述N+1个输入端中的一个输入端，所述N个第二传输路径中的N个第二功分器的输入端分别为所述功率放大器的所述N+1个输入端中的其余N个输入端，所述合路器的输出端为所述功率放大器的输出端。
  13. 根据权利要求12所述的功率放大器，其中，所述控制功率放大器为AB类功率放大器，所述控制功率放大器为平衡功率放大器为C类功率放大器。
  14. 根据权利要求12或13所述的功率放大器，其中，所述N的值为2。
  15. 一种电路板，包括：功率放大器；所述功率放大器为根据权利要求1至8中任一项所述的功率放大器、或者权利要求9至11中任一项所述的功率放大器、或者权利要求12至14中任一项所述的功率放大器中的至少一个。
PCT/CN2022/117175 2021-09-06 2022-09-06 功率放大器和电路板 WO2023030530A1 (zh)

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