WO2023030466A1 - 片上存储的地址重映射电路 - Google Patents

片上存储的地址重映射电路 Download PDF

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WO2023030466A1
WO2023030466A1 PCT/CN2022/116610 CN2022116610W WO2023030466A1 WO 2023030466 A1 WO2023030466 A1 WO 2023030466A1 CN 2022116610 W CN2022116610 W CN 2022116610W WO 2023030466 A1 WO2023030466 A1 WO 2023030466A1
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address
storage
memory
dimensional
array
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PCT/CN2022/116610
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French (fr)
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常亮
葛建明
李甲
满新攀
侯红朝
姚飞
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海飞科(南京)信息技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention relates to the fields of computer system structure, chip design and fault tolerance, in particular to an address remapping circuit stored on a chip.
  • Machine learning, scientific computing and graphics processing require huge computing power, which is generally provided by large chips (such as GPU, TPU, APU, etc.) to achieve highly complex machine learning tasks and graphics processing tasks.
  • Using machine learning to do recognition requires a huge deep learning network and massive image data, and the training process is very time-consuming; in a 3D application or game scene, if recursive ray-tracing (Recursive Ray-Tracing) is used for rendering, and the scene If it is complex, massive calculations are required.
  • This requires extremely high performance, and therefore requires a large on-chip storage to support its cache (cache) requirements, and the on-chip storage module array has become an important component of large chips.
  • the invention aims at proposing a method for reconfiguring the memory module in a large chip and its address mapping, which is used for reorganizing the chip with low power consumption and can also improve the fault-tolerant performance of the chip.
  • the present invention firstly discloses an address remapping circuit for on-chip storage.
  • the basic unit of on-chip storage is a storage block.
  • Each storage block is provided with an enable bit E[i] and a base address register A[i], and by setting the enable bit E[i] to 0, the associated storage block is powered off and isolated from other circuits; the base address register A[ i] Reconfiguration implements address remapping.
  • the address mapping method of static reconstruction is as follows:
  • the address mapping method of dynamic reconstruction is as follows:
  • a control module is set, and the base address register A[i] is reconfigured by using the control module to reconfigure the base address.
  • Two-dimensional arrays are divided into two cases:
  • Case 1 For a two-dimensional address allocation array M[i][j] in block order, treat M[i][j] as a one-dimensional array M'[a] for address remapping.
  • Case 2 For a two-dimensional address allocation array in row/column order, divide it into a one-dimensional array for dimensionality reduction.
  • the one-dimensional array contains n storage units, and each storage unit contains 1 row/1 column storage block; It is treated as a one-dimensional array for address remapping.
  • Three-dimensional array three-dimensional array M[i][j][l] is assigned addresses sequentially by blocks, and M[i][j][l] is regarded as a one-dimensional array M’[a] for address remapping.
  • each memory group is used as a one-dimensional memory array to perform address reconstruction by referring to the above static/dynamic reconfiguration method; the isolated/power-off memory blocks of each memory group are the same in other groups location of the memory block for isolation/power-off operations.
  • the invention is used for chip low-power reorganization.
  • the reorganization process isolates defective storage blocks, and can automatically generate a reconfigured storage array global address/dynamically reconfigure the storage array and configure the global address of the array, ensuring the continuity of the global storage address.
  • the fault-tolerant performance of the chip can be improved, the yield of the chip can be greatly improved, and the address allocation of the RAM can be made dynamic, so that the address mapping relationship of the RAM can be changed within a certain range.
  • Figure 1 is a simple schematic diagram of storage array isolation
  • Figure 2 is a schematic diagram of the basic reconfiguration circuit of array storage
  • Figure 3 is a schematic diagram of the basic array dynamic reconfiguration circuit
  • Figure 4 is a schematic diagram of a two-dimensional general array reconstruction circuit
  • Figure 5 is a schematic diagram of a two-dimensional general array reconstruction circuit
  • the basic unit in the present invention is a storage block, each storage block has a width of W and a depth of D, and can store D ⁇ W bit data.
  • W is an arbitrary width
  • D 2 K , both of which are some integer powers of 2.
  • Data access takes W bits as the unit, and the address in the storage block is K bits.
  • the basic unit of isolation is the storage block.
  • the basic method is to set an effective bit (Enable bit E[i]) for each storage module, which can be reconfigured by means of a fuse (eFuse).
  • One method uses serially connected rolling address adders to automatically generate the module base address.
  • Another method adopts a configurable address register, and places the base address of the storage block in it, which is suitable for dynamic reconstruction.
  • Valid bits are used to control a memory block, powering it down and isolating it from other circuits.
  • Each module has a base address decoder (D[i]). After the module is isolated, a section of storage address will be vacant. The array needs to be reconstructed to achieve continuous address mapping, and the array size (depth) needs to be provided. The register is for system query to avoid addressing out of bounds. This requires address reconstruction circuitry.
  • the basic circuit is shown in Figure 1.
  • M[0], M[1], . . . , M[n-1] to mark n on-chip memory modules, and these modules form a 1-dimensional array M[0:n-1].
  • the array also contains a module number register R N .
  • the present invention is also applicable to situations where the number of modules n is not a power of 2, as explained below.
  • Embodiment 1 The rolling adder reconstructs the address mapping.
  • the fuse approach is best for static refactoring.
  • the logic value generated after the fuse is blown is fixed, and there is no need to consider the dynamic delay.
  • the serial method is used to realize the static reconstruction, and n adders are required to be connected in series, and each adder has m-bit-wide data. The serial method is explained below.
  • Each module is equipped with an effective bit, and E[i] represents the effective bit of the module M[i].
  • E[i] represents the effective bit of the module M[i].
  • the valid bit of the module is 1, the module is normally put into use. If the valid bit of the module is 0, the module is not used.
  • Each module M[i] also has an m-bit base address register A[i], and the base address of module M[0] is always 0.
  • the base addresses of n modules are A[0], A[1], ..., A[n-1] respectively.
  • the base address A[i] has m bits.
  • the global address B has m+K bits, wherein the high m bits are the base address of the storage block, and the low K bits are the internal address of the block.
  • Embodiment 2 the configuration register reconfigures the address mapping.
  • n readable and writable base address registers R[i] and n memory block effective bits E[i] are required.
  • a control module can read and write to configure each base address register and each valid bit (with the base address register, each RAM can be mapped to any base address.
  • the reconstruction circuit receives an address access request, it first subtracts the base address The address R[i], the high bit is compared with A[i] to see which RAM is hit). If a memory block M[i] is not used during operation, E[i] can be set to 0, and the controller is used to reconfigure the base address. This circuit is shown in Figure 3.
  • Common two-dimensional array storage address composition methods include sequential address allocation (row-wise/column-wise) and interleaved addressing. These two methods require their own dedicated reconfiguration address mapping circuits.
  • Embodiment 3 mapping by block switch and sequential address allocation.
  • the base address (block number) of M[i][j] in the array is i ⁇ n+j; for column-wise address allocation, M[ The block number of i][j] in the array is j ⁇ p+i.
  • the low K bit of the global address A is the address in the storage block, and the high q ⁇ r bits are the storage block number;
  • mapping of global addresses is also similar in a column-wise manner.
  • M[i][j] the one-dimensional array M'[a] is equivalent to considering M[i][j].
  • M' is a one-dimensional array containing n ⁇ p memory blocks
  • the reconstruction circuit requires n ⁇ p base address registers and block valid bits.
  • the rolling addition reconstruction (embodiment 1) and the dynamic configuration reconstruction mapping method (embodiment 2) of the one-dimensional basic array can be directly applied here.
  • This method can also be extended to a 3-dimensional array, and the 3-dimensional array can be used as a 2-dimensional storage body composed of basic arrays.
  • Embodiment 4 mapping by row/column switch and sequential address allocation.
  • any row or rows of modules in the array can be turned off or turned on for use. For example, if row i is closed, then modules M[i][0], M[i][1], ..., M[i][n-1] are all closed.
  • the whole array is regarded as being divided into n groups, and each group has p storage blocks. The addresses in each column are required to be consecutive.
  • each row is regarded as a one-dimensional array, and the methods in Embodiment 1 and Embodiment 2 can also be directly applied to here.
  • Figure 4 shows a schematic diagram of a two-dimensional general array reconstruction circuit.
  • the diagram shows a 4x4 RAM matrix, each RAM has a depth of 256.
  • the numbers in the figure are global continuous addresses, and all addresses in the figure are hash addresses.
  • ram02, ram10, and ram21 have bad blocks and cannot be used, use EN to close them in the address mapping algorithm, so that the continuous addresses are shown in the figure, bypassing the damaged ram; because the RAM in the last line is not damaged, but due to The first row of RAM with continuous address distribution has no space. In order not to affect the judgment, the last ram33 cannot be used either.
  • Embodiment 5 mapping of interleaved storage.
  • Cross-mapping aims at randomly and evenly mapping continuous memory addresses to different memory groups to improve memory bandwidth.
  • each group is a one-dimensional storage array. If address a is mapped to storage group i, address a+1 will generally be mapped to a different storage group. In this way, in the best case, n values can be fetched at a time, achieving good storage bandwidth.
  • a group mapping hash function f is used to map address a to a certain storage group i
  • the cross-mapping address reconstruction adopts the method procedureSerial_Address_Generate of a one-dimensional basic array, and each group is reconstructed according to this method. If there is no defective storage block in a group array M[i], then the valid bit E[i][p-1] of the last block in the group is set to 0, and the valid bits of the remaining storage blocks are 1. This approach can be extended to up to k defective modules per group.
  • the invention divides the storage address into two parts, one part represents the storage group number, and the other part represents the address within the group.
  • the interleaved memory address range without defects is p ⁇ q.
  • the present invention performs reconstruction and address mapping for exclusive-or (XOR) hash functions and remainder (modulo) hash functions.
  • Set an address upper-line register R lim and generate an error or interrupt signal when the address exceeds the range.
  • Figure 5 shows a schematic diagram of a two-dimensional address interleaved array reconstruction circuit.
  • the diagram shows a 4x4 RAM matrix, each RAM has a depth of 256.
  • the numbers in the figure are global continuous addresses, and all addresses in the figure are hash addresses.
  • ram02, ram10, and ram21 have bad blocks and cannot be used, use EN to close them in the address mapping algorithm, so that the continuous addresses are shown in the figure, bypassing the damaged ram; because the RAM in the last line is not damaged, but due to The first row of RAM with continuous address distribution has no space. In order not to affect the judgment, the last ram33 cannot be used either.

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Abstract

本发明公开了一种片上存储的地址重映射电路，所述片上存储的基本单元为存储块；其特征在于，每个存储块设置一个使能位E[i]和基地址寄存器A[i]，通过将使能位E[i]置0将所属存储块断电并与其他电路隔离；基地址寄存器A[i]重新配置实现地址重映射。本发明用以芯片低功耗重组，重组过程将缺陷存储块孤立，可以自动生成重构的存储阵列全局地址/动态重构存储阵列并配置阵列的全局地址，保证全局存储地址的连续性。

Description

片上存储的地址重映射电路 技术领域
本发明涉及计算机体系结构、芯片设计和容错领域，具体是一种片上存储的地址重映射电路。
背景技术
机器学习、科学计算和图形处理需要巨大的计算能力，一般由大型芯片(如GPU、TPU、APU等)提供这样的算力，来实现高度复杂的机器学习任务和图形处理任务。用机器学习来做识别需要巨大的深度(Deep Learning)网络和海量的图像数据，训练过程非常耗时；一个三维应用或游戏场景中,若采用递归光追踪(Recursive Ray-Tracing)渲染,且场景复杂，则需要做海量运算。这就要求极高的性能，也因此需要很大的片上存储来支持其缓存(cache)需求，片上存储模块阵列就成为了大型芯片重要的组成部件。
然而，大型芯片中往往会有部分存储块在特定时间范围内闲置，或者出现制造缺陷。但是，其余的存储块仍然需要构成具有连续地址的系统，特别是在分布式共享存储(distributed shared memory)处理器中。需要将一些存储块隔离出来，而让其余的存储块组成连续地址的系统。在设计过程中就将芯片分割成功能比较独立的模块，并采用专门的方法使得模块可以被隔离，让其他模块可以在连续的全局地址中继续完成计算任务。隔离模块可以降低动态功耗，也可以增强容错性能。
如何实现上述目的是业内给予解决的技术难题。
发明内容
本发明旨在于提出大型芯片中存储模块的重构及其地址映射的方法，用以芯片低功耗重组，亦可以提高芯片的容错性能。
技术方案：
本发明首先公开了一种片上存储的地址重映射电路，所述片上存储的基本单元为存储块，每个存储块的宽度是W，深度是D，存储D×W比特数据，数据的存取以W比特为单位，存储块内地址为K位，W为任意宽度，D＝2 K；
每个存储块设置一个使能位E[i]和基地址寄存器A[i]，通过将使能位E[i]置0将所属存储块断电并与其他电路隔离；基地址寄存器A[i]重新配置实现地址重映射。
一维阵列：
静态重构的地址映射方法如下：
含n个存储块，设置n-1个加法器串联n个存储块实现基地址寄存器A[i]的重新配置。
动态重构的地址映射方法如下：
设置一个控制模块，使用控制模块重新配置基地址实现基地址寄存器A[i]的重新配置。
二维阵列分两种情况：
情况1：对于二维按块顺序地址分配阵列M[i][j]，将M[i][j]视为一维阵列M’[a]进行地址重映射。
情况2：对于二维按行/列顺序地址分配阵列，将其降维拆分至一维阵列，一维阵列中包含n个存储单元，每个存储单元包含1行/1列存储块；将其视为一维阵列进行地址重映射。
三维阵列：三维按块顺序地址分配阵列M[i][j][l]，将M[i][j][l]视为一维阵列M’[a]进行地址重映射。
对于交叉存储阵列，包括多个存储器组，每个存储器组作为一维存储阵列参照上述静态/动态重构的方法进行地址重构；各存储器组被隔离/断电的存储块在其他组中相同位置的存储块做隔离/断电操作。
本发明的有益效果
本发明用以芯片低功耗重组，重组过程将缺陷存储块孤立，可以自动生成重构的存储阵列全局地址/动态重构存储阵列并配置阵列的全局地址，保证全局存储地址的连续性。
采用该方案后，可以提高芯片的容错性能，可以大大提高芯片的成品率，可以使RAM的地址分配动态化，从而可以在一定范围内改变RAM的地址映射关系。
附图说明
图1为存储阵列隔离简单示意图
图2为阵列存储基本重构电路示意图
图3为基本阵列动态重构电路示意图
图4为二维一般阵列重构电路示意图
图5为二维一般阵列重构电路示意图
具体实施方式
下面结合实施例对本发明作进一步说明，但本发明的保护范围不限于此：
本发明中基本单元是存储块，每个存储块的宽度是W，深度是D，可以存储D×W比特数据。这里W为任意宽度，D＝2 K二者都是2的某整数次幂。数据的存取以W比特为单位，存储块内地址为K位。
一维阵列存储模块的重构与地址映射
隔离的基本单位是存储块，基本方法就是给每个存储模块设置一个有效位(Enable bit E[i])，可以用熔丝(eFuse)方式重构。一种方法采用串接的滚动地址加法器，自动产生模块基地址。另外一种方式采用可配置地址寄存器，将存储块的基地址置于其中，适用于动态重构。有效位用来控制一个存储块，将其断电并与其他电路隔离。
每个模块有一个基地址译码器(D[i])，模块被隔离后就会造成一段存储地址的空缺，需要重构阵列来实现连续地址映射，还需要配有阵列大小(深度depth)寄存器供系统查询，以免造成寻址出界。这就需要地址重构电路。基本电路如图1所示。
用M[0]、M[1]、…、M[n-1]来标注n个片上存储模块，这些模块构成个1维阵列M[0:n-1]。对于一般存储器，n＝2 m，即模块的个数为2的m次方。阵列也包含一个模块数目寄存器R N。本发明也适用于模块数目n不为2的某次方之情景，如下面解释。
实施例1、滚动加法器重构地址映射。
熔丝方式最适合静态重构。熔丝熔断后产生的逻辑值是固定的，无需考虑动态时延。采用串行方法实现静态重构，需要n个加法器串联，每个加法器m比特宽的数据。串行方法解释如下。
每个模块配有一个有效位，用E[i]表示模块M[i]的有效位。当该模块有效位置1，该模块正常投入使用。若模块有效位置0，不使用该模块。每个模块M[i]还有一个m位的基地址寄存器A[i]，模块M[0]的基地址总是为0。n个模块的基地址分别为A[0]、A[1]、…、A[n-1]。M[i]的地址A[i]由A[i-1]和E[i]生成，即M[i]＝A[i-1]+E[i]。基地址A[i]有m位。全局地址B有m+K位，其中高m位是存储块基址，低K位是块内地址。
如此，阵列中不使用的模块可以被其有效位隔离开来，不再使用。假定模块M[0],…,M[i-1]在使用，但M[i]被关闭，则令其有效位E[i]＝0，而其他有效位置1。现在A[0]＝0，A[1]＝1，…，A[i-1]＝i-1，A[i]＝A[i-1]+E[i]＝A[i-1]。这样，不用的模块地址不增加，该模块被隔离了，而下一模块的地址A[i+1]＝i-1+E[i+1]。如果M[i+1]在使用，A[i+1]＝i，这是预期的结果。
下面的伪代码准确说明串联方法。
procedureSerial_Address_Generate(n,d,E,A,unused)；
1.mem_depth＝d×(n unused)；
2.foreach(E[i])if(E[i]＝＝0)turn_off M[i]；
3.foreach(E[i])A[i]＝A[i-1]+E[i]；
上面的方法中，unused是阵列中不使用的存储模块数目，E[i]代表了每个模块是否使用。 这种串行方法生成(n-unused)个有效模块基地址，实现阵列重构。此种电路总共需要n-1个加法器，由于串行速度慢(时延为O(n))，这种方法最适合静态地址重构，电路如图2所示。
实施例2、配置寄存器重构地址映射。
较上述静态重构更为灵活的是使用配置寄存器的动态重构方式，能够适应芯片运行中出现的故障。这种方式需要稍多一些片上硬件资源来换取更灵活的执行方式。
对于n个存储模块，需要n个可读写基地址寄存器R[i]以及n个存储块有效位E[i]。一个控制模块可以读写配置每一个基地址寄存器和每一个有效位(有了基地址寄存器，每个RAM都可以映射为任意基地址。重构电路在收到地址访问请求时，先减去基地址R[i]，高位再与A[i]比较，看hit到哪个RAM)。当运行过程中如果某个存储块M[i]不使用，可以将E[i]置0，同时使用控制器来重新配置基地址。此电路示于图3中。
二维阵列存储模块的重构电路与地址映射
给定一个n×p二维存储阵列M[i][j]，这里0≤i<p,0≤j<n，且n＝2 q，p＝2 r。常见的二维阵列存储地址组成方式分为按序地址分配(按行row-wise/按列column-wise)和交叉地址分配(interleaved addressing)。这两种方式需要各自专门的重构地址映射电路。
实施例3、按块开关、顺序地址分配的映射。
这里，假定阵列中任意一个或几个模块可以被关闭或者打开使用。对于按行地址分配(row-wise)方式，M[i][j]在阵列中的基地址(块号码)为i×n+j；对于按列(column-wise)地址分配方式，M[i][j]在阵列中的块号码为j×p+i。
依照按行(row-wise)方式，全局地址A的低K位为存储块内地址，高q×r位是存储块号；
依照按列(column-wise)方式，全局地址的映射也类似。
将M[i][j]记作M’[a]，一维阵列M’[a]等同于考虑M[i][j]。这里，a＝i×n+j，如果按行地址分配；a＝j×p+i，如果按列地址分配。
由于M’是含有n×p个存储块的一维阵列，重构电路需要n×p个基地址寄存器和块有效比特。这样，一维基本阵列的滚动加法重构(实施例1)与动态配置重构映射方式(实施例2)就可以直接应用到这里了。此种方法亦可扩展到3维阵列，将3维阵列作为由基本阵列构成的2维存储体即可。
实施例4、按行/列开关、顺序地址分配的映射。
这里，假定阵列中任意一行或几行模块可以被关闭或者打开使用。例如，第i行被关闭，则模块M[i][0]、M[i][1]、…、M[i][n-1]都关闭。
对于此种阵列的重构地址映射，可以把每一列当作一维模块阵列Q[j]，由{M[0][j], M[1][j],…,M[p-1][j]}堆叠构成，模块宽度W为任意宽度，深度D＝2 K。整个阵列看成是分为n组，每组有p个存储块。要求每一列内的地址是连续的。
由于关闭的是一行中全部模块，这对于所有列的要求相同。因此，每一列需要关闭的模块号都是相同的。只需要把一列模块当作一个一维阵列，实施例1和实施例2中的方法就可以直接应用到这里。
如果阵列中任意一列或几列模块可以被关闭或者打开使用，且地址是按列分配的，则把每一行当作一个一维阵列，实施例1和实施例2中的方法亦可以直接应用到这里。
图4给出了二维一般阵列重构电路示意图，图示为一个4x4的RAM矩阵，每个RAM深度为256，图中数字为全局连续地址，该图中的所有地址为哈希地址。假设其中ram02,ram10,ram21有坏块，无法使用，则利用EN将其在地址mapping算法中关闭，使连续地址如图所示，绕过损坏的ram；由于最后一行的RAM没有损坏，但由于连续地址分布的第一行RAM已经没有空间了，为了不影响判断，所以最后一个ram33也不能使用。
实施例5、交叉存储的映射。
交叉映射旨在于将连续的存储地址随机地、均匀地映射到不同的存储器组，以提高存储带宽。这里，每一个组就是一个一维存储阵列。如果地址a映射到存储组i，地址a+1一般都会映射到另一个不同的存储组。这样，在最好的情况下一次可以取出n个数值，实现很好的存储带宽。一般地，用一个组映射哈希函数f将地址a映射到某个存储组i，用另一个哈希函数g将a映射到存储组i中的某个地址j，即i＝f(a)和j＝g(a)。地址映射应该是双向(bijection)的而且是一一对应的(one-on-one)。
由于交叉映射地址是比较随机地分配到各个模块组，这就要求每个组中的存储块个数相同。一般的哈希函数对于每一行中的模块都是均匀分布的，如果要关闭某个组中的一个模块，则其他组中在同一个位置的模块也需要关闭。否则，很难实现均匀分布，或者有些地址很难映射到。因此，这里要求同时关闭每个组中同一位置的模块。此处以关闭1-2个组内模块为基础来说明重构方法。
交叉映射地址重构采用一维基本阵列的方式procedureSerial_Address_Generate，将每个组按照此方法重构。如果一个组阵列M[i]中没有缺损的存储块，那就将组中最后一个块的有效位E[i][p-1]置0，其余存储块的有效位置1。此方式可以扩展到每组最多k个缺陷模块。
重构后需要做地址映射。本发明将存储地址分为两部分，一部分表示存储组号，另一部分表示组内地址。没有缺陷的交叉存储地址范围是p×q。本发明针对异或型(XOR)哈希函数和余数型(modulo)哈希函数做重构和地址映射。
对于异或类哈希函数，n＝2 m,q＝2 k,p＝2 L都是2的整数幂，总地址空间2 m+k+L。假定每组最多有一个缺陷的存储块，重构后地址空间为2 k(2 L-1)2 m＝2 m+k+L-2 m+k。本发明采用低位交叉方式，哈希函数i＝f(a)与无缺陷存储系统一致，且令g(a)＝a[2 m+k+L-1:2 m]，并将其取值范围限制在0到q(p-1)＝2 k(2 L-1)之内。设置一个地址上线寄存器R lim，当地址超出范围时产生错误或者中断信号。
对于余数型哈希函数，i＝a mod n为存储组号，j＝a/n为组内地址。同理，设置一个地址上线寄存器R lim，当地址超出范围时产生错误或者中断信号。哈希函数不需要改变。
图5给出了二维地址交叉阵列重构电路示意图，图示为一个4x4的RAM矩阵，每个RAM深度为256，图中数字为全局连续地址，图中的所有地址为哈希地址。假设其中ram02,ram10,ram21有坏块，无法使用，则利用EN将其在地址mapping算法中关闭，使连续地址如图所示，绕过损坏的ram；由于最后一行的RAM没有损坏，但由于连续地址分布的第一行RAM已经没有空间了，为了不影响判断，所以最后一个ram33也不能使用。
本文中所描述的具体实施例仅仅是对本发明精神做举例说明。本发明所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，但并不会偏离本发明的精神或者超越所附权利要求书所定义的范围。

Claims (10)

  1. 一种片上存储的地址重映射电路，所述片上存储的基本单元为存储块，
    其特征在于，每个存储块设置一个使能位E[i]和基地址寄存器A[i]，通过将使能位E[i]置0将所属存储块断电并与其他电路隔离；基地址寄存器A[i]重新配置实现地址重映射；
    对于一维阵列，一维阵列中含n个存储块，设置n-1个加法器串联n个存储块，每个存储块设置一个可读写基地址寄存器R[i]，地址重映射电路设置一个控制模块，控制模块读写配置可读写基地址寄存器R[i]和使能位E[i]实现基地址寄存器A[i]的重新配置。
  2. 根据权利要求1所述的电路，其特征在于对于n×p二维按块顺序地址分配阵列M[i][j]，0≤i<p,0≤j<n，且n＝2 q，p＝2 r；将M[i][j]视为一维阵列M’[a]进行地址重映射。
  3. 根据权利要求2所述的电路，其特征在于对于二维按行地址分配方式，a＝i×n+j。
  4. 根据权利要求2所述的电路，其特征在于对于二维按列地址分配方式，a＝j×p+i。
  5. 根据权利要求1所述的电路，其特征在于对于二维按行/列顺序地址分配阵列，将其降维拆分至一维阵列，一维阵列中包含n个存储单元，每个存储单元包含1行/1列存储块。
  6. 根据权利要求1所述的电路，其特征在于对于三维按块顺序地址分配阵列M[i][j][l]，将M[i][j][l]视为一维阵列M’[a]进行地址重映射。
  7. 根据权利要求1所述的电路，其特征在于所述使能位E[i]通过熔丝方式重构。
  8. 一种片上存储的地址重映射电路，所述片上存储的基本单元为存储块，
    其特征在于，每个存储块设置一个使能位E[i]和基地址寄存器A[i]，通过将使能位E[i]置0将所属存储块断电并与其他电路隔离；基地址寄存器A[i]重新配置实现地址重映射；
    对于交叉存储阵列，包括多个存储器组，每个存储器组作为一维存储阵列进行地址重构；各存储器组被隔离/断电的存储块在其他组中相同位置的存储块做隔离/断电操作。
  9. 根据权利要求8所述的电路，其特征在于所述交叉存储阵列进行地址重构后，进行地址映射。
  10. 一种片上存储模块，包括存储块，其特征在于设置有如权利要求1-9任一项所述的地址重映射电路。
PCT/CN2022/116610 2021-09-02 2022-09-01 片上存储的地址重映射电路 WO2023030466A1 (zh)

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