WO2023025064A1

WO2023025064A1 - Chip, three-dimensional chip, and chip preparation method

Info

Publication number: WO2023025064A1
Application number: PCT/CN2022/113702
Authority: WO
Inventors: 王慧梅
Original assignee: 西安紫光国芯半导体有限公司
Priority date: 2021-08-26
Filing date: 2022-08-19
Publication date: 2023-03-02

Abstract

The present invention provides a chip, a three-dimensional chip, and a chip preparation method. The chip comprises: at least one chip unit. A pad area of the chip unit is provided with a first bump array, and a non-pad area is provided with a second bump array. The second bump array is added in the area without pads, the first bump array and the second bump array are used for transmitting heat to a substrate, and the substrate then transmits heat to the outside of the substrate by means of a ball grid array package (BGA), thereby improving heat dissipation effect of a semiconductor device.

Description

A kind of chip, three-dimensional chip and chip preparation method

Cross References to Related Applications

This application claims its priority based on the Chinese patent application 202110990169.6 submitted on August 26, 2021 and the Chinese patent applications 202110994344.9 and 202110994512.4 submitted on August 27, 2021. The entire content of the description is hereby incorporated by reference.

【Technical field】

The invention relates to the technical field of integrated circuits, in particular to a chip, a three-dimensional chip and a method for preparing the chip.

【Background technique】

The clock signal and data signal in the chip need to be led out through the packaging format of flip chip ball grid array (FCBGA, Flip Chip Ball Grid Array). But because of the high power consumption of the chip, heat dissipation will be a big challenge.

In related technologies, heat dissipation for FCBGA packaging is mainly solved by means of selection of substrate material, selection of substrate layers, and placement of heat sinks. However, these methods will increase the cost of the substrate without exception. There are also some that solve the heat dissipation problem through the distribution of bumps. It is mainly to simulate places with high temperature through simulation, and appropriately increase the distribution density of the bumps, so that the heat can be transmitted to the substrate through the high-density bumps and then dissipated.

Although the method of changing the distribution of bumps is helpful for package heat dissipation, there are also the following problems: the position of the chip pad has been fixed, and the position of the original pad must be changed to increase the density of the bumps, and rewiring is required, which will lead to Signal integrity issues such as extended signal traces, increased interference and reflection of high-frequency signals. In addition, the number of pads drawn on the chip is limited, and the pad space is limited. Even if the heat dissipation is improved by increasing the bump density, there is still a limited number of pads, and there is no way to add more bumps, which leads to the lack of heat dissipation effect. make sure.

【Content of invention】

Aiming at the problems existing in the prior art, the embodiment of the present invention provides a chip, a three-dimensional chip and a chip manufacturing method, which are used to solve the technical problem in the prior art that heat dissipation effect of packaging cannot be ensured.

In a first aspect, the present application provides a chip, including: at least one chip unit, a pad area of the chip unit is provided with a first bump array, and a non-pad area is provided with a second bump array.

Optionally, the distance between the second bumps in the second bump array is greater than the distance between the first bumps in the first bump array.

Optionally, at least part of the second bumps in the second bump array are grounded to replace the grounding function of the first bump array.

Optionally, the grounded first bump in the first bump array includes: a first grounded first bump and a second grounded first bump; the first grounded first bump is used to eliminate interference signals, The second grounding first bump is used for the test ground on the wafer; the second grounding first bump is in a disconnected state; or the grounding first bump in the first bump array includes: a first Grounding the first bump and the second grounding first bump; the first grounding first bump is used to eliminate interference signals, and the second grounding first bump is used for testing ground on the wafer; The grounding strategy for grounding the second bump in the two-bump array is consistent with the grounding strategy when the second grounding first bump is not disconnected.

Optionally, the second power-connected bump in the second bump array is connected to the power supply, and the power-connection strategy of the second power-connected bump is consistent with the power-connection strategy of the first power-connected bump.

Optionally, a metal layer is disposed between the second bumps in the second bump array.

Optionally, in the first bump array, a metal layer is arranged between the first bumps connected to the same power supply.

Optionally, a window is opened on the first surface of the chip unit, and the first bump in the first bump array is disposed in the window; the second bump in the second bump array is The positions of the first bumps are staggered; the first bumps are used to transmit signals, the second bumps are used to disperse the stress of the first bumps, and the first bumps and the second bumps are The height difference between blocks is less than or equal to the threshold.

Optionally, the chip further includes: a top metal layer disposed at the bottom of the window; a chip pad disposed on the top metal layer and located in the window, and the first bump is disposed on the chip pad .

Optionally, it also includes: a passivation layer disposed on the first surface and the sidewall of the window and covering the top metal layer not provided with chip pads; a transition layer, the transition layer covering the passivation layer , and fill the window; the transition layer has a groove corresponding to the position where the second bump is arranged, and the second bump is arranged on the passivation layer corresponding to the first surface, and from The groove is exposed; or, the second bump is disposed on the transition layer.

Optionally, the passivation layer is provided with a first metal layer at a position corresponding to the second bump, and the second bump is disposed on the first metal layer; the chip pad corresponds to the first metal layer. A second metal layer is arranged at the position of a bump, and the first bump is arranged on the second metal layer.

Optionally, the density of the first bumps is positively correlated with stress distribution.

Optionally, the size of the first metal layer is larger than the size of the second metal layer.

Optionally, the orthographic projection of the first bump on the chip unit and the orthographic projection of the second bump on the chip unit are both circular, and the first bump is on the The diameter of the orthographic projection on the chip unit is larger than the diameter of the orthographic projection of the second bump on the chip unit; or the orthographic projection of the first bump on the chip unit and the second bump on the chip unit The orthographic projections on the above-mentioned chip units are all rectangles.

Optionally, the orthographic projection of the first metal layer on the chip unit is a first projection, the orthographic projection of the second metal layer on the chip unit is a second projection, and the first projection and The second projection is circular; or the first projection and the second projection are rectangular; the area of the first projection is larger than the area of the second projection.

In a second aspect, the present application provides a three-dimensional chip, including: a first chip, the first chip includes the chip described in any one of the above; a second chip, the second chip is arranged at a distance from the first chip One side of the first bump array and the second bump array, and the second chip is electrically connected to the first chip.

In a third aspect, the present application provides a chip manufacturing method, the method comprising: providing at least one chip unit; forming a first bump array in the pad area of the chip unit; and forming a second bump array in the non-pad area. bump array.

Optionally, after the first array of bumps is formed in the pad area of the chip unit and the second array of bumps is formed in the non-pad area, the method further includes: at least Part of the second bumps are grounded to replace the grounding function of the first bump array.

Optionally, after forming the first bump array in the pad area of the chip unit and forming the second bump array in the non-pad area, the method further includes: in the second bump array A metal layer is arranged between the second bumps.

Optionally, before forming the second bump array in the non-pad area, it includes: determining the warpage information of the substrate according to the normal stress in the X direction of the substrate, the normal stress in the Y direction and the shear stress in the XOY plane ; Determine the density of the second bump array according to the warpage information.

The invention provides a chip, a three-dimensional chip and a method for preparing the chip. The chip is provided with a first bump array in the pad area and a second bump array in the non-pad area. In this way, by adding the second bump array in the area without pads, the first bump array and the second bump array are used to transfer heat to the substrate, and the substrate then transfers the heat to the outside of the substrate through the ball grid array package BGA, Therefore, the heat dissipation effect of the semiconductor device is improved.

【Description of drawings】

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:

FIG. 1 is a schematic plan view of a chip provided by an embodiment of the present application;

FIG. 2 is a partial cross-sectional view of a chip provided by an embodiment of the present application;

FIG. 3 is a partial cross-sectional view of another chip provided by the embodiment of the present application;

FIG. 4 is a partial cross-sectional view of another chip provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of a second bump provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of an embodiment of a three-dimensional chip of the present application;

FIG. 7 is a schematic structural diagram of another embodiment of a three-dimensional chip of the present application;

FIG. 8 is a schematic flowchart of an embodiment of a method for preparing a chip of the present application.

【Detailed ways】

In order to solve the technical problem of the heat dissipation effect of chip packaging, the invention provides a chip, a three-dimensional chip and a method for preparing the chip. Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The technical solution of the present invention will be further described in detail below with reference to the drawings and specific embodiments.

The first aspect of the embodiment of the present application provides a chip. FIG. 1 is a plan view of a chip provided by the embodiment of the present application. The chip includes a chip unit 100 , and the chip unit 100 includes a pad area 130 and a non-pad area 140 . Wherein, the pad region 130 is provided with a first bump 110, and the non-pad region 140 is provided with a second bump 120, wherein a plurality of first bumps 110 form a first bump array, and a plurality of second bumps The blocks 120 make up the second bump array.

In this way, the first bump 110 in the pad region 130 and the second bump 120 in the non-pad region 140 can be used to transfer heat to the substrate, and the substrate then transfers heat to the substrate through the ball grid array package BGA External, thereby improving the heat dissipation effect of the chip.

In one embodiment, the distance between the second bumps 120 in the second bump array is greater than the distance between the first bumps 110 in the first bump array. For example, the distance between the second bumps 120 can be 2 to 2.22 times the distance between the first bumps 110; another example: if the distance between the first bumps 110 is 180 μm, then the second bump The distance between 120 may be 360˜400 μm.

Specifically, in the second bump array, the arrangement density of the second bumps 120 in different regions can be determined according to the warpage information of the substrate, so as to further avoid package warpage.

In one embodiment, at least some of the second bumps 120 in the second bump array are grounded to replace the grounding function of the first bump array.

In one embodiment, the first bumps 110 include three types, namely: first bumps for grounding, first bumps for connecting power, and first bumps for signal transmission. The grounding first bump includes: a first grounding first bump and a second grounding first bump, the first grounding first bump is arranged between each signal transmission first bump, and is used to eliminate each signal transmission first bump. The interference signal between the bumps; the position of the second ground and the first bump is not limited, and it is used for the test ground on the wafer.

In one embodiment, the grounded first bump 110 in the first bump array includes: a first grounded first bump and a second grounded first bump; the first grounded first bump is used to eliminate interference signal, the second grounding first bump is used for the test ground on the wafer; the second grounding first bump is in a disconnected state.

In one embodiment, the grounded first bump 110 in the first bump array includes: a first grounded first bump and a second grounded first bump; the first grounded first bump is used to eliminate Interference signal, the second grounded first bump is used for the test ground on the wafer; the grounding strategy of the grounded second bump in the second bump array is not disconnected from the second grounded first bump The grounding strategy is the same.

The second bump 120 may include two types: a ground second bump and a power second bump.

The grounding strategy for grounding the second bump in the second bump array is consistent with the grounding strategy when the second grounding first bump is not disconnected.

For example, if the second grounding first bump is not disconnected, the grounding strategy is: a part of the second grounding first bump is connected to the digital ground, and the other part of the second grounding first bump is connected to the analog ground; then Connect the second ground bump on the left to digital ground, and connect the second ground bump on the right to analog ground.

After at least part of the second bumps 120 in the second bump array are grounded, the second grounded first bumps are disconnected, that is, the second grounded first bumps are in a disconnected state.

In this embodiment, the second bump connected to the power supply in the second bump array is connected to the power supply, and the power connection strategy of the second bump connected to the power supply is consistent with the power connection strategy of the first bump connected to the power supply.

For example, if the first row is connected to the power supply, the first bump needs to be connected to the first type of power supply (5V), and the second row is connected to the first bump of the power supply, and the first bump needs to be connected to the second type of power supply (24V); then in the second bump array , the first column is connected to the power supply and the second bump is correspondingly connected to the first type of power supply, and the second column is connected to the power supply and the second bump is correspondingly connected to the second type of power supply. In this way, the way that the second bump connected to the power supply and the first bump connected to the power supply correspond to the power supply can facilitate wiring on the substrate.

In this way, by adding the second bump array in the area without the pad, the first bump array and the second bump array are used to transfer heat to the substrate, and the substrate then transfers the heat to the outside of the substrate through the ball grid array package BGA, thereby Improve the heat dissipation effect of semiconductor devices.

In one embodiment, a metal layer is disposed between the second bumps 120 in the second bump array.

In one embodiment, in the first bump array, a metal layer is disposed between the first bumps 110 connected to the same power source.

Specifically, when wiring on the package substrate, in the first bump array, a metal layer is provided between the first bumps 110 connected to the same power supply. In order to ensure that there is still a ground copper connection between the second bumps 120, after the second bump array is formed in the non-pad area, a metal is provided between the second bumps 120 in the second bump array. layer. In this way, there is a ground copper connection between the second bumps 120, because of the isolation of the ground, the integrity of the signal can be maintained; at the same time, the copper coverage of the first metal layer on the substrate is increased, avoiding the first layer If the coverage difference between the metal layer and the metal layer of the symmetrical layer is too large (exceeding 10%), package warpage will occur. It should be noted that if the substrate includes 4 metal layers, and the four metal layers are arranged in order from top to bottom, and named sequentially, the symmetrical layer metal layer of the first metal layer is the fourth metal layer; if the substrate It includes 6 metal layers, and the symmetrical metal layer of the first metal layer is the sixth metal layer.

It should be noted that the first bump 110 and the second bump 120 are independent.

Please refer to FIG. 2 , which is a partial cross-sectional view of an embodiment of the chip of the present application. As shown in Figure 2, the chip provided by the embodiment of the present application includes: a chip unit 100, the chip unit 100 is provided with a first bump 110, a second bump 120 and a window 101; the first bump 110 is partially embedded in the window 101 inside.

In one embodiment, a first metal layer 112 is disposed in the window 101, the first bump 110 is disposed on the first metal layer 112, and further, a second metal layer 122 is disposed at a position corresponding to the second bump 120. , the second bump 120 is disposed on the second metal layer 122 . In one embodiment, the size of the first metal layer 112 is greater than the size of the second metal layer 122 .

It should be noted that the size refers to the length and width of a rectangle or the diameter of a circle, and the size may also refer to the area of the first metal layer 112 or the second metal layer 122 on a plane parallel to the chip unit 100. The first metal The thickness of the layer 112 and the second metal layer 122 may generally be the same, and the thickness refers to the thickness in a direction perpendicular to the chip unit 100 .

It should be noted that the chip may be at least one of a die (die or chip) and a wafer (wafer), but is not limited thereto, and may be any replacement conceivable by those skilled in the art. Wherein, a wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and a chip or a die refers to a silicon wafer obtained by dividing the aforementioned wafer on which a semiconductor circuit is manufactured. In the specific embodiments of the present application, a chip is taken as an example for introduction.

It is easy to understand that the chip is integrated with electronic devices and connection lines, and some signals in the chip need to be led out from the chip to the packaging substrate, and the packaging substrate then outputs the signals to other electronic devices or circuits, which is not specifically limited in this application. The first bump 110 can be provided on the chip to realize the signal transmission between some signals in the chip and the packaging substrate through the first bump 110 . Usually, it is necessary to set the first bump 110 based on the specific position of the signal input and output lines. Therefore, the distribution of the first bump 110 on the chip is not uniform, which is likely to cause stress concentration on the chip, thereby causing the chip to break. Or the bumps are broken, affecting the reliability and service life of the chip. As shown in Figure 1, the chip provided by the embodiment of the present application has a first bump 110 and a second bump 120 arranged on the same side of the chip unit 100, the first bump 110 is electrically connected to the chip unit 100, and the second bump 120 can play a supporting role, and the supporting role of the second bump 120 can disperse the stress concentration caused by the uneven distribution of the first bump 110 . And, the second bump 120 can fill the area where the first bump 110 is not provided, which can make the distribution of the first bump 110 and the second bump 120 tend to be even, and can avoid bumps (first bumps) on the chip unit 100 The uneven distribution of the bumps 110 and the second bumps 120) causes the stress concentration problem of the chip. Usually, since the first bump 110 needs to be electrically connected with the chip unit 100, by setting the window 101, the first bump 110 may be partially embedded in the film layer of the chip unit 100; If it is electrically connected to the chip unit 100, the second bump 120 can be directly connected to the surface on one side of the chip unit 100; therefore, when the first bump 110 and the second bump 120 are prepared, it is easy to cause the second bump 120 The difference in height from the first bump 110 may easily cause poor electrical connection between the first bump 110 and the packaging substrate, resulting in chip failure. In one embodiment, setting the difference between the height of the first bump 110 and the height of the second bump 120 to be smaller than the height difference threshold can enable the second bump 120 to fully share the support burden of the first bump 110 At the same time, it is ensured that the first bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection. It should be noted that the height of the first bump 110 can be greater than the height of the second bump 120, and the height of the first bump 110 can be smaller than the height of the second bump 120, as long as the height of the first bump 110 and the height of the second bump 120 are satisfied. The height difference between the two bumps 120 can be less than the height difference threshold. The height difference threshold can be understood as the error value allowed by the packaging process in the packaging process section. The height difference threshold can be adapted according to the size of the chip and the size of the first bump 110. Sexual settings, this application does not make specific limitations. As long as the difference between the height of the first bump 110 and the height of the second bump 120 is less than the height difference threshold, the reliability of the electrical connection between the first bump 110 and the package substrate can be guaranteed. The preparation process of the first bump 110 and the second bump 120 usually adopts a reflow soldering process. According to the characteristics of the reflow soldering process, the size of the first metal layer 112 can determine the height of the first bump 110, and the size of the second metal layer 122 The size of the second bump 120 can also be determined. In order to realize that the difference between the height of the first bump 110 and the height of the second bump 120 is less than the height difference threshold, the size of the first metal layer 112 is set to be larger than the size of the second metal layer 122 , the height of the first bump 110 can be made greater than the height of the second bump 120, and the second bump 120 can fully play the role of sharing the support burden of the first bump 110 while ensuring that the first bump 110 and the packaging The substrate can be in normal contact to achieve a stable electrical connection. It should be noted that both the first bump 110 and the second bump 120 are protrusion structures prepared on one side of the chip.

In one embodiment, in order to better disperse the stress, the density of the first bumps 110 is positively correlated with the stress distribution. That is, the greater the density, the greater the density of the first bumps 110 .

In the chip provided by the embodiment of the present application, by setting the first bump 110 and the second bump 120 on the chip unit 100, the first bump 110 is used to realize the communication connection of the chip unit 100, and the second bump 120 can function as The supporting function, the supporting function of the second bump 120 can disperse the stress concentration caused by the uneven distribution of the first bump 110 . And, the second bump 120 can fill the area where the first bump 110 is not provided, which can make the distribution of the first bump 110 and the second bump 120 tend to be uniform, and can avoid the uneven distribution of bumps on the chip unit 100. The problem of stress concentration of the chip. In combination with the setting of the window 101, the size of the second bump 120 after reflow soldering is reduced by setting the size of the first metal layer 112 larger than the size of the second metal layer 122. The size of the second bump 120 can specifically refer to the height, By reducing the height difference between the first bump 110 and the second bump 120, the second bump 120 can fully play the role of sharing the support burden of the first bump 110, while ensuring that the first bump 110 and the package The substrate can be in normal contact to achieve a stable electrical connection.

In some embodiments, the chip unit 100 includes a first area and a second area, the first area is a pad area 130, the second area is a non-pad area 140, the first bump 110 is disposed in the first area, and the second area is a pad area 130. Two bumps 120 are disposed in the second area.

In the chip provided by the embodiment of the present application, by setting the second bump 120 in the second region, the second bump 120 can disperse the stress concentration formed by the first bump 110 in the first region, and the second bump 120 can fill the gap. The area where the first bumps 110 are provided can make the distribution of the first bumps 110 and the second bumps 120 tend to be uniform, and can avoid the problem of stress concentration on the chip caused by uneven distribution of bumps on the chip unit 100 . Moreover, the first bump 110 and the second bump 120 can jointly transmit the heat generated by the chip unit 100 to the substrate, so as to improve the cooling effect of the chip.

In some implementation manners, for example, FIG. 3 is a partial cross-sectional view of another chip provided in the embodiment of the present application. As shown in Figure 3, the surface of one side of the chip unit 100 is provided with a transition layer 170, the second bump 120 is in direct contact with the transition layer 170 and connected, the chip unit 100 is provided with a window 101 in the first region, the first bump 110 is partially embedded in the window 101, the bottom of the window 101 is provided with a chip pad 180, the first metal layer 112 is connected to the chip pad 180, so as to realize the electrical connection between the first bump 110 and the chip unit 100, the chip pad 180 Usually, it is electrically connected with the circuit in the chip unit 100 , and the circuit is usually arranged inside the chip unit 100 , therefore, the chip pad 180 is usually arranged in the window 101 . In order to simplify the manufacturing process, usually the first bump 110 and the second bump 120 can be prepared at the same time, and the same material is used for preparation. Since the second bump 120 is connected to the transition layer 170 on the surface of the chip unit 100, the transition layer 170 If the insulating material is used, no electrical connection will be formed between the second bump 120 and the chip unit 100 . The first bump 110 and the second bump 120 prepared in the same manufacturing process are usually close in size, but because the first bump 110 is partially embedded in the window 101, it is easy to cause the second bump 120 to be different from the first bump. The heights of the bumps differ greatly. As shown in Figure 3, the first bump 110 in the first bump array is arranged in the window 101; the second bump 120 in the second bump array is staggered from the first bump 110 ; The first bump 110 is used to transmit signals, the second bump 120 is used to disperse the stress setting of the first bump, the height H1 of the first bump 110 and the height H2 of the second bump 120 The difference is smaller than the height difference threshold, so that the second bump 120 can fully share the support burden of the first bump 110 and at the same time ensure that the first bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection.

It should be noted that the height H1 of the first bump 110 is the height of the first bump 110 beyond the surface of the chip unit 100. Similarly, the height H2 of the second bump 120 is the height of the second bump 120 beyond the surface of the chip unit 100. high.

In some embodiments, referring to FIG. 3 , the chip unit 100 includes a top metal layer 150 , a passivation layer 160 and a transition layer 170 , and the passivation layer 160 is disposed between the top metal layer 150 and the transition layer 170 . Specifically, the top metal layer 150 is disposed at the bottom of the window 101; the chip pad 180 is disposed on the top metal layer 150 and is located in the window 101, and the first bump 110 is disposed on the chip pad 180 .

The passivation layer 160 is disposed on the first surface of the chip unit 100 , the sidewall of the window 101 and covers the top metal layer 150 where the chip pad 180 is not disposed. The transition layer 170 covers the passivation layer 160 and fills the window 101 . The transition layer 170 has grooves corresponding to the positions where the second bumps 120 are arranged, and the second bumps 120 are arranged on the passivation layer 160 corresponding to the first surface, and from the grooves The groove is exposed; or, the second bump is disposed on the transition layer 170 .

The top metal layer 150 includes circuits of the chip unit 100 , which is not specifically limited in this application. The transition layer 170 may be made of a polymer material, and the function of the transition layer 170 may be to relieve the stress of the passivation layer 160 and improve the toughness of the chip unit 100 .

In the chip provided by the embodiment of the present application, the first bump 110 is partially embedded in the window 101 , so that the first metal layer 112 is connected to the chip pad 180 to realize the electrical connection between the first bump 110 and the chip unit 100 . Both the first bump 110 and the second bump 120 are made of conductive materials, and the second bump 120 is connected to the transition layer 170 , so the second bump 120 is not electrically connected to the chip unit 100 .

In the chip of the embodiment of the present application, the second metal layer 122 corresponding to the second bump 120 may be directly disposed on the transition layer 170 , or disposed on the passivation layer 160 and pass through a groove on the transition layer 170 .

Exemplarily, continuing to refer to FIG. 3 , the thickness of the transition layer 170 can be in the range of 5-10 μm, and the upper surface of the chip pad 180 can be lower than the upper surface of the passivation layer 160 by 2-3 μm. According to the precision requirements of the packaging process, when When the height difference threshold is greater than 12 μm, poor contact between the first bump 110 and the package substrate is likely to occur, resulting in disconnection of the circuit and failure of the product. Therefore, the height difference threshold cannot be greater than 12 μm.

In some implementations, the chip provided in the embodiment of the present application further includes a packaging substrate, the first bump 110 and the second bump 120 are arranged between the chip unit 100 and the packaging substrate, and the first bump 110 is connected to the chip unit 100 respectively. electrically connected to the packaging substrate. Filling glue is disposed between the chip unit 100 and the packaging substrate.

Exemplarily, FIG. 4 is a partial cross-sectional view of another chip provided by the embodiment of the present application. As shown in FIG. 4 , the chip provided by the embodiment of the present application further includes: a package substrate 200 , a printed circuit board 300 and a heat sink 400 . The first bump 110 and the second bump 120 are disposed between the chip unit 100 and the package substrate 200 , and the first bump 110 is electrically connected to the chip unit 100 and the package substrate 200 respectively. The package substrate 200 and the printed circuit board 300 can be connected by solder balls 310, the solder balls 310 can provide electrical signal transmission between the package substrate 200 and the printed circuit board 300, the solder balls 310 can be made of tin-silver material, printed circuit The pads at the corresponding positions of the board 300 and the solder balls 310 may be plated with copper, which is not specifically limited in this application. The packaging substrate 200 and the printed circuit board 300 may also be electrically connected through solder balls, which is not specifically limited in this application. A filling glue 210 is provided between the chip unit 100 and the packaging substrate 200, and the filling glue 210 can fill the gap between the first bump 110 and the second bump 120, and fill the gap between the chip unit 100 and the packaging substrate 200 The filling compound 210 can relieve stress, protect the first bump 110 and the second bump 120 , and prevent the package substrate 200 , the first bump 110 and the second bump 120 from cracking. The heat sink 400 can provide the first heat dissipation channel A and the third heat dissipation channel C for the chip unit 100, and the chip unit 100 can also dissipate heat through the second heat dissipation channel B formed by the packaging substrate 200 and the printed circuit board 300, and this application does not make specific limited. The packaging substrate 200 may be provided with a second pad, and the ends of the first bump 110 and the second bump 120 away from the chip unit 100 may be connected to the second pad, which is not specifically limited in this application.

In the chip provided by the embodiment of the present application, a first bump 110 and a second bump 120 are provided between the chip unit 100 and the packaging substrate 200, the first bump 110 is used to electrically connect the chip unit 100 and the packaging substrate 200, and the second The bumps 120 are used to disperse the support stress concentration caused by the first bump 110, and avoid chip breakage caused by the support stress concentration caused by the first bump 110; in addition, in combination with the setting of the window 101, the first metal layer 112 The size of the second metal layer 122 is larger than the size of the second metal layer 122 to reduce the size of the second bump 120 after reflow soldering, so as to reduce the height difference between the first bump 110 and the second bump 120, which can avoid the first bump after reflow soldering. The excessive difference in height between the first bump 110 and the second bump 120 causes poor contact between the first bump 110 and the packaging substrate 200 .

In some embodiments, the orthographic projection of the first bump 110 on the chip unit 100 and the orthographic projection of the second bump 120 on the chip unit 100 are both circular. And in an embodiment, the diameter of the orthographic projection of the first bump 110 on the chip unit 100 is larger than the diameter of the orthographic projection of the second bump 120 on the chip unit 100 . Exemplarily, both the first bump 110 and the second bump 120 may be spherical in shape, and the diameter of the first bump 110 is larger than that of the second bump 120 . In the case that both the first bump 110 and the second bump 120 are spherical, since the first bump 110 is partially embedded in the window 101, by setting the diameter of the first bump 110 larger than the diameter of the second bump 120 , so that the difference between the height H1 of the first bump 110 and the height H2 of the second bump 120 is smaller than the height difference threshold.

In another embodiment, the orthographic projection of the first bump 110 on the chip unit 100 and the orthographic projection of the second bump 120 on the chip unit 100 are both rectangular. Specifically, if the orthographic projection of the first bump 110 on the chip unit 100 and the orthographic projection of the second bump 120 on the chip unit 100 are both rectangular, then the first bump 110 and the second bump 120 can be a cube or a cuboid. wait.

In some embodiments, the orthographic projection of the first metal layer 112 on the chip unit 100 is a first projection, and the orthographic projection of the second metal layer 122 on the chip unit 100 is a second projection, and the area of the first projection is larger than that of the second projection. projected area. In an embodiment, both the first projection and the second projection are circular, or both the first projection and the second projection are rectangular. In another feasible embodiment of the present application, it is also possible to set the first projection to be a circle and the second projection to be a rectangle; or set the first projection to be a rectangle and the second projection to be a circle, which is not specifically limited.

The first bump 110 may be integrated with the first metal layer 112 through a reflow process; the second bump 120 may be integrated with the second metal layer 122 through a reflow process. According to the characteristics of the reflow soldering process, the size of the first metal layer 112 can determine the size of the first bump 110, and the size of the second metal layer 122 can also determine the size of the second bump 120. Therefore, the area of the first projection is larger than that of the first projection. The area of the two projections can make the size of the first bump 110 larger than the size of the second bump 120, so that the difference between the height H1 of the first bump 110 and the height H2 of the second bump 120 is less than the height difference threshold, the second The bumps 120 can fully share the support burden of the first bumps 110 and at the same time ensure that the first bumps 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection.

Exemplarily, the preparation materials of the first metal layer 112 and the second metal layer 122 may be the same, and the preparation materials of the first bump 110 and the second bump 120 may be the same; the first metal layer 112 and the second metal layer 122 The preparation material may include metals such as copper and nickel, and the first bump 110 and the second bump 120 may be prepared by using solder material, which may be a tin-silver alloy, which is not specifically limited in this application. The preparation process is usually as follows: Firstly, the first metal layer 112 and the second metal layer 122 are prepared, and then the first bump 110 and the second bump 120 are prepared; at the same time, the first bump 110 and the second bump 120 are reflowed Soldering process is used to integrate the first metal layer 112 with the first bump 110 and to form the second metal layer 122 with the second bump 120 as a whole. Both the first bump 110 and the second bump 120 can be prepared through an electroplating process in the same process flow, which is not specifically limited in this application.

The orthographic projection of the first metal layer 112 on the chip unit 100 is a first projection, and the orthographic projection of the second metal layer 122 on the chip unit 100 is a second projection, and the area of the first projection is larger than the area of the second projection. If both the first projection and the second projection are circular, and the diameter of the first projection is greater than the diameter of the second projection, the difference between the diameter of the first projection and the diameter of the second projection can be set as a set threshold. The set threshold can be set according to the size requirements of the first bump 110 and the second bump 120 , which is not specifically limited in the present application. Exemplarily, the value range of the set threshold can be 5-8 μm. The area of the orthographic projection of the first bump 111 on the chip unit 100 is greater than the area of the orthographic projection of the second bump 121 on the chip unit 100 .

Exemplarily, the first projection and the second projection may also be shapes such as ellipses and polygons, which are not specifically limited in this application.

Exemplarily, according to the process characteristics of reflow soldering, the size of the first bump 110 is usually based on the size of the first metal layer 112, and the size of the second bump 120 is usually based on the size of the second metal layer 122. It can be understood that the first The size of a bump 110 is positively correlated with the size of the first metal layer 112 , and the size of the second bump 120 is positively correlated with the size of the second metal layer 122 . FIG. 5 is a schematic structural diagram of a second bump provided by an embodiment of the present application. As shown in FIG. 5 , when the orthographic projection of the second metal layer 122 on the chip unit 100 is circular, the radius of the second metal layer 122 is r, and the second bump 120 after the reflow soldering process is spherical. The radius is R, and the height from the center of the spherical second bump 120 to the surface of the second metal layer 122 is h, then the height of the second bump 120 is R+h. According to the process characteristics of reflow soldering, the radius r of the second metal layer 120 can determine h and R, and then the radius r of the second metal layer 122 can affect the height R+h of the second bump 120 . Therefore, the height of the second bump 120 and the second metal layer 122 after reflow can be reduced by setting the size of the second metal layer 122 smaller than the size of the first metal layer 112, so as to reduce the size of the first bump 110 and the second metal layer. The height difference of the bumps 120 is such that the difference between the height H1 of the first bump 110 and the height H2 of the second bump 120 is smaller than the height difference threshold. Specifically, the area of the first projection may be set to be larger than the area of the second projection. If both the first projection and the second projection are circular, the difference between the diameter of the first projection and the diameter of the second projection is a set threshold. It can also be set that the area of the orthographic projection of the first bump 110 on the chip unit 100 is larger than the area of the orthographic projection of the second bump 120 on the chip unit 100 .

The chip provided in the embodiment of the present application can enable the second bump 120 to fully share the support burden of the first bump 110 while ensuring that the first bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection. Moreover, the first bump 110 and the second bump 120 jointly conduct the heat in the chip to improve the heat dissipation effect.

The present application also provides a three-dimensional chip, please refer to FIG. 6 for details. FIG. 6 is a schematic structural diagram of an embodiment of the three-dimensional chip of the present application. The three-dimensional chip includes a first chip 1000 and a second chip 2000, the first chip 1000 is the chip shown in any one of the above-mentioned Figures 1 to 4, and the second chip 2000 is arranged on the first chip 1000 away from the first bump array and One side of the second bump array, and the second chip 2000 is electrically connected to the first chip 1000 . In an embodiment, the second chip 2000 is electrically connected to the first chip 1000 through the connection structure 2100 formed by a hybrid bonding process.

In one embodiment, the connection structure 2100 may be a copper-copper metal bonding structure, which is not specifically limited in the present application.

It should be noted that the three-dimensional chip provided in the embodiment of the present application may also include more chip units. For example, the three-dimensional chip of the present application may be formed by bonding three layers of chips, or bonding four or five layers of chips. No specific limitation is made here.

In the three-dimensional chip provided by the embodiment of the present application, by setting the first bump 110 and the second bump 120 on the chip unit 100, the first bump 110 communicates with the chip unit 100, and the second bump 120 is insulated from the chip unit 100. Specifically, the second bump 120 can play a supporting role, and the supporting function of the second bump 120 can disperse the stress concentration caused by the uneven distribution of the first bump 110 . And, the second bump 120 can fill the area where the first bump 110 is not provided, which can make the distribution of the first bump 110 and the second bump 120 tend to be uniform, and can avoid the uneven distribution of bumps on the chip unit 100. The problem of stress concentration of the chip. Furthermore, the second bumps 120 can also be combined with the first bumps 110 to conduct the heat generated inside the three-dimensional chip to the substrate, and then dissipate it to improve the heat dissipation effect of the three-dimensional chip. Combined with the setting of the window 101, by setting the size of the first metal layer 112 larger than the size of the second metal layer 122, the size of the second bump 120 after reflow soldering is reduced to reduce the size of the first bump 110 and the second bump 120 The height difference can make the second bump 120 fully play the role of sharing the support burden of the first bump 110 and at the same time ensure that the first bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection.

In one embodiment, in order to solve the problem of stress concentration caused by uneven bumps and a small number of bumps, the solution adopted by the present invention is: add second bumps 120 in the area where there is no first bump 110, and ensure that The height difference between the first bump 110 and the second bump 120 meets the tolerance requirement for chip flipping, generally ±12um, which is guaranteed in principle not to cause false soldering after chip flipping. The first bump 110 is used to transmit signals, and the second bump 120 is used to disperse the stress of the first bump 120 .

Wherein, the second bump 120 may be directly disposed on the first surface of the chip unit 100 , that is, on the transition layer 170 . Alternatively, the second bump 120 may be disposed on the passivation layer 160 of the chip unit 100, and when the second bump 120 is disposed on the passivation layer 160, the transition layer 170 is provided with a recess at a position corresponding to the second bump 120. groove, the second bump 120 is exposed through the groove.

In the embodiment shown in FIG. 6 , the orthographic projections of the first bump 110 and the second bump 120 are circular. In another embodiment, the orthographic projections of the first bump 110 and the second bump 120 are circular. It can also be a rectangle, as shown in FIG. 7 .

Specifically, a first metal layer 112 is further disposed at a position corresponding to the first bump 110 , and a second metal layer 122 is further disposed at a position corresponding to the second bump 120 . Materials of the first metal layer 112 and the second metal layer 122 may be Ti and Cu. In one embodiment, the thickness of the transition layer 170 and the passivation layer 160 may be 5 um, and the embedded depth of the chip pad 180 is 2 um.

The second bump 120 is directly grown on the transition layer 170, then the height difference between the second bump 120 and the first bump 110 is: the thickness of the transition layer 170 + the thickness of the passivation layer 160 + process error, namely: 5um +2um+process error≤12um. Therefore, it is necessary to control the welding accuracy and the process error well. The coplanarity between the second bump 120 and the first bump 110 cannot exceed the tolerance of 12um that the back-end packaging factory can accept for flip-chip mounting.

The embodiment of the present application also provides a method for preparing a chip, as shown in FIG. 8 , the method includes:

S110: Provide at least one chip unit.

S120: Forming a first array of bumps in a pad area of the chip unit, and forming a second array of bumps in a non-pad area.

Specifically, the prior art simulates places with higher temperatures, and appropriately increases the distribution density of the bumps in the places with higher temperatures, so that the heat is finally transmitted to the substrate through the high-density bumps and dissipated. However, this method has the following problems: the position of the chip pad is fixed, and the position of the original pad needs to be changed to increase the density of the bump, and rewiring is required, which will lead to extended signal routing, increased interference and high-frequency signal interference. Signal integrity issues such as reflections. In addition, the number of pads drawn on the chip is limited, and the pad space is limited. Even if the heat dissipation is improved by increasing the bump density, there is still a limited number of pads, and there is no way to add more bumps, which leads to the lack of heat dissipation effect. make sure.

In the chip manufacturing method proposed in this application, a first array of bumps is formed in the pad area of the chip, and a second array of bumps is formed in the non-pad area, so that the bumps in the pad area and the bumps in the non-pad area The bumps collectively conduct heat away. At the same time, setting the second bumps can also solve the problem of stress concentration caused by uneven distribution of the first bumps.

In another embodiment of the present application, the preparation method of the present application can also be applied to three-dimensional chips. Specifically, when preparing three-dimensional chips, at least two wafers are provided. It should be noted that wafers are the bases for preparing chips. material. The provided at least two wafers may be wafers with the same function, or wafers with different functions. For example, when there are two wafers and the functions of the two wafers are different, one of the wafers can be a memory wafer, and the other wafer can be a logic wafer.

Wherein, the storage wafer is arranged in order from bottom to top: a substrate, a device layer, a first stack formed by a metal layer and a dielectric layer, and an aluminum PAD; wherein, the metal layer and the dielectric layer include at least one layer, and the metal layer and the dielectric layer The positional relationship of the dielectric layers is cross lamination. Tungsten is filled between the device layer and the underlying metal layer as a barrier layer.

The logic wafer is provided in order from bottom to top: a substrate, a device layer, a second stack formed by a metal layer and a dielectric layer, and a copper PAD. Similarly, the metal layer and the dielectric layer in the logic wafer both include at least one layer, and the positional relationship between the metal layer and the dielectric layer is cross-stacked. Tungsten is filled between the device layer and the underlying metal layer as a barrier layer.

Then at least two wafers can be bonded to form a hybrid bonding portion between the at least two wafers, and the at least two wafers are electrically connected through the hybrid bonding portion.

In an optional embodiment, forming a hybrid bond between at least two wafers includes: forming a hybrid bond between a metal layer of one wafer and a metal layer of another wafer in a semiconductor device department.

Specifically, a first bonding portion is provided in the first stack formed by the metal layer and the dielectric layer of a wafer, and the first bonding portion penetrates through the first stack and is electrically connected to the underlying metal layer of the wafer. .

Similarly, a second bonding portion is provided in the second stack formed by the metal layer and the dielectric layer of another wafer, and the second bonding portion runs through the second stack and is electrically connected to the underlying metal layer of another wafer. connect.

Wherein, for any wafer, when the front side of the wafer faces upward, the bottom metal layer is the metal layer located at the bottom of the stack, and can also be understood as the first metal layer of the wafer. The front side of the wafer is the side where the device layer is formed, and the material of the first bonding portion and the second bonding portion can be a conductive material, such as copper, aluminum, tungsten, etc., and copper is preferred in this embodiment.

Specifically, when two wafers are bonded, the front side of one wafer may face up, and the front side of the other wafer may face down, so that the first bonding portion and the second bonding portion are aligned and contacted, The electrical connection between the first bonding part and the second bonding part is realized. Then the mixed bonding part includes: the first bonding part and the second bonding part after being electrically connected. Wherein, the hybrid bonding portion may be shown as a mark 21 in FIG. 2 .

After at least two wafers are bonded, pad regions and non-pad regions are formed on the side of a wafer in the semiconductor device that needs to be connected to the substrate. It can be understood that the pad region may be a region where pads are formed in the wafer, and the non-pad region may be a region where pads are not formed in the wafer.

For example, the thinning process is used to thin the substrate side of a wafer to form through-silicon vias (TSVs) that penetrate the wafer substrate; use the through-silicon vias to lead out pads, and solder on one side of the substrate. The area where the pad is located is the pad area; the area without the pad is the non-pad area. After the pad area and the non-pad area are determined, a first array of bumps is formed in the pad area, and a second array of bumps is formed in the non-pad area. Wherein, the first bump array is composed of a plurality of first bumps, and the second bump array is composed of a plurality of second bumps. In this way, by adding the second bump array in the area without pads, the first bump array and the second bump array are used to transfer heat to the substrate, and the substrate then transfers the heat to the outside of the substrate through the ball grid array package BGA, improving the performance of the substrate. Heat dissipation effect of semiconductor devices. At the same time, setting the second bumps can also solve the problem of stress concentration caused by uneven distribution of the first bumps.

In this embodiment, the second array of bumps is disposed in an area without the first array of bumps, and the first array of bumps and the second array of bumps are independently separated.

The spacing between the second bumps in the second bump array is greater than the spacing between the first bumps in the first bump array. For example, the distance between the second bumps may be 2-2.22 times the distance between the first bumps; for example, if the distance between the first bumps is 180 μm, then the distance between the second bumps may be 360-400 μm.

Specifically, in the second bump array, the arrangement density of the second bumps in different regions can be determined according to the warpage information of the substrate, so as to further avoid package warpage.

Then, before forming the second bump array in the non-pad area, it includes: determining the warpage information of the substrate according to the normal stress in the X direction of the substrate, the normal stress in the Y direction, and the shear stress in the XOY plane; determining according to the warpage information The density of the second bump array.

Among them, the method of determining the warpage information of the substrate is as follows: obtain the packaging material parameters of the semiconductor device; the packaging material parameters include: the thickness of the semiconductor device (chip), the thickness of the substrate, the thickness of the molding compound, the glass transition temperature of the core board and the prepreg of the substrate, The glass transition temperature, thermal expansion coefficient and Young's modulus of the molding compound; simulate the parameters of the packaging material to obtain the simulation results; determine the warpage of the substrate according to the simulation results.

If it is determined based on the degree of warpage that the warpage of the substrate is uniform, the intervals between the second bumps in the second bump array are uniform. If it is determined based on the degree of warpage that the warpage of the substrate is non-uniform, then the intervals of the second bumps can be set correspondingly according to the degree of warpage.

For example, if the warpage is positive, the second bumps with relatively dense spacing can be arranged in the center of the non-pad area, and the second bumps with relatively loose spacing can be arranged around the non-pad area.

For example, for a certain type of device, if the non-warping range is determined to be (-150 ~ 150 μm), that is, when the warping degree is within this range, the warping can be considered uniform; when the warping degree When the range is exceeded, the degree of warpage is considered to be non-uniform. When the warpage is 160 μm, it is determined that the substrate is warped unevenly (the warpage at the edge is smaller than the warpage at the center). At this time, the distance between the second bumps at the center of the non-pad area can be set to 360 μm, which is located at The pitch of the second bumps around the non-pad area is set to 390 μm.

In this embodiment, in an optional embodiment, after forming the second bump array in the non-pad area, the method further includes: for each first bump in the first bump array, A metal layer is arranged between the first bumps of the same power supply.

When wiring on the package substrate, in order to ensure that there is still a ground copper connection between the second bumps, after forming the second bump array in the non-pad area, it also includes: each of the second bump arrays A metal layer is arranged between the second bumps. In this way, there is a ground copper connection between the second bumps, and because of the isolation of the ground, the integrity of the signal can be maintained; at the same time, the copper coverage of the first metal layer on the substrate is increased to avoid the first metal layer If the coverage gap between the layer and the metal layer of the symmetrical layer is too large (over 10%), package warpage will occur.

Here, if the substrate includes 4 metal layers, the symmetrical metal layer of the first metal layer is the fourth metal layer; if the substrate includes 6 metal layers, the symmetrical metal layer of the first metal layer is the sixth metal layer. layer.

Further, in this embodiment, after forming the first bump array in the pad area, and forming the second bump array in the non-pad area, the method further includes: grounding at least part of the second bumps in the second bump array, To replace the grounding function of the first bump array.

In this embodiment, the first bumps include three types, namely: first bumps for grounding, first bumps for connecting power, and first bumps for signal transmission. The grounding first bump includes: a first grounding first bump and a second grounding first bump, the first grounding first bump is arranged between each signal transmission first bump, and is used to eliminate each signal transmission first bump. The interference signal between the bumps; the position of the second ground and the first bump is not limited, and it is used for the test ground on the wafer.

Likewise, the second bump can include two types: a second bump for grounding and a second bump for connecting to power.

In an optional embodiment, grounding at least part of the second bumps in the second bump array includes determining a second grounded first bump in the first bump array, and grounding the first bump includes: first Grounding the first bump and the second grounding first bump; based on the grounding strategy when the second grounding first bump is not disconnected, correspondingly grounding the grounding second bump in the second bump array.

For example, if the second grounding first bump is not disconnected, the grounding strategy is: a part of the second grounding first bump (such as the second first bump on the left side) is connected to the digital ground, and the second Ground the other part of the first bump (such as the second first bump on the right) to the analog ground; then connect the second ground bump on the left to the digital ground, and connect the second ground bump on the right to the analog ground land.

In an optional embodiment, after grounding at least part of the second bumps in the second bump array, the method further includes: determining the second grounded first bump in the first bump array, and grounding the first bump It includes: the first grounding first bump and the second grounding first bump; the second grounding first bump is disconnected.

In an optional embodiment, after grounding at least part of the second bumps in the second bump array, the method further includes: determining the first bump connected to the power supply in the first bump array, based on the first bump connected to the power supply The power connection strategy of the block corresponds to connecting the second bump in the second bump array to the power supply.

By adding the second bump array in the area without pads, the first bump array and the second bump array are used to transfer heat to the substrate, and the substrate then transfers the heat to the outside of the substrate through the ball grid array package BGA, thereby improving Heat dissipation effect of semiconductor devices. The second bump 120 can also play a supporting role, and the supporting function of the second bump 120 can disperse the stress concentration caused by the uneven distribution of the first bump 110 . Specifically, the second bumps 120 can fill the area where the first bumps 110 are not provided, which can make the distribution of the first bumps 110 and the second bumps 120 tend to be even, and can avoid bumps on the chip unit 100 (the first The uneven distribution of the bumps 110 and the second bumps 120) causes stress concentration on the chip. And because the second bump 120 does not need to be electrically connected with the chip unit 100, the second bump 120 can be directly connected to the surface of the chip unit 100 side; therefore, when preparing the first bump 110 and the second bump 120 , it is easy to cause a height difference between the second bump 120 and the first bump 110 , and it is easy to cause poor electrical connection between the first bump 110 and the packaging substrate, resulting in chip failure. In one embodiment, setting the difference between the height of the first bump 110 and the height of the second bump 120 to be smaller than the height difference threshold can enable the second bump 120 to fully share the support burden of the first bump 110 At the same time, it is ensured that the first bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection. The preparation process of the first bump 110 and the second bump 120 usually adopts a reflow soldering process. According to the characteristics of the reflow soldering process, the size of the first metal layer 112 can determine the height of the first bump 110, and the size of the second metal layer 122 The size of the second bump 120 can also be determined. In order to realize that the difference between the height of the first bump 110 and the height of the second bump 120 is less than the height difference threshold, the size of the first metal layer 112 is set to be larger than the size of the second metal layer 122 , the height of the first bump 110 can be made greater than the height of the second bump 120, and the second bump 120 can fully play the role of sharing the support burden of the first bump 110 while ensuring that the first bump 110 and the packaging The substrate can be in normal contact to achieve a stable electrical connection.

The above description is only a preferred embodiment of the present invention, and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims

A chip, characterized in that the chip comprises:

At least one chip unit, the pad area of the chip unit is provided with a first bump array, and the non-pad area is provided with a second bump array.
The chip according to claim 1, wherein the distance between the second bumps in the second bump array is greater than the distance between the first bumps in the first bump array.
The chip according to claim 1, characterized in that,

At least part of the second bumps in the second bump array are grounded to replace the grounding function of the first bump array.
The chip according to claim 1, characterized in that,

The grounded first bump in the first bump array includes: a first grounded first bump and a second grounded first bump; the first grounded first bump is used to eliminate interference signals, and the second grounded first bump is used to eliminate interference signals. The grounding first bump is used for the test ground on the wafer; the second grounding first bump is in a disconnected state; or

The grounded first bump in the first bump array includes: a first grounded first bump and a second grounded first bump; the first grounded first bump is used to eliminate interference signals, and the second grounded first bump is used to eliminate interference signals. The grounding first bump is used as a test ground on the wafer; the grounding strategy for grounding the second bump in the second bump array is consistent with the grounding strategy when the second grounding first bump is not disconnected.
The chip according to claim 1, characterized in that,

The second power-connected bump in the second bump array is connected to the power source, and the power-connection strategy of the second power-connected bump is consistent with the power-connection strategy of the first power-connected bump.
The chip according to claim 1, wherein a metal layer is arranged between each second bump in the second bump array.
The chip according to claim 1, wherein in the first bump array, a metal layer is arranged between the first bumps connected to the same power supply.
The chip according to claim 1, wherein a window is opened on the first surface of the chip unit,

A first bump in the first bump array is disposed in the window;

The second bumps in the second bump array are staggered from the first bumps;

The first bump is used to transmit signals, the second bump is used to disperse the stress of the first bump, and the height difference between the first bump and the second bump is less than or equal to a threshold .
The chip according to claim 1, further comprising:

a top metal layer disposed on the bottom of the window;

A chip pad is disposed on the top metal layer and located in the window, and the first bump is disposed on the chip pad.
The chip according to claim 9, further comprising:

a passivation layer, disposed on the first surface, the sidewall of the window, and covering the top metal layer that is not provided with a chip pad;

a transition layer covering the passivation layer and filling the window;

The transition layer has a groove corresponding to the position where the second bump is disposed, and the second bump is disposed on the passivation layer corresponding to the first surface and is exposed from the groove; or , the second bump is disposed on the transition layer.
The chip according to claim 10, characterized in that,

The passivation layer is provided with a second metal layer at a position corresponding to the second bump, and the second bump is arranged on the second metal layer;

A first metal layer is disposed on the chip pad corresponding to the first bump, and the first bump is disposed on the first metal layer.
The chip according to claim 8, wherein the density of the first bumps is positively correlated with stress distribution.
The chip according to claim 11, wherein the size of the first metal layer is larger than the size of the second metal layer.
The chip according to claim 8, wherein the orthographic projection of the first bump on the chip unit and the orthographic projection of the second bump on the chip unit are both circular, and The diameter of the orthographic projection of the first bump on the chip unit is larger than the diameter of the orthographic projection of the second bump on the chip unit; or

The orthographic projection of the first bump on the chip unit and the orthographic projection of the second bump on the chip unit are both rectangular.
The chip according to claim 13, wherein the orthographic projection of the first metal layer on the chip unit is a first projection, and the orthographic projection of the second metal layer on the chip unit is a second projection. Two projections, the first projection and the second projection are circular; or the first projection and the second projection are rectangular;

The area of the first projection is larger than the area of the second projection.
A three-dimensional chip is characterized in that it comprises:

a first chip, the first chip comprising the chip according to any one of claims 1-15;

A second chip, the second chip is arranged on a side of the first chip away from the first bump array and the second bump array, and the second chip is electrically connected to the first chip.
A method for preparing a chip, characterized in that the method comprises:

providing at least one chip unit;

A first bump array is formed in the pad area of the chip unit, and a second bump array is formed in the non-pad area.
The method according to claim 17, characterized in that, after forming the first bump array in the pad area of the chip unit and forming the second bump array in the non-pad area, the method further comprises:

Grounding at least part of the second bumps in the second bump array replaces the grounding function of the first bump array.
The method according to claim 17, characterized in that, after forming the first bump array in the pad area of the chip unit and forming the second bump array in the non-pad area, the method further comprises:

A metal layer is provided between each second bump in the second bump array.
The method according to claim 17, wherein, before forming the second bump array in the non-pad area, comprising:

determining the warpage information of the substrate according to the normal stress in the X direction of the substrate, the normal stress in the Y direction, and the shear stress in the XOY plane;

The density of the second bump array is determined according to the warping information.