WO2023024246A1 - 一种乱序数据的产生方法、装置、设备及存储介质 - Google Patents

一种乱序数据的产生方法、装置、设备及存储介质 Download PDF

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WO2023024246A1
WO2023024246A1 PCT/CN2021/127319 CN2021127319W WO2023024246A1 WO 2023024246 A1 WO2023024246 A1 WO 2023024246A1 CN 2021127319 W CN2021127319 W CN 2021127319W WO 2023024246 A1 WO2023024246 A1 WO 2023024246A1
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data
thread
threads
current thread
transmission permission
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PCT/CN2021/127319
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English (en)
French (fr)
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王向科
杨萌
刘凯
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苏州浪潮智能科技有限公司
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Priority to US18/255,922 priority Critical patent/US11907758B2/en
Publication of WO2023024246A1 publication Critical patent/WO2023024246A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Definitions

  • the present application relates to a method, device, equipment and storage medium for generating out-of-sequence data.
  • AXI (Advanced eXtensible Interface, Advanced Extensible Interface) protocol is a high-performance, high-bandwidth, low-latency on-chip bus protocol that supports out-of-order transmission characteristics. Specifically, for out-of-order transmission characteristics, the sender can return data with different IDs out of order through the AXI bus (AXI bus is a bus based on the AXI protocol for data transmission), which is not constrained by the order of the IDs, while the receiver is from the AXI After the data is read on the bus, the read data can be analyzed to obtain correct data.
  • AXI bus is a bus based on the AXI protocol for data transmission
  • the receiving end needs to support the out-of-order reading of the AXI protocol; however, the inventor realizes that in the prior art, in order to verify whether the receiving end supports the out-of-order reading of the AXI protocol, it is usually through a single thread Generating continuous data, and then transmitting the continuous data to the receiving end through the AXI bus, obviously cannot effectively simulate the scene of out-of-order reading, and thus cannot realize the effective test of whether the receiving end supports AXI protocol out-of-order reading.
  • Embodiments of the present application provide a method for generating out-of-order data, including:
  • the transmission permission is reclaimed, and the step of instructing all threads to acquire the transmission permission by random delay is returned.
  • the embodiment of the present application also provides a device for generating out-of-sequence data, including:
  • the sending module is used to: instruct all threads to obtain the transmission permission by means of random delay, and after any thread in all threads obtains the transmission permission, determine that any thread is the current thread, and instruct the current thread to transfer the currently generated data And the corresponding data identification is driven to the AXI bus for the receiving end to read, so as to realize the out-of-order reading test based on the data read by the receiving end and the corresponding data identification; wherein, only one thread is allowed to obtain the transmission authority at the same time; and
  • the return module is used to reclaim the transmission permission after the current thread sends the currently generated data and the corresponding data identifier, and return to execute to instruct all threads to obtain the transmission permission by random delay.
  • Embodiments of the present application also provide a computer device, including a memory and one or more processors, where computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by the one or more processors, one or more A processor executes the steps of any method for generating out-of-order data as described above.
  • Embodiments of the present application also provide one or more non-volatile computer-readable storage media storing computer-readable instructions, and when the computer-readable instructions are executed by one or more processors, the one or more A plurality of processors execute the steps of any method for generating out-of-sequence data as described above.
  • Fig. 1 is a flowchart of a method for generating out-of-sequence data provided by one or more embodiments of the present application.
  • Fig. 2 is a block diagram of an apparatus for generating out-of-sequence data provided by one or more embodiments of the present application.
  • FIG. 1 shows a flow chart of a method for generating out-of-order data provided by an embodiment of the present application, which may specifically include:
  • S11 Determine whether it is necessary to test whether the receiving end supports out-of-order reading of the AXI protocol, and create multiple threads based on the above confirmation, wherein the multiple threads correspond to multiple data identifiers one by one.
  • the execution subject of a method for generating out-of-sequence data may be the corresponding generation device, and the generation device may be set in the sending end, so the execution subject of the test method may be the sending end, and the following uses the test
  • the execution body of the method is specified by the sender.
  • the sending end is a terminal for generating and sending simulated data
  • the receiving end (with corresponding IP) is a terminal that needs to test whether it can support out-of-sequence reading of the AXI protocol.
  • the sending end can create multiple threads locally, and each thread can generate data and send the generated data independently (the data is the test data used to realize the test), and then simulate Data generation and transmission.
  • the data identifier can be a data ID (Identifier, an identifier that can identify different AXI protocol transmission transactions, used to distinguish between multi-transaction transmissions), and of course other settings can be made according to actual needs.
  • the embodiments of this application are all based on The data is identified as a data ID for specific description; the data generated by the simulation is grouped by data ID, the data generated by the same data ID is continuous, and different data IDs have different data streams.
  • the thread and data ID set to be created are one Corresponding relationship, and then the data generated by any thread is the data with the data identifier corresponding to the arbitrary thread, and the multiple data generated by the arbitrary thread are the data streams corresponding to the data identifier of the arbitrary thread.
  • S12 Instruct all threads to obtain the transmission permission through a random delay, and after any thread in all threads obtains the transmission permission, determine that any thread is the current thread, and instruct the current thread to identify the currently generated data and corresponding data Drive to the AXI bus for the receiving end to read, so as to realize the out-of-order reading test based on the data read by the receiving end and the corresponding data identification; wherein, only one thread is allowed to obtain the transmission permission at the same time.
  • the receiving end randomly initiates multiple threads for reading data transactions through the reading data channel, and the thread for reading data transactions reads the data sent by the sending end and the corresponding data identifier from the AXI bus, and the read data corresponds to the data ID at random ,
  • the data address is random, that is, the data is read out of order.
  • the sender can start all the created threads, and each thread in these threads will generate data cyclically.
  • the data generated by the thread is the data corresponding to the data ID that needs to be driven to the AXI bus, and the data generated by the thread can be random.
  • any thread (only one thread can use the AXI bus to send data at the same time), and the arbitrary thread that has obtained the transmission permission can drive the latest data generated by itself to the AXI bus for the receiving end to read from the AXI bus , after the arbitrary thread drives the data and the corresponding data identifier to the AXI bus, the transmission permission can be released, so that all threads started by the sender can obtain the transmission permission after a random delay, that is, the moment when all threads obtain the transmission permission It is random, so reciprocating, to realize the data generated by the random thread driving on the AXI bus and the corresponding data identification; since the thread and the data ID are in one-to-one correspondence, the data generated by the random thread driving on the AXI bus is realized, That is to realize that the
  • any thread can send the data every time it generates one data, and then generate the next data after sending the data, and can also make other settings according to actual needs, all of which are within the scope of protection of this application.
  • multiple threads are set in this application, and different threads correspond to different data identifiers, and each thread will generate data corresponding to the data identifier in a loop, and then select a random thread through the loop, and drive the data generated by the selected thread and the corresponding data identifier to
  • the receiving end can read random data identifiers and corresponding data from the AXI bus cyclically, which can effectively simulate the scene of AXI protocol out-of-order reading, and then realize the effective test of whether the receiving end supports AXI protocol out-of-order reading .
  • instructing all threads to obtain the transmission permission through random delay may include:
  • the key is a tool that enables the thread to use the corresponding semaphore to realize the corresponding data transmission of the AXI protocol;
  • Reclaim the transmission permission after the current thread sends the currently generated data and the corresponding data identifier which can include:
  • the key is reclaimed after the current thread sends the currently generated data and the corresponding data identifier.
  • the embodiment of the present application can create a semaphore, which can be regarded as the access control to the same resource, and any thread can enter the use of the AXI bus through the semaphore (including drive the data to the AXI bus); and allocate a key for the semaphore, after any thread obtains the key, it can use the key to use the corresponding semaphore, and then realize the use of the AXI bus through the semaphore.
  • any thread in the embodiment of the present application can first obtain the key when it needs to drive data to the AXI bus, and then use the key to use the corresponding semaphore after obtaining the key, and then drive the data to the AXI bus through the semaphore, and then Then return the key in time to start a new round of key acquisition and use of the AXI bus.
  • the method may further include:
  • the sending end can be provided with a thread queue to be executed, and then the thread that can currently use the AXI bus can be taken out from the queue to be executed, and then the thread is executed to realize the driving of the generated data to the AXI bus, while for other threads
  • the threads are all stored in the queue of threads to be executed as threads to be executed, waiting for execution; it can be seen that the present application can improve the convenience of thread management through the setting of the thread queue.
  • controlling the current thread to generate data corresponding to the data identifier may include:
  • a clock can be set in the embodiment of the present application, and then when any thread generates data, each beat of the clock corresponds to one data, so that the setting of the clock can also be complied with when the data is sent, thereby ensuring efficient data generation and send.
  • the method may also include:
  • a random delay can also be inserted into the adjacent data generated by each thread.
  • the random delay can be a random number of clock delays, thereby generating a random number of random clock intervals.
  • Data construct randomized data out-of-order reading, fully verify the AXI reading processing performance of the receiving end under the condition of multiple data interleaving, and fully verify the AXI bus protocol support of the receiving end.
  • the method may also include:
  • the data generated by the current thread and the corresponding data identifier are sent to the test device for the test device to perform a corresponding out-of-order read test based on the data sent by the current thread, the data received by the receiving end and the corresponding data identifiers.
  • the sending end in addition to driving the data and the corresponding data identifier to the AXI bus, can also send the data and the corresponding data identifier to the test device; correspondingly, the test device receives the data generated by the sending end and the corresponding data identifier Finally, you can also obtain the data read and processed out of order by the receiving end and the corresponding data identifier, and then compare the two. If the two are consistent, it means that the receiving end can support data out of order reading, otherwise, it means The receiving end cannot support data out-of-order reading, thereby effectively improving the test efficiency of whether the receiving end can support data out-of-order reading.
  • creating multiple threads may include:
  • the verification coding language can specifically be the System Verilog language, and the System Verilog language (a high-level verification programming language that supports object-oriented) can initiate and execute multiple threads at the same time, each thread is executed independently, and there is a thread between the threads.
  • Inter-thread communication methods can realize sequential execution between threads (such as events), conflict handling of resource sharing between threads (such as semaphores), and synchronous data transmission between threads (such as mailboxes).
  • the AXI multi-transaction data read and return has only one set of AXI bus, and the data returned by multiple data IDs needs to perform access control to the same bus resource, just as multiple threads request control of the same resource, so the embodiment of this application is based on System Verilog
  • the language creates multiple threads, and then through multi-threading combined with semaphore access control, the data of multiple data IDs is interleaved and processed in the clock beat dimension, ensuring that only one thread occupies the AXI bus to return data in each clock beat, and does not occupy the bus
  • the thread data is waiting to be sent, so as to ensure that the data of each thread is still in its own clock order, and can effectively implement operations such as thread control.
  • test device of the embodiment of the present application can also be understood as a UVM (Universal Verification Methodology) constructed, which is a verification platform based on the System Verilog class library, and utilizes its reusable components to construct a function with a standardized hierarchy and interface. Verify the environment.
  • UVM Universal Verification Methodology
  • the application When the application is verifying the AXI bus function, it uses multi-threading to simulate the multi-transaction read data returned to the AXI bus in the clock beat dimension, which satisfies the interleaving of different ID data supported in the AXI protocol, so as to test the receiver's understanding of the AXI protocol.
  • Support for multi-transaction out-of-order reading at the same time, insert random delays in each thread to simulate multiple interleaving situations, and further fully test the receiving end's support for AXI bus out-of-order reading; among them, the same ID data is still in accordance with the data
  • the data is returned in order, and there is no fixed order requirement between data with different IDs.
  • steps in the flow chart of FIG. 1 are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Fig. 1 may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, the execution of these sub-steps or stages The order is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
  • the embodiment of the present application also provides a device for generating out-of-sequence data, as shown in FIG. 2 , which may specifically include:
  • the creating module 11 is used for: determining whether it is necessary to test whether the receiving end supports out-of-order reading of the AXI protocol, and creating multiple threads based on the above confirmation, wherein the multiple threads correspond to multiple data identifiers one by one.
  • the sending module 12 is used to: instruct all threads to obtain the transmission authority by acquiring the transmission authority after a random delay, and after any thread in all threads obtains the transmission authority, determine that any thread is the current thread, and indicate that the current thread will generate the current
  • the data and the corresponding data identification are driven to the AXI bus for the receiving end to read, so as to realize the out-of-order reading test based on the data read by the receiving end and the corresponding data identification; wherein, only one thread is allowed to obtain the transmission permission at the same time.
  • the return module 13 is used to reclaim the transmission permission after the current thread sends the currently generated data and the corresponding data identifier, and return to execute to instruct all threads to obtain the transmission permission after a random delay.
  • the sending module may include:
  • the acquisition unit is used to: instruct all threads to obtain the transmission authority by obtaining the key after a random delay; wherein, the key is a tool that enables the thread to use the corresponding semaphore to realize the corresponding data transmission of the AXI protocol;
  • Return modules can include:
  • the recovery unit is configured to: recover the key after the current thread sends the currently generated data and the corresponding data identifier.
  • the device may also include:
  • Adding a module is used to: after creating multiple threads, add the created threads as threads to be executed to the queue of threads to be executed;
  • the fetching module is used for: after determining the current thread, taking the current thread as the execution thread from the waiting queue to execute the current thread.
  • the device may also include:
  • the insertion module is used for: inserting a random time delay before each time the current thread generates data and corresponding data identifiers.
  • the device may also include:
  • the generating module is used for: controlling the current thread to generate the data corresponding to the data identifier of the current thread according to the principle that each beat clock corresponds to one data.
  • the device may also include:
  • the test module is used to: send the data generated by the current thread and the corresponding data identifier to the test device, so that the test device can perform a corresponding out-of-order read test based on the data sent by the current thread, the data received by the receiving end, and the corresponding data identifiers .
  • creating modules can include:
  • the creation unit is used for: creating multiple threads based on the SystemVerilog language.
  • the embodiment of the present application also provides a computer device, which may include a memory and one or more processors.
  • Computer-readable instructions are stored in the memory.
  • one or more A processor executes the steps of any method for generating out-of-order data as described above.
  • the embodiment of the present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions.
  • the computer-readable instructions are executed by one or more processors, the one or more processing The device executes the steps of any method for generating out-of-sequence data as described above.
  • relevant parts of the out-of-sequence data generation device, equipment, and storage medium provided in the embodiment of the present application, please refer to the detailed description of the corresponding part in the out-of-order data generation method provided in the embodiment of the application. description and will not be repeated here.
  • the parts of the technical solutions provided in the embodiments of the present application that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as not to repeat them too much.

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Abstract

本申请公开了一种乱序数据的产生方法，包括：创建多个线程；指示全部线程通过随机延时后获取的方式获取传输权限，并在任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；在当前线程发送当前产生的数据及对应数据标识结束后回收传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限的步骤；多个线程与多个数据标识一一对应，同一时刻仅允许一个线程获取传输权限。

Description

一种乱序数据的产生方法、装置、设备及存储介质
相关申请的交叉引用
本申请要求于2021年8月25日提交中国专利局，申请号为202110978207.6，申请名称为“一种乱序数据的产生方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种乱序数据的产生方法、装置、设备及存储介质。
背景技术
AXI(Advanced eXtensible Interface，先进可扩展接口)协议是一种高性能、高带宽、低延迟的片内总线协议，支持乱序传输特性。具体来说，针对乱序传输特性，发送端可以通过AXI总线(AXI总线为基于AXI协议实现数据传输的总线)乱序返回不同ID的数据，不受ID的顺序约束，而接收端在从AXI总线上读取到数据后，可以将读取到的数据进行解析得到正确的数据。为了实现上述乱序传输特性，需要接收端支持AXI协议的乱序读取；然而，发明人意识到，现有技术中为了验证接收端是否支持AXI协议的乱序读取，通常是通过单一线程产生连续数据，进而将该连续数据通过AXI总线传输至接收端，这显然无法有效模拟乱序读取的场景，进而无法实现接收端是否支持AXI协议乱序读取的有效测试。
发明内容
本申请的实施例提供一种乱序数据的产生方法，包括：
确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确认创建多个线程，其中，多个线程与多个数据标识一一对应；
指示全部线程通过随机延时后获取的方式获取传输权限，并在全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于 接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限；及
在当前线程发送当前产生的数据及对应数据标识结束后回收所述传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限的步骤。
本申请的实施例还提供了一种乱序数据的产生装置，包括：
创建模块，用于：确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确定创建多个线程，其中，多个线程与多个数据标识一一对应；
发送模块，用于：指示全部线程通过随机延时后获取的方式获取传输权限，并在全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限；及
返回模块，用于：在当前线程发送当前产生的数据及对应数据标识结束后回收所述传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限。
本申请的实施例还提供了一种计算机设备，包括存储器及一个或多个处理器，存储器中储存有计算机可读指令，计算机可读指令被一个或多个处理器执行时，使得一个或多个处理器执行如上所述的任一种乱序数据的产生方法的步骤。本申请的实施例还提供了一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如上所述的任一种乱序数据的产生方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请的一个或多个实施例提供的一种乱序数据的产生方法的流程图。
图2为本申请的一个或多个实施例提供的一种乱序数据的产生装置的框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其示出了本申请的实施例提供的一种乱序数据的产生方法的流程图，具体可以包括：
S11：确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确认创建多个线程，其中，多个线程与多个数据标识一一对应。
本申请实施例提供的一种乱序数据的产生方法的执行主体可以为对应产生装置，而该产生装置可以设置于发送端内，因此该测试方法的执行主体可以为发送端，以下以该测试方法的执行主体为发送端进行具体说明。需要说明的是，发送端为模拟数据产生及发送的终端，而接收端(具有相应IP)则为需要测试其是否能够支持AXI协议的乱序读取的终端。
其中，在确定出发送端及接收端后，发送端可以在本地创建多个线程，每个线程均可以单独产生数据以及发送产生的数据(数据即为用于实现测试的测试数据)，进而模拟数据的产生及发送。具体来说，数据标识可以为数据ID(Identifier，标识，能够标识不同AXI协议传输事务的标志，用于区分多事务传输)，当然也可以根据实际需要进行其他设定，本申请实施例均以数据标识为数据ID进行具体说明；模拟产生的数据以数据ID分组，同一数据ID生成的数据连续，不同数据ID具有不同的数据流，本申请实施例中设置创建的线程与数据ID为一一对应的关系，进而任意线程产生的数据则为具有该任意线程对应数据标识的数据，而该任意线程产生的多个数据则为该任意线程 对应数据标识的数据流。
S12：指示全部线程通过随机延时后获取的方式获取传输权限，并在全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限。
接收端通过读取数据通道随机发起多个读取数据事务的线程，读取数据事务的线程从AXI总线上读取发送端发送的数据及对应数据标识，且读取到的数据对应数据ID随机、数据地址随机，也即为乱序读取数据。对应的，发送端可以启动创建的全部线程，这些线程中每个线程都会循环产生数据，线程产生的数据即为需要驱动至AXI总线的对应数据ID的数据，而线程产生数据可以是随机的，也可以是按照根据实际需要设定的规则实现的，均在本申请的保护范围之内；并且，这些线程还会随机延时后获取传输权限，或者说将传输权限随机赋予给这些线程中的任意线程(同一时刻只有一个线程能够使用AXI总线实现数据发送)，而获取到传输权限的该任意线程则可以将自己最新产生的一个数据驱动到AXI总线上，供接收端从AXI总线上读取，在该任意线程将数据及对应数据标识驱动到AXI总线上后，则可以释放传输权限，以供发送端启动的全部线程随机延时后获取该传输权限，也即全部线程获取传输权限的时刻是随机的，如此往复，以实现随机线程向AXI总线上驱动所产生的数据及对应数据标识；由于线程与数据ID是一一对应的，因此实现随机线程向AXI总线上驱动所产生的数据，也即为实现随机数据ID的数据驱动到AXI总线上，从而实现乱序读取的模拟。
另外，任意线程可以每产生一个数据则发送该数据，并在发送该数据后再产生下一个数据，也可以根据实际需要进行的其他设置，均在本申请的保护范围之内。
S13：在当前线程发送当前产生的数据及对应数据标识结束后回收传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限的步骤。
本申请中设置多个线程，不同线程对应不同数据标识，且每个线程均会循环产生对应数据标识的数据，进而通过循环选取随机线程，并将所选取线程产生的数据及对应数据标识驱动至AXI总线上，使得接收端能够循环从AXI 总线上读取随机数据标识及相应的数据，能够有效模拟AXI协议乱序读取的场景，进而实现接收端是否支持AXI协议乱序读取的有效测试。
在一些实施例中，指示全部线程通过随机延时后获取的方式获取传输权限，可以包括：
指示全部线程通过随机延时后获取钥匙的方式获取传输权限；其中，钥匙为使得线程能够使用相应旗语实现AXI协议对应数据发送的工具；
在当前线程发送当前产生的数据及对应数据标识结束后回收传输权限，可以包括：
在当前线程发送当前产生的数据及对应数据标识结束后回收钥匙。
需要说明的是，为了简便有效的实现传输权限的管控，本申请实施例可以创建一个旗语，该旗语可被视为对同一资源的访问控制，任意线程能够通过该旗语进入AXI总线的使用(包括将数据驱动至AXI总线上)；并且为该旗语分配一个钥匙，任意线程获取该钥匙后则可以利用该钥匙使用相应旗语，进而通过旗语实现对AXI总线的使用。相应的，本申请实施例中任意线程在需要将数据驱动到AXI总线上时可以先获取钥匙，进而在获取到钥匙之后利用该钥匙使用相应旗语，进而通过旗语将数据驱动到AXI总线上，然后再及时将钥匙返回，从而开始新一轮的钥匙获取及AXI总线使用。
在一些实施例中，创建多个线程后，该方法还可以包括：
将创建的线程均作为待执行线程加入至待执行线程队列中；
确定出当前线程后，还可以包括：
将当前线程作为执行线程从待执行队列中取出，以执行当前线程。
本申请实施例中发送端可以设置有待执行线程队列，进而对于当前能够使用AXI总线的线程则可以从待执行队列中取出，进而执行该线程以实现所产生数据至AXI总线的驱动，而对于其他线程则均作为待执行线程存储在待执行线程队列中，等待执行；可见，本申请能够通过线程队列的设置提高线程管理的便利性。
在一些实施例中，控制当前线程产生对应数据标识的数据，可以包括：
控制当前线程按照每拍时钟对应一个数据的原则，产生当前线程对应数据标识的数据。
需要说明的是，本申请实施例中可以设置有时钟，进而待任意线程产生数据时，每拍时钟对应一个数据，从而在实现数据发送时也能够符合时钟的 设置，从而保证数据的高效产生及发送。
在一些实施例中，该方法还可以包括：
在当前线程每次产生数据及对应数据标识前插入随机时延。
需要说明的是，本申请实施例还可以在每个线程产生的相邻数据中插入随机时延，该随机时延可以为随机个数的时钟延时，进而产生随机时钟个数间隔的乱序数据，构建随机化的数据乱序读取，充分验证接收端多种数据交织情况下的AXI读取处理性能，充分验证接收端的AXI总线协议支持情况。
在一些实施例中，该方法还可以包括：
将当前线程产生的数据及对应数据标识发送至测试装置，以供测试装置基于当前线程发送的数据、接收端接收的数据及分别对应的数据标识进行相应乱序读取测试。
本申请实施例中发送端在将数据及对应数据标识驱动至AXI总线外，还可以将数据及对应数据标识发送至测试装置；相应的，测试装置在接收到发送端产生的数据及对应数据标识后，还可以获取接收端乱序读取并处理后的数据及对应数据标识，进而将这两者进行比对，如果两者一致，则说明接收端能够支持数据乱序读取，否则，说明接收端无法支持数据乱序读取，从而有效提高接收端能否支持数据乱序读取的测试效率。
在一些实施例中，创建多个线程，可以包括：
基于验证编程语言创建多个线程。
需要说明的是，验证编码语言具体可以为System Verilog语言，System Verilog语言(一种支持面向对象的高级验证编程语言)可以同时发起并执行多个线程，各个线程独立执行，并且线程之间有线程间的通信方式，可以实现线程间的先后执行(如事件)，线程间资源共享的冲突处理(如旗语)，线程间的数据同步传输(如信箱)。而AXI多事务数据的读取返回只有一套AXI总线，多个数据ID返回数据需要对同一总线资源进行访问控制，正如多个线程对同一资源的请求控制，因此采用本申请实施例基于System Verilog语言创建多个线程，进而通过多线程结合旗语的访问控制，实现多个数据ID的数据在时钟节拍维度的交织时序处理，保证在每个时钟节拍只有一个线程占用AXI总线返回数据，未占用总线的线程数据等待发送，从而保证每个线程的数据仍是其本身的时钟顺序，且能够有效实现线程管控等操作。另外，本申请实施例的测试装置也可以理解为构建的UVM(Universal Verification  Methodology)，其是一个以System Verilog类库为主体的验证平台，利用其可重用组件构建具有标准化层次结构和接口的功能验证环境。
本申请在进行AXI总线功能验证时，使用多线程在时钟节拍维度模拟产生返回AXI总线的多事务的读数据，满足AXI协议中支持的不同ID数据的交织情况，从而测试接收端对AXI协议中多事务乱序读取的支持情况；同时在每个线程中插入随机延时模拟多种交织情况，进一步充分测试接收端对AXI总线读乱序的支持情况；其中，同一ID数据仍按照数据的顺序进行返回，而不同ID的数据之间没有固定的顺序要求。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本申请的实施例还提供了一种乱序数据的产生装置，如图2所示，具体可以包括：
创建模块11，用于：确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确认创建多个线程，其中，多个线程与多个数据标识一一对应。
发送模块12，用于：指示全部线程通过随机延时后获取的方式获取传输权限，并在全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限。
返回模块13，用于：在当前线程发送当前产生的数据及对应数据标识结束后回收传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限。
在一些实施例中，发送模块可以包括：
获取单元，用于：指示全部线程通过随机延时后获取钥匙的方式获取传 输权限；其中，钥匙为使得线程能够使用相应旗语实现AXI协议对应数据发送的工具；
返回模块可以包括：
回收单元，用于：在当前线程发送当前产生的数据及对应数据标识结束后回收钥匙。
在一些实施例中，该装置还可以包括：
加入模块，用于：创建多个线程后，将创建的线程均作为待执行线程加入至待执行线程队列中；
取出模块，用于：确定出当前线程后，将当前线程作为执行线程从待执行队列中取出，以执行当前线程。
在一些实施例中，该装置还可以包括：
插入模块，用于：在当前线程每次产生数据及对应数据标识前插入随机时延。
在一些实施例中，该装置还可以包括：
产生模块，用于：控制当前线程按照每拍时钟对应一个数据的原则，产生当前线程对应数据标识的数据。
在一些实施例中，该装置还可以包括：
测试模块，用于：将当前线程产生的数据及对应数据标识发送至测试装置，以供测试装置基于当前线程发送的数据、接收端接收的数据及分别对应的数据标识进行相应乱序读取测试。
在一些实施例中，创建模块可以包括：
创建单元，用于：基于SystemVerilog语言创建多个线程。
本申请实施例还提供了一种计算机设备，可以包括存储器及一个或多个处理器，存储器中储存有计算机可读指令，计算机可读指令被一个或多个处理器执行时，使得一个或多个处理器执行如上所述的任一种乱序数据的产生方法的步骤。
本申请实施例还提供了一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如上所述的任一种乱序数据的产生方法的步骤。需要说明的是，本申请实施例提供的一种乱序数据的产生装置、设备及存储介质中相关部分的说明请参见本申请实施例提供的一种乱序数据的产生方法中对 应部分的详细说明，在此不再赘述。另外本申请实施例提供的上述技术方案中与现有技术中对应技术方案实现原理一致的部分并未详细说明，以免过多赘述。
对所公开的实施例的上述说明，使本领域技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种乱序数据的产生方法，其特征在于，包括：
    确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确认创建多个线程，其中，多个线程与多个数据标识一一对应；
    指示全部线程通过随机延时后获取的方式获取传输权限，并在所述全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限；及
    在当前线程发送当前产生的数据及对应数据标识结束后回收所述传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限的步骤。
  2. 根据权利要求1所述的方法，其特征在于，指示全部线程通过随机延时后获取的方式获取传输权限，包括：
    指示全部线程通过随机延时后获取钥匙的方式获取传输权限；其中，所述钥匙为使得线程能够使用相应旗语实现AXI协议对应数据发送的工具；
    在当前线程发送当前产生的数据及对应数据标识结束后回收所述传输权限，包括：
    在当前线程发送当前产生的数据及对应数据标识结束后回收所述钥匙。
  3. 根据权利要求2所述的方法，其特征在于，创建多个线程后，还包括：
    将创建的线程均作为待执行线程加入至待执行线程队列中；
    确定出当前线程后，还包括：
    将当前线程作为执行线程从待执行队列中取出，以执行当前线程。
  4. 根据权利要求3所述的方法，其特征在于，还包括：
    在当前线程每次产生数据及对应数据标识前插入随机时延。
  5. 根据权利要求4所述的方法，其特征在于，控制当前线程产生对应数据标识的数据，包括：
    控制当前线程按照每拍时钟对应一个数据的原则，产生当前线程对应数据标识的数据。
  6. 根据权利要求5所述的方法，其特征在于，还包括：
    将当前线程产生的数据及对应数据标识发送至测试装置，以供测试装置基于当前线程发送的数据、所述接收端接收的数据及分别对应的数据标识进行相应乱序读取测试。
  7. 根据权利要求6所述的方法，其特征在于，创建多个线程，包括：
    基于验证编程语言创建多个线程。
  8. 一种乱序数据的产生装置，其特征在于，包括：
    创建模块，用于：确定需要对接收端是否支持AXI协议的乱序读取进行测试，基于上述确认创建多个线程，其中，多个线程与多个数据标识一一对应；
    发送模块，用于：指示全部线程通过随机延时后获取的方式获取传输权限，并在所述全部线程中的任意线程获取到传输权限后确定该任意线程为当前线程，指示当前线程将当前产生的数据及对应数据标识驱动到AXI总线上供接收端读取，以基于接收端读取的数据及对应数据标识实现乱序读取测试；其中，同一时刻仅允许一个线程获取传输权限；及
    返回模块，用于：在当前线程发送当前产生的数据及对应数据标识结束后回收所述传输权限，并返回执行指示全部线程通过随机延时后获取的方式获取传输权限。
  9. 一种计算机设备，其特征在于，包括存储器及一个或多个处理器，所述存储器中储存有计算机可读指令，所述计算机可读指令被所述一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1-7任意一项所述的方法的步骤。
  10. 一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，其特征在于，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1-7任意一项所述的方法的步骤。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113419869B (zh) * 2021-08-25 2021-12-03 苏州浪潮智能科技有限公司 一种乱序数据的产生方法、装置、设备及存储介质
US20230297418A1 (en) * 2022-03-21 2023-09-21 Volvo Car Corporation Computer-Implemented Method for Performing a System Assessment
CN118708525A (zh) * 2024-08-23 2024-09-27 中科亿海微电子科技（苏州）有限公司 Axi总线的乱序传输与超前传输控制装置及方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1842054A (zh) * 2005-03-31 2006-10-04 华为技术有限公司 模拟数据包传输乱序的方法及装置
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
CN102096734A (zh) * 2011-01-26 2011-06-15 北京中星微电子有限公司 一种验证总线乱序传输的方法和装置
US20160188501A1 (en) * 2014-12-19 2016-06-30 Sonics, Inc. Reordering Responses in a High Performance On-Chip Network
CN107203462A (zh) * 2016-03-16 2017-09-26 阿里巴巴集团控股有限公司 一种数据生成方法及装置
CN110324370A (zh) * 2018-03-29 2019-10-11 北京京东尚科信息技术有限公司 服务端向客户端推送数据的方法和装置
CN111835770A (zh) * 2020-07-14 2020-10-27 全时云商务服务股份有限公司 一种数据处理方法、装置、服务器及存储介质
CN113419869A (zh) * 2021-08-25 2021-09-21 苏州浪潮智能科技有限公司 一种乱序数据的产生方法、装置、设备及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7308686B1 (en) * 1999-12-22 2007-12-11 Ubicom Inc. Software input/output using hard real time threads
US9444757B2 (en) * 2009-04-27 2016-09-13 Intel Corporation Dynamic configuration of processing modules in a network communications processor architecture
CN102004709B (zh) * 2009-08-31 2013-09-25 国际商业机器公司 处理器局部总线到高级可扩展接口之间的总线桥及映射方法
US8972995B2 (en) * 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8438306B2 (en) * 2010-11-02 2013-05-07 Sonics, Inc. Apparatus and methods for on layer concurrency in an integrated circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1842054A (zh) * 2005-03-31 2006-10-04 华为技术有限公司 模拟数据包传输乱序的方法及装置
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
CN102096734A (zh) * 2011-01-26 2011-06-15 北京中星微电子有限公司 一种验证总线乱序传输的方法和装置
US20160188501A1 (en) * 2014-12-19 2016-06-30 Sonics, Inc. Reordering Responses in a High Performance On-Chip Network
CN107203462A (zh) * 2016-03-16 2017-09-26 阿里巴巴集团控股有限公司 一种数据生成方法及装置
CN110324370A (zh) * 2018-03-29 2019-10-11 北京京东尚科信息技术有限公司 服务端向客户端推送数据的方法和装置
CN111835770A (zh) * 2020-07-14 2020-10-27 全时云商务服务股份有限公司 一种数据处理方法、装置、服务器及存储介质
CN113419869A (zh) * 2021-08-25 2021-09-21 苏州浪潮智能科技有限公司 一种乱序数据的产生方法、装置、设备及存储介质

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