WO2023024083A1

WO2023024083A1 - Spin logic device, processing-in-memory device, half adder and full adder

Info

Publication number: WO2023024083A1
Application number: PCT/CN2021/115054
Authority: WO
Inventors: 李文静; 叶力; 向清懿
Original assignee: 华为技术有限公司
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2023-03-02
Also published as: CN117321688A

Abstract

Provided in the embodiments of the present disclosure are a spin logic device, a processing-in-memory device, a half adder and a full adder. In the spin logic device, a magnetic unit comprises a spin Hall effect layer and a ferromagnetic layer, which are stacked in a first direction. The magnetic unit comprises a first port on a first side, a second port on a second side that is opposite the first side in a second direction, and a third port, which is located between and above the first port and the second port. A first negative differential resistance is coupled between the first port and the third port. A second negative differential resistance is coupled between the second port and the third port. The spin logic device can generate significantly different output voltages at two ends of the first negative differential resistance and/or the second negative differential resistance, so as to identify different logic outputs. In this way, a voltage-type spin logic device can be realized, thereby reducing the power consumption of the device, and improving the performance thereof. In addition, the spin logic device does not need a magnetic field for assisting in magnetic moment reversal, and is easy to integrate.

Description

Spin Logic Devices, Memory-Computer Devices, Half Adders and Full Adders

technical field

Embodiments of the present disclosure relate generally to logic devices, and more particularly to spin logic devices, store-and-operate devices, half adders, and full adders.

Background technique

Currently, logic operations are performed by using Complementary Metal Oxide Semiconductor (CMOS) devices. However, in CMOS devices, data is volatile, and when logic operations are performed, the operation results need to be stored in memory separately. Since the computer's data calculation and storage are separated, the transmission of data between the processor and the memory becomes a major limiting factor that limits the speed and performance of the computer. By combining storage and logical operation units, in-memory computing or integration of storage and computing can be realized, in which in-memory computing requires logic devices to have both data computing and storage capabilities. Spin logic devices, also known as magnetic logic devices, can be used to realize storage-computing integration technology. A spin logic device is a digital logic device designed using the spin characteristics of electrons in magnetic materials. Compared with conventional semiconductor logic devices, this device has the advantages of fast speed, low power consumption, non-volatile logic information, radiation protection, and CMOS technology is compatible and other advantages, so it is considered to be very promising to replace traditional semiconductor logic devices. However, the existing spin logic device is a current mode logic device, and its output signal is a current signal, which consumes a lot of power, and there is still room for further improvement.

Contents of the invention

Embodiments of the present disclosure provide a spin logic device, a memory-computing integrated device, a half adder and a full adder.

According to a first aspect of the present disclosure, a spin logic device is provided. In the spin logic device, the first magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the first magnetic unit, and the first magnetic unit includes a The first port, the second port on the second side opposite to the first side along the second direction of the first magnetic unit, and the second port located between the first port of the first magnetic unit and the second port of the first magnetic unit and at the Third port above the first magnetic unit. The second direction is perpendicular to the first direction. The first port of the first magnetic unit is coupled to the first terminal of the spin logic device, the second port of the first magnetic unit is coupled to the second terminal of the spin logic device, and the third port of the first magnetic unit is coupled to the second terminal of the spin logic device. The third end of the spin logic device is coupled. The first negative differential resistor is coupled between the first terminal and the third terminal of the spin logic device. The second negative differential resistor is coupled between the second terminal and the third terminal of the spin logic device.

The spin Hall effect layer can generate a spin-orbit torque when there is an electric current from the first port to the second port of the first magnetic unit. Under the action of the spin-orbit torque, by means of the anomalous Hall effect, a Hall voltage can be generated in the stacking direction in the ferromagnetic layer, so that the Hall voltage can be embodied at the third port of the first magnetic unit. Due to the existence of the Hall voltage, an asymmetry is generated between the left voltage and the right voltage, where the left voltage and the right voltage respectively represent the voltage between the first terminal and the third terminal of the spin logic device and the self The voltage between the second terminal and the third terminal of the spin logic device. Negative differential resistance has the effect of further increasing large voltages and further reducing small voltages, therefore, asymmetry between voltages can be amplified. The spin logic device can generate significantly different output voltages across the first negative differential resistance and/or the second negative differential resistance to identify different logic outputs. In this way, voltage-mode spin logic devices can be realized. Current-mode spin logic devices represent different logic outputs through different current magnitudes. In order to distinguish between different logics, a larger current is required, so the device consumes more power. In contrast, voltage-mode spin logic devices do not require high current operation, thereby reducing device power consumption and improving device performance. In addition, the magnetic material of this voltage-type spin logic device is magnetized in-plane, does not need a magnetic field to assist magnetic moment reversal, and is easy to integrate.

In some embodiments, the first magnetic unit is symmetrical with respect to an axis of symmetry parallel to the first direction, the second port of the first magnetic unit is symmetrical with the first port of the first magnetic unit with respect to the axis of symmetry, and the first magnetic unit The third port of is located on the axis of symmetry. Through this symmetrical structure, the asymmetry of voltages corresponding to different logic outputs can be amplified as much as possible, so that it is easier to identify different logic outputs.

In some embodiments, the first terminal of the spin logic device is configured to be coupled to a first voltage, and the second terminal of the spin logic device is configured to be coupled to a second voltage to generate a second voltage in the spin logic device. Current flow between one terminal and the second terminal of a spin logic device. The spin logic device is used to output a third voltage representing the output of the first logic between the first terminal of the spin logic device and the third terminal of the spin logic device, and/or the spin logic device is used to output the third voltage between the spin logic device and the spin logic device. A fourth voltage representing the second logic output is output between the second terminal of the device and the third terminal of the spin logic device. With the help of the vertical orthogonal relationship between the current direction, the magnetization direction, and the direction of the symmetry axis, due to the spin Hall effect, the current between the first end and the second end of the spin logic device can generate a Hall effect in the direction of the symmetry axis. The Er voltage causes an imbalance between the third voltage and the fourth voltage, so that the spin logic device can use the third voltage and/or the fourth voltage to realize a logic output.

In some embodiments, the magnetization direction represents the logic input of the first magnetic unit.

In some embodiments, the first negative differential resistance and/or the second negative differential resistance may be realized by complementary junction field effect transistors or resonant tunneling diodes.

In some embodiments, the spin Hall effect layer includes a heavy metal layer and/or a topological insulator layer.

In some embodiments, the magnetization direction is flipped in response to a write current between the first port of the first magnetic unit and the second port of the first magnetic unit.

In some embodiments, the first negative differential resistance and the second negative differential resistance are the same.

In some embodiments, the spin logic device may further include a second magnetic unit, the second magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along the first direction of the second magnetic unit, the second magnetic unit including a first port on a first side of the second magnetic unit, a second port on a second side opposite to the first side of the second magnetic unit along a second direction of the second magnetic unit, and a Between the first port and the second port of the second magnetic unit and the third port above the second magnetic unit, the second direction of the second magnetic unit is perpendicular to the first direction of the second magnetic unit, wherein the second magnetic unit The first port of the second magnetic unit is coupled to the first terminal of the spin logic device, the second port of the second magnetic unit is coupled to the second terminal of the spin logic device, and the third port of the second magnetic unit is coupled to the spin logic device The third terminal is coupled. For example, the second magnetic unit may have the same arrangement as the first magnetic unit above. The spin logic device may further include a third magnetic unit, the third magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along the first direction of the third magnetic unit, the third magnetic unit is included in the third magnetic unit The first port on the first side of the third magnetic unit, the second port on the second side opposite to the first side of the third magnetic unit along the second direction of the third magnetic unit, and the first port located between the first port of the third magnetic unit and the third Between the second port of the magnetic unit and the third port above the third magnetic unit, the second direction of the third magnetic unit is perpendicular to the first direction of the third magnetic unit, the first port of the third magnetic unit is connected to the spin The first terminal of the logic device is coupled, the second port of the third magnetic unit is coupled to the second terminal of the spin logic device, and the third port of the third magnetic unit is coupled to the third terminal of the spin logic device. For example, the third magnetic unit may have the same arrangement as the first magnetic unit above. Through the first magnetic unit to the third magnetic unit, the spin logic device can realize various logic gates.

In some embodiments, the magnetization direction of the first magnetic unit is indicative of a logic input of the first magnetic unit. The magnetization direction of the second magnetic unit represents the logic input of the second magnetic unit. The spin logic device is configured to output a third voltage representing a first logic output of the spin logic device between a first terminal of the spin logic device and a third terminal of the spin logic device, wherein if the magnetization of the third magnetic unit direction is the first magnetization direction, the first logic output acts as the first logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit, and if the magnetization direction of the third magnetic unit is the second magnetization direction, the first The logic output is used as a second logic operation representing the logic input of the first magnetic unit and the second magnetic unit, and/or the spin logic device is used between the second terminal of the spin logic device and the third terminal of the spin logic device The intermediate output represents the fourth voltage of the second logic output of the spin logic device, wherein if the magnetization direction of the third magnetic unit is the first magnetization direction, the second logic output acts as the logic representing the first magnetic unit and the second magnetic unit. A third logic operation of the input, and if the magnetization direction of the third magnetic unit is the second magnetization direction, the second logic output acts as a fourth logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit.

In some embodiments, the first logical operation and the second logical operation include "AND" and "NOR", and the third logical operation and the fourth logical operation include "AND" and "OR".

According to a second aspect of the present disclosure, an integrated storage and calculation device is provided. The storage-computing integrated device includes the logic gate in the first aspect. In addition, the integrated storage and calculation device further includes a transistor, and the control terminal of the transistor is coupled to the third terminal of the logic gate. The memory-computing integrated device also includes a fourth magnetic unit, the fourth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along the first direction of the fourth magnetic unit, the fourth magnetic unit is included in the fourth magnetic unit The first port on the first side and the second port on the second side opposite to the first side of the fourth magnetic unit along the second direction of the fourth magnetic unit, the second direction of the fourth magnetic unit is perpendicular to the fourth magnetic unit In the first direction of the unit, the first port of the fourth magnetic unit is coupled to the first terminal of the transistor, and the second port of the fourth magnetic unit is coupled to the power supply. In the storage-computing integrated device, logic operations are performed through logic gates, and the results of logic operations are stored in the fourth magnetic unit.

In some embodiments, the fourth magnetic unit is symmetrical with respect to the axis of symmetry parallel to the first direction of the fourth magnetic unit, and the second port of the fourth magnetic unit is the same as the axis of symmetry of the fourth magnetic unit with respect to the axis of symmetry of the fourth magnetic unit. The first port is symmetrical.

In some embodiments, the write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit.

According to a third aspect of the present disclosure, a half adder is provided. The half adder includes a first NOR gate and a second NOR gate implemented by the first aspect of the present disclosure. The first end of the first NOR gate is coupled to the first end of the second NOR gate, the second end of the first NOR gate is coupled to the second end of the second NOR gate, and the first NOR gate is coupled to the second end of the second NOR gate. Logic inputs of the first magnetic unit and the first magnetic unit of the second NOR gate are complementary, and logic inputs of the second magnetic unit of the first NOR gate and the second magnetic unit of the second NOR gate are complementary. The half adder also includes a first switch, the control terminal of the first switch is coupled to the third terminal of the first NOR gate; a second switch, the control terminal of the second switch is coupled to the third terminal of the second NOR gate end; and a fifth magnetic unit, the fifth magnetic unit comprising a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the fifth magnetic unit, the fifth magnetic unit comprising a The first port and the second port on the second side opposite to the first side of the fifth magnetic unit along the second direction of the fifth magnetic unit, the second direction of the fifth magnetic unit is perpendicular to the first side of the fifth magnetic unit direction, the first port of the fifth magnetic unit is coupled to the power supply, and the second port of the fifth magnetic unit is coupled to the first switch and the second switch.

In some embodiments, the write current of the fifth magnetic unit has a direction from the first port of the fifth magnetic unit to the second port of the fifth magnetic unit.

According to a fourth aspect of the present disclosure, a full adder is provided. The full adder includes a first NOR gate, a second NOR gate, a third NOR gate and a fourth NOR gate implemented by the first aspect of the present disclosure. The logic input of the first magnetic unit of the first NOR gate is a first addend, and the logic input of the second magnetic unit of the first NOR gate is a second addend. The first end of the first NOR gate is coupled to the first end of the second NOR gate, and the second end of the first NOR gate is coupled to the second end of the second NOR gate, wherein the second NOR gate The logic input of the first magnetic unit of the NOR gate is the complement of the first addend, and the logic input of the second magnetic unit of the second NOR gate is the complement of the second addend. The control terminal of the first switch is coupled to the third terminal of the first NOR gate. The control terminal of the second switch is coupled to the third terminal of the second NOR gate, and the first terminal of the second switch is coupled to the first terminal of the first switch to provide a first logic output. The logic input of the second magnetic unit of the third NOR gate is the carry number of adjacent lower bits. The first end of the third NOR gate is coupled to the first end of the fourth NOR gate, the second end of the third NOR gate is coupled to the second end of the fourth NOR gate, and the third NOR gate is coupled to the second end of the fourth NOR gate. The second port of the first magnetic unit is coupled to the second port of the first magnetic unit of the fourth NOR gate, and the first port of the first magnetic unit of the fourth NOR gate is coupled to the first logic output, wherein The logic input of the second magnetic unit of the fourth NOR gate is the complement number of the carry number of the adjacent low bit. The control terminal of the third switch is coupled to the third terminal of the third NOR gate. The control terminal of the fourth switch is coupled to the third terminal of the fourth NOR gate. The full adder further includes a sixth magnetic unit, the sixth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the sixth magnetic unit, and the sixth magnetic unit is included in the sixth magnetic unit. A first port on one side and a second port on a second side opposite to the first side of the sixth magnetic unit along a second direction of the sixth magnetic unit, the second direction of the sixth magnetic unit being perpendicular to the sixth magnetic unit In the first direction, the first port of the sixth magnetic unit is coupled with the power supply, and the second port of the sixth magnetic unit is coupled with the third switch and the fourth switch, and the sixth magnetic unit is used for storage and bit. The switch circuit is used for activating the first NOR gate and the second NOR gate for a first period of time to store the first logic output in the first magnetic unit of the third NOR gate and to store the second NOR gate complementary to the first logic output. Two logic outputs are stored in the first storage unit of the fourth NOR gate, and during a second time period, the third NOR gate and the fourth NOR gate are activated to store the logic output in the sixth magnetic unit. The full adder also includes the memory-computing integrated device according to the second aspect of the present disclosure. The logic input of the first magnetic unit of the storage-calculation integrated device is the value of the first addend, the logic input of the second magnetic unit of the storage-calculation integrated device is the value of the second addend, and the logic input of the third magnetic unit of the storage-calculation integrated device is The logic input is the carry number of the adjacent low bit, and the fourth magnetic unit of the memory-calculation integrated device stores the carry number to the adjacent high bit.

In some embodiments, the write current of the sixth magnetic unit has a direction from the first port of the sixth magnetic unit to the second port of the sixth magnetic unit. The write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit.

According to a fifth aspect of the present disclosure, an apparatus is provided. The device includes a printed circuit board, and further includes a spin logic device according to the first aspect of the present disclosure. The spin logic device is arranged on a printed circuit board.

According to a sixth aspect of the present disclosure, an apparatus is provided. The device includes a printed circuit board, and further includes an integrated storage and computing device according to the second aspect of the present disclosure. The storage and calculation integrated device is arranged on the printed circuit board.

According to a seventh aspect of the present disclosure, an apparatus is provided. The device includes a printed circuit board, and further includes a half adder according to the third aspect of the present disclosure. The half adder is provided on the printed circuit board.

According to an eighth aspect of the present disclosure, an apparatus is provided. The device includes a printed circuit board, and further includes a full adder according to the fourth aspect of the present disclosure. The full adder is arranged on the printed circuit board.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or principal characteristics of the disclosure, nor is it intended to limit the scope of the disclosure.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing the exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings, wherein, in the exemplary embodiments of the present disclosure, the same reference numerals are generally represent the same part.

Figure 1A shows a schematic diagram of a spin logic device according to some embodiments of the present disclosure.

FIG. 1B shows a perspective view of a magnetic unit of the spin logic device in FIG. 1A .

FIG. 2 shows a schematic diagram of a spin logic device according to some embodiments of the present disclosure.

Fig. 3 shows a schematic diagram of an integrated storage and calculation device according to some embodiments of the present disclosure.

FIG. 4 shows a schematic diagram of a half adder according to some embodiments of the present disclosure.

FIG. 5 shows a schematic diagram of a carry calculation part of a full adder according to some embodiments of the present disclosure.

FIG. 6 shows a schematic diagram of a sum bit calculation part of a half adder according to some embodiments of the present disclosure.

FIG. 7 shows an equivalent circuit of a sum bit calculation part of a half adder in a first mode according to some embodiments of the present disclosure.

FIG. 8 shows an equivalent circuit of a sum bit calculation part of a half adder in a second mode according to some embodiments of the present disclosure.

In accordance with common practice, the various features shown in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Additionally, some figures may not depict all components of a given system, method, or device. Finally, like reference numerals may be used to refer to like features throughout the specification and drawings.

specific embodiment

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. The term "coupled" may indicate a direct connection between one component and another component, and may also include an indirect connection via other components. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

Any reference to direction or orientation is for convenience of description only and does not limit the scope of the present disclosure in any way. For example, "lower", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and "bottom" and their derivatives (such as "horizontal "ground", "upward", "downward", etc.) and related terms are used in the discussion to refer to orientations described below or shown in the accompanying drawings. These relative terms are for convenience of description only and do not require the device to be constructed or operated in a particular orientation.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

Embodiments of the present disclosure provide an improved spin logic device, which can be implemented in various logic circuits, for example, processors, etc., and can also be implemented in a memory-computing integrated device. For example, spin logic devices can be used to implement logic operations for applications in computing devices such as processors or controllers. Spin logic devices can be combined with each other to form various logic gates to realize logic operations. Further, by combining logic gates, duplicated computing functions can be realized to implement a processor or controller. Spin logic devices, logic gates, and processors or controllers can be arranged on a printed circuit board (PCB) to be incorporated in a variety of devices, such as computers, servers, laptops, desktops, mobile phones , cellular phones, personal digital assistants, wearables, or electronic devices such as set-top boxes, and can also be used in applications such as self-driving cars. In addition, a spin logic device that performs computation functions can be combined with a memory device for storing computation results to realize a memory-computing integrated device. All-in-one devices can be placed on a printed circuit board (PCB) to be incorporated into various devices such as computers, servers, laptops, desktops, mobile phones, cellular phones, personal digital assistants, wearable devices or set-top boxes and other electronic devices, and can also be used in applications such as self-driving cars.

FIG. 1A shows a schematic diagram of a spin logic device 10 according to some embodiments of the present disclosure. As shown in FIG. 1A , the spin logic device 10 includes a magnetic unit 5 , wherein FIG. 1B shows a perspective view of the magnetic unit 5 . FIG. 1A shows a cross-sectional view of the magnetic unit 5 perpendicular to the z-axis direction, ie, a cross-sectional view in the x-y plane. In other words, FIG. 1A shows a top view of the magnetic unit 5 of FIG. 1B . As shown in Figure 1B, the magnetic unit 5 includes a spin Hall effect (Spin Hall Effect, SHE) layer 52 and a ferromagnetic layer 53 arranged along the stacking direction, wherein the stacking direction is the z-axis direction, and the ferromagnetic layer 53 The magnetization direction is along the y-axis direction. The SHE layer 52 may include metal materials with spin Hall effect, for example, heavy metal materials, especially β-Ta, W, Pt and other materials with relatively large spin Hall effect. Alternatively, the SHE layer 52 may also include a topological insulator material. The ferromagnetic layer 53 may include various ferromagnetic materials such as Fe, Co, Ni and alloys thereof such as CoFeB and the like. In some embodiments, the ferromagnetic layer 53 may include a magnetic material having in-plane anisotropy, for example, CoFeB, CoFe, NiFe, and the like. As shown in FIG. 1B , a SHE layer 52 is formed over a substrate 51 , and a ferromagnetic layer 53 is formed over the SHE layer 52 . For example, the thickness of the SHE layer 52 and the ferromagnetic layer 53 may be in the range of several nanometers. In some embodiments, the in-plane anisotropy of the ferromagnetic layer 53 can be enhanced by increasing the thickness of the ferromagnetic layer 53 . In one embodiment, the SHE layer 52 and the ferromagnetic layer 53 can be grown on a thermally oxidized silicon substrate by magnetron sputtering.

The magnetization direction of the ferromagnetic layer 53 can be realized along the y-axis direction through a variety of different embodiments. In one embodiment, the ferromagnetic layer 53 has a first width along the x-axis direction and a second width along the y-axis direction. The first width may be smaller than the second width so that the magnetization direction of the ferromagnetic layer 53 is along the y-axis direction. In another embodiment, during the process of growing the ferromagnetic layer 53 , by applying a magnetic field along the y-axis direction, the ferromagnetic layer 53 can be induced to generate a magnetization direction along the y-axis direction.

As shown in FIG. 1A, the magnetic unit 5 includes a first port 1 on a first side, a second port 2 on a second side opposite to the first side along the x-axis direction, and a first port 1 and a second port 3 located at the first port 1 and the second port 3. The third port 3 between and above the magnetic unit 5 . The first port 1 is coupled to the first terminal 11 of the spin logic device 10, the second port 2 is coupled to the second terminal 12 of the spin logic device 10, and the third port 3 is coupled to the third terminal of the spin logic device 13 coupling. For example, the first port 1 , the second port 2 and the third port 3 may be respectively coupled to the first terminal 11 , the second terminal 12 and the third terminal 13 through metal electrodes.

Figure 1B shows a first electrode 55, a second electrode 56 and a third electrode 57, wherein the first electrode 55 is used to couple the first port (not shown) of the magnetic unit 5 with the first end (not shown) The second electrode 56 is used to couple the second port (not shown) of the magnetic unit 5 with the second terminal (not shown), and the third electrode 57 is used to couple the third port (not shown) of the magnetic unit 5 Out) is coupled with a third terminal (not shown). Although not explicitly shown, in the embodiment of FIG. 1B , the first port of the magnetic unit 5 may be the portion of the SHE layer 52 in contact with the first electrode 55, and the first end of the spin logic device may be the first electrode 55. The part that connects with the external circuit. For the second port and the third port of the magnetic unit 5 and the second terminal and the third terminal of the spin logic device, no more details are given here. It should be understood that although the first electrode 55 and the second electrode 56 are only in contact with the SHE layer 52 in FIG. 1B , the first electrode 55 and the second electrode 56 may have other configurations. For example, the first electrode 55 and the second electrode 56 may have the same height as the stack of the SHE layer 52 and the ferromagnetic layer 53 . For another example, the height of one of the first electrode 55 and the second electrode 56 is different from that of the other electrode. In an embodiment where the SHE layer 52 includes a metal layer, both the SHE layer 52 and the ferromagnetic layer 53 are conductive, therefore, the first electrode 55 and the second electrode 56 are in contact with at least a part of the SHE layer 52 and the ferromagnetic layer 53. . In an embodiment where the SHE layer 52 contains a topological insulator, the inside of the SHE layer 52 may not conduct electricity, but only generate current on the surface, which may require contacting the first electrode 55 and the second electrode 56 with the ferromagnetic layer 53 .

As shown in FIG. 1A, the first terminal 11 of the spin logic device 10 is connected to a first voltage (for example, an input voltage Vin), and the second terminal 12 of the spin logic device 10 is coupled to a second voltage (for example, ground). catch. It should be understood that the second voltage may also be other voltages than ground. For convenience of discussion, the following will describe the embodiments of the present disclosure based on the input voltage Vin and ground. As shown in FIG. 1B , a first voltage may be applied to the first electrode 55 and a second voltage may be applied to the second electrode 56 . In this way, a voltage difference can be generated between the first electrode 55 and the second electrode 56 (ie, in the x-axis direction), thereby generating a write current in the x-axis direction in the SHE layer 52 . Under the action of the write current, the SHE layer 52 can generate spin-orbit torque by virtue of the spin Hall effect. Under the action of spin-orbit torque, due to the anomalous Hall effect (Anomalous Hall Effect, AHE) in the ferromagnetic layer 53, a Hall voltage is generated in the z-axis direction, resulting in a left voltage V ₁₃ and a right voltage V ₂₃ There is an asymmetry between them, wherein the left voltage V ₁₃ and the right voltage V ₂₃ respectively represent the voltage between the first terminal and the third terminal and the voltage between the second terminal and the third terminal.

Typically, the voltage asymmetry produced by the anomalous Hall effect is so small that it is difficult to detect. Asymmetry between voltages can be amplified by negative differential resistance. Negative differential resistance has the effect of further increasing large voltages and further reducing small voltages, therefore, asymmetry between voltages can be amplified. As shown in FIG. 1A , a first negative differential resistance (Negative Differential Resistance, NDR) 4 is coupled between the first terminal 11 and the third terminal 13 of the spin logic device 10 . The second negative differential resistor 6 is coupled between the second terminal 12 and the third terminal 13 of the spin logic device 10 . For example, the first NDR 4 and the second NDR 6 may be the same, or may have the same resistance characteristics. The first NDR 4 and the second NDR 6 can be realized by elements having a negative differential resistance effect such as complementary junction field effect transistors or resonant tunneling transistors. When the input voltage Vin is applied at the first end 11 , current flows along the x-axis direction in the magnetic unit 5 . Due to the anomalous Hall effect, a Hall voltage is generated in the direction of the z-axis, resulting in an asymmetry between the voltage _V13 across the first NDR 4 and the voltage _V23 across the second NDR 6, that is, one of _V13 and _V23 is One for high voltage and one for low voltage. If the magnetization direction of the magnetic unit 5 is changed, the Hall voltage is reversed, so that one of V ₁₃ and V ₂₃ is a low voltage and the other is a high voltage. During logic operation, the magnetization direction of the magnetic unit 5 is used as a logic input. For example, the direction of magnetization along the +y axis may be defined as a logic input "1" and the direction of magnetization along the -y axis may be defined as a logic input "0". Alternatively, it is also possible to define the magnetization direction along the +y-axis direction as a logic input "0" and the magnetization direction along the -y-axis direction as a logic input "1". The voltage magnitude of V ₁₃ and V ₂₃ may correspond to a logic output, for example, a high voltage is a logic output "1", and a low voltage is a logic output "0". The asymmetry of the output voltage caused by the abnormal Hall effect is not high, therefore, the first NDR 4 and the second NDR 6 can be used to amplify the asymmetry of the output voltage, so as to achieve the purpose of identifying the logic output.

In the embodiment shown in FIGS. 1A and 1B , the magnetic unit 5 is symmetrical with respect to an axis of symmetry, which lies in the yz plane and is parallel to the z axis. The first port 1 and the second port 2 are symmetrical with respect to the axis of symmetry, and the third port 3 is located on the axis of symmetry. According to this symmetrical structure, when no Hall voltage is generated in the magnetic unit 5, there is no asymmetry in the voltages V ₁₃ and V ₂₃ . Thus, when the Hall voltage is generated in the magnetic unit 5, this symmetrical structure is more conducive to creating a clear asymmetry in the voltages V ₁₃ and V ₂₃ , making it easier to identify the logic output. It should be understood that although FIGS. 1A and 1B show that the magnetic unit 5 has a square structure, the magnetic unit 5 may also have other shapes, especially other symmetrical shapes.

Current-mode spin logic devices represent different logic outputs through different current magnitudes. In order to distinguish between different logics, a larger current is required, so the device consumes more power. In contrast, voltage-mode spin logic devices do not require high current operation, thereby reducing device power consumption and improving device performance. In addition, the magnetic material of this voltage-type spin logic device is magnetized in-plane, does not need a magnetic field to assist magnetic moment reversal, and is easy to integrate.

FIG. 2 shows a schematic diagram of a spin logic device 100 according to some embodiments of the present disclosure. As shown in FIG. 2 , the spin logic device 100 includes a first magnetic unit 101 , a second magnetic unit 102 and a third magnetic unit 103 , and each magnetic unit can be realized by the magnetic unit 5 shown in FIG. 1 . The logic states of the first magnetic unit 101 , the second magnetic unit 102 and the third magnetic unit 103 may be represented by bits a, b and c, respectively.

As shown in FIG. 2 , the first magnetic unit 101 , the second magnetic unit 102 and the third magnetic unit 103 are coupled in parallel. In other words, the first port 1 of the first magnetic unit 101, the second magnetic unit 102, and the third magnetic unit 103 is coupled to the first terminal 111 of the spin logic device 100, and the first magnetic unit 101, the second magnetic unit 102, and The second port 2 of the third magnetic unit 103 is coupled to the second terminal 112 of the spin logic device 100, and the third port 3 of the first magnetic unit 101, the second magnetic unit 102, and the third magnetic unit 103 is coupled to the spin logic device 100. The third terminal 113 of the logic device 100 is coupled. In addition, the first NDR 104 is coupled between the first terminal 111 and the third terminal 113 of the spin logic device 100, and the second NDR 106 is coupled between the first terminal 112 and the third terminal 113 of the spin logic device 100 between. The first terminal 111 of the spin logic device 100 is coupled to the input voltage Vin, and the second terminal 112 of the spin logic device 100 is grounded.

By controlling the bit c, the spin logic device 100 can implement four logic operations of "AND", "OR", "NAND" and "NOR". For each magnetic unit 101-103, current flows in from the first terminal 1 and flows out from the second terminal 2 to ground. The magnetization directions of the first magnetic unit 101 and the second magnetic unit 102 may be logic inputs. For example, it is possible to define the magnetization direction along the +y axis as a logic input "1", and the -y axis direction as a logic input "0". The magnetization direction of the third magnetic unit 103 can be used as a bias condition to implement different logic operations. Voltages V ₁₃ and V ₂₃ may be logic outputs, where an output high voltage is a logic "1" and an output low voltage is a logic "0".

By controlling different logic inputs, bias conditions, and logic output channels, AND, OR, NAND, and NOR can be implemented. When the logic state of the third magnetic unit 103 is "0", the voltage V ₁₃ corresponds to "AND" (AND) logic, and the voltage V ₂₃ corresponds to "AND" (NAND) logic; the logic state of the third magnetic unit 103 When it is "1", the voltage V ₁₃ corresponds to "OR" (OR) logic, and the voltage V ₂₃ corresponds to "NOR" (NOR) logic. Table 1 shows the logic table of this embodiment. When the state (c) of the third magnetic unit 103 is "0", the logic inputs (a, b) of the first magnetic unit 101 and the second magnetic unit 102 are (1,1), (1,0), respectively, (0,1), (0,0), the voltage V ₁₃ is high potential ("1"), low potential ("0"), low potential ("0") and low potential ("0") respectively, Corresponds to the AND logic operation. In addition, the voltages V ₂₃ are respectively low potential (“0”), high potential (“1”), high potential (“1”), and high potential (“1”), corresponding to NAND logic operations. When the logic state of the third magnetic unit (bit c) is "1", the logic inputs (a, b) of the first magnetic unit 101 and the second magnetic unit 102 are (1,1), (1,0) respectively , (0,1), (0,0), the voltage V ₁₃ is high potential ("1"), high potential ("1"), high potential ("1") and low potential ("0") respectively , corresponding to the OR logic operation. Meanwhile, the output voltages of the input voltage V ₂₃ are respectively low potential (“0”), low potential (“0”), low potential (“0”) and high potential (“1”), corresponding to NOR logic operation. It should be understood that the above numbers are provided as examples only and that different devices may achieve different data results.

Table 1

FIG. 3 shows a schematic diagram of an integrated storage and calculation device 200 according to some embodiments of the present disclosure. As shown in FIG. 3 , the storage-computing integrated device 200 can implement logic operations and storage of output results at the same time. By combining the spin logic device 100 shown in FIG. 2 with a storage part, a memory-computing integrated device 200 can be formed. The first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 can all be realized by the magnetic unit 10 shown in FIG. 1 . The first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 are represented by bits a, b and c, respectively.

As shown in FIG. 3 , the first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 are coupled in parallel. The first NDR 204 is coupled between the first terminal 211 and the third terminal 213 of the integrated storage and calculation device 200, and the second NDR 206 is coupled between the second terminal 212 and the third terminal 213 of the integrated storage and calculation device 200 . The first terminal 211 of the integrated storage and calculation device 200 is coupled to the input voltage Vin, and the second terminal 212 of the integrated storage and calculation device 200 is grounded. The third terminal 213 of the integrated storage and calculation device 200 is coupled to the control terminal (ie, the gate) of the transistor 207, and the first terminal (eg, the source terminal or the drain terminal) of the transistor 207 is connected to the first terminal of the magnetic unit 205 (state d). One terminal 1 is coupled, and the second terminal (for example, the drain terminal or the source terminal) of the transistor 207 is grounded. In addition, the second terminal 2 of the magnetic unit 205 is coupled to the power supply V _DD to form a loop from the power supply V _DD to the ground.

For example, the initial state of the magnetic unit 205 can be set as logic "0", that is, the magnetization direction is the -y axis direction. When the logic part of the integrated storage and calculation device 200 outputs "0", the output voltage of the logic part is less than the turn-on voltage of the transistor 207, the transistor 207 is not conducting, and there is no current in the loop from the power supply V _DD to the ground, and the magnetic unit 205 The magnetization direction does not change and is "0". When the logic part of the integrated storage and calculation device 200 outputs "1", the output voltage of the logic part is greater than the turn-on voltage of the transistor 207, the transistor 207 is turned on, and there is a write current I _O flowing through the magnetic circuit in the loop from the power supply V _DD to the ground. Unit 205. Under the action of the spin-orbit torque caused by the write current _I0 , the magnetization direction of the magnetic unit 205 is reversed and turned into the +y-axis direction, that is, logic “1”, thereby completing the storage of the logic output result in the magnetic unit 205 . By changing the direction of the write current _IO , the logic operation on the magnetic unit 205 can be changed. For example, the power supply V _DD can be coupled to the first port 1 of the magnetic unit 205 , and the second port 2 of the magnetic unit 205 can be connected to the transistor 207 to change the direction of the write current I _O .

It should be understood that although transistor 207 is shown in FIG. 3 as a field effect transistor, any other suitable switch may be used to implement transistor 207 .

FIG. 4 shows a schematic diagram of a half adder 300 according to some embodiments of the present disclosure. As shown in FIG. 4, the half adder 300 includes two instances of the spin logic device 100 shown in FIG. Three magnetic units 303 and first NDR 304 and second NDR 306, the second example of spin logic device 100 includes first magnetic unit 351, second magnetic unit 352 and third magnetic unit 353 and first NDR 354 and second NDR 356. The logic input of the first magnetic unit 301 is bit a, and the logic input of the first magnetic unit 351 is bit

It is complementary to bit a. The logic input of the second magnetic unit 302 is bit b, and the logic input of the second magnetic unit 352 is bit b

It is complementary to bit b. The logic state of the third magnetic unit 303 is bit c ₁ , and the logic state of the third magnetic unit 353 is bit c ₂ . As shown in FIG. 2, an instance of spin logic device 100 can be used as a logic gate. For ease of discussion, the first instance of the spin logic device 100 is referred to as a first logic gate, and the second instance of the spin logic device 100 is referred to as a second logic gate. Through the control bits of the

third logic units

303 and 353 , an "exclusive OR" (XOR) of bits a and b can be realized, thereby realizing a half adder.

As described in conjunction with FIG. 2 , by changing the control bit c of the third logic unit, two types of logic gates, "NAND" and "NOR", can be generated. "Exclusive OR" can be realized by a combination of "NOR" logic gates:

Both the first logic gate and the second logic gate can be used to realize the "NOR" gate, wherein the logic input of one "NOR" gate is bit a and bit b, and the magnetization direction of the control bit c ₁ is the +y-axis direction ( logic "1"), thereby realizing a NOR b; the logic input of the other "NOR" gate is a bit

with bit

The magnetization direction of the two is opposite to that of bit a and bit b, and the magnetization direction of bit _c2 is controlled to the +y-axis direction (logic "1"), thereby realizing

The third terminal 313 of the first logic gate (aNORb) is coupled to the control terminal (eg, gate) of the transistor 307, and the second logic gate

The third terminal 363 of is coupled to the control terminal (eg, gate) of the transistor 309 .

Transistors

307 and 309 are coupled in parallel between magnetic unit 305 (bit d) and ground. First terminals (eg, source or drain) of

transistors

307 and 309 are connected in series with second port 2 of magnetic unit 305, second terminals (eg, drain or source) of

transistors

307 and 309 are grounded and the magnetic unit The first port 1 of 305 is coupled to the power supply V _DD so as to form a loop between the power supply and the ground.

When both the first logic gate and the second logic gate output "0", the

transistors

307 and 309 are not turned on, and there is no current in the loop. When one of the logic gates outputs “1”, at least one of the

transistors

307 and 309 is turned on, and a write current flows through the magnetic unit 305 in the loop. Under the action of the spin-orbit torque caused by the write current, the magnetization direction of the magnetic unit 305 is reversed. The preset magnetization direction of the magnetic unit 305 is the +y-axis direction (logic “1”). When at least one of the

transistors

307 and 309 is turned on, the write current I _O passes through the magnetic unit 305 . Under the action of the spin-orbit torque caused by the write current, the magnetization direction of the magnetic unit 305 is reversed and becomes the direction of the -y axis, that is, the "0" state. When the

transistors

307 and 309 are both off, no write current I _O passes through the magnetic unit 305, and the magnetization direction of the magnetic unit 305 remains "1". Therefore, the

transistors

307 and 309 and the magnetic unit 305 realize the "NOR" NOR of the output results of the two logic gates, thereby realizing (a NOR b)NOR

That is, the magnetic unit 305 stores the XOR operation result of bit a and bit b. Table 2 shows a logical table according to some embodiments of the present disclosure.

Table 2

According to some embodiments of the present disclosure, the spin logic devices 100 shown in FIG. 2 can be combined to form a full adder. The full adder can realize the addition operation of two binary digits (referred to as the first addend and the second addend respectively), and output the sum bit and the carry bit. In the spin logic device 100 shown in FIG. 2 , if the third magnetic unit 103 is used as a logic input bit instead of a control bit, the carry function can be realized. As shown in Table 3, the logic inputs Ai and Bi represent the first addend and the second addend, the logic input Ci-1 represents the carry number of the adjacent low bit, and the logic output C _i represents the carry number to the adjacent high bit.

table 3

FIG. 5 shows a schematic diagram of a carry calculation part 400 of a full adder according to some embodiments of the present disclosure. Same as the spin logic device 100, the carry calculation part 400 includes a first magnetic unit 401, a second magnetic unit 402 and a third magnetic unit 403, wherein the first magnetic unit 401, the second magnetic unit 402 and the third magnetic unit 403 are respectively Receives logic inputs Ai, Bi, and Ci-1. The first NDR 404 is coupled between the first terminal 411 and the third terminal 413, and the second NDR 406 is coupled between the second terminal 412 and the third terminal 413.

As shown in FIG. 5 , the third terminal 413 is coupled to the control terminal (for example, the gate) of the transistor 407, and the first terminal (for example, the source terminal or the drain terminal) of the transistor 407 is coupled to the second port 2 of the magnetic unit 405. connected, the second terminal (eg, the drain terminal or the source terminal) of the transistor 407 is grounded, and the first port 1 of the magnetic unit 405 is coupled to the power supply V _DD .

As shown in Table 3, the initial state of the magnetic unit 405 may be set to logic "1". When the carry calculation part 400 outputs "0", the output voltage is lower than the turn-on voltage of the transistor 407, the transistor 407 is not turned on, and there is no current in the loop from the power supply V _DD to the ground, and the logic state of the magnetic unit 405 remains unchanged, which is "1". When the carry calculation part 400 outputs "1", the output voltage is greater than the turn-on voltage of the transistor 407, the transistor 407 is turned on, and a write current flows through the magnetic unit 405 in the loop from the power supply V _DD to the ground. Under the action of the spin-orbit torque caused by the write current, the magnetization direction of the magnetic unit 405 is reversed, corresponding to logic "0", thereby completing information storage.

FIG. 6 shows a schematic diagram of a sum bit calculation part 500 of a full adder according to some embodiments of the present disclosure. The sum bit of the full adder can be realized by combining the half adder 300 ("exclusive OR" XOR) shown in Figure 4:

Si=SUM(Ai,Bi,Ci-1)=(Ai XOR Bi)XOR Ci-1.

As shown in FIG. 6, the sum bit calculation part 500 includes a first magnetic unit 501 (logic input Ai), a second magnetic unit 502 (logic input Bi), a third magnetic unit 503 (control bit c ₁ ), a first NDR 504 , second NDR 506, first magnetic unit 551 (logic input

Complement of logic input Ai), second magnetic unit 552 (logic input

Complement of logic input Bi), third magnetic unit 553 (control bit c ₂ ), first NDR 554 and second NDR 556 . In addition, the sum bit calculation part 500 also includes a first magnetic unit 521 (logic input is Ii), a second magnetic unit 522 (logic input Ci-1), a third magnetic unit 523 (control bit c ₃ ), a first NDR 524 , second NDR 526, first magnetic unit 571 (logic input

Complement of logic input Ii), second magnetic unit 572 (logic input

Complement of logic inputs Ci−1), third magnetic unit 573 (control bit c ₄ ), first NDR 574 and second NDR 576 .

In this embodiment, as shown in Table 3, the initial states of bit I _i and bit S _i may be logic "1", that is, the magnetization direction is the +y-axis direction. The logical operations shown in Table 3 are similar to the logical operations described in conjunction with FIG. 4 , and will not be repeated here.

In addition, sum bit calculation section 500 also includes

transistors

505 , 525 , 555 and 575 , which may operate as described in connection with FIG. 4 . The sum bit calculation part 500 may further include a switch circuit for switching the sum bit calculation part 500 between the first mode and the second mode. In the example shown in FIG. 6, the switching circuit includes transistors 531-542. For example, the second port 2 of the first magnetic unit 521 is selectively coupled to the second port 2 of the first magnetic unit 571 via the transistor 537 . FIG. 7 shows an equivalent circuit 600 of the first mode of the sum bit calculation section 500 , and FIG. 8 shows an equivalent circuit 700 of the second mode of the sum bit calculation section 500 . The equivalent circuit 600 realizes the "exclusive OR" operation of bit A _i and bit B _i , and stores the operation result in the middle bit I _i and

That is, I _i =A _i XOR B _i . The equivalent circuit 700 realizes the "exclusive OR" operation of bit I _i and bit C _i-1 , and stores the operation result in the sum bit S _i , that is, S _i =I _i XOR C _i-1 =(A _i XOR B _i ) XOR C _i-1 . The calculation of the sum bit can be realized by operating the sum bit calculating section 500 alternately in the first mode and the second mode.

In some embodiments, the sum bit calculation part 500 further includes a controller 510 to realize automatic switching between the first mode and the second mode. The controller 510 may operate under the control of a clock CLK, and may include a first output Q ₁ and a second output Q ₂ . The first output _Q1 is coupled to control terminals (eg, gates) of the

transistors

531 , 533 , 537 and 538 for turning on and off the

transistors

531 , 533 , 537 and 538 . The second output _Q2 is coupled to the control terminals (eg, gates) of the

transistors

532, 534, 535, 536, 539, 541, and 542 for turning on and off the

transistors

532, 534, 535, 536, 539, 541 and 542.

During a first period of time (eg, the first part of a clock cycle), the first output _Q1 may turn on

transistors

531, 533, 537, and 538, and the second output _Q2 may turn on

transistors

532, 534, 535, 536, 539, 541 and 542 are off. FIG. 7 shows a schematic diagram of the sum bit calculation section 500 in this state. As shown in Figure 7, the circuit 600 implements the "exclusive OR" operation of bit A _i and bit B _i , and stores the operation result in the middle bit I _i and

That is, I _i =A _i XOR B _i .

During a second period of time (eg, another portion of a clock cycle), the first output _Q1 may turn

transistors

531, 533, 537, and 538 off, and the second output _Q2 may turn

transistors

532, 534, 535, 536, 539, 541 and 542 are turned on. FIG. 8 shows a schematic diagram of the sum bit calculation section 500 in this state. As shown in FIG. 8 , the circuit diagram 700 implements the "exclusive OR" operation of bit I _i and bit C _i-1 , and stores the operation result in the sum bit S _i , that is, S _i =I _i XOR C _i-1 =( A _i XOR B _i )XOR C _i-1 .

Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can easily understand from this disclosure that, according to this disclosure, existing or future developed processes and machine devices that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in this disclosure can be used , manufacture, composition of matter, tool, method or step. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and combinations of individual claims and embodiments are within the scope of the present disclosure.

Claims

A spin logic device comprising:

A first magnetic unit, the first magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the first magnetic unit, the first magnetic unit is included in the first magnetic unit of the first magnetic unit A first port on one side, a second port on a second side opposite to the first side along a second direction of the first magnetic unit, and a first port located between the first magnetic unit and the first magnetic unit Between the second port of the unit and the third port above the first magnetic unit, the second direction is perpendicular to the first direction, the first port of the first magnetic unit is connected to the spin logic The first terminal of the device is coupled, the second port of the first magnetic unit is coupled to the second terminal of the spin logic device, and the third port of the first magnetic unit is coupled to the spin logic device The third terminal coupling;

a first negative differential resistor coupled between the first terminal and the third terminal of the spin logic device; and

The second negative differential resistor is coupled between the second terminal and the third terminal of the spin logic device.
The spin logic device according to claim 1, wherein the first magnetic unit is symmetrical with respect to a symmetry axis parallel to the first direction, and the second port of the first magnetic unit is connected to the second port of the first magnetic unit. A first port of a magnetic unit is symmetrical with respect to the axis of symmetry, and a third port of the first magnetic unit is located on the axis of symmetry.
The spin logic device according to claim 1, characterized in that,

The first terminal of the spin logic device is configured to be coupled to a first voltage, and the second terminal of the spin logic device is configured to be coupled to a second voltage to generate a first voltage in the spin logic device. current flow between one terminal and a second terminal of the spin logic device; and

The spin logic device is configured to output a third voltage representing a first logic output between the first terminal of the spin logic device and the third terminal of the spin logic device, and/or the spin logic device A logic device for outputting a fourth voltage representing a second logic output between the second terminal of the spin logic device and the third terminal of the spin logic device.
The spin logic device of claim 1, wherein the magnetization direction represents a logic input of the first magnetic unit.
The spin logic device according to claim 1, wherein at least one of the first negative differential resistance and the second negative differential resistance comprises: a complementary junction field effect transistor or a resonant tunneling diode.
The spin logic device according to claim 1, wherein the spin Hall effect layer comprises at least one of the following: a heavy metal layer or a topological insulator layer.
The spin logic device of claim 1 , wherein in response to a write current between the first port of the first magnetic unit and the second port of the first magnetic unit, the magnetization direction A rollover occurs.
The spin logic device according to any one of claims 1-7, further comprising:

A second magnetic unit, the second magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the second magnetic unit, the second magnetic unit is included in the second magnetic unit The first port on the first side of the second magnetic unit, the second port on the second side opposite to the first side of the second magnetic unit along the second direction of the second magnetic unit, and the second port located at the second magnetic unit Between the first port and the second port of the second magnetic unit and the third port above the second magnetic unit, the second direction of the second magnetic unit is perpendicular to the first direction of the second magnetic unit A direction, wherein the first port of the second magnetic unit is coupled to the first end of the spin logic device, and the second port of the second magnetic unit is coupled to the second end of the spin logic device connected, and the third port of the second magnetic unit is coupled to the third terminal of the spin logic device; and

A third magnetic unit, the third magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the third magnetic unit, the third magnetic unit is included in the third magnetic unit The first port on the first side of the third magnetic unit, the second port on the second side opposite to the first side of the third magnetic unit along the second direction of the third magnetic unit, and the Between the first port and the second port of the third magnetic unit and the third port above the third magnetic unit, the second direction of the third magnetic unit is perpendicular to the first port of the third magnetic unit In one direction, the first port of the third magnetic unit is coupled to the first end of the spin logic device, and the second port of the third magnetic unit is coupled to the second end of the spin logic device , and the third port of the third magnetic unit is coupled to the third terminal of the spin logic device.
The spin logic device according to claim 8, characterized in that,

the magnetization direction of the first magnetic unit is indicative of a logic input of the first magnetic unit;

the magnetization direction of the second magnetic unit is indicative of a logic input to the second magnetic unit; and

the spin logic device is configured to output a third voltage representing a first logic output of the spin logic device between a first terminal of the spin logic device and a third terminal of the spin logic device, wherein if the magnetization direction of the third magnetic unit is the first magnetization direction, the first logic output acts as a first logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit, and if The magnetization direction of the third magnetic unit is the second magnetization direction, then the first logic output acts as a second logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit, and/or the The spin logic device is configured to output a fourth voltage representing a second logic output of the spin logic device between the second terminal of the spin logic device and the third terminal of the spin logic device, wherein If the magnetization direction of the third magnetic unit is the first magnetization direction, the second logic output operates as a third logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit, and if the If the magnetization direction of the third magnetic unit is the second magnetization direction, the second logic output serves as a fourth logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit.
The spin logic device according to claim 9, wherein the first logic operation and the second logic operation include "AND" and "NOR", and the third logic operation and the first Four logical operations including "AND" and "OR".
A memory-computing integrated device, comprising:

The spin logic device according to any one of claims 8-10;

a transistor, the control terminal of which is coupled to the third terminal of the spin logic device;

A fourth magnetic unit, the fourth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along the first direction of the fourth magnetic unit, the fourth magnetic unit is included in the fourth magnetic unit The first port on the first side of the fourth magnetic unit and the second port on the second side opposite to the first side of the fourth magnetic unit along the second direction of the fourth magnetic unit, the first port of the fourth magnetic unit The two directions are perpendicular to the first direction of the fourth magnetic unit, the first port of the fourth magnetic unit is coupled to the first terminal of the transistor, and the second port of the fourth magnetic unit is coupled to power supply.
The storage and calculation integrated device according to claim 11, characterized in that,

The fourth magnetic unit is symmetrical with respect to a symmetry axis parallel to the first direction of the fourth magnetic unit, and the second port of the fourth magnetic unit is the same as the first port of the fourth magnetic unit with respect to the symmetry axis of the fourth magnetic unit. The first ports of the four magnetic units are symmetrical.
The storage and calculation integrated device according to claim 12, characterized in that,

The write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit.
A half adder consisting of:

A first NOR gate comprising a spin logic device according to any one of claims 8-10;

A second NOR gate, comprising the spin logic device according to any one of claims 8-10, the first end of the first NOR gate is coupled to the first end of the second NOR gate , the second end of the first NOR gate is coupled to the second end of the second NOR gate, the first magnetic unit of the first NOR gate and the first magnetic unit of the second NOR gate the logic inputs of the magnetic units are complementary, and the logic inputs of the second magnetic unit of the first NOR gate and the second magnetic unit of the second NOR gate are complementary;

a first switch, the control terminal of the first switch is coupled to the third terminal of the first NOR gate;

a second switch, the control terminal of the second switch is coupled to the third terminal of the second NOR gate; and

A fifth magnetic unit, the fifth magnetic unit including a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the fifth magnetic unit, the fifth magnetic unit included in the fifth magnetic unit The first port on the first side of the fifth magnetic unit and the second port on the second side opposite to the first side of the fifth magnetic unit along the second direction of the fifth magnetic unit, the first port of the fifth magnetic unit The two directions are perpendicular to the first direction of the fifth magnetic unit, the first port of the fifth magnetic unit is coupled to a power supply, and the second port of the fifth magnetic unit is connected to the first switch and the first switch. Two switches are coupled.
The half adder according to claim 14, wherein,

A write current of the fifth magnetic unit has a direction from a first port of the fifth magnetic unit to a second port of the fifth magnetic unit.
A full adder comprising:

A first NOR gate, comprising a spin logic device according to any one of claims 8-10, wherein the logic input of the first magnetic unit of the first NOR gate is a first addend, and the The logic input of the second magnetic unit of the first NOR gate is a second addend;

A second NOR gate, comprising the spin logic device according to any one of claims 8-10, the first end of the first NOR gate is coupled to the first end of the second NOR gate , the second terminal of the first NOR gate is coupled to the second terminal of the second NOR gate, wherein the logic input of the first magnetic unit of the second NOR gate is the complement of the first addend number, and the logic input of the second magnetic unit of the second NOR gate is the complement of the second addend;

a first switch, the control terminal of the first switch is coupled to the third terminal of the first NOR gate;

A second switch, the control end of the second switch is coupled to the third end of the second NOR gate, the first end of the second switch is coupled to the first end of the first switch to provide first logic output;

The third NOR gate, comprising the spin logic device according to any one of claims 8-10, wherein the logic input of the second magnetic unit of the third NOR gate is the carry number of the adjacent lower bit;

A fourth NOR gate, comprising the spin logic device according to any one of claims 8-10, the first end of the third NOR gate is coupled to the first end of the fourth NOR gate , the second end of the third NOR gate is coupled to the second end of the fourth NOR gate, the second port of the first magnetic unit of the third NOR gate is connected to the fourth NOR gate The second port of the first magnetic unit of the gate is coupled, and the first port of the first magnetic unit of the fourth NOR gate is coupled to the first logic output, wherein the fourth NOR gate The logic input of the two magnetic units is the complement of the carry number of the adjacent low bit;

a third switch, the control terminal of the third switch is coupled to the third terminal of the third NOR gate;

a fourth switch, the control terminal of the fourth switch is coupled to the third terminal of the fourth NOR gate;

A sixth magnetic unit, the sixth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer stacked along a first direction of the sixth magnetic unit, the sixth magnetic unit is included in the sixth magnetic unit The first port on the first side of the sixth magnetic unit and the second port on the second side opposite to the first side of the sixth magnetic unit along the second direction of the sixth magnetic unit, the first port of the sixth magnetic unit The two directions are perpendicular to the first direction of the sixth magnetic unit, the first port of the sixth magnetic unit is coupled to a power supply, and the second port of the sixth magnetic unit is connected to the third switch and the a fourth switch coupled to the sixth magnetic unit for storage and bit;

switch circuit for activating said first NOR gate and said second NOR gate for a first period of time to store a first logic output in said third NOR gate's first magnetic unit and to A second logic output complementary to the first logic output is stored in the first storage unit of the fourth NOR gate, and during a second time period, the third NOR gate and the fourth NOR gate are activated , to store a logic output at said sixth magnetic unit; and

The integrated storage and calculation device according to any one of claims 11-13, wherein the logic input of the first magnetic unit of the storage and calculation integrated device is the value of the first addend, and the second of the storage and calculation integrated device The logical input of the magnetic unit is the value of the second addend, the logical input of the third magnetic unit of the integrated storage and calculation device is the carry number of the adjacent low bit, and the fourth magnetic unit of the integrated storage and calculation device stores High carry digits.
The full adder according to claim 16, wherein,

a write current of the sixth magnetic unit has a direction from a first port of the sixth magnetic unit to a second port of the sixth magnetic unit; and

The write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit.
A device comprising:

printed circuit boards; and

The spin logic device according to any one of claims 1-10, the spin logic device is arranged on the printed circuit board.
A device comprising:

printed circuit boards; and

According to the integrated storage and calculation device according to any one of claims 11-13, the integrated storage and calculation device is arranged on the printed circuit board.
A device comprising:

printed circuit boards; and

The half adder according to any one of claims 14-15, the half adder is arranged on the printed circuit board.
A device comprising:

printed circuit boards; and

The full adder according to any one of claims 16-17, the full adder is arranged on the printed circuit board.