WO2023020470A1 - Storage motherboard based on feiteng processor - Google Patents

Storage motherboard based on feiteng processor Download PDF

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Publication number
WO2023020470A1
WO2023020470A1 PCT/CN2022/112722 CN2022112722W WO2023020470A1 WO 2023020470 A1 WO2023020470 A1 WO 2023020470A1 CN 2022112722 W CN2022112722 W CN 2022112722W WO 2023020470 A1 WO2023020470 A1 WO 2023020470A1
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WO
WIPO (PCT)
Prior art keywords
power supply
capacitor
output interface
controller
chip
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PCT/CN2022/112722
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French (fr)
Chinese (zh)
Inventor
李修录
尹善腾
朱小聪
吴健全
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深圳市安信达存储技术有限公司
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Publication of WO2023020470A1 publication Critical patent/WO2023020470A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiment of the utility model relates to the field of chip technology, in particular to a storage motherboard based on a Phytium processor.
  • the storage disk of the existing Phytium processor is usually integrated with PCIe transmission data differential pin pairs for data storage, but the number of PCIe transmission data differential pin pairs integrated in the storage disk of the existing Phytium processor is limited, resulting in Some storage disks of Phytium processors cannot meet the demand for large-capacity and fast storage of data in the information age.
  • the embodiment of the present utility model provides a storage motherboard based on the Feiteng processor, which is used to solve the problems of small storage capacity and low storage efficiency of the storage disk of the existing Feiteng processor.
  • the utility model provides a storage motherboard based on a Feiteng processor, comprising:
  • Embedded memory chip the board is pasted on described Feiteng processor, and described embedded memory chip is connected with described Feiteng processor; Described embedded memory chip comprises controller, flash memory and buffer memory, and described controller is connected described flash memory and The cache; the embedded memory chip is used to store the data to be processed transmitted by the Feiteng processor.
  • the embedded memory chip is provided with four sets of first PCIe transmission data differential pin pairs;
  • the Feiteng processor is provided with two sets of second PCIe transmission data differential pin pairs and two sets of third PCIe transmission data differential pin pairs;
  • two sets of first PCIe transmission data differential pin pairs are respectively corresponding to the two second PCIe transmission data differential pin pairs, and wherein two groups of first PCIe transmission data differential pin pairs are respectively connected to the corresponding second PCIe transmission data differential pin pairs.
  • the differential pin pairs of PCIe transmission data are connected in communication to realize signal transmission; the other two first PCIe transmission data differential pin pairs correspond to the two third PCIe transmission data differential pin pairs one by one, and the other two groups
  • the first differential pin pair for PCIe transmission data is communicatively connected with the corresponding third differential pin pair for PCIe transmission data, so as to realize signal transmission.
  • the embedded memory chip further includes a bus controller, and the controller is connected to the bus controller;
  • Described flashing memory comprises Flash controller and Flash flash memory chip array; Described Flash controller is connected with described Flash flash memory chip array and described bus controller respectively;
  • the cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected to the DDR3 DRAM storage array and the bus controller respectively.
  • the storage motherboard further includes a power supply circuit
  • the power supply circuit includes a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;
  • the first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
  • the first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface;
  • the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
  • the first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller, and the first output interface is connected to the first One end of a capacitor, the other end of the first capacitor is grounded;
  • the second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
  • the second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
  • the second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
  • the second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
  • the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with One or more third decoupling capacitors for energy storage.
  • controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
  • the storage motherboard based on the Phytium processor provided by the embodiment of the utility model is pasted on the Phytium processor through an embedded memory chip board, and the embedded memory chip installed on the Phytium processor occupies a small space and has good shock resistance;
  • the storage chip has a high degree of integration, and the data is stored through the Phytium processor combined with the embedded memory chip, which increases the capacity of data storage and improves the efficiency of data storage, which can meet the requirements of large-capacity storage and fast storage of data in the information age. storage needs.
  • FIG. 1 is a schematic diagram of the overall structure of a storage motherboard based on a Feiteng processor according to an embodiment of the present invention
  • FIG. 1-1 is a schematic structural diagram of the embedded memory chip in the storage motherboard based on the Phytium processor according to the embodiment of the present invention
  • FIG. 2 is a schematic circuit diagram of a first power supply circuit in a storage motherboard based on a Feiteng processor according to an embodiment of the present invention
  • FIG. 3 is a schematic circuit diagram of a second power supply circuit in a storage motherboard based on a Phytium processor according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the circuit connection of one or more first decoupling capacitors in the storage motherboard based on the Phytium processor according to the embodiment of the present invention
  • FIG. 5 is a schematic diagram of circuit connections of one or more second decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of circuit connections of one or more second decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of circuit connection of one or more third decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention.
  • Feiteng processor also known as Feiteng platform, Feiteng processor can be FT2000/4 core.
  • FT2000/4-core series processors are mainly for desktop applications and high-end embedded applications. This series includes 8 products. It is a high-performance general-purpose processor for desktop applications. It integrates four 64-bit high-performance nuclear. The main frequency is 2.6GHz, and the built-in password acceleration engine is a nationally produced CPU in my country (Central Processing Unit / Processor, one of the central processing unit).
  • the embedded storage chip may be an AXD PCIe NVMe BGA SSD embedded storage chip; it is a self-developed BGA that integrates NAND Flash flash memory, DRAM cache, and a self-developed controller Package embedded memory chips.
  • the storage disks of domestic chip platforms such as the Feiteng platform are all standard solid-state hard disks, such as solid-state hard disks of mSATA (mini-SATA, a mini-version SATA interface, which is a computer bus), 7+15PIN (chip ) interface solid-state hard disk, at least the following defects:
  • the data stored in the solid-state hard drive of the existing Phytium platform usually uses the SATA protocol (Serial Advanced Technology Attachment, a protocol used to transmit signals through an industry-standard serial hardware drive interface) or the USB protocol (Universal Serial Bus, a A protocol used to transmit signals through the universal serial bus) for data transmission, the upper limit of the speed is not high, and it cannot meet the processing needs of big data in the information age.
  • SATA protocol Serial Advanced Technology Attachment, a protocol used to transmit signals through an industry-standard serial hardware drive interface
  • USB protocol Universal Serial Bus, a A protocol used to transmit signals through the universal serial bus
  • the present invention aims to provide a data storage scheme based on Feiteng processor, in this scheme:
  • the data transmission protocol between the self-developed AXD PCIe NVMe embedded memory chip and the Phytium platform is PCIe3.0X4, with a bandwidth of 8GB/s and a high speed limit, which can meet the needs of big data processing in the information age.
  • the self-developed AXD PCIe NVM embedded memory chip is a BGA-packaged embedded memory chip that integrates NAND Flash flash memory, DRAM cache, and a self-developed controller. The chain from the CPU to the domestic storage medium.
  • One or more embodiments will be provided below to specifically introduce the data storage solution based on the Feiteng processor.
  • FIG. 1 it schematically shows the overall structure of a storage motherboard 1 based on a Phytium processor according to an embodiment of the present invention.
  • the storage motherboard 1 based on the Feiteng processor includes: the Feiteng processor 2 and an embedded memory chip 3, and the embedded memory chip 3 is attached to the Feiteng processor 2.
  • the embedded memory chip 3 is connected to the Feiteng processor 2; the embedded memory chip 3 includes a controller 4, flash memory and cache memory, and the controller 4 is connected to the flash memory and the cache memory; the embedded memory chip 3 It is used for storing the data to be processed transmitted by the Feiteng processor 2 .
  • the Phytium processor 2 is an FT-2000/4 chip.
  • Embedded memory chip can be AXD PCIe NVMe BGA SSD embedded memory chip. Described flash memory can be NAND Flash flash memory 5.
  • the cache can be DRAM cache 6 (Dynamic Random Access Memory, dynamic random access memory).
  • the board paste is a point-to-point connection
  • the space occupied by the embedded memory chip 3 on the Feiteng processor 2 is small, and the connection between the embedded memory chip 3 and the Feiteng processor 2 is effectively improved. shock resistance.
  • the embedded memory chip 3 has a high degree of integration; the interface of the memory main board 1 is rich in types, which can meet various usage demands of users for memory products.
  • the embedded memory chip 3 is provided with four sets of first PCIe transmission data differential Pin pair;
  • the Feiteng processor 2 is provided with two groups of second PCIe transmission data differential pin pairs and two groups of third PCIe transmission data differential pin pairs; wherein the first two groups of PCIe transmission data differential pin pairs are connected respectively The two sets of second differential pin pairs for PCIe transmission data, and the other two sets of first differential pin pairs for PCIe transmission data are respectively connected to the two sets of third differential pin pairs for PCIe transmission data.
  • the corresponding relationship between the four first PCIe transmission data differential pin pairs and the two second PCIe transmission data differential pin pairs and the two third PCIE transmission data differential pin pairs follows RX and TX one-to-one Corresponding principle, wherein, RX means receive differential signal, TX means send differential signal, P means positive pole, and N means negative pole.
  • the embedded storage chip 3 also includes a bus controller, and the controller 4 is connected to the bus controller;
  • the flash memory includes a Flash controller and a Flash controller. Flash memory chip array;
  • the Flash controller is connected with the Flash flash memory chip array and the bus controller respectively;
  • the cache includes a DRAM controller and a DDR3 DRAM storage array;
  • the DRAM controller is connected with the DDR3 DRAM storage The array is connected to the bus controller.
  • the flash memory and the cache are controlled by the controller 4 to realize the data storage function of the embedded memory chip 3 .
  • the embedded memory chip 3 realizes the signal transmission between its internal modules and realizes the connection between the embedded memory chip 3 and the external processor through the PCIe bus (peripheral component interconnect express, which is a high-speed serial computer expansion bus standard). (such as Phytium processor 2) through the signal transmission of the PCIe end.
  • the PCIe bus includes a PCIe physical layer
  • the PCIe physical layer is the bottom layer of the PCIe bus
  • the PCIe physical layer also includes a PCIe MAC (Media Access Control, media data storage control) layer.
  • PCIe NVMe standard an industry standard for SSDs based on the PCIe protocol.
  • Described embedded storage chip 3 comprises bus controller, dual-core CPU (ie controller 4), RAID codec, Flash controller, Flash flash memory chip array, security engine, main system buffer zone, DMA controller, DRAM controller And DDR3 DRAM (a cache product of computer memory specification), in which the bus controller is connected to the dual-core CPU, RAID codec (Redundant Arrays of Independent Disks, disk array codec), Flash controller, security engine, main system buffer, DMA controller (Direct Memory Access, direct memory access, a controller that allows hardware devices of different speeds to communicate) and The DRAM controller, the Flash controller is connected to the Flash memory chip array, and the DRAM controller is connected to the DDR3 DRAM.
  • dual-core CPU ie controller 4
  • RAID codec Redundant Arrays of Independent Disks, disk array codec
  • Flash controller security engine
  • main system buffer main system buffer
  • DMA controller Direct Memory Access, direct memory access, a controller that allows hardware devices of different speeds to communicate
  • the controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
  • BGA All Grid Array
  • BGA packaging technology is a ball grid array packaging technology, which is a high-density surface mount packaging technology.
  • Embedded memory chips using BGA packaging technology have smaller volume, faster and more effective heat dissipation performance and electrical performance under the same capacity.
  • the storage motherboard 1 also includes a power supply circuit, and the power supply circuit includes a first power supply circuit connected to the first power supply chip and a power supply circuit connected to the first power supply chip. A second power supply circuit connected to the second power supply chip;
  • the first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
  • the first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface;
  • the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
  • the first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller 4, and the first output interface is connected to the one end of the first capacitor, and the other end of the first capacitor is grounded;
  • the second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
  • the second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
  • the second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
  • the second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
  • FIG. 2 schematically shows a schematic diagram of a power supply circuit of the first power supply circuit
  • FIG. 3 schematically shows a schematic diagram of a second power supply circuit. details as follows:
  • the first power supply circuit As shown in Figure 2, the first power supply circuit:
  • the first power supply circuit includes a first power supply chip, and the first power supply chip includes multiple sets of first power input interfaces, such as two sets of VIN1, two sets of VIN2, two sets of VIN3 and VIN, and the multiple sets of first The power input interface is connected to the external power supply H33V.
  • first power input interface is connected to the external power supply H33V.
  • two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through wires, all of which are connected to the external power supply H33V.
  • Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected to a capacitor and then grounded.
  • the first power supply chip also includes a first output interface VOUT3 (such as pin G1) and a second output interface, and the second output interface includes a second main output interface VOUT1 (such as pins D5, D6) and a second I/O output interface VOUT2 (such as pin E6);
  • the first power supply circuit includes a first inductor L3 for elegance, a second inductor L2 for voltage stabilization, a first capacitor C19 for coupling, and The second capacitor C10 for coupling and the third capacitor C16 for coupling.
  • the first power supply circuit also includes a first inductance connection interface LX3 (such as pins F3 and G3), the first inductance connection interface LX3 is connected to one end of the first inductance L3, and the other end of the first inductance L3 Connect the first output interface VOUT3 to the input terminal VCCK of the controller 4 (such as pins G7, G8, G11, G12, H7, H8, H11, H12, J7, J8, J11, J12), the first An output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor C19 is grounded.
  • a first inductance connection interface LX3 such as pins F3 and G3
  • the first inductance connection interface LX3 is connected to one end of the first inductance L3, and the other end of the first inductance L3 Connect the first output interface VOUT3 to the input terminal VCCK of the controller 4 (such as pins G7, G8, G11, G12, H7, H8, H
  • the second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory (such as pins D10, E9, E10, W9, W10, Y9, Y10), and the second main output interface VOUT1 is connected to the second One end of the capacitor C10, and the other end of the second capacitor C10 are grounded.
  • the first power supply circuit also includes a second inductance connection interface LX2 (such as pins F5 and F6), the second inductance connection interface LX2 is connected to one end of the second inductance L2, and the other end of the second inductance L2 Connect the second I/O output interface VOUT2 and the second input terminal VCCFQ of the flash memory (such as pins R8, R11, R12, T7, T8, T11, T12, U7, U8, U11, U12), the The second I/O output interface VOUT2 is connected to one end of the third capacitor C16, and the other end of the third capacitor C16 is grounded.
  • a second inductance connection interface LX2 such as pins F5 and F6
  • the second inductance connection interface LX2 is connected to one end of the second inductance L2
  • the other end of the second inductance L2 Connect the second I/O output interface VOUT2 and the second input terminal VCCFQ of the flash memory (such as pins R8, R11, R
  • the first power supply circuit also includes a first ground interface PGND1 (such as pin A5, A6), a second ground interface PGND2 (such as pin E5), a third ground interface PGND3 (such as pin F4, G4) and a fourth Ground interface AGND (such as pin C1).
  • PGND1 such as pin A5, A6
  • PGND2 such as pin E5
  • PGND3 such as pin F4, G4
  • fourth Ground interface AGND such as pin C1
  • the second power supply circuit As shown in Figure 3, the second power supply circuit:
  • the second power supply circuit includes a second power supply chip, the second power supply chip includes a second power input interface VIN and an enable pin EN, and the second power input interface VIN and the enable pin EN Connect the external power supply H33V; the second power supply circuit includes a fourth capacitor C23 for coupling;
  • the second power supply chip also includes a third output interface VOUT, the third output interface VOUT is connected to the input terminal V18 of the buffer (such as pin R7), and the third output interface VOUT is connected to the fourth capacitor one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.
  • the second power supply chip also includes ground terminals, such as GND and SGND.
  • the first power supply circuit is connected to one or more A first decoupling capacitor for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with one or more third decoupling capacitors for energy storage.
  • the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor Through the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor, the interference of other signals is avoided during signal transmission, and the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor are all It has the function of caching energy.
  • the first decoupling capacitor includes capacitor C6542, capacitor BC46, capacitor BC47, and capacitor BC49, wherein one end of capacitor C6542 is connected to the input terminal VCCK of the controller 4, and one end of capacitor C6542 is connected to the terminal of capacitor BC46.
  • One end, the other end of capacitor C6542 is connected to the other end of capacitor BC46, and the other end of capacitor C6542 is grounded;
  • one end of capacitor BC46 is connected to one end of capacitor BC47, the other end of capacitor BC46 is connected to the other end of capacitor BC47;
  • one end of capacitor BC47 is connected to capacitor One end of BC49 and the other end of capacitor BC47 are connected to the other end of capacitor BC49.
  • the second decoupling capacitor includes a capacitor C5437, a capacitor BC48, a capacitor BC35, and a capacitor BC40, wherein one end of the capacitor C5437 is connected to the first input terminal VCC3F of the flash memory, and one end of the capacitor C5437 is connected to one end of the capacitor BC48 , the other end of capacitor C5437 is connected to the other end of capacitor BC48, and the other end of capacitor C5437 is grounded; one end of capacitor BC48 is connected to one end of capacitor BC35, the other end of capacitor BC48 is connected to the other end of capacitor BC35; one end of capacitor BC35 is connected to capacitor BC40 One end of the capacitor BC35 is connected to the other end of the capacitor BC40.
  • the second decoupling capacitor also includes capacitor C6541, capacitor BC51, capacitor BC38, capacitor BC52 and capacitor BC55, wherein one end of capacitor C6541 is connected to the second input terminal VCCFQ of the flash memory, and one end of capacitor C6541 is connected to One end of capacitor BC51, the other end of capacitor C6541 is connected to the other end of capacitor BC51, and the other end of capacitor C6541 is grounded; one end of capacitor BC51 is connected to one end of capacitor BC38, and the other end of capacitor BC51 is connected to the other end of capacitor BC38; the other end of capacitor BC38 One end is connected to one end of capacitor BC52, the other end of capacitor BC38 is connected to the other end of capacitor BC52; one end of capacitor BC52 is connected to one end of capacitor BC55, and the other end of capacitor BC52 is connected to the other end of capacitor BC55.
  • the third decoupling capacitor also includes capacitor C6538 and capacitor BC45, wherein one end of capacitor C6538 is connected to the input terminal V18 of the buffer, one end of capacitor C6538 is connected to one end of capacitor BC45, and the other end of capacitor C6538 is connected to The other end of the capacitor BC45, and the other end of the capacitor C6538 is grounded.
  • the embedded memory chip is directly mounted on the Phytium processor. Compared with the storage solid-state hard disk with golden fingers, it occupies less space and has better shock resistance.
  • the data transmission protocol of the embedded memory chip is the PCIe3.0X4 protocol, the bandwidth can reach 8GB/s, and the upper limit of the speed is high, which can meet the demand for fast data storage in today's information age.
  • the embedded memory chip is a BGA-packaged embedded memory chip integrating NAND Flash flash memory, DRAM cache, and self-developed controller. It is matched with the Feiteng platform to realize a national production platform, which will help promote domestic CPUs to domestic The development of storage media.

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Abstract

Provided in the present application is a storage motherboard based on a Feiteng processor. The storage motherboard comprises: a Feiteng processor and an embedded storage chip, wherein the embedded storage chip is attached to the Feiteng processor, and the embedded storage chip is connected to the Feiteng processor; the embedded storage chip comprises a controller, a flash memory and a cache, and the controller is connected to the flash memory and the cache; and the embedded storage chip is used for storing data to be processed, which is transmitted by the Feiteng processor. In the present application, an embedded storage chip, which is attached to a Feiteng processor, is combined with the Feiteng processor, and the embedded storage chip has a high integration degree, thereby facilitating rapid data storage, and improving the data storage efficiency.

Description

基于飞腾处理器的存储主板Storage motherboard based on Phytium processor 技术领域technical field
本实用新型实施例涉及芯片技术领域，尤其涉及一种基于飞腾处理器的存储主板。The embodiment of the utility model relates to the field of chip technology, in particular to a storage motherboard based on a Phytium processor.
背景技术Background technique
随着信息技术的发展，信息化时代对于大数据存储的需求也随之提高。目前，国内大部分计算机产品中应用的CPU（Central Processing Unit / Processor，中央处理器）的存储盘设计采用的是国外的CPU芯片结合国外的存储芯片实现数据的存储。由于芯片留有后门，国外的存储芯片应用到国产的计算机系统中，信息的安全性和保密性难以得到保证。因此，国产化CPU芯片应运而生，比如飞腾处理器。With the development of information technology, the demand for big data storage in the information age has also increased. At present, the storage disk design of the CPU (Central Processing Unit / Processor, central processing unit) used in most domestic computer products uses a foreign CPU chip combined with a foreign memory chip to realize data storage. Because the chip has a back door, and foreign memory chips are applied to domestic computer systems, it is difficult to guarantee the security and confidentiality of information. Therefore, localized CPU chips came into being, such as Phytium processors.
技术问题technical problem
现有的飞腾处理器的存储盘通常集成有用于实现数据存储的PCIe传输数据差分引脚对，但现有的飞腾处理器的存储盘集成的PCIe传输数据差分引脚对的数量有限，导致现有的飞腾处理器的存储盘无法满足信息化时代对于数据的大容量存储和快速存储的需求。The storage disk of the existing Phytium processor is usually integrated with PCIe transmission data differential pin pairs for data storage, but the number of PCIe transmission data differential pin pairs integrated in the storage disk of the existing Phytium processor is limited, resulting in Some storage disks of Phytium processors cannot meet the demand for large-capacity and fast storage of data in the information age.
技术解决方案technical solution
有鉴于此，本实用新型实施例提供了一种基于飞腾处理器的存储主板，用于解决现有的飞腾处理器的存储盘存储容量小、存储效率低的问题。In view of this, the embodiment of the present utility model provides a storage motherboard based on the Feiteng processor, which is used to solve the problems of small storage capacity and low storage efficiency of the storage disk of the existing Feiteng processor.
本实用新型实施例是通过下述技术方案来解决上述技术问题：The utility model embodiment solves the above technical problems through the following technical solutions:
本实用新型提供一种基于飞腾处理器的存储主板，包括：The utility model provides a storage motherboard based on a Feiteng processor, comprising:
所述飞腾处理器；以及the Phytium processor; and
嵌入式存储芯片，板贴于所述飞腾处理器，所述嵌入式存储芯片连接所述飞腾处理器；所述嵌入式存储芯片包括控制器、闪存和缓存，所述控制器连接所述闪存和所述缓存；所述嵌入式存储芯片用于存储所述飞腾处理器传输的待处理数据。Embedded memory chip, the board is pasted on described Feiteng processor, and described embedded memory chip is connected with described Feiteng processor; Described embedded memory chip comprises controller, flash memory and buffer memory, and described controller is connected described flash memory and The cache; the embedded memory chip is used to store the data to be processed transmitted by the Feiteng processor.
可选地，所述嵌入式存储芯片设置有四组第一PCIe传输数据差分引脚对；Optionally, the embedded memory chip is provided with four sets of first PCIe transmission data differential pin pairs;
所述飞腾处理器设有两组第二PCIe传输数据差分引脚对和两组第三PCIe传输数据差分引脚对；The Feiteng processor is provided with two sets of second PCIe transmission data differential pin pairs and two sets of third PCIe transmission data differential pin pairs;
其中两组第一PCIe传输数据差分引脚对分别一一对应于所述两组第二PCIe传输数据差分引脚对，且其中两组第一PCIe传输数据差分引脚对分别与对应的第二PCIe传输数据差分引脚对通信连接，以实现信号传输；另外两组第一PCIe传输数据差分引脚对分别一一对应于所述两组第三PCIe传输数据差分引脚对，且另外两组第一PCIe传输数据差分引脚对分别与对应的第三PCIe传输数据差分引脚对通信连接，以实现信号传输。Among them, two sets of first PCIe transmission data differential pin pairs are respectively corresponding to the two second PCIe transmission data differential pin pairs, and wherein two groups of first PCIe transmission data differential pin pairs are respectively connected to the corresponding second PCIe transmission data differential pin pairs. The differential pin pairs of PCIe transmission data are connected in communication to realize signal transmission; the other two first PCIe transmission data differential pin pairs correspond to the two third PCIe transmission data differential pin pairs one by one, and the other two groups The first differential pin pair for PCIe transmission data is communicatively connected with the corresponding third differential pin pair for PCIe transmission data, so as to realize signal transmission.
可选地，所述嵌入式存储芯片还包括总线控制器，所述控制器连接所述总线控制器；Optionally, the embedded memory chip further includes a bus controller, and the controller is connected to the bus controller;
所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；Described flashing memory comprises Flash controller and Flash flash memory chip array; Described Flash controller is connected with described Flash flash memory chip array and described bus controller respectively;
所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。The cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected to the DDR3 DRAM storage array and the bus controller respectively.
可选地，所述存储主板还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；Optionally, the storage motherboard further includes a power supply circuit, and the power supply circuit includes a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;
所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；The first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；The first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface; the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；The first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller, and the first output interface is connected to the first One end of a capacitor, the other end of the first capacitor is grounded;
所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；The second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；The second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；The second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。The second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
可选地，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。Optionally, the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with One or more third decoupling capacitors for energy storage.
可选地，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。Optionally, the controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
本实用新型实施例提供的基于飞腾处理器的存储主板，通过嵌入式存储芯片板贴于飞腾处理器上，嵌入式存储芯片安装在飞腾处理器上所占的空间小，抗震性好；嵌入式存储芯片集成化程度高，且通过飞腾处理器结合嵌入式存储芯片对数据进行存储，增大了数据存储的容量，提高了数据存储的效率，能够满足信息化时代对于数据的大容量存储和快速存储的需求。The storage motherboard based on the Phytium processor provided by the embodiment of the utility model is pasted on the Phytium processor through an embedded memory chip board, and the embedded memory chip installed on the Phytium processor occupies a small space and has good shock resistance; The storage chip has a high degree of integration, and the data is stored through the Phytium processor combined with the embedded memory chip, which increases the capacity of data storage and improves the efficiency of data storage, which can meet the requirements of large-capacity storage and fast storage of data in the information age. storage needs.
以下结合附图和具体实施例对本实用新型进行详细描述，但不作为对本实用新型的限定。The utility model will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the utility model.
附图说明Description of drawings
图1为本发明实施例之基于飞腾处理器的存储主板的整体结构示意图；1 is a schematic diagram of the overall structure of a storage motherboard based on a Feiteng processor according to an embodiment of the present invention;
图1-1为本发明实施例之基于飞腾处理器的存储主板中所述嵌入式存储芯片的结构示意图；FIG. 1-1 is a schematic structural diagram of the embedded memory chip in the storage motherboard based on the Phytium processor according to the embodiment of the present invention;
图2为本发明实施例之基于飞腾处理器的存储主板中第一供电电路的电路示意图；2 is a schematic circuit diagram of a first power supply circuit in a storage motherboard based on a Feiteng processor according to an embodiment of the present invention;
图3为本发明实施例之基于飞腾处理器的存储主板中第二供电电路的电路示意图；3 is a schematic circuit diagram of a second power supply circuit in a storage motherboard based on a Phytium processor according to an embodiment of the present invention;
图4为本发明实施例之基于飞腾处理器的存储主板中一个或多个第一去耦电容的电路连接示意图；4 is a schematic diagram of the circuit connection of one or more first decoupling capacitors in the storage motherboard based on the Phytium processor according to the embodiment of the present invention;
图5为本发明实施例之基于飞腾处理器的存储主板中一个或多个第二去耦电容的电路连接示意图；5 is a schematic diagram of circuit connections of one or more second decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention;
图6为本发明实施例之基于飞腾处理器的存储主板中一个或多个第二去耦电容的电路连接示意图；6 is a schematic diagram of circuit connections of one or more second decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention;
图7为本发明实施例之基于飞腾处理器的存储主板中一个或多个第三去耦电容的电路连接示意图。FIG. 7 is a schematic diagram of circuit connection of one or more third decoupling capacitors in a storage motherboard based on a Phytium processor according to an embodiment of the present invention.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
需要说明的是，在本发明实施例中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本发明要求的保护范围之内。It should be noted that the descriptions involving "first", "second", etc. in the embodiments of the present invention are only for the purpose of description, and should not be understood as indicating or implying their relative importance or implicitly indicating the indicated technical features quantity. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist , nor within the scope of protection required by the present invention.
在本发明的描述中，需要理解的是，步骤前的数字标号并不标识执行步骤的前后顺序，仅用于方便描述本发明及区别每一步骤，因此不能理解为对本发明的限制。In the description of the present invention, it should be understood that the numerals before the steps do not indicate the order in which the steps are performed, but are only used to facilitate the description of the present invention and distinguish each step, and therefore cannot be construed as limiting the present invention.
术语解释：Explanation of terms:
飞腾处理器：又称飞腾平台，飞腾处理器可以为FT2000/4核。FT2000/4核系列处理器主要面向桌面应用，及高端嵌入式的应用，该系列包含了有8款产品，其是一款面向桌面应用的高性能通用处理器，集成了4个64位高性能核。主频是2.6GHz，内置密码加速引擎，是我国全国产化CPU（Central Processing Unit / Processor，中央处理器）的之一。Feiteng processor: also known as Feiteng platform, Feiteng processor can be FT2000/4 core. FT2000/4-core series processors are mainly for desktop applications and high-end embedded applications. This series includes 8 products. It is a high-performance general-purpose processor for desktop applications. It integrates four 64-bit high-performance nuclear. The main frequency is 2.6GHz, and the built-in password acceleration engine is a nationally produced CPU in my country (Central Processing Unit / Processor, one of the central processing unit).
嵌入式存储芯片：在本实施例中，所述嵌入式存储芯片可以为AXD PCIe NVMe BGA SSD嵌入式存储芯片；是自研发的集NAND Flash闪存、DRAM缓存、自主研发的控制器为一体的BGA封装嵌入式存储芯片。Embedded storage chip: In this embodiment, the embedded storage chip may be an AXD PCIe NVMe BGA SSD embedded storage chip; it is a self-developed BGA that integrates NAND Flash flash memory, DRAM cache, and a self-developed controller Package embedded memory chips.
本发明人了解到：诸如飞腾平台的国产芯片平台的存储盘都是标准固态硬盘，例如：mSATA（mini-SATA，迷你版SATA接口，为一种计算机总线）的固态硬盘、7+15PIN（芯片）接口的固态硬盘，至少存在以下缺陷：The inventor understands that: the storage disks of domestic chip platforms such as the Feiteng platform are all standard solid-state hard disks, such as solid-state hard disks of mSATA (mini-SATA, a mini-version SATA interface, which is a computer bus), 7+15PIN (chip ) interface solid-state hard disk, at least the following defects:
（1）现有飞腾平台的固态硬盘占用空间较大、抗震性较差。(1) The solid-state hard drive of the existing Feiteng platform takes up a lot of space and has poor shock resistance.
（2）现有飞腾平台的固态硬盘存储数据通常采用SATA协议（Serial Advanced Technology Attachment，一种通过基于行业标准的串行硬件驱动器接口传输信号时使用的协议）或者USB协议（Universal Serial Bus，一种通过通用串行总线传输信号时使用的协议）进行数据传输，速度上限不高，无法满足信息化时代的大数据的处理需求。(2) The data stored in the solid-state hard drive of the existing Phytium platform usually uses the SATA protocol (Serial Advanced Technology Attachment, a protocol used to transmit signals through an industry-standard serial hardware drive interface) or the USB protocol (Universal Serial Bus, a A protocol used to transmit signals through the universal serial bus) for data transmission, the upper limit of the speed is not high, and it cannot meet the processing needs of big data in the information age.
（3）现有飞腾平台的固态硬盘集成程度较差。(3) The integration level of the solid-state hard disk of the existing Feiteng platform is poor.
为解决上述问题，下文将提供多个实施例，下文提供的各个实施例可以用于实现基于飞腾处理器的数据存储。In order to solve the above problems, several embodiments will be provided below, and each embodiment provided below can be used to implement data storage based on a Feiteng processor.
本发明旨在提供一种基于飞腾处理器的数据存储方案，在本方案中：The present invention aims to provide a data storage scheme based on Feiteng processor, in this scheme:
（1）通过将自研发的AXD PCIe NVMe嵌入式存储芯片板贴于飞腾平台上，实现占空间小，抗震性好的效果。(1) By pasting the self-developed AXD PCIe NVMe embedded memory chip board on the Phytium platform, it achieves the effects of small footprint and good shock resistance.
（2）自研发的AXD PCIe NVMe嵌入式存储芯片与飞腾平台进行数据传输的数据传输协议是PCIe3.0X4的，带宽为8GB/s，速度上限高，可以满足信息化时代的大数据处理需求。(2) The data transmission protocol between the self-developed AXD PCIe NVMe embedded memory chip and the Phytium platform is PCIe3.0X4, with a bandwidth of 8GB/s and a high speed limit, which can meet the needs of big data processing in the information age.
（3）自研发的AXD PCIe NVM嵌入式存储芯片是集NAND Flash闪存、DRAM缓存、自主研发的控制器为一体的BGA封装嵌入式存储芯片，搭配飞腾平台，实现全国产化平台，打造属于国产CPU到国产存储介质的链条。(3) The self-developed AXD PCIe NVM embedded memory chip is a BGA-packaged embedded memory chip that integrates NAND Flash flash memory, DRAM cache, and a self-developed controller. The chain from the CPU to the domestic storage medium.
以下将提供一个或多个实施例，来具体介绍基于飞腾处理器的数据存储方案。One or more embodiments will be provided below to specifically introduce the data storage solution based on the Feiteng processor.
参阅图1，示意性示出了本发明实施例之一种基于飞腾处理器的存储主板1的整体结构示意图。Referring to FIG. 1 , it schematically shows the overall structure of a storage motherboard 1 based on a Phytium processor according to an embodiment of the present invention.
如图1所示，所述基于飞腾处理器的存储主板1包括：所述飞腾处理器2以及嵌入式存储芯片3，所述嵌入式存储芯片3板贴于所述飞腾处理器2，所述嵌入式存储芯片3连接所述飞腾处理器2；所述嵌入式存储芯片3包括控制器4、闪存和缓存，所述控制器4连接所述闪存和所述缓存；所述嵌入式存储芯片3用于存储所述飞腾处理器2传输的待处理数据。其中，所述飞腾处理器2为FT-2000/4芯片。嵌入式存储芯片可以为AXD PCIe NVMe BGA SSD嵌入式存储芯片。所述闪存可以为NAND Flash闪存5。所述缓存可以为DRAM缓存6（Dynamic Random Access Memory，动态随机存取存储器）。As shown in Figure 1, the storage motherboard 1 based on the Feiteng processor includes: the Feiteng processor 2 and an embedded memory chip 3, and the embedded memory chip 3 is attached to the Feiteng processor 2. The embedded memory chip 3 is connected to the Feiteng processor 2; the embedded memory chip 3 includes a controller 4, flash memory and cache memory, and the controller 4 is connected to the flash memory and the cache memory; the embedded memory chip 3 It is used for storing the data to be processed transmitted by the Feiteng processor 2 . Wherein, the Phytium processor 2 is an FT-2000/4 chip. Embedded memory chip can be AXD PCIe NVMe BGA SSD embedded memory chip. Described flash memory can be NAND Flash flash memory 5. The cache can be DRAM cache 6 (Dynamic Random Access Memory, dynamic random access memory).
在本发明中，由于板贴是点对点的连接，因此所述嵌入式存储芯片3安装在飞腾处理器2上所占的空间小，并且有效提高了嵌入式存储芯片3在飞腾处理器2上的抗震性。并且所述嵌入式存储芯片3集成化程度高；所述存储主板1的接口种类丰富，可以满足用户对存储产品的多种使用需求。In the present invention, since the board paste is a point-to-point connection, the space occupied by the embedded memory chip 3 on the Feiteng processor 2 is small, and the connection between the embedded memory chip 3 and the Feiteng processor 2 is effectively improved. shock resistance. Moreover, the embedded memory chip 3 has a high degree of integration; the interface of the memory main board 1 is rich in types, which can meet various usage demands of users for memory products.
为了保证所述嵌入式存储芯片3和所述飞腾处理器2之间能够实现正常的信号传输，在示例性的实施例中，所述嵌入式存储芯片3设置有四组第一PCIe传输数据差分引脚对；所述飞腾处理器2设有两组第二PCIe传输数据差分引脚对和两组第三PCIe传输数据差分引脚对；其中两组第一PCIE传输数据差分引脚对分别连接所述两组第二PCIe传输数据差分引脚对，另外两组第一PCIe传输数据差分引脚对分别连接所述两组第三PCIe传输数据差分引脚对。在本实施中，四组第一PCIe传输数据差分引脚对分别和两组第二PCIe传输数据差分引脚对以及两组第三PCIE传输数据差分引脚对的对应关系遵循RX与TX一一对应的原则，其中，RX表示接收差分信号，TX表示发送差分信号，P表示正极，N表示负极。In order to ensure normal signal transmission between the embedded memory chip 3 and the Feiteng processor 2, in an exemplary embodiment, the embedded memory chip 3 is provided with four sets of first PCIe transmission data differential Pin pair; the Feiteng processor 2 is provided with two groups of second PCIe transmission data differential pin pairs and two groups of third PCIe transmission data differential pin pairs; wherein the first two groups of PCIe transmission data differential pin pairs are connected respectively The two sets of second differential pin pairs for PCIe transmission data, and the other two sets of first differential pin pairs for PCIe transmission data are respectively connected to the two sets of third differential pin pairs for PCIe transmission data. In this implementation, the corresponding relationship between the four first PCIe transmission data differential pin pairs and the two second PCIe transmission data differential pin pairs and the two third PCIE transmission data differential pin pairs follows RX and TX one-to-one Corresponding principle, wherein, RX means receive differential signal, TX means send differential signal, P means positive pole, and N means negative pole.
为了实现嵌入式存储芯片3中各个模块之间的信号传输，所述嵌入式存储芯片3还包括总线控制器，所述控制器4连接所述总线控制器；所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。在本实施例中，通过控制器4控制所述闪存和所述缓存以实现所述嵌入式存储芯片3的数据存储功能。In order to realize the signal transmission between each module in the embedded storage chip 3, the embedded storage chip 3 also includes a bus controller, and the controller 4 is connected to the bus controller; the flash memory includes a Flash controller and a Flash controller. Flash memory chip array; the Flash controller is connected with the Flash flash memory chip array and the bus controller respectively; the cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected with the DDR3 DRAM storage The array is connected to the bus controller. In this embodiment, the flash memory and the cache are controlled by the controller 4 to realize the data storage function of the embedded memory chip 3 .
结合图1-1，示出了所述嵌入式存储芯片3的结构示意图。所述嵌入式存储芯片3通过PCIe总线（peripheral component interconnect express，是一种高速串行计算机扩展总线标准）实现其内部各个模块之间的信号传输以及实现所述嵌入式存储芯片3与外部处理器（如飞腾处理器2）之间通过PCIe端的信号传输。其中，所述PCIe总线包括PCIe物理层，PCIe物理层为PCIe总线的最底层，PCIe物理层还包括PCIe MAC（Media Access Control，媒体数据存储控制）层。在本发明中，PCIe MAC层涉及的核心为PCIe NVMe标准（是一种适用于基于PCIe协议的固态硬盘行业标准）。Referring to FIG. 1-1 , a schematic structural diagram of the embedded memory chip 3 is shown. The embedded memory chip 3 realizes the signal transmission between its internal modules and realizes the connection between the embedded memory chip 3 and the external processor through the PCIe bus (peripheral component interconnect express, which is a high-speed serial computer expansion bus standard). (such as Phytium processor 2) through the signal transmission of the PCIe end. Wherein, the PCIe bus includes a PCIe physical layer, the PCIe physical layer is the bottom layer of the PCIe bus, and the PCIe physical layer also includes a PCIe MAC (Media Access Control, media data storage control) layer. In the present invention, PCIe The core involved in the MAC layer is the PCIe NVMe standard (an industry standard for SSDs based on the PCIe protocol).
所述嵌入式存储芯片3包括总线控制器、双核CPU（即控制器4）、RAID编解码器、Flash控制器、Flash闪存芯片阵列、安全引擎、主系统缓冲区、DMA控制器、DRAM控制器以及DDR3 DRAM（一种计算机内存规格的缓存产品），其中，总线控制器连接分别连接双核CPU、RAID编解码器(Redundant Arrays of Independent Disks, 磁盘阵列编解码器)、Flash控制器、安全引擎、主系统缓冲区、DMA控制器（Direct Memory Access，直接存储器访问，一种允许不同速度的硬件装置沟通的控制器）和DRAM控制器，Flash控制器连接Flash闪存芯片阵列，DRAM控制器连接DDR3 DRAM。Described embedded storage chip 3 comprises bus controller, dual-core CPU (ie controller 4), RAID codec, Flash controller, Flash flash memory chip array, security engine, main system buffer zone, DMA controller, DRAM controller And DDR3 DRAM (a cache product of computer memory specification), in which the bus controller is connected to the dual-core CPU, RAID codec (Redundant Arrays of Independent Disks, disk array codec), Flash controller, security engine, main system buffer, DMA controller (Direct Memory Access, direct memory access, a controller that allows hardware devices of different speeds to communicate) and The DRAM controller, the Flash controller is connected to the Flash memory chip array, and the DRAM controller is connected to the DDR3 DRAM.
在示例性的实施例中，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。BGA(Ball Grid Array)封装技术为球状引脚栅格阵列封装技术，是一种高密度表面装配封装技术。采用BGA封装技术的嵌入式存储芯片在相同容量下，具有更小的体积、更加快速有效的散热性能和电性能。In an exemplary embodiment, the controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology. BGA (Ball Grid Array) packaging technology is a ball grid array packaging technology, which is a high-density surface mount packaging technology. Embedded memory chips using BGA packaging technology have smaller volume, faster and more effective heat dissipation performance and electrical performance under the same capacity.
为了实现对所述嵌入式存储芯片3的供电；在示例性的实施例中，所述存储主板1还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；In order to realize the power supply to the embedded storage chip 3; in an exemplary embodiment, the storage motherboard 1 also includes a power supply circuit, and the power supply circuit includes a first power supply circuit connected to the first power supply chip and a power supply circuit connected to the first power supply chip. A second power supply circuit connected to the second power supply chip;
所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；The first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；The first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface; the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器4的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；The first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller 4, and the first output interface is connected to the one end of the first capacitor, and the other end of the first capacitor is grounded;
所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；The second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；The second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；The second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。The second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
为了更好的控制预设上电时序，请参阅图2和图3，图2示意性示出了第一供电电路的供电电路示意图，图3示意性示出了第二供电电路示意图。具体如下：In order to better control the preset power-on sequence, please refer to FIG. 2 and FIG. 3 , FIG. 2 schematically shows a schematic diagram of a power supply circuit of the first power supply circuit, and FIG. 3 schematically shows a schematic diagram of a second power supply circuit. details as follows:
如图2所示，第一供电电路：As shown in Figure 2, the first power supply circuit:
所述第一供电电路包括第一电源供电芯片，所述第一电源供电芯片包括多组第一电源输入接口，例如两组VIN1、两组VIN2、两组VIN3和VIN，所述多组第一电源输入接口连接外部电源H33V。示例性的，两组VIN1、两组VIN2、两组VIN3和VIN通过导线并联，均连接外部电源H33V。两组VIN1、两组VIN2、两组VIN3和VIN均连接一个电容之后接地。The first power supply circuit includes a first power supply chip, and the first power supply chip includes multiple sets of first power input interfaces, such as two sets of VIN1, two sets of VIN2, two sets of VIN3 and VIN, and the multiple sets of first The power input interface is connected to the external power supply H33V. Exemplarily, two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through wires, all of which are connected to the external power supply H33V. Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected to a capacitor and then grounded.
所述第一电源供电芯片还包括第一输出接口VOUT3（如引脚G1）和第二输出接口，所述第二输出接口包括第二主输出接口VOUT1（如引脚D5、D6）和第二I/O输出接口VOUT2（如引脚E6）；所述第一供电电路包括用于文雅的第一电感L3、用于稳压的第二电感L2、用于耦合的第一电容C19、用于耦合的第二电容C10和用于耦合的第三电容C16。The first power supply chip also includes a first output interface VOUT3 (such as pin G1) and a second output interface, and the second output interface includes a second main output interface VOUT1 (such as pins D5, D6) and a second I/O output interface VOUT2 (such as pin E6); the first power supply circuit includes a first inductor L3 for elegance, a second inductor L2 for voltage stabilization, a first capacitor C19 for coupling, and The second capacitor C10 for coupling and the third capacitor C16 for coupling.
所述第一供电电路还包括第一电感连接接口LX3（如引脚F3、G3），所述第一电感连接接口LX3连接所述第一电感L3的一端，所述第一电感L3的另一端连接所述第一输出接口VOUT3和所述控制器4的输入端VCCK（例如引脚G7、G8、G11、G12、H7、H8、H11、H12、J7、J8、J11、J12），所述第一输出接口VOUT3连接所述第一电容C19的一端，所述第一电容C19的另一端接地。The first power supply circuit also includes a first inductance connection interface LX3 (such as pins F3 and G3), the first inductance connection interface LX3 is connected to one end of the first inductance L3, and the other end of the first inductance L3 Connect the first output interface VOUT3 to the input terminal VCCK of the controller 4 (such as pins G7, G8, G11, G12, H7, H8, H11, H12, J7, J8, J11, J12), the first An output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor C19 is grounded.
所述第二主输出接口VOUT1连接所述闪存的第一输入端VCC3F（例如引脚D10、E9、E10、W9、W10、Y9、Y10），所述第二主输出接口VOUT1连接所述第二电容C10的一端，所述第二电容C10的另一端接地。The second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory (such as pins D10, E9, E10, W9, W10, Y9, Y10), and the second main output interface VOUT1 is connected to the second One end of the capacitor C10, and the other end of the second capacitor C10 are grounded.
所述第一供电电路还包括第二电感连接接口LX2（如引脚F5、F6），所述第二电感连接接口LX2连接所述第二电感L2的一端，所述第二电感L2的另一端连接所述第二I/O输出接口VOUT2和所述闪存的第二输入端VCCFQ（例如引脚R8、R11、R12、T7、T8、T11、T12、U7、U8、U11、U12），所述第二I/O输出接口VOUT2连接所述第三电容C16的一端，所述第三电容C16的另一端接地。The first power supply circuit also includes a second inductance connection interface LX2 (such as pins F5 and F6), the second inductance connection interface LX2 is connected to one end of the second inductance L2, and the other end of the second inductance L2 Connect the second I/O output interface VOUT2 and the second input terminal VCCFQ of the flash memory (such as pins R8, R11, R12, T7, T8, T11, T12, U7, U8, U11, U12), the The second I/O output interface VOUT2 is connected to one end of the third capacitor C16, and the other end of the third capacitor C16 is grounded.
所述第一供电电路还包括第一接地接口PGND1（如引脚A5、A6）、第二接地接口PGND2（如引脚E5）、第三接地接口PGND3（如引脚F4、G4）以及第四接地接口AGND（如引脚C1）。The first power supply circuit also includes a first ground interface PGND1 (such as pin A5, A6), a second ground interface PGND2 (such as pin E5), a third ground interface PGND3 (such as pin F4, G4) and a fourth Ground interface AGND (such as pin C1).
如图3所示，第二供电电路：As shown in Figure 3, the second power supply circuit:
所述第二供电电路包括第二电源供电芯片，所述第二电源供电芯片包括第二电源输入接口VIN和使能引脚EN，所述第二电源输入接口VIN和所述使能引脚EN连接所述外部电源H33V；所述第二供电电路包括用于耦合的第四电容C23；The second power supply circuit includes a second power supply chip, the second power supply chip includes a second power input interface VIN and an enable pin EN, and the second power input interface VIN and the enable pin EN Connect the external power supply H33V; the second power supply circuit includes a fourth capacitor C23 for coupling;
所述第二电源供电芯片还包括第三输出接口VOUT，所述第三输出接口VOUT连接所述缓存的输入端V18（例如引脚R7），所述第三输出接口VOUT连接所述第四电容的一端，所述第四电容的另一端接地。所述第二电源供电芯片还包括接地端，例如GND和SGND。The second power supply chip also includes a third output interface VOUT, the third output interface VOUT is connected to the input terminal V18 of the buffer (such as pin R7), and the third output interface VOUT is connected to the fourth capacitor one end of the fourth capacitor, and the other end of the fourth capacitor is grounded. The second power supply chip also includes ground terminals, such as GND and SGND.
为了在供电电路无法为所述嵌入式存储芯片3供电或者无法及时供电时，保证嵌入式存储芯片3的正常运行，如图4-图7所示，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。通过上述第一去耦电容、第二去耦电容和第三去耦电容，在信号传输过程中避免其他信号的干扰，且第一去耦电容、第二去耦电容以及第三去耦电容均具备缓存能量的功能。在高频器件工作的时候，在频率的影响下，产生很大的电感影响，而导致嵌入式存储芯片3各个模块的供电不及时或者是供电电路与嵌入式存储芯片3断开连接时，通过上述去耦电容及时为所述嵌入式存储芯片3各个模块供电，保证嵌入式存储芯片3能够正常运行。In order to ensure the normal operation of the embedded memory chip 3 when the power supply circuit cannot supply power to the embedded memory chip 3 or cannot supply power in time, as shown in Figures 4-7, the first power supply circuit is connected to one or more A first decoupling capacitor for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with one or more third decoupling capacitors for energy storage. Through the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor, the interference of other signals is avoided during signal transmission, and the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor are all It has the function of caching energy. When the high-frequency device is working, under the influence of the frequency, a large inductance effect is generated, which causes the power supply of each module of the embedded memory chip 3 to be untimely or when the power supply circuit is disconnected from the embedded memory chip 3. The above-mentioned decoupling capacitor supplies power to each module of the embedded memory chip 3 in time to ensure that the embedded memory chip 3 can operate normally.
如图4所示，第一去耦电容包括包括电容C6542、电容BC46、电容BC47、电容BC49，其中，电容C6542的一端连接所述控制器4的输入端VCCK，电容C6542的一端连接电容BC46的一端，电容C6542的另一端连接电容BC46的另一端，且电容C6542的另一端接地；电容BC46的一端连接电容BC47的一端，电容BC46的另一端连接电容BC47的另一端；电容BC47的一端连接电容BC49的一端，电容BC47的另一端连接电容BC49的另一端。As shown in Figure 4, the first decoupling capacitor includes capacitor C6542, capacitor BC46, capacitor BC47, and capacitor BC49, wherein one end of capacitor C6542 is connected to the input terminal VCCK of the controller 4, and one end of capacitor C6542 is connected to the terminal of capacitor BC46. One end, the other end of capacitor C6542 is connected to the other end of capacitor BC46, and the other end of capacitor C6542 is grounded; one end of capacitor BC46 is connected to one end of capacitor BC47, the other end of capacitor BC46 is connected to the other end of capacitor BC47; one end of capacitor BC47 is connected to capacitor One end of BC49 and the other end of capacitor BC47 are connected to the other end of capacitor BC49.
如图5所示，第二去耦电容包括电容C5437、电容BC48、电容BC35、电容BC40，其中，电容C5437的一端连接所述闪存的第一输入端VCC3F，电容C5437的一端连接电容BC48的一端，电容C5437的另一端连接电容BC48的另一端，且电容C5437的另一端接地；电容BC48的一端连接电容BC35的一端，电容BC48的另一端连接电容BC35的另一端；电容BC35的一端连接电容BC40的一端，电容BC35的另一端连接电容BC40的另一端。As shown in Figure 5, the second decoupling capacitor includes a capacitor C5437, a capacitor BC48, a capacitor BC35, and a capacitor BC40, wherein one end of the capacitor C5437 is connected to the first input terminal VCC3F of the flash memory, and one end of the capacitor C5437 is connected to one end of the capacitor BC48 , the other end of capacitor C5437 is connected to the other end of capacitor BC48, and the other end of capacitor C5437 is grounded; one end of capacitor BC48 is connected to one end of capacitor BC35, the other end of capacitor BC48 is connected to the other end of capacitor BC35; one end of capacitor BC35 is connected to capacitor BC40 One end of the capacitor BC35 is connected to the other end of the capacitor BC40.
如图6所示，第二去耦电容还包括电容C6541、电容BC51、电容BC38、电容BC52和电容BC55，其中，电容C6541的一端连接所述闪存的第二输入端VCCFQ，电容C6541的一端连接电容BC51的一端，电容C6541的另一端连接电容BC51的另一端，且电容C6541的另一端接地；电容BC51的一端连接电容BC38的一端，电容BC51的另一端连接电容BC38的另一端；电容BC38的一端连接电容BC52的一端，电容BC38的另一端连接电容BC52的另一端；电容BC52的一端连接电容BC55的一端，电容BC52的另一端连接电容BC55的另一端。As shown in Figure 6, the second decoupling capacitor also includes capacitor C6541, capacitor BC51, capacitor BC38, capacitor BC52 and capacitor BC55, wherein one end of capacitor C6541 is connected to the second input terminal VCCFQ of the flash memory, and one end of capacitor C6541 is connected to One end of capacitor BC51, the other end of capacitor C6541 is connected to the other end of capacitor BC51, and the other end of capacitor C6541 is grounded; one end of capacitor BC51 is connected to one end of capacitor BC38, and the other end of capacitor BC51 is connected to the other end of capacitor BC38; the other end of capacitor BC38 One end is connected to one end of capacitor BC52, the other end of capacitor BC38 is connected to the other end of capacitor BC52; one end of capacitor BC52 is connected to one end of capacitor BC55, and the other end of capacitor BC52 is connected to the other end of capacitor BC55.
如图7所示，第三去耦电容还包括电容C6538和电容BC45，其中，电容C6538的一端连接所述缓存的输入端V18，电容C6538的一端连接电容BC45的一端，电容C6538的另一端连接电容BC45的另一端，且电容C6538的另一端接地。As shown in Figure 7, the third decoupling capacitor also includes capacitor C6538 and capacitor BC45, wherein one end of capacitor C6538 is connected to the input terminal V18 of the buffer, one end of capacitor C6538 is connected to one end of capacitor BC45, and the other end of capacitor C6538 is connected to The other end of the capacitor BC45, and the other end of the capacitor C6538 is grounded.
本发明实施例至少具有以下有益效果：Embodiments of the present invention at least have the following beneficial effects:
（1）所述嵌入式存储芯片直接板贴在飞腾处理器上，相比于有金手指的存储固态硬盘，所占空间小，抗震性能好。(1) The embedded memory chip is directly mounted on the Phytium processor. Compared with the storage solid-state hard disk with golden fingers, it occupies less space and has better shock resistance.
（2）所述嵌入式存储芯片的数据传输协议为PCIe3.0X4协议，带宽可达到8GB/s，速度上限高，可以满足当今信息化时代的对数据快速存储的需求。(2) The data transmission protocol of the embedded memory chip is the PCIe3.0X4 protocol, the bandwidth can reach 8GB/s, and the upper limit of the speed is high, which can meet the demand for fast data storage in today's information age.
（3）所述嵌入式存储芯片是集NAND Flash闪存、DRAM缓存、自主研发控制器为一体的BGA封装嵌入式存储芯片，搭配飞腾平台，实现全国产化平台，有助于推动国产CPU到国产存储介质的发展。(3) The embedded memory chip is a BGA-packaged embedded memory chip integrating NAND Flash flash memory, DRAM cache, and self-developed controller. It is matched with the Feiteng platform to realize a national production platform, which will help promote domestic CPUs to domestic The development of storage media.
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation.
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technical fields , are all included in the scope of patent protection of the present invention in the same way.

Claims (6)

  1. 一种基于飞腾处理器的存储主板，其特征在于，包括：A storage motherboard based on a Feiteng processor, characterized in that it comprises:
    所述飞腾处理器；以及the Phytium processor; and
    嵌入式存储芯片，板贴于所述飞腾处理器，所述嵌入式存储芯片连接所述飞腾处理器；所述嵌入式存储芯片包括控制器、闪存和缓存，所述控制器连接所述闪存和所述缓存；所述嵌入式存储芯片用于存储所述飞腾处理器传输的待处理数据。Embedded memory chip, the board is pasted on described Feiteng processor, and described embedded memory chip is connected with described Feiteng processor; Described embedded memory chip comprises controller, flash memory and buffer memory, and described controller is connected described flash memory and The cache; the embedded memory chip is used to store the data to be processed transmitted by the Feiteng processor.
  2. 根据权利要求1所述的基于飞腾处理器的存储主板，其特征在于，所述嵌入式存储芯片设置有四组第一PCIe传输数据差分引脚对；The storage motherboard based on the Feiteng processor according to claim 1, wherein the embedded memory chip is provided with four sets of first PCIe transmission data differential pin pairs;
    所述飞腾处理器设有两组第二PCIe传输数据差分引脚对和两组第三PCIe传输数据差分引脚对；The Feiteng processor is provided with two sets of second PCIe transmission data differential pin pairs and two sets of third PCIe transmission data differential pin pairs;
    其中两组第一PCIe传输数据差分引脚对分别一一对应于所述两组第二PCIe传输数据差分引脚对，且其中两组第一PCIe传输数据差分引脚对分别与对应的第二PCIe传输数据差分引脚对通信连接，以实现信号传输；另外两组第一PCIe传输数据差分引脚对分别一一对应于所述两组第三PCIe传输数据差分引脚对，且另外两组第一PCIe传输数据差分引脚对分别与对应的第三PCIe传输数据差分引脚对通信连接，以实现信号传输。Among them, two sets of first PCIe transmission data differential pin pairs are respectively corresponding to the two second PCIe transmission data differential pin pairs, and wherein two groups of first PCIe transmission data differential pin pairs are respectively connected to the corresponding second PCIe transmission data differential pin pairs. The differential pin pairs of PCIe transmission data are connected in communication to realize signal transmission; the other two first PCIe transmission data differential pin pairs correspond to the two third PCIe transmission data differential pin pairs one by one, and the other two groups The first differential pin pair for PCIe transmission data is communicatively connected with the corresponding third differential pin pair for PCIe transmission data, so as to realize signal transmission.
  3. 根据权利要求1所述的基于飞腾处理器的存储主板，其特征在于，所述嵌入式存储芯片还包括总线控制器，所述控制器连接所述总线控制器；The storage motherboard based on the Feiteng processor according to claim 1, wherein the embedded memory chip also includes a bus controller, and the controller is connected to the bus controller;
    所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；Described flashing memory comprises Flash controller and Flash flash memory chip array; Described Flash controller is connected with described Flash flash memory chip array and described bus controller respectively;
    所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。The cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected to the DDR3 DRAM storage array and the bus controller respectively.
  4. 根据权利要求1所述的基于飞腾处理器的存储主板，其特征在于，所述存储主板还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；The storage motherboard based on the Feiteng processor according to claim 1, wherein the storage motherboard further comprises a power supply circuit, and the power supply circuit includes a first power supply circuit connected to a first power supply chip and a second power supply circuit a second power supply circuit connected to the power supply chip;
    所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；The first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
    所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；The first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface; the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
    所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；The first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller, and the first output interface is connected to the first One end of a capacitor, the other end of the first capacitor is grounded;
    所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；The second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
    所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；The second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
    所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；The second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
    所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。The second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
  5. 根据权利要求4所述的基于飞腾处理器的存储主板，其特征在于，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。The storage motherboard based on the Feiteng processor according to claim 4, wherein the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more first decoupling capacitors for energy storage The second decoupling capacitor; the second power supply circuit is connected with one or more third decoupling capacitors for energy storage.
  6. 根据权利要求1所述的基于飞腾处理器的存储主板，其特征在于，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。The storage motherboard based on the Phytium processor according to claim 1, wherein the controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
PCT/CN2022/112722 2021-08-17 2022-08-16 Storage motherboard based on feiteng processor WO2023020470A1 (en)

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