WO2023015878A1 - 一种基于寄存器灵活时序库的电路时序优化方法 - Google Patents
一种基于寄存器灵活时序库的电路时序优化方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Definitions
- the invention relates to a digital integrated circuit timing optimization method, which belongs to the technical field of EDA.
- Static timing analysis is an important step in verifying whether the circuit timing constraints are satisfied in digital integrated circuit circuits.
- the propagation delay of the register is considered to be related to the setup time (the minimum time for the input data to remain stable before the clock signal jumps) and the hold time (the minimum time for the input data to remain stable after the clock signal jumps).
- the shortest time to maintain stability) is irrelevant, and the three are uniquely determined by the input signal conversion time of the register, the clock signal conversion time and the register load capacitance.
- the propagation delay of a register is related to both the setup slack (the time the input data is actually stable before the clock signal transitions) and the hold slack (the clock signal It is related to the time when the input data actually remains stable after the jump).
- the setup slack the time the input data is actually stable before the clock signal transitions
- the hold slack the clock signal It is related to the time when the input data actually remains stable after the jump.
- the propagation delay of the register is independent of the setup time and hold time, which is determined by the setup time, hold time and propagation delay in the traditional register timing library
- the setup time check and hold time check Check whether all register paths in the circuit meet the setup time check and hold time check.
- a circuit timing optimization method based on a register flexible timing library the setup time T setup , hold time T hold and propagation delay T cq of the register respectively refer to the specific input signal conversion in the traditional timing library of the register
- the minimum time for input data to remain stable before clock signal jumps, the minimum time for input data to remain stable after clock signal jumps, and the minimum time for slave clock signal jumps under the combination of time S data, clock signal transition time S ck , and register load capacitance C L time interval to output data;
- the registers are established to relax the stay loose and the actual propagation delay Respectively refer to the time when the input data is actually stable before the clock signal jumps and the input data is actually kept stable after the clock signal jumps under the combination of the specific input signal conversion time S data , the clock signal conversion time S ck and the register load capacitance C L time to stabilize and build up slack at a specific and stay slack In the case, the time interval from the clock signal transition to the output data;
- the register flexible timing library refers to a variety of corresponding establishment relaxations under a specific combination of input signal transition time S data , clock signal transition time S ck and register load capacitance C L stay loose and the actual propagation delay combination;
- the register path refers to the data path in the circuit with the register as the starting point and the ending point, wherein the starting point register is marked as FF i , and the ending point register is marked as FF j , i and j are the numbers of the starting point register and the ending point register respectively, 1 ⁇ i , j ⁇ N FF , N FF is the number of registers in the circuit;
- the setup time margin based on the register traditional timing library and hold time margin Respectively as shown in (1) and as follows:
- T is the clock period, and Respectively represent the time when the clock signal arrives at the start register FF i and the end register FF j , and Denote the maximum delay and minimum delay of the data path in all register paths between the start register FF i and the end register FF j , respectively, and Indicate the setup time and hold time of the terminal register FF j respectively, Indicates the propagation delay of the starting point register FF i ;
- the setup time margin based on the register flexible timing library and hold time margin Respectively as shown in (3) and as follows:
- the methods include:
- a circuit timing optimization method based on a register flexible timing library of the present invention is to characterize the correlation between register establishment slack, hold slack, and actual propagation delay, and establish slack and hold slack simulation when changing registers On the basis of obtaining the corresponding actual propagation delay, the actual propagation delay of different setup and hold slacks can be obtained by linear interpolation method. Compared with the traditional register timing library, it can be more comprehensive by characterizing the correlation between the three Reflect the timing characteristics of registers and provide a basis for timing optimization. Secondly, the present invention uses the correlation between establishing slack, maintaining slack, and actual propagation delay to perform static timing analysis on the register path in the circuit.
- the present invention can fully Using the setup time margin and the hold time margin of the adjacent register path, on the premise that the setup time margin and the hold time margin of all the register paths are greater than zero, the clock cycle is reduced to the minimum, thereby improving the circuit performance.
- Figure 1 is a schematic diagram of register setup time, hold time, setup slack, hold slack, and propagation delay;
- Figure 2 is a schematic diagram of the correlation between register establishment slack (setup slack), hold slack (hold slack) and actual propagation delay (clock-to-q delay);
- FIG. 3 is a schematic diagram of adjacent register paths.
- a circuit timing optimization method based on a register flexible timing library wherein the register setup time T setup , hold time T hold and propagation delay T cq respectively refer to the specific input signal transition time S data in the traditional timing library of the register , the combination of clock signal conversion time S ck and register load capacitance C L , the minimum time for the input data to remain stable before the clock signal jumps, the minimum time for the input data to remain stable after the clock signal jumps, and the minimum time from the clock signal to the output The time interval of the data.
- Register establishment slack stay loose and the actual propagation delay Respectively refer to the time when the input data is actually stable before the clock signal jumps and the input data is actually kept stable after the clock signal jumps under the combination of the specific input signal conversion time S data , the clock signal conversion time S ck and the register load capacitance C L time to stabilize and build up slack at a specific and stay slack case, the time interval from a clock signal transition to output data.
- the register flexible timing library refers to a variety of corresponding set-up relaxations under a specific combination of input signal transition time S data , clock signal transition time S ck , and register load capacitance C L stay loose and the actual propagation delay combination.
- the register path refers to the data path with the register as the starting point and the ending point in the circuit, where the starting point register is marked as FF i and the ending point register is marked as FF j , i and j are the numbers of the starting point register and the ending point register respectively, 1 ⁇ i,j ⁇ N FF , N FF is the number of registers in the circuit.
- the setup time margin based on the register traditional timing library and hold time margin Respectively as shown in (1) and as follows:
- T is the clock period, and Respectively represent the time when the clock signal arrives at the start register FF i and the end register FF j , and Denote the maximum delay and minimum delay of the data path in all register paths between the start register FF i and the end register FF j , respectively, and Indicate the setup time and hold time of the terminal register FF j respectively, Indicates the propagation delay of the origin register FF i .
- the setup time margin based on the register flexible timing library and hold time margin Respectively as shown in (3) and as follows:
- Circuit timing optimization methods based on the register flexible timing library include:
- step S1 for each combination of input signal transition time, clock signal transition time and register load capacitance in the register traditional timing library, determine the establishment slack stay slack with is valid for
- the specific method is as follows: firstly, build the slack stay slack with Take a sufficiently large value for simulation to obtain the corresponding actual propagation delay A sufficiently large value means that when the value continues to increase or increase hour no longer decreases; then maintains constant decrease simulation until began to increase, at this time the corresponding for Keep constant decrease simulation until began to increase, at this time the corresponding for then keep unchanged continue to decrease simulation, Continue to increase until the simulation fails, that is, the output data cannot be obtained when the register clock signal jumps, and the corresponding for Keep unchanged continue to decrease simulation, Continue to increase until the simulation fails, at this time the corresponding for
- step S1 for each combination of input signal transition time, clock signal transition time and register load capacitance in the traditional timing library of registers, in and The effective range is simulated to obtain all effective and corresponding to the combination
- the specific method is as follows: firstly, take T step as the interval and Select the simulation point in the valid range of , where There are N setups of simulation points, which are respectively Where 0 ⁇ n setup ⁇ N setup -1, n setup is The nth simulation point, N setup is to satisfy The largest positive integer of , There are N hold simulation points, respectively Where 0 ⁇ n hold ⁇ N hold -1, n hold is The nth simulation point of , N hold is to satisfy The largest positive integer; then for N setup Simulation points and N hold The simulation points are combined in pairs, and the simulation is performed under all combinations to obtain the corresponding
- step S2 for all register paths in the circuit, use the traditional register timing library for timing analysis to obtain the clock period T of the circuit, and for the register paths between the start register FF i and the end register FF j , obtain the setup time margin and hold time margin Data Path Maximum Latency and minimum delay Setup time of end point register FF j and hold time Propagation delay of start register FF i and the input signal transition time of the start register FF i Clock Signal Transition Time and load capacitance Input signal transition time of end point register j Clock Signal Transition Time and load capacitance
- the input signal conversion time are respectively S data and
- the clock signal conversion time is respectively S ck and register load capacitors are C L and build slack for and keep slack for and
- the actual propagation delay of the register in 32 cases, the conversion time of the input signal obtained by linear interpolation is The clock signal transition time is The register load capacitance is build slack is stay slack yes The actual propagation delay of the corresponding register FF i when
- the linear interpolation method is specifically:
- Step 1 Treat each of the 32 combinations and the target combination as a spatial coordinate, then there are at most 4 identical coordinate values in any two spatial coordinates, and there will be registers corresponding to the two coordinates in this case
- the propagation delay is denoted as and And perform one-dimensional linear interpolation for each pair in the dimensions with different coordinate values, and the different dimensions are respectively recorded as And use x 1 to represent the coordinate value of the target combination on this dimension to get the new interpolation coordinate and the register delay corresponding to the interpolation coordinate 1 ⁇ i ⁇ 16, the formula is as follows:
- Step 2 For the 16 spatial coordinates obtained in the first step, any two spatial coordinates still have the same value in up to four dimensions, and the common dimension of the two coordinates that meets this condition is the value of the target combination. Dimensions with different coordinate values are denoted as and Use x 2 to represent the coordinate value of the target combination in this dimension, and perform one-dimensional linear interpolation to obtain the new space coordinates and the corresponding register propagation delay 1 ⁇ j ⁇ 8, the formula is as follows:
- the third step In the second step, 8 spatial coordinates are obtained. Any two spatial coordinates still have the same value in four dimensions at most, and the two coordinates that meet this condition have the same two-dimensional value as the target combination value. Dimensions with different coordinate values are denoted as and Use x 3 to represent the coordinate value of the target combination in this dimension, and perform one-dimensional linear interpolation to obtain the new space coordinates and the corresponding register propagation delay 1 ⁇ m ⁇ 4, the formula is as follows:
- Step 4 Obtain 4 spatial coordinates from the second step. Any two spatial coordinates still have at most four dimensions with the same value, and the common three dimensions of the two coordinates satisfying this condition are the values of the target combination.
- the dimensions with different coordinate values in the coordinates are denoted as and Use x 4 to represent the coordinate value of the target combination in this dimension, and perform one-dimensional linear interpolation to obtain the new space coordinates and the corresponding register propagation delay 1 ⁇ n ⁇ 2, the formula is as follows:
- Step 5 Obtain two coordinates from the fourth step. Only one dimension of the two coordinates has a different value, and the values of the other four dimensions are the same as the target combination. Record the dimension with different coordinate values in the two coordinates as and Use x 5 to represent the coordinate value of the target combination on this dimension, and perform interpolation on dimensions with different coordinate values to obtain the interpolation target
- step S2 for all register paths in the circuit, the slack is established by changing the destination register FF j and stay slack At the same time change the establishment slack of the start register FF i and stay slack So that the corresponding actual propagation delay can be obtained by interpolation calculation Enables setup time margins in the register-based flexible timing library that satisfies each register path and hold time margin When both are greater than zero, the clock period can be changed to make it the minimum, that is, in the case of satisfying (10) and (11), the minimum value of the clock period T is obtained, where the establishment of the start register i and the end register j are relaxed and maintained The slack change range satisfies (12) and (13).
- the data signal conversion time is set at 50 ps to 800 ps, and the value is uniformly taken in this range with a step size of 50 ps, and there are 16 value points;
- the step size is evenly selected in this range, and there are 5 value points in total;
- the register load capacitance is set from 1fF to 5fF, and the value is uniformly selected in this range with a step size of 1fF, and there are 5 value points in total. Any combination of the above values can get 400 combinations.
- the clock signal transition time of 247ps the register load capacitance of 2.1fF
- the setup slack of 284ps the hold slack of 384ps register propagation delay
- the clock signal transition time is 200ps
- the register load capacitance is 2fF
- the combination of setup slack and hold slack is 280ps and 380ps respectively
- the data signal transition time is 200ps
- the clock signal transition time is 250ps
- the register load capacitance is 3fF
- the setup slack and Keep the combinations with slack of 300ps and 400ps respectively and use these data as interpolation points to obtain the register propagation delay of the target combination through linear interpolation.
- the setup time of the DFF1 register 422ps, hold time 300ps, input signal transition time 307ps, clock signal transition time 181ps, the register load capacitance is 2Ff, the corresponding register propagation delay 2.066ns
- the setup time of the DFF2 register 457ps, hold time 213ps, input signal transition time 160ps, clock signal transition time 197ps, the register load capacitance is 2fF, the corresponding register propagation delay is 1.818ns
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Abstract
本发明公开了一种基于寄存器灵活时序库的电路时序优化方法,首先通过在多组输入信号转换时间、时钟信号转换时间和寄存器负载电容情况下分别对寄存器仿真,通过改变寄存器的建立松弛和保持松弛,获得此时对应的实际传播延时,并通过线性插值获得特定的输入信号转换时间、时钟信号转换时间、寄存器负载电容、建立松弛和保持松弛下寄存器实际传播延时,从而建立寄存器灵活时序库;然后利用该库对电路中的所有寄存器路径进行静态时序分析,通过改变寄存器的建立松弛和保持松弛,找到满足建立时间余量和保持时间余量均大于零条件的最小时钟周期,从而在不改变电路设计、不增加电路面积开销的情况下提高电路性能。
Description
本发明涉及一种数字集成电路时序优化方法,属于EDA技术领域。
静态时序分析是数字集成电路电路中验证电路时序约束是否满足的重要步骤。当采用传统的寄存器时序库进行静态时序分析时,寄存器的传播延时被认为与建立时间(时钟信号跳变前输入数据需保持稳定的最短时间)和保持时间(时钟信号跳变后输入数据需保持稳定的最短时间)无关,三者由寄存器的输入信号转换时间、时钟信号转换时间和寄存器负载电容唯一决定。然而,实际情况下对于特定的输入信号转换时间、时钟信号转换时间和寄存器负载电容,寄存器的传播延时与建立松弛(时钟信号跳变前输入数据实际保持稳定的时间)和保持松弛(时钟信号跳变后输入数据实际保持稳定的时间)有关。考虑三者相关性建立寄存器时序库被称为寄存器灵活时序库,在该库中,当建立松弛和保持松弛改变时,寄存器实际传播延时随之发生变化。
当采用传统寄存器时序库对数字集成电路进行静态时序分析时,即认为寄存器的传播延时与建立时间和保持时间无关时,由传统的寄存器时序库中的建立时间、保持时间和传播延时决定了电路中所有寄存器路径是否满足建立时间检查和保持时间检查。在满足所有寄存器路径的建立时间检查条件下,确定电路时序正确所需的最小时钟周期。如果该最小时钟周期(对应最高工作频率)不满足设计要求,则需对电路进行优化,付出额外的设计迭代时间及电路面积开销。
发明内容
发明目的:针对上述现有技术,提出一种基于寄存器灵活时序库的电路时序优化方法,采用更小的时钟周期满足建立时间和保持时间检查,在不改变电路设计、不增加电路面积开销的情况下提高电路性能。
技术方案:一种基于寄存器灵活时序库的电路时序优化方法,所述寄存器的建立时间T
setup、保持时间T
hold和传播延时T
cq分别指的是寄存器传统时序库中在特定的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L组合下时钟信号跳变前输入数据需保持稳定的最短时间、时钟信号跳变后输入数据需保持稳定的最短时间以及从时钟信号跳变到输出数据的时间间隔;
所述寄存器的建立松弛
保持松弛
和实际传播延时
分别指的是在特定的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L组合下时钟信号跳变前输入数据实际保持稳定的时间、时钟信号跳变后输入数据实际保持稳定的时间以及在特定建立松弛
和保持松弛
情况下,从时钟信号跳变到输出数据的时间间隔;
所述寄存器路径指的是电路中以寄存器为起点和终点的数据路径,其中起点寄存器记为FF
i,终点寄存器记为FF
j,i和j分别是起点寄存器和终点寄存器的编号,1≤i,j≤N
FF,N
FF是电路中寄存器的个数;
其中,T表示时钟周期,
和
分别表示时钟信号到达起点寄存器FF
i和终点寄存器FF
j的时间,
和
分别表示起点寄存器FF
i和终点寄存器FF
j之间所有寄存器路径中数据路径的最大延时和最小延时,
和
分别表示终点寄存器FF
j的建立时间和保持时间,
表示起点寄存器FF
i的传播延时;
所述方法包括:
S1:对于电路中的所有寄存器,确定其输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L的范围,在该范围内选择多组输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,仿真获得所有有效的建立松弛和保持松弛对,及对应的实际传播延时;
S2:对于电路中所有寄存器路径,根据每个起点寄存器和终点寄存器的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L,改变起点寄存器和终点寄存器的建立松弛和保持松弛,在满足每条寄存器路径基于寄存器灵活时序库的建立时间余量和保持时间余量都大于零的情况下,使得时钟周期最小。
有益效果:本发明的一种基于寄存器灵活时序库的电路时序优化方法,首先本发明为表征寄存器建立松弛、保持松弛和实际传播延时之间的相关性,在改变寄存器建立松弛和保持松弛仿真获得对应的实际传播延时的基础上,通过线性插值的方法获得不同建立松弛和保持松弛时的实际传播延时,和传统寄存器时序库相比,通过表征三者之间的相关性能够更全面反映寄存器时序特征,为时序优化提供依据。其次,本发明利用建立松弛、保持松弛和实际传播延时之间的相关性,对电路中的寄存器路径进行静态时序分析,与基于传统寄存器时序库的静态时序分析方法相比,本发明能够充分利用相邻寄存器路径的建立时间余量和保持时间余量,在满足所有寄存器路径的建立时间余量和保持时间余量都大于零的前提下,将时钟周期降低至最小,从而提高电路性能。
图1为寄存器建立时间、保持时间、建立松弛、保持松弛、传播延时示意图;
图2为寄存器建立松弛(setup slack)、保持松弛(hold slack)和实际传播延时(clock-to-q delay)之间的相关性示意图;
图3为相邻寄存器路径示意图。
下面结合附图对本发明做更进一步的解释。
一种基于寄存器灵活时序库的电路时序优化方法,其中,寄存器的建立时间T
setup、保持时间T
hold和传播延时T
cq分别指的是寄存器传统时序库中在特定的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L组合下时钟信号跳变前输入数据需保持稳定的最短时间、时钟信号跳变后输入数据需保持稳定的最短时间以及从时钟信号 跳变到输出数据的时间间隔。
寄存器的建立松弛
保持松弛
和实际传播延时
分别指的是在特定的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L组合下时钟信号跳变前输入数据实际保持稳定的时间、时钟信号跳变后输入数据实际保持稳定的时间以及在特定建立松弛
和保持松弛
情况下,从时钟信号跳变到输出数据的时间间隔。
寄存器路径指的是电路中以寄存器为起点和终点的数据路径,其中起点寄存器记为FF
i,终点寄存器记为FF
j,i和j分别是起点寄存器和终点寄存器的编号,1≤i,j≤N
FF,N
FF是电路中寄存器的个数。
其中,T表示时钟周期,
和
分别表示时钟信号到达起点寄存器FF
i和终点寄存器FF
j的时间,
和
分别表示起点寄存器FF
i和终点寄存器FF
j之间所有寄存器路径中数据路径的最大延时和最小延时,
和
分别表示终点寄存器FF
j的建立时间和保持时间,
表示起点寄存器FF
i的传播延时。
基于寄存器灵活时序库的电路时序优化方法包括:
S1:对于电路中的所有寄存器,确定其输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L的范围,在该范围内选择多组输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,仿真获得所有有效的建立松弛和保持松弛对,及对应的实际传播延时。
S2:对于电路中所有寄存器路径,根据每个起点寄存器和终点寄存器的输入信号转换时间S
data、时钟信号转换时间S
ck和寄存器负载电容C
L,改变起点寄存器和终点寄存器的建立松弛和保持松弛,在满足每条寄存器路径基于寄存器灵活时序库的建立时间余量和保持时间余量都大于零的情况下,使得时钟周期最小。
步骤S1中,对于寄存器传统时序库中每种输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,确定建立松弛
与保持松弛
的有效范围为
具体方法为:首先将建立松弛
与保持松弛
取足够大值进行仿真获得对应的实际传播延时
足够大值指的是当继续增加
或增加
时
不再减小;然后保持
不变减小
仿真,直至
开始增加,此时对应的
为
保持
不变减小
仿真,直至
开始增加,此时对应的
为
然后保持
不变继续减小
仿真,
继续增加直至仿真失败,即寄存器时钟信号跳变时无法得到输出数据,此时对应的
为
保持
不变继续减小
仿真,
继续增加直至仿真失败,此时对应的
为
步骤S1中,对于寄存器传统时序库中每种输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,在
与
的有效范围进行仿真获得所有有效的
和
组合下对应的
具体方法为:首先以T
step为间隔在
与
的有效范围中选择仿真点,其中
的仿真点有N
setup个,分别为
其中0≤n
setup≤N
setup-1, n
setup为
的第n个仿真点,N
setup是满足
的最大正整数,
的仿真点有N
hold个,分别为
其中0≤n
hold≤N
hold-1,n
hold为
的第n个仿真点,N
hold是满足
的最大正整数;然后对于N
setup个
仿真点和N
hold个
仿真点两两组合,在所有组合下进行仿真获得对应的
步骤S2中,对于电路中所有寄存器路径,采用寄存器传统时序库进行时序分析,获得电路的时钟周期T,对于起点寄存器FF
i和终点寄存器FF
j间的寄存器路径,获得建立时间余量
和保持时间余量
数据路径的最大延时
和最小延时
终点寄存器FF
j的建立时间
和保持时间
起点寄存器FF
i的传播延时
以及起点寄存器FF
i的输入信号转换时间
时钟信号转换时间
和负载电容
终点寄存器j的输入信号转换时间
时钟信号转换时间
和负载电容
根据寄存器传统时序库中所有输入信号转换时间、时钟信号转换时间和寄存器负载电容及步骤S1中所有仿真所得的有效的建立松弛、保持松弛及对应的实际传播延时进行插值计算,获得起点寄存器FF
i的建立松弛和保持松弛分别为
和
时,对应的实际传播延时
具体过程为:
首先,选取寄存器传统时序中最接近
且小于
的输入信号转换时间
S
data,最接近
且小于
的时钟信号转换时间
S
ck,最接近
且小于
的负载电容
C
L;选取寄存器传统时序中最接近
且大于
的输入信号转换时间
最接近
且大于
的时钟信号转换时间
最接近
且大于
的负载电容
然后,当寄存器FF
i的建立松弛和保持松弛分别为
和
时,选取N
setup个
仿真点中最接近
且小于
的建立松弛
选取N
hold个
仿真点中最接近
且小于
的建立松弛
选取N
setup个
仿真点中最接近
且大于
的建立松弛
选取N
hold个
仿真点中最接近
且大于
的建立松弛
最后,根据输入信号转换时间分别为
S
data和
时钟信号转换时间分别为
S
ck和
寄存器负载电容分别为
C
L和
建立松弛分别为
和
保持松弛分别为
和
时共32种情况下的寄存器实际传播延时,通过线性插值方式得到输入信号转换时间是
时钟信号转换时间是
寄存器负载电容是
建立松弛是
保持松弛是
时对应的寄存器FF
i的实际传播延时
线性插值方式具体为:
第一步:将32种组合中的每一个组合以及目标组合都视为一个空间坐标,则任意两个空间坐标最多存在4个相同的坐标值,将存在这种情况的两坐标相对应的寄存器传播延时记为
与
并在坐标值不同的维度上对每一对进行一维线性插值,不同的维度上分别记为
并用x
1表示目标组合在该维度上的坐标值,得到新的插值坐标以及该插值坐标对应的寄存器延时
1≤i≤16,公式如下:
第二步:第一步得到的16个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的一维就是目标组合的值,将两坐标中坐标值不同的维度记为
与
用x
2表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时
1≤j≤8,公式如下:
第三步:第二步得到8个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的两维为目标组合的值,将两坐标中坐标值不同的维度记为
与
用x
3表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时
1≤m≤4,公式如下:
第四步:由第二步得到4个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的三个维度为目标组合的值,将两坐标中坐标值不同的维度记为
与
用x
4表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时
1≤n≤2,公式如下:
第五步:由第四步得到两个坐标,两坐标只有一个维度的值不同,其余四个维度的值与目标组合的值相同,将两坐标中坐标值不同的维度记为
与
用x
5表示目标组合在该维度上的坐标值,在坐标值不同的维度上进行插值,得到插值目标
步骤S2中,对于电路中所有寄存器路径,通过改变终点寄存器FF
j的建立松弛
和保持松弛
同时改变起点寄存器FF
i的建立松弛
和保持松弛
从而通过插值计算得到对应的实际传播延时
使得在满足每条寄存器路径的基于寄存器灵活时序库的建立时间余量
和保持时间余量
都大于零的情况下,能够改变时钟周期使得其最小,即在满足(10)和(11)的情况下,取得时钟周期T的最小值,其中起点寄存器i和终点寄存器j的建立松弛和保持松弛改变范围满足(12)和(13)。
本实施例中,将数据信号转换时间设置在50ps至800ps,以50ps为步长在该范围均匀取值,共有16个取值点;将时钟信号转换时间设置在100ps至500ps,同样以50ps为步长在该范围均匀取值,共有5个取值点;将寄存器负载电容设置在1fF至5fF,以1fF为步长在该范围内均匀取值,共有5个取值点。将以上取值任意组合可得到400种 组合。
对每一种组合,将寄存器的建立松弛设为3ns,保持松弛从3ns逐渐减小至100ps,记录寄存器传播延时刚开始增大的保持松弛以及仿真失败时的保持松弛,即为保持松弛的范围,为200ps至1000ps;将寄存器的保持松弛设为3ns,建立松弛从3ns逐渐减小至100ps,记录寄存器传播延时刚开始增大的建立松弛以及仿真失败时的建立松弛,即为建立松弛的范围,为200ps至1000ps。以20ps为步长对建立松弛与保持松弛取值,共1296中组合,仿真得到所有组合的寄存器传播延时。
要得到数据信号转换时间为153ps,时钟信号转换时间为247ps,寄存器负载电容为2.1fF,建立松弛为284ps,保持松弛为384ps的寄存器传播延时,首先在上述组合中选取数据信号转换时间为150ps,时钟信号转换时间为200ps,寄存器负载电容为2fF,建立松弛与保持松弛分别为280ps与380ps的组合以及数据信号转换时间为200ps,时钟信号转换时间为250ps,寄存器负载电容为3fF,建立松弛与保持松弛分别为300ps与400ps的组合,以这些数据为插值点通过线性插值得到目标组合的寄存器传播延时。
以图3中三个寄存器连接路径作为说明,时钟信号的周期为5ns,其中寄存器DFF1至寄存器DFF2的路径不存在建立时间违规,该路径建立时间余量为0.785ns,寄存器DFF2至寄存器DFF3的路径存在建立时间违规,建立时间余量为-0.917ns。其中DFF1寄存器的建立时间
为422ps,保持时间
为300ps,输入信号转换时间
为307ps,时钟信号转换时间
为181ps,寄存器负载电容
为2Ff,对应的寄存器传播延时
为2.066ns;DFF2寄存器的建立时间
为457ps,保持时间
为213ps,输入信号转换时间
为160ps,时钟信号转换时间
为197ps,寄存器负载电容
为2fF,对应的寄存器传播延时
为1.818ns;DFF3寄存器的建立时间
为388ps,保持时间
为100ps,输入信号转换时间
为267ps,时钟信号转换时间
为224ps,寄存器负载电容
为2fF,对应的寄存器传播延时
为2.038ns;分别保持三个寄存器的输入信号转换时间,时钟信号转换时间,寄存器负载电容不变,取DFF1的建立松弛
与保持松弛
为930ps与500ps,通过寄存器灵活时序库插值得到该取值下对应的寄存 器实际传播延时
为2.065ns,取DFF2的建立松弛
与保持松弛
为950ps与950ps,通过寄存器灵活时序库插值得到该取值下对应的寄存器实际传播延时
为1.533ns,取DFF3的建立松弛
与保持松弛
为300ps与540ps,通过寄存器灵活时序库插值得到该取值下对应的寄存器实际传播延时
为3.082ns;上述取值使得寄存器DFF1至寄存器DFF2路径以及寄存器DFF2至寄存器DFF3路径的建立时间余量分别变为893ps与56ps,从而消除了时序违规,此时可得时钟周期最小值T
min为5.6ns。与基于寄存器传统时序库相比,消除时序违规所需时钟周期最小值为5.917ns,降低了5.4%。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (6)
- 一种基于寄存器灵活时序库的电路时序优化方法,其特征在于,所述寄存器的建立时间T setup、保持时间T hold和传播延时T cq分别指的是寄存器传统时序库中在特定的输入信号转换时间S data、时钟信号转换时间S ck和寄存器负载电容C L组合下时钟信号跳变前输入数据需保持稳定的最短时间、时钟信号跳变后输入数据需保持稳定的最短时间以及从时钟信号跳变到输出数据的时间间隔;所述寄存器的建立松弛 保持松弛 和实际传播延时 分别指的是在特定的输入信号转换时间S data、时钟信号转换时间S ck和寄存器负载电容C L组合下时钟信号跳变前输入数据实际保持稳定的时间、时钟信号跳变后输入数据实际保持稳定的时间以及在特定建立松弛 和保持松弛 情况下,从时钟信号跳变到输出数据的时间间隔;所述寄存器路径指的是电路中以寄存器为起点和终点的数据路径,其中起点寄存器记为FF i,终点寄存器记为FF j,i和j分别是起点寄存器和终点寄存器的编号,1≤i,j≤N FF,N FF是电路中寄存器的个数;其中,T表示时钟周期, 和 分别表示时钟信号到达起点寄存器FF i和终点寄存器FF j的时间, 和 分别表示起点寄存器FF i和终点寄存器FF j之间所有寄存器路径中数据路径的最大延时和最小延时, 和 分别表示终点寄存器FF j的建立时间和保持时间, 表示起点寄存器FF i的传播延时;所述方法包括:S1:对于电路中的所有寄存器,确定其输入信号转换时间S data、时钟信号转换时间S ck和寄存器负载电容C L的范围,在该范围内选择多组输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,仿真获得所有有效的建立松弛和保持松弛对,及对应的实际传播延时;S2:对于电路中所有寄存器路径,根据每个起点寄存器和终点寄存器的输入信号转换时间S data、时钟信号转换时间S ck和寄存器负载电容C L,改变起点寄存器和终点寄存器的建立松弛和保持松弛,在满足每条寄存器路径基于寄存器灵活时序库的建立时间余量和保持时间余量都大于零的情况下,使得时钟周期最小。
- 根据权利要求1所述的基于寄存器灵活时序库的电路时序优化方法,其特征在于,所述步骤S1中,对于寄存器传统时序库中每种输入信号转换时间、时钟信号转换时间和寄存器负载电容组合,确定建立松弛 与保持松弛 的有效范围为 具体方法为:首先将建立松弛 与保持松弛 取足够大值进行仿真获得对应的实际传播延时 所述足够大值指的是当继续增加 或增加 时 不再减小;然后保持 不变减小 仿真,直至 开始增加,此时对应的 为 保持 不变减小 仿真,直至 开始增加,此时对应的 为 然后保持 不变继续减小 仿真, 继续增加直至仿真失败,即寄存器时钟信号跳变时无法得到输出数据,此时对应的 为 保持 不变继续减小 仿真, 继续增加直至仿真失败,此时对应的 为
- 根据权利要求2所述的基于寄存器灵活时序库的电路时序优化方法,其特征在于,所述步骤S1中,对于寄存器传统时序库中每种输入信号转换时间、时钟信号转换时间 和寄存器负载电容组合,在 与 的有效范围进行仿真获得所有有效的 和 组合下对应的 具体方法为:首先以T step为间隔在 与 的有效范围中选择仿真点,其中 的仿真点有N setup个,分别为 其中0≤n setup≤N setup-1,n setup为 的第n个仿真点,N setup是满足 的最大正整数, 的仿真点有N hold个,分别为 其中0≤n hold≤N hold-1,n hold为 的第n个仿真点,N hold是满足 的最大正整数;然后对于N setup个 仿真点和N hold个 仿真点两两组合,在所有组合下进行仿真获得对应的
- 根据权利要求1所述的基于寄存器灵活时序库的电路时序优化方法,其特征在于,所述步骤S2中,对于电路中所有寄存器路径,采用寄存器传统时序库进行时序分析,获得电路的时钟周期T,对于起点寄存器FF i和终点寄存器FF j间的寄存器路径,获得建立时间余量 和保持时间余量 数据路径的最大延时 和最小延时 终点寄存器FF j的建立时间 和保持时间 起点寄存器FF i的传播延时 以及起点寄存器FF i的输入信号转换时间 时钟信号转换时间 和负载电容 终点寄存器j的输入信号转换时间 时钟信号转换时间 和负载电容根据寄存器传统时序库中所有输入信号转换时间、时钟信号转换时间和寄存器负载电容及步骤S1中所有仿真所得的有效的建立松弛、保持松弛及对应的实际传播延时进行插值计算,获得起点寄存器FF i的建立松弛和保持松弛分别为 和 时,对应的实际传播延时 具体过程为:首先,选取寄存器传统时序中最接近 且小于 的输入信号转换时间 S data,最接近 且小于 的时钟信号转换时间 S ck,最接近 且小于 的负载电容 C L;选取寄存器传统时序中最接近 且大于 的输入信号转换时间 最接近 且大于 的时钟信号转换时间 最接近 且大于 的负载电容然后,当寄存器FF i的建立松弛和保持松弛分别为 和 时,选取N setup个 仿真点中最接近 且小于 的建立松弛 选取N hold个 仿真点中最接近 且小于 的建立松弛 选取N setup个 仿真点中最接近 且大于 的建立松弛 选取N hold个 仿真点中最接近 且大于 的建立松弛
- 根据权利要求4所述的基于寄存器灵活时序库的电路时序优化方法,其特征在于,所述线性插值方式具体为:第一步:将32种组合中的每一个组合以及目标组合都视为一个空间坐标,则任意两个空间坐标最多存在4个相同的坐标值,将存在这种情况的两坐标相对应的寄存器传播延时记为 与 并在坐标值不同的维度上对每一对进行一维线性插值,不同的维度上分别记为 并用x 1表示目标组合在该维度上的坐标值,得到新的插值坐标以及该插值坐标对应的寄存器延时 公式如下:第二步:第一步得到的16个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的一维就是目标组合的值,将两坐标中坐标值不同的维度记为 与 用x 2表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时 公式如下:第三步:第二步得到8个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的两维为目标组合的值,将两坐标中坐标值不同的维度记为 与 用x 3表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时 公式如下:第四步:由第二步得到4个空间坐标,任意两个空间坐标仍最多存在四个维度的值相同,且满足这种条件的两坐标共同的三个维度为目标组合的值,将两坐标中坐标值不同的维度记为 与 用x 4表示目标组合在该维度上的坐标值,并做一维线性插值得到新的空间坐标以及对应的寄存器传播延时 公式如下:第五步:由第四步得到两个坐标,两坐标只有一个维度的值不同,其余四个维度的值与目标组合的值相同,将两坐标中坐标值不同的维度记为 与 用x 5表示目标组合在该维度上的坐标值,在坐标值不同的维度上进行插值,得到插值目标
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