WO2023010652A1

WO2023010652A1 - Array substrate and display panel

Info

Publication number: WO2023010652A1
Application number: PCT/CN2021/118026
Authority: WO
Inventors: 马涛; 吴志林; 艾飞
Original assignee: 武汉华星光电技术有限公司
Priority date: 2021-08-04
Filing date: 2021-09-13
Publication date: 2023-02-09
Also published as: US20240030228A1; CN113629076A

Abstract

Disclosed in the present application are an array substrate and a display panel. The array substrate comprises: a base substrate; a seed crystal layer, which is arranged on one side of the base substrate; and a first metal layer, which is arranged on one side of the seed crystal layer and away from the base substrate, wherein the first metal layer is in direct contact with the seed crystal layer. In the present application, the seed crystal layer, which is in direct contact with the first metal layer, is utilized to induce crystallization of the first metal layer, grains formed by the first metal layer are relatively large, and grain boundaries are few, such that scattering of charge carriers is less, thereby reducing the resistivity of the first metal layer.

Description

Array substrate and display panel

technical field

The present application relates to the display field, in particular to an array substrate and a display panel.

Background technique

Liquid crystal display (Liquid Crystal Display, LCD) and other flat-panel display devices are widely used in mobile phones, TVs, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. Various consumer electronic products have become the mainstream of display devices. LCD has two display technologies corresponding to A-Si (amorphous silicon) thin film transistor/LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) thin film transistor. LTPS thin film transistor is widely used in high specification due to its advantages of high mobility. panel technology.

The first metal layer wires in the LTPS thin film transistor display products are limited by the high temperature process, if it needs to be around 600 degrees Celsius, molybdenum (Mo) metal is mostly used in the industry at present. However, Mo metal resistance is high, and it does not take advantage of the high charging rate product demand of high-resolution, high-frequency medium-sized products.

technical problem

The present application provides an array substrate and a display panel, which can reduce the resistivity of the first metal layer.

technical solution

The present application provides an array substrate, including: a substrate, a seed layer disposed on one side of the substrate, and a first metal layer disposed on the seed layer side and away from the substrate;

Wherein, the first metal layer is in direct contact with the seed layer.

In the array substrate of the present application, the lattice structure of the first metal layer is the same as the lattice structure of the seed crystal layer.

In the array substrate of the present application, the ratio between the difference between the lattice constant of the first metal layer and the lattice constant of the seed crystal layer and the lattice constant of the first metal layer is between Within 20%.

In the array substrate of the present application, the lattice constant of the first metal layer is the same as the lattice constant of the seed crystal layer.

In the array substrate of the present application, the lattice structure of the first metal layer and the seed layer is a body-centered cubic lattice, and the lattice constant is 3.14pm.

In the array substrate of the present application, the thickness of the seed layer is in the range of 50 to 1000 angstroms, and the material of the seed layer can be tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound. at least one.

In the array substrate of the present application, the distribution density of crystal grains in the seed crystal layer is greater than the distribution density of crystal grains in the first metal layer.

In the array substrate of the present application, the grain size of the first metal layer close to the seed layer is larger than the grain size of the first metal layer far away from the seed layer.

In the array substrate of the present application, the array substrate further includes a second metal layer located on the first metal layer, the second metal layer is made of the same material as the first metal layer, and the second metal layer is made of the same material as the first metal layer. The grain size of the metal layer is smaller than the grain size of the first metal layer.

The embodiment of the present application also provides a display panel, the display panel includes an array substrate, and the array substrate includes: a substrate, a seed layer arranged on one side of the substrate, and a seed layer arranged on one side of the seed layer. side and away from the first metal layer of the substrate;

Wherein, the first metal layer is in direct contact with the seed layer.

In the array substrate of the present application, the thickness of the seed layer ranges from 50 to 1000 angstroms.

In the array substrate of the present application, the material of the seed layer is at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound.

Beneficial effect

The present application proposes an array substrate and a display panel, wherein the array substrate includes a substrate, a seed layer disposed on one side of the substrate, and a seed layer disposed on the side of the seed layer and away from the substrate. The first metal layer, wherein the first metal layer is in direct contact with the seed layer, the present application utilizes the seed layer in direct contact with the first metal layer to induce the crystallization of the metal in the first metal layer, so that the crystal formed by the first metal layer The grains are larger, the grain boundaries are less, the charge carriers are less scattered, and the resistivity of the first metal layer is reduced. In the embodiment of the present application, the resistivity of the first metal layer is reduced without adding a photomask.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of an array substrate in the prior art;

FIG. 2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

FIG. 3 is another schematic structural view of the array substrate provided by the embodiment of the present application;

Fig. 4 is a comparative schematic diagram of the grain size of the first metal layer provided by the embodiment of the present application;

FIG. 5 is a schematic flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

Embodiments of the present invention

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

In this application, unless otherwise expressly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

The following disclosure provides many different implementations or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and arrangements of specific examples are described below. Of course, they are examples only and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or reference letters in various instances, such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art may recognize the use of other processes and/or the use of other materials.

In the prior art, the wires of the first metal layer in the display panel are limited by the high-temperature process, and molybdenum metal is mostly used at present. As shown in FIG. 1 , the array substrate 100 includes a substrate 110 and a first metal layer 130 disposed on the substrate 110 . Wherein, the material of the first metal layer 130 is Mo metal. However, the high impedance of Mo metal is not conducive to the product demand for high-resolution, high-frequency, medium-sized products and high charging rates. The present application proposes the following technical solutions to solve the above technical problems.

FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application. The array substrate 100 includes a substrate 110, a seed layer 120 disposed on one side of the substrate 110, and a first metal layer 130 disposed on the side of the seed layer 120 and away from the substrate 110, the first metal layer 130 and the seed layer Layers 120 are in direct contact. Wherein, the substrate 110 may be a rigid substrate or a flexible substrate. The material for making the substrate 101 includes glass, quartz or polyimide and the like.

Wherein, the grain size of the first metal layer 130 is larger than the first threshold. The first threshold is the grain size of the first metal layer 130 when no seed layer 120 is provided. Assuming that the grain size of the first metal layer 130 is 27.5 nm when the seed layer 120 is not provided, the first threshold value is 27.5 nm.

In this embodiment, by setting the seed layer 120 in direct contact with the first metal layer 130 , the Mo metal grows on the seed layer 120 , that is, the crystallization of the first metal layer 130 is induced by the seed layer 120 . In this way, the crystal grains formed in the first metal layer 130 are larger, the grain boundaries are less, the scattering of charge carriers is less, and the resistivity of the first metal layer 130 is reduced.

In this application, the resistivity of the first metal layer 130 is reduced without changing the machine or adding a photomask, providing a high-temperature-resistant and low-resistance first metal layer solution for medium and large-sized display products, and improving the display panel. competitiveness.

The structure of the array substrate in the present application will be described below by taking any thin film transistor as an example. As shown in FIG. 3 , the array substrate 100 includes a substrate 110 , a light shielding layer 111 , a buffer layer 112 , a semiconductor layer 113 , a gate insulating layer 114 , a seed layer 120 , a first metal layer 130 , and an interlayer insulating layer arranged in sequence. layer 115 and a second metal layer 116 . In other embodiments, the array substrate 100 may further include other more film layers.

Wherein, the light-shielding layer 111 is disposed on the substrate 110 , and the light-shielding layer 111 is patterned. Patterning means that the material of the light-shielding layer coated on the entire substrate 110 is processed through processes such as exposure and etching, and a patterned light-shielding layer 111 is finally formed. The material of the light-shielding layer 111 is, for example, molybdenum-aluminum alloy, chromium metal, molybdenum metal, or other materials having both light-shielding function and conductive property. The buffer layer 112 is disposed on the light shielding layer 111 and the substrate 110 . The semiconductor layer 113 is disposed on the buffer layer 112 , and the semiconductor layer 113 is an active layer formed by patterning. The gate insulating layer 114 is disposed on the semiconductor layer 113 and the buffer layer 112 , and the gate insulating layer 114 may be made of silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiNxOy).

The seed layer 120 is disposed on the gate insulating layer 114 , the first metal layer 130 is formed on the seed layer 120 , and then the first metal layer 130 is exposed and etched to form a patterned first metal layer 130 . The patterned first metal layer 130 includes a gate layer. Wherein, the material for making the first metal layer is a high temperature resistant conductive material, such as metal Mo.

The interlayer insulating layer 115 is disposed on the first metal layer 130 and the gate insulating layer 114, the second metal layer 116 is formed on the interlayer insulating layer, and then the second metal layer 116 is exposed and etched to form a patterned The second metal layer 116 . The patterned second metal layer 116 includes source and drain layers.

In one embodiment, the lattice structure of the seed layer 120 is the same as that of the first metal layer 130 . For example, the lattice structure is body-centered cubic lattice, face-centered cubic lattice or hexagonal close-packed lattice. The seed layer 120 and the first metal layer 130 use the same lattice structure, which improves the effect of the seed layer 120 in inducing metal crystallization in the first metal layer 130 .

In one embodiment, the lattice constant of the seed layer 120 is similar to that of the first metal layer 130 . Wherein, the lattice constant refers to the side length of the unit cell, that is, the side length of each parallelepiped unit. For example, the ratio of the difference between the lattice constant of the first metal layer 130 and the lattice constant of the seed layer 120 to the lattice constant of the first metal layer 130 is within 20%. In some cases, the lattice constant of the seed layer 120 is the same as the lattice constant of the first metal layer 130 .

Using the seed layer 120 with a similar/same lattice constant as the first metal layer 130 can improve the effect of the lattice constant of the seed layer and metal crystallization in the first metal layer 130 .

In one embodiment, the lattice structure of the seed layer 120 is the same as that of the first metal layer 130 , and the lattice constant of the seed layer 120 is similar/same as that of the first metal layer 130 . Especially when the lattice structure of the seed crystal layer 120 is the same as that of the first metal layer 130, and the lattice constant of the seed crystal layer 120 is the same as that of the first metal layer 130, the first metal The crystallization effect of the metal in the layer 130 is the best, such as the order of the induced crystallization is the best, the formed grain size is the largest, the grain is the most uniform, and the junction is the smallest, the scattering of the charge carrier is the least, and the maximum degree of reduction resistivity of the first metal layer 130 .

For example, the lattice structures of the first metal layer 130 and the seed layer 120 are both body-centered cubic lattices, and the lattice constants of the first metal layer 130 and the seed layer 120 are both 3.14 picometers (pm).

The above-mentioned seed layer 120 has a thickness ranging from 50 to 1000 angstroms. Wherein, the thickness of the first metal layer 130 can be determined according to the actual requirements of the array substrate, and the thickness of the first metal layer 130 is inversely proportional to the resistance. After the thickness of the seed layer 120 reaches a certain thickness, such as the thickness corresponding to the above-mentioned thickness range, the change of the resistivity caused by increasing the thickness is not large, and the thickness of the array substrate 100 will be increased, and the cost will be increased.

The material of the aforementioned seed layer 120 may be at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound. Among them, the tungsten-molybdenum compound includes MoW ₅₀ , the aluminum-molybdenum compound includes MoAl ₂₀ , MoAl ₂₀ Ti ₁₀ , the titanium-molybdenum compound includes MoTi ₅₀ and the like.

In the above embodiment, since the seed crystal layer 120 induces metal crystallization in the first metal layer 130, the grain size in the seed crystal layer 120 is smaller than the crystal grain size in the first metal layer 130, correspondingly, the seed crystal layer The distribution density of crystal grains in 120 is greater than the distribution density of crystal grains in the first metal layer 130 .

In the above embodiment, in the first metal layer 130 , the grain size of the first metal layer 130 close to the seed layer 120 is larger than the grain size of the first metal layer 130 away from the seed layer 120 . This is because the crystal grains in the first metal layer close to the seed crystal layer 120 are crystallized first, and the crystal grains with larger sizes will also drop due to gravity.

In the above embodiment, the array substrate further includes the second metal layer 116 located on the first metal layer 130. When the first metal layer 130 and the second metal layer 116 are made of the same material, such as Mo, because The seed layer 120 is used in the first metal layer 130 to induce metal crystallization, so that the grain size of the second metal layer 116 is smaller than the grain size of the first metal layer 130 .

When the materials of the first metal layer 130 and the second metal layer 116 are the same and the grain size of the second metal layer 116 is smaller than the grain size of the first metal layer 130, in one embodiment, the second metal layer 116 can be The first metal layer 130 overlaps to form a capacitor. In this embodiment, the first metal layer 130 may be a gate layer, and the second metal layer 116 is also a metal layer, but not a source-drain layer.

In one embodiment, in the first metal layer 130 , the crystal grains close to the seed layer 120 are larger and more evenly distributed, and the crystal grains farther away from the seed layer 120 are smaller and less uniform.

In one embodiment, in the first metal layer 130, the grain size in the middle area is larger than the grain size in the two sides, so that the impedance of the edge area is greater than the impedance of the middle area to avoid overloading, which is equivalent to making the first metal layer in the edge area A metal layer acts as a protective layer.

In the above-mentioned array substrate 100, the seed crystal layer 120 is used to induce the crystallization of the first metal layer 130. Compared with that without the seed crystal layer 120, the crystal grains in the formed first metal layer 130 are larger and the grain boundaries are less. The charge carriers scatter, reducing the impedance of the first metal layer 130 . Wherein, using the seed layer 120 to induce crystallization of the first metal layer 130 can reduce the impedance in the first metal layer 130 by 30% compared with that without using the seed layer 120, thereby obtaining an array substrate with high temperature resistance and reduced impedance.

Using the seed layer 120 to induce crystallization of the first metal layer 130, the corresponding coherent diffraction line size (coherently) for measuring the grain size in the first metal layer 130 diffracting domain size) is larger than the coherent diffraction line size corresponding to the non-used seed layer 120 . Among them, the larger the size of the coherent diffraction line, the larger the crystal grain, and the smaller the corresponding resistivity. Moreover, the crystallization of the first metal layer 130 is induced by using the seed crystal layer 120 , and the grain size of the obtained first metal layer 130 is larger than that corresponding to that without the seed crystal layer 120 . For details, please refer to Table 1 below.

Table 1 Comparison of diffraction line size and grain size with and without seed layer

薄膜层 film layer	相干衍射线尺寸（nm） Coherent Diffraction Line Size (nm)	晶粒大小（nm） Grain size (nm)
第一金属层（Mo） The first metal layer (Mo)	48.7 48.7	27.5 27.5
种晶层+第一金属层（Mo） Seed layer + first metal layer (Mo)	62.7 62.7	38.7 38.7

It can be seen from Table 1 that the coherent diffraction line size corresponding to the use of the seed crystal layer 120 is 62.7nm, and the grain size is 38.7nm; while the coherent diffraction line size corresponding to the use of the seed crystal layer 120 is 48.7nm, The grain size is 27.5nm. It should be noted that the sizes shown in Table 1 and the examples of the present application are all average sizes, and the sizes shown are also average sizes.

Regardless of the size of the coherent diffraction line or the grain size, the size corresponding to the use of the seed layer 120 is larger than the size corresponding to the use of the seed layer 120 . The seed crystal layer 120 is used to induce crystallization of the first metal layer 130 , so that the crystal grains formed in the first metal layer are larger, with fewer grain boundaries, less scattering of charge carriers, and lower resistivity of the first metal layer.

As shown in FIG. 4 , it is a schematic diagram of the comparison of the grain size of the first metal layer provided by the embodiment of the present application. In Figure 2, the longer horizontal line is a reference line, and the distance between two irregular vertical lines represents the distance between grain boundaries, corresponding to the grain size. The left figure corresponds to the grain size in the first metal layer without using the seed crystal layer 120 , and the right figure corresponds to the grain size in the first metal layer corresponding to the seed crystal layer 120 . It can be seen that the (average) grain size in the right graph is larger than the (average) grain size in the left graph.

In the above embodiment, by setting the seed layer 120, the Mo metal in the first metal layer 130 grows on the seed crystals of the seed layer 120, and the seed layer 120 is used to induce the crystallization of the Mo metal, so that in the first metal layer 130 The crystal grains become larger, the grain boundaries become less, and the charge carriers at the grain boundaries scatter less, which reduces the scattering of charge carriers and reduces the resistivity of the first metal layer 130 . In the embodiment of the present application, the resistivity of the first metal layer 130 is reduced without changing the machine and without adding a photomask.

FIG. 5 is a schematic flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application. The manufacturing method of the array substrate includes the following steps.

S101, providing a substrate.

S102, forming a seed layer on the substrate at a first temperature.

A seed layer 120 is deposited on the substrate 110 using a first temperature. When depositing the seed crystal layer 120, the power of the corresponding construction equipment should be above 40kw, and the pressure when depositing the seed crystal layer 120 should be below 0.4pa.

The first temperature may be any temperature between 150 and 300 degrees, such as 200 degrees.

Specifically, the seed layer 120 may be formed using a physical vapor deposition process or a magnetron sputtering process.

S103, forming a first metal layer at a side of the seed layer away from the substrate using a second temperature, wherein the first temperature is greater than the second temperature, and the first metal layer directly contacts the seed layer.

Since the first temperature at which the seed layer is formed is greater than the second temperature at which the first metal layer is formed, the seed layer 120 and the first metal layer 130 may be formed using different temperatures in different chambers.

Wherein, the first temperature is higher than the second temperature, so that the formed seed layer 120 has better compactness, fewer defects, and better crystal form, which is beneficial to the growth of Mo crystal grains in the first metal layer 130 . The first metal layer 130 directly contacts the seed layer 120 , and the seed layer 120 is used to induce metal crystallization in the first metal layer 130 , which is beneficial to the growth of Mo grains in the first metal layer 130 .

In the array substrate 100 formed in this embodiment, a seed layer is formed, and the first metal layer 130 is formed on the seed layer, and the seed layer is used to induce the crystallization of the metal in the first metal layer, so that Larger grains, fewer grain boundaries, less scattering of charge carriers, lower resistivity of the first metal layer. In this embodiment, the resistivity of the first metal layer 130 is reduced without changing the machine tool or adding a mask.

In other embodiments, a light shielding layer 111, a buffer layer 112, a semiconductor layer 113, and a gate insulating layer 114 are sequentially formed on the substrate 110, a seed layer 120 is formed on the gate insulating layer 114, and a seed layer 120 is formed on the seed layer 120. A first metal layer 130 is formed, and the first metal layer 130 is patterned to obtain a patterned first metal layer 130 . On the patterned first metal layer 130 and the gate insulating layer 114 , an interlayer insulating layer 115 and a second metal layer 116 are sequentially formed.

An embodiment of the present application further provides a display panel, which includes the array substrate corresponding to any one of the above embodiments. For the content of the array substrate and corresponding beneficial effects, please refer to the description in the above embodiments.

In one embodiment, the display panel further includes a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.

In one embodiment, the display panel further includes a light-emitting layer disposed on the array substrate, and the light-emitting layer may include OLED (Organic Light-Emitting Diode, organic light-emitting semiconductor) light-emitting devices, mini-LEDs, micro-LEDs, etc. either.

FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 1000 includes an array substrate 100 , a color filter substrate 300 disposed opposite to the array substrate, and a liquid crystal layer 200 located between the array substrate 100 and the color filter substrate 300 .

The present application proposes an array substrate, a manufacturing method of the array substrate, and a display panel, wherein the array substrate includes a substrate, a seed layer disposed on one side of the substrate, and a seed layer disposed on the side of the seed layer and away from the substrate. The first metal layer, wherein the grain size of the first metal layer is greater than a first threshold. Under the premise of not changing the machine or adding a photomask, the present application only uses the seed crystal layer to induce the crystallization of the metal in the first metal layer, so that the crystal grains formed by the first metal layer are larger and have fewer grain boundaries, which is beneficial to the electric current. Carrier scattering is less, the resistivity of the first metal layer is reduced, and a high-temperature-resistant and low-resistance first metal layer solution is provided for medium and large-sized display products, which improves the competitiveness of the display panel.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

The above is a detailed introduction to an electronic device provided by the embodiment of the present application. In this paper, specific examples are used to illustrate the principle and implementation of the present application. The description of the above embodiment is only used to help understand the technical solution of the present application. and its core idea; those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the corresponding The essence of the technical solutions deviates from the scope of the technical solutions of the embodiments of the present application.

Claims

An array substrate, comprising: a substrate, a seed layer disposed on one side of the substrate, and a first metal layer disposed on the seed layer side and away from the substrate;

Wherein, the first metal layer is in direct contact with the seed layer.
The array substrate according to claim 1, wherein the lattice structure of the first metal layer is the same as that of the seed crystal layer.
The array substrate according to claim 2, wherein the difference between the lattice constant of the first metal layer and the lattice constant of the seed layer is equal to the difference between the lattice constant of the first metal layer The ratio is within 20%.
The array substrate according to claim 3, wherein the lattice constant of the first metal layer is the same as that of the seed crystal layer.
The array substrate according to claim 4, wherein the lattice structure of the first metal layer and the seed layer is a body-centered cubic lattice, and the lattice constant is 3.14pm.
The array substrate according to claim 1, wherein the seed layer has a thickness ranging from 50 to 1000 angstroms.
The array substrate according to claim 1, wherein a distribution density of crystal grains in the seed crystal layer is greater than a distribution density of crystal grains in the first metal layer.
The array substrate according to claim 1, wherein a grain size of the first metal layer close to the seed layer is larger than a grain size of the first metal layer far away from the seed layer.
The array substrate according to claim 1, wherein the array substrate further comprises a second metal layer located on the first metal layer, the second metal layer is made of the same material as the first metal layer, The grain size of the second metal layer is smaller than the grain size of the first metal layer.
The array substrate according to claim 1, wherein the material of the seed layer is at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound.
A display panel, which includes an array substrate, and the array substrate includes: a substrate, a seed layer arranged on one side of the substrate, and a second layer arranged on the side of the seed layer and away from the substrate. a metal layer;

Wherein, the first metal layer is in direct contact with the seed layer.
The display panel according to claim 11, wherein the lattice structure in the first metal layer is the same as that of the seed layer.
The display panel according to claim 12, wherein the difference between the lattice constant of the first metal layer and the lattice constant of the seed layer is equal to the difference between the lattice constant of the first metal layer The ratio is within 20%.
The display panel according to claim 13, wherein the lattice constant of the first metal layer is the same as the lattice constant of the seed layer.
The display panel according to claim 14, wherein the lattice structure of the first metal layer and the seed layer is a body-centered cubic lattice, and the lattice constant is 3.14pm.
The display panel according to claim 11, wherein the seed layer has a thickness ranging from 50 to 1000 angstroms.
The display panel according to claim 11, wherein a distribution density of crystal grains in the seed layer is greater than a distribution density of crystal grains in the first metal layer.
The display panel of claim 11, wherein a grain size of the first metal layer close to the seed layer is larger than a grain size of the first metal layer far from the seed layer.
The display panel according to claim 11, wherein the array substrate further comprises a second metal layer on the first metal layer, and the second metal layer is made of the same material as the first metal layer, The grain size of the second metal layer is smaller than the grain size of the first metal layer.
The display panel according to claim 11, wherein the material of the seed layer is at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound.