WO2023010234A1 - Circuit d'émission-réception et dispositif d'émission-réception pour synchronisation d'horloge - Google Patents

Circuit d'émission-réception et dispositif d'émission-réception pour synchronisation d'horloge Download PDF

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Publication number
WO2023010234A1
WO2023010234A1 PCT/CN2021/109946 CN2021109946W WO2023010234A1 WO 2023010234 A1 WO2023010234 A1 WO 2023010234A1 CN 2021109946 W CN2021109946 W CN 2021109946W WO 2023010234 A1 WO2023010234 A1 WO 2023010234A1
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WIPO (PCT)
Prior art keywords
clock signal
phase
clock
transceiver
transceiver circuit
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PCT/CN2021/109946
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English (en)
Chinese (zh)
Inventor
王东
赵兴
雷张伟
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华为技术有限公司
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Priority to PCT/CN2021/109946 priority Critical patent/WO2023010234A1/fr
Priority to CN202180099154.9A priority patent/CN117480743A/zh
Publication of WO2023010234A1 publication Critical patent/WO2023010234A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the embodiments of the present application relate to the field of electronic technologies, and in particular, to a transceiver circuit and a transceiver for clock synchronization.
  • the data receiving device needs to perform clock signal synchronization (also referred to as clock synchronization) with the data sending device, so that the data receiving device and the data sending device can communicate based on the synchronized clock signal.
  • clock signal synchronization also referred to as clock synchronization
  • An existing clock synchronization method is as follows: configure a master clock device, and the master clock device provides a reference clock signal to each of the multiple transceiver devices respectively, so that multiple transceiver devices can be based on the reference clock signal transfer data.
  • the second transceiver device among the plurality of transceiver devices uses the reference clock signal provided by the master clock device to send data to the first transceiver device among the plurality of transceiver devices
  • the first transceiver device uses the reference clock signal provided by the master clock device to transmit data from
  • the second transceiver device receives data, that is, the master clock device provides the same clock signal to the first transceiver device and the second transceiver device, so that the clock signal of the second transceiver device is synchronized with the clock signal of the first transceiver device.
  • the above method of clock synchronization needs to provide a master clock device separately, so a dedicated physical clock line must be laid out separately to connect the master clock device and multiple transceiver devices, which will occupy the interface resources of the transceiver device.
  • the embodiments of the present application provide a transceiver circuit and a transceiver device for clock synchronization, which can realize clock synchronization between the transceiver devices without occupying interface resources of the transceiver devices.
  • the embodiment of the present application provides a transceiver circuit, including: a clock adjustment module, a frequency and phase detector, and a first phase-locked loop; wherein, the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit , the first output of the clock adjustment module is connected to the first input of the frequency and phase detector, the output of the frequency and phase detector is connected to the input of the first phase-locked loop, and the output of the first phase-locked loop Connect the second input end of the clock adjustment module and the second input end of the frequency and phase detector;
  • the above-mentioned frequency and phase detector is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop at a moment;
  • the above-mentioned first phase-locked loop is configured to output a first clock signal according to the above-mentioned frequency difference
  • the above-mentioned clock adjustment module is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; and adjust the above-mentioned first clock signal according to the phase difference to obtain a second clock signal, the The second clock signal is synchronized with the clock signal of the first transceiver device; and the receiving clock signal of the transceiver circuit is updated to the second clock signal, and the second clock signal is used for receiving data from the first transceiver device.
  • the frequency detector and phase detector in the transceiver circuit can determine the current receiving clock signal of the transceiver circuit and the clock output by the first phase-locked loop in the transceiver circuit at a previous moment The frequency difference of the signal; and the first phase-locked loop outputs the first clock signal according to the frequency difference; then, the clock adjustment module in the transceiver circuit communicates with the clock signal of the first transceiver device on the first phase-locked loop in the transceiver circuit The phase difference of the clock signal output at a moment adjusts the first clock signal to obtain a second clock signal, and the second clock signal is synchronized with the clock signal of the first transceiver device.
  • the transceiver circuit for clock synchronization provided by the embodiment of the present application does not need to set up a master clock device for providing a reference clock signal, so there is no need to occupy the interface resources of the transceiver device during the clock synchronization process. That is to say, the transceiver circuit for clock synchronization provided by the embodiment of the present application can
  • the above-mentioned clock adjustment module may include: a phase detection module and a first phase interpolator; the first input end of the phase detection module is coupled to the first input end of the above-mentioned clock adjustment module, and the phase detection module
  • the output terminal of the first phase interpolator is connected to the first input terminal of the first phase interpolator
  • the second input terminal of the first phase interpolator is coupled to the second input terminal of the above-mentioned clock adjustment module
  • the output terminal of the first phase interpolator is coupled to the above-mentioned
  • the first output end of the clock adjustment module, and the output end of the first phase interpolator is connected to the second input end of the phase detection module
  • the above-mentioned phase detection module is used to determine the phase difference between the clock signal of the above-mentioned first transceiver device and the current clock signal of the transceiver circuit;
  • the first phase interpolator is configured to adjust the first clock signal according to the phase difference to obtain the second clock signal.
  • the above-mentioned transceiver circuit further includes: an analog-to-digital converter, the input end of the analog-to-digital converter is coupled to the input end of the above-mentioned transceiver circuit, and the output end of the analog-to-digital converter is connected to the clock adjustment module. input terminal;
  • the aforementioned analog-to-digital converter is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.
  • the transceiver circuit further includes a second phase interpolator, the first input terminal of the second phase interpolator is connected to the output terminal of the first phase-locked loop, and the second phase interpolator of the second phase interpolator The input end is connected to the second output end of the clock adjustment module, and the output end of the phase detection module is coupled to the second output end of the clock adjustment module;
  • the second phase interpolator is used to adjust the above-mentioned first clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a third clock signal, and the third clock signal is the same as the clock of the above-mentioned first transceiver device signal synchronization; and updating the sending clock signal of the transceiver circuit to the third clock signal, where the third clock signal is used to send data to the first transceiver device.
  • the above-mentioned transceiver circuit further includes: a second phase interpolator and a second phase-locked loop, the input end of the second phase-locked loop is connected to the output end of the above-mentioned frequency and phase detector, and the second phase-locked loop The output end of the phase loop is connected to the first input end of the second phase interpolator, the second input end of the second phase interpolator is connected to the second output end of the above-mentioned clock adjustment module, and the output end of the above-mentioned phase detection module is coupled to the above-mentioned clock adjusting the second output terminal of the module;
  • the above-mentioned second phase-locked loop is used to output the fourth clock signal according to the above-mentioned frequency difference
  • the second phase interpolator is configured to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a fifth clock signal, which is identical to that of the first transceiver device Clock signal synchronization; and updating the sending clock signal of the transceiver circuit to the fifth clock signal, the fifth clock signal is used to send data to the first transceiver device.
  • the embodiment of the present application provides another transceiver circuit, including: a clock adjustment module, a low-pass filter, and a first phase-locked loop; wherein, the first input end of the clock adjustment module is coupled to the input end of the transceiver circuit , the first output end of the clock adjustment module is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the first phase-locked loop, and the output end of the first phase-locked loop is connected to the clock adjustment the second input terminal of the module;
  • the above-mentioned low-pass filter is used to determine the frequency difference between the current receiving clock signal of the above-mentioned transceiver circuit and the receiving clock signal of the previous moment of the transceiver circuit;
  • the above-mentioned first phase-locked loop is configured to output a first clock signal according to the above-mentioned frequency difference
  • the clock adjustment module is configured to determine a first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and adjust the first clock signal according to the first phase difference to obtain the first phase difference Two clock signals, the second clock signal is synchronized with the clock signal of the above-mentioned first transceiver device; Receive data.
  • the low-pass filter in the transceiver circuit can determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the previous moment of the transceiver circuit, and convert the frequency The difference is sent to the first phase-locked loop; the first phase-locked loop adjusts and outputs the first clock signal to the receiving clock signal of the transceiver circuit at a moment according to the frequency difference, and then realizes the clock signal output by the first phase-locked loop at a moment Synchronization with the frequency of the current receiving clock signal of the transceiver circuit; then, the clock adjustment module determines the first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and according to the first phase difference pair The first clock signal is adjusted to obtain a second clock signal, and the second clock signal is synchronized with the clock signal of the first transceiver device.
  • the transceiver circuit for clock synchronization provided by the embodiment of the present application does not need to set up a master clock device for providing a reference clock signal, so there is no need to occupy the interface resources of the transceiver device during the clock synchronization process. That is to say, the transceiver circuit for clock synchronization provided in the embodiment of the present application can realize clock synchronization between transceiver devices without occupying interface resources of the transceiver devices.
  • the above-mentioned low-pass filter is specifically used to determine the The frequency difference between the current reception clock signal of the transceiver circuit and the reception clock signal of the previous moment of the transceiver circuit.
  • the above-mentioned clock adjustment module includes a phase detection module and a first phase interpolator; the first input end of the phase detection module is coupled to the first input end of the above-mentioned clock adjustment module, and the first input end of the phase detection module
  • the output terminal is coupled to the first output terminal of the above-mentioned clock adjustment module, the second output terminal of the phase detection module is connected to the first input terminal of the first phase interpolator, and the second input terminal of the first phase interpolator is coupled to the above-mentioned clock
  • the second input terminal of the adjustment module, the output terminal of the first phase interpolator is connected to the second input module of the phase detection module;
  • the above-mentioned phase detection module is used to determine the first phase difference according to the clock signal of the above-mentioned first transceiver device and the current receiving clock signal of the above-mentioned transceiver circuit;
  • the first phase interpolator is configured to adjust the first clock signal according to the first phase difference to obtain a second clock signal.
  • the above-mentioned transceiver circuit further includes an analog-to-digital converter, the input end of the analog-to-digital converter is coupled to the input end of the above-mentioned transceiver circuit, and the output end of the analog-to-digital converter is connected to the input of the above-mentioned clock adjustment module end;
  • the aforementioned analog-to-digital converter is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.
  • the transceiver circuit further includes a second phase interpolator, the first input terminal of the second phase interpolator is connected to the output terminal of the first phase-locked loop, and the second phase interpolator of the second phase interpolator The input end is connected to the second output end of the above-mentioned clock adjustment module, and the output end of the above-mentioned phase detection module is also coupled with the second output end of the above-mentioned clock adjustment module;
  • the above-mentioned second phase interpolator is used to adjust the first clock signal according to the second phase difference output by the second output terminal of the clock adjustment module to obtain the third clock signal, and the third clock signal is compatible with the above-mentioned first transceiver
  • the clock signal of the device is synchronized; and the sending clock signal of the transceiver circuit is updated to a third clock signal, and the third clock signal is used to send data to the first transceiver device.
  • the above-mentioned transceiver circuit further includes a second phase interpolator and a second phase-locked loop, the input end of the second phase-locked loop is connected to the output end of the above-mentioned low-pass filter, and the second phase-locked loop
  • the output end of the second phase interpolator is connected to the first input end of the second phase interpolator
  • the second input end of the second phase interpolator is connected to the second output end of the above-mentioned clock adjustment module
  • the output end of the above-mentioned phase detection module is also connected to the above-mentioned clock adjustment module
  • the second output terminal coupling
  • the above-mentioned second phase-locked loop is used to output the fourth clock signal according to the above-mentioned frequency difference
  • the second phase interpolator is configured to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain the fifth clock signal, which is compatible with the first transceiver
  • the clock signal of the device is synchronized; and the sending clock signal of the above-mentioned transceiver circuit is updated to the fifth clock signal, and the fifth clock signal is used to send data to the first sending and receiving device.
  • the embodiment of the present application provides a transceiver device, which includes the transceiver circuit described in any one of the first aspect and its possible implementations or any one of the second aspect and its possible implementations The transceiver circuit.
  • FIG. 1 is a schematic diagram 1 of a circuit system for clock synchronization provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a phase offset provided by an embodiment of the present application.
  • FIG. 3 is a first schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application
  • FIG. 4 is a second schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application
  • FIG. 5 is a third schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application.
  • FIG. 6 is a fourth schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a transceiver circuit for clock synchronization provided in the embodiment of the present application (5);
  • FIG. 8 is a first schematic diagram of a communication system provided by an embodiment of the present application.
  • FIG. 9 is a sixth schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a transceiver circuit for clock synchronization provided in the embodiment of the present application VII;
  • FIG. 11 is a schematic diagram eight of a transceiver circuit for clock synchronization provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a transceiving circuit for clock synchronization provided in the embodiment of the present application 9;
  • FIG. 13 is a schematic diagram of a transceiver circuit for clock synchronization provided by an embodiment of the present application.
  • FIG. 14 is a second schematic diagram of a communication system provided by an embodiment of the present application.
  • FIG. 15 is a first schematic flow diagram of a synchronous clock signal flow provided by an embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first clock signal and the second clock signal are used to distinguish different clock signals, not to describe a specific sequence of clock signals.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • Fig. 1 is a schematic diagram of an existing circuit for clock synchronization, the clock synchronization circuit includes device A, device B, device C and a master clock device; wherein, device A, device B and device C are all transceiver devices , which has a similar structure.
  • a transceiver device includes: a sending unit, a receiving unit, and a phase buffer, where the sending unit is used to send data, the receiving unit is used to receive data, and the phase buffer is used to store a phase offset.
  • the clock signals used to send or receive data on the three devices of device A, device B, and device C are different. Therefore, the master clock device provides reference clock signals to device A, device B, and device C respectively, that is, the master clock The devices synchronize the same reference clock signal to device A, device B, and device C respectively, so that device A, device B, and device C all use the reference clock signal provided by the master clock device to send or receive data, that is, the reference clock signal is three The clock signal after clock synchronization of two devices.
  • the data sending device needs to compensate the phase of the reference clock signal to reduce
  • the error between the clock signals of the three devices keeps the clock signals of the three devices in sync.
  • device A before device A sends data to device B, device A first obtains phase offset 1 from the phase buffer, then device A adjusts the reference clock signal according to phase offset 1 to obtain clock signal 1, and then Send data to device B according to clock signal 1.
  • Device B obtains the actual clock signal used by device A to send data (the clock signal may be clock signal 1, or a clock signal with a certain phase deviation from clock signal 1, the deviation is due to ambient temperature or noise, etc.
  • device B calculates the phase offset 2 according to the actual clock signal and the reference clock signal of the device B, and then device B adjusts the reference clock signal according to the phase offset 2 to obtain Clock signal 2, and then device B receives data sent by device A based on clock signal 2, and device B sends the above-mentioned phase offset 2 to device A based on clock signal 2 (it should be understood that at this time, phase offset 2 is used as a data sent to device A).
  • device A calculates the phase offset 3 based on the acquired actual clock signal used by device B to send data (the data is phase offset 2) and the reference clock signal of device A, and then the device A adjusts the reference clock signal of device A according to the phase offset 3 to obtain clock signal 3, and then device A receives the phase offset 2 sent by device B based on clock signal 3, and stores the phase offset 2 in the phase buffer of device A
  • the phase offset is updated from phase offset 1 to phase offset 2 for sending data to device B subsequently.
  • the above method of clock synchronization needs to provide a master clock device separately, so a dedicated physical clock line must be laid out separately to connect the master clock device with the data sending device and the data receiving device, which will occupy the interface resources of the data sending device and the data receiving device .
  • the embodiment of the present application provides a transceiver circuit and a transceiver device for clock synchronization, which can be used without occupying the interface resources of the transceiver device In the case of , implement clock synchronization between transceiver devices.
  • the transceiver circuit includes: a clock adjustment module 13, a frequency and phase detector 11, and a first phase-locked loop 12; the first input terminal 131 of the clock adjustment module 13 is coupled to the transceiver circuit The input end, the first output end 132 of the clock adjustment module 13 is connected to the first input end 111 of the frequency and phase detector 11, and the output end 113 of the frequency and phase detector 11 is connected to the input end 121 of the first phase-locked loop 12, The output terminal 122 of the first phase-locked loop 12 is connected to the second input terminal 133 of the clock adjustment module 13 and the second input terminal 112 of the frequency and phase detector 11 .
  • the frequency and phase detector 11 is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output at a moment on the first phase-locked loop 12; the first phase-locked loop 12 is used to Output the first clock signal; the clock adjustment module 13 is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; and adjust the first clock signal according to the phase difference to obtain the second clock signal; and updating the receiving clock signal of the transceiver circuit to a second clock signal, the second clock signal is synchronized with the clock signal of the first transceiver device, and the second clock signal is used to receive data from the first transceiver device.
  • the current receiving clock signal (denoted as clock signal a) of the above-mentioned transceiver circuit is used as the reference clock signal of the frequency and phase detector 11, and the clock signal (denoted as clock signal a) output by the first phase-locked loop 12 at a previous moment is used as be the clock signal b) as the feedback clock signal of the frequency and phase detector 11, the frequency and phase detector 11 performs frequency discrimination on the above-mentioned reference clock signal and the feedback clock signal, and outputs the frequency between the above-mentioned reference clock signal and the feedback clock signal Difference.
  • the transceiver device to which the transceiver circuit shown in FIG. 3 is applied is referred to as a second transceiver device.
  • the above-mentioned frequency difference between the reference clock signal and the feedback clock signal may be expressed in a frequency control word, and the frequency control word is used to indicate the frequency difference between the clock signal a and the clock signal b.
  • the first phase-locked loop 12 adjusts the frequency of the clock signal b according to the frequency difference to obtain the first clock signal, wherein , the frequency of the first clock signal is the same as that of the clock signal b.
  • the frequency detector and phase detector in the transceiver circuit can determine the current receiving clock signal of the transceiver circuit and the clock output by the first phase-locked loop in the transceiver circuit at a previous moment The frequency difference of the signal; and the first phase-locked loop outputs the first clock signal according to the frequency difference; then, the clock adjustment module in the transceiver circuit communicates with the clock signal of the first transceiver device on the first phase-locked loop in the transceiver circuit The phase difference of the clock signal output at a moment adjusts the first clock signal to obtain a second clock signal, and the second clock signal is synchronized with the clock signal of the first transceiver device.
  • the transceiver circuit for clock synchronization provided by the embodiment of the present application does not need to separately provide a master clock device for providing a reference clock signal, so there is no need to occupy the interface resources of the transceiver device during the clock synchronization process That is to say, the transceiver circuit for clock synchronization provided in the embodiment of the present application can realize clock synchronization between transceiver devices without occupying interface resources of the transceiver devices.
  • the clock adjustment module 13 includes: a phase detection module 14 and a first phase interpolator 15 ; the first input terminal 141 of the phase detection module 14 is coupled to the clock adjustment module 13 The first input terminal 131, the output terminal 142 of the phase detection module 14 is connected to the first input terminal 151 of the first phase interpolator 15, and the second input terminal 152 of the first phase interpolator 15 is coupled to the second input of the clock adjustment module 13 terminal 133 , the output terminal 153 of the first phase interpolator 15 is coupled to the first output terminal 132 of the clock adjustment module 13 , and the output terminal 153 of the first phase interpolator 15 is connected to the second input terminal 143 of the phase detection module 14 .
  • the phase detection module 14 is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; the first phase interpolator 15 is used to adjust the first clock signal according to the phase difference to obtain Second clock signal.
  • the above-mentioned first phase interpolator 15 is used to adjust the first clock signal according to the above-mentioned phase difference, and in the process of obtaining the second clock signal, adjusting the first clock signal may include the following adjustment method A or adjustment method Either of B.
  • Adjustment method A When the frequency of the clock signal of the first transceiver device is greatly different from the frequency of the first clock signal, both the frequency and phase of the first clock signal need to be adjusted to obtain the second clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference, for example, when the phase difference is a positive number, the phase of the first clock signal is shifted forward (for example, along the X-axis of the coordinate system Right offset), the offset is the phase difference; when the phase difference is a negative number, the phase of the first clock signal is shifted backward, and the offset is the phase difference; since the phase difference is the integral of the frequency difference Therefore, the frequency difference between the clock signal of the first transceiver device and the first clock signal is calculated according to the phase difference, and then the frequency of the first clock signal is adjusted according to the frequency difference, for example, when the above-mentioned phase difference is a positive number , reducing the frequency of the first clock signal, wherein the amount of reduction is the frequency difference; when the above-
  • Adjustment mode B under the condition that the frequency of the clock signal of the first transceiver device is slightly different from the frequency of the first clock signal, the frequency of the first clock signal may not be adjusted (the frequency of the first clock signal is different from that of the first transceiver device).
  • the frequency difference of the clock signal is very small, and the frequency difference can be ignored, that is, the frequency of the first clock signal is considered to be approximately equal to the frequency of the first transceiver device), and only the phase of the first clock signal is adjusted to obtain the second clock signal.
  • the phase of the first clock signal is shifted according to the phase difference, for example, when the phase difference is a positive number, the phase of the first clock signal is shifted forward, and the shift amount is the phase difference; When the phase difference is a negative number, the phase of the first clock signal is shifted backward by the phase difference.
  • the transceiver circuit for clock synchronization may further include: an analog-to-digital converter 16, and the input terminal 161 of the analog-to-digital converter 16 is coupled to the transceiver circuit
  • the input terminal 162 of the analog-to-digital converter 16 is connected to the input terminal 131 of the clock adjustment module 13 .
  • the analog-to-digital converter 16 is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.
  • the processing of the clock signal is usually processed in the form of a digital signal. Therefore, after the transceiver circuit obtains the clock signal (the clock signal is an analog signal) of the first transceiver device, the analog-to-digital converter 16 converts The clock signal of the first transceiver device is converted from an analog signal to a digital signal, and then the clock signal in the form of a digital signal is input to the clock adjustment module 13 .
  • the transceiver circuit for clock synchronization may further include a component or module for synchronizing the sending clock signal of the transceiver circuit, that is, when the transceiver circuit receives the data sent by the first transceiver device, Not only the receiving clock signal of the transceiver circuit is synchronized with the clock signal of the first transceiver device, but also the sending clock signal of the transceiver circuit is synchronized with the clock signal of the first transceiver circuit.
  • the transceiver circuit for clock synchronization provided by the embodiment of the present application further includes a second phase interpolator 17, the first input of the second phase interpolator 17
  • the terminal 171 is connected to the output terminal 122 of the first phase-locked loop
  • the second input terminal 172 of the second phase interpolator 17 is connected to the second output terminal 134 of the clock adjustment module 13
  • the output terminal 142 of the above-mentioned phase detection module 14 is coupled to the clock adjustment module.
  • the second output terminal 134 of the module 13 is coupled to the clock adjustment module.
  • the second phase interpolator 17 is used to adjust the first clock signal according to the phase difference output by the second output terminal 134 of the clock adjustment module 13 to obtain a third clock signal, which is the same as the clock signal of the first transceiver device synchronizing; and updating the sending clock signal of the transceiver circuit to a third clock signal, the third clock signal is used to send data to the first transceiver device.
  • the second phase interpolator 17 adjusts the first clock signal according to the above-mentioned phase difference.
  • Adjustment, during the process of obtaining the third clock signal, adjusting the first clock signal may include any one of the following adjustment mode C and adjustment mode D.
  • Adjustment mode C When the frequency of the clock signal of the first transceiver device differs greatly from the frequency of the first clock signal, both the frequency and phase of the first clock signal need to be adjusted to obtain a third clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference; since the phase difference is the integral of the frequency difference, the clock signal of the first transceiver device and the phase of the first clock signal are calculated according to the phase difference. frequency difference, and then adjust the frequency of the first clock signal according to the frequency difference, and then obtain the adjusted first clock signal, that is, the third clock signal.
  • Adjustment mode D When the difference between the frequency of the clock signal of the first transceiver device and the frequency of the first clock signal is small, only adjust the phase of the first clock signal to obtain the third clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference, so as to obtain the adjusted first clock signal, that is, the third clock signal.
  • the second transceiving device applying the transceiving circuit provided in the embodiment of the present application includes a transmitting unit and a receiving unit. It should be understood that the clock adjustment module 13 in the above-mentioned transceiver circuit is set on the receiving unit, and the above-mentioned second phase interpolator 17 Set on the sending unit.
  • the phase difference can be stored in a buffer table corresponding to the second phase interpolator 17 (for example, : In the look-up table (look up table, LUT)), when the second transceiver device sends data to the first transceiver device, the second phase interpolator 17 reads the phase difference from the LUT table, and adjusts the first phase difference according to the phase difference a clock signal to obtain a third clock signal, so that the second transceiver device sends data to the first transceiver device according to the third clock signal.
  • a buffer table for example, : In the look-up table (look up table, LUT)
  • phase difference module 14 in the above-mentioned clock adjustment module 13 filters the phase difference (that is: includes a filter in the phase detection module 14), and then the first phase interpolator 15 adjusts the first clock signal according to the filtered phase difference (that is: a more accurate phase difference); at the same time, the buffer corresponding to the second phase interpolator 17
  • the phase difference stored in the table is also the phase difference after filtering.
  • the transceiver circuit for clock synchronization may further include: a second phase interpolator 17 and a second phase-locked loop 18, the The input 181 of the second phase-locked loop 18 is connected to the output 113 of the frequency and phase detector 11, and the output 182 of the second phase-locked loop 18 is connected to the first input 171 of the second phase interpolator 17, and the second phase interpolation
  • the second input terminal 172 of the device 17 is connected to the second output terminal 134 of the clock adjustment module 13
  • the output terminal 142 of the phase detection module 14 is coupled to the second output terminal 134 of the clock adjustment module 13 .
  • the second phase-locked loop 18 is used for outputting the fourth clock signal according to the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of a moment on the transceiver circuit; the second phase interpolator 17 is used for adjusting the module according to the clock The phase difference output by the second output terminal 134 of 13 adjusts the fourth clock signal to obtain the fifth clock signal, and the fifth clock signal is synchronized with the clock signal of the first transceiver device; and the sending clock signal of the transceiver circuit is updated to the first Five clock signals, the fifth clock signal is used to send data to the first transceiver device.
  • the above-mentioned fourth clock signal and the first clock signal are clock signals output according to the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop 12 at a moment, so The above-mentioned fourth clock signal is exactly the same clock signal as the first clock signal.
  • adjusting the fourth clock signal may include the following adjustment method E and adjustment method Either of F.
  • Adjustment method E When the frequency of the clock signal of the first transceiver device is greatly different from the frequency of the fourth clock signal, both the frequency and phase of the fourth clock signal need to be adjusted to obtain the fifth clock signal.
  • the above-mentioned adjustment method E is similar to the above-mentioned adjustment method A, and for details, reference may be made to the related description of the above-mentioned embodiment about the adjustment method A.
  • Adjustment mode F when the difference between the frequency of the clock signal of the first transceiver device and the frequency of the fourth clock signal is small, only adjust the phase of the fourth clock signal to obtain the fifth clock signal.
  • the above-mentioned adjustment method F is similar to the above-mentioned adjustment method B, and for details, reference may be made to the related description about the adjustment method B in the above-mentioned embodiment.
  • an embodiment of the present application provides a transceiver device, which includes a transceiver circuit as shown in any one of FIGS.
  • the specific process for the transceiver circuit corresponding to the second transceiver device to synchronize the clock signal of the first transceiver device is as follows:
  • the clock adjustment module in the transceiver device determines the phase difference 1 between the two clock signals according to the clock signal corresponding to the first data and the current receiving clock signal of the second transceiver device; the clock adjustment module adjusts the first clock signal according to the phase difference 1
  • the phase and frequency of the clock signal output at a moment on the phase-locked loop obtain clock signal 1, wherein, the clock signal 1 is synchronized with the clock signal of the first transceiver device;
  • the clock signal is updated to clock signal 1.
  • the clock adjustment module of the second transceiver device sends the phase difference 1 to the second phase difference device of the second transceiver device; at the same time, the clock adjustment module of the second transceiver device sends the clock signal 1 to the frequency identification
  • the phase detector, the frequency detector and the phase detector determine the frequency difference 1 of the two clock signals according to the clock signal 1 and the clock signal output by the first phase-locked loop at a moment, and the frequency detector sends the frequency difference 1 to the first phase lock loop
  • the first phase-locked loop adjusts the frequency of the clock signal output at a moment on the first phase-locked loop according to the frequency difference 1 to obtain a clock signal 2, wherein the clock signal 2 is synchronized with the frequency of the clock signal 1,
  • the first phase-locked loop sends the clock signal 2 to the sending unit and the receiving unit of the second transceiver device, so that when the first transceiver device sends second data to the second transceiver device, the clock adjustment module adjusts the clock signal according to the phase difference 2 Clock
  • the first transceiver device sends the second data to the second transceiver device
  • the phase of the clock signal for sending the data may be shifted; therefore, the first transceiver device sends the second data to the second transceiver device.
  • the second transceiver device needs to continue to synchronously send the clock signal corresponding to the second data, and the synchronization process of the clock signal is specifically: the clock adjustment module in the second transceiver device matches the clock signal corresponding to the second data with the second transceiver The current receiving clock signal of the device (i.e.
  • clock signal 1 determines the phase difference 2 of the two clock signals; the clock adjustment module adjusts the phase sum of the clock signal 2 output by the first phase-locked loop at the previous moment according to the phase difference 2 frequency, to obtain the clock signal 3, it should be noted here that the clock signal 3 is synchronized with the frequency of the first transceiver device, therefore, the frequency adjustment of the clock signal 3 by the clock adjustment module according to the phase difference 2 is negligibly small.
  • the clock adjustment module updates the current receiving clock signal (that is: clock signal 1) of the second transceiver device to clock signal 3, and in addition, the clock adjustment module sends the phase difference 2 to the sending unit of the second transceiver device; Simultaneously, the clock adjustment module sends this clock signal 3 to the frequency detector; The frequency difference is 2, and the frequency difference detector sends the frequency difference 2 to the first phase-locked loop.
  • the first phase-locked loop adjusts the frequency of the clock signal 2 output at a moment on the first phase-locked loop according to the frequency difference 2 to obtain a clock signal 4, wherein the clock signal 4 is synchronized with the frequency of the clock signal 3, and the first phase-locked loop
  • the ring transmits this clock signal 4 to the transmitting unit and the receiving unit of the second transceiving device.
  • the sending unit of the second transceiver device When the sending unit of the second transceiver device receives the clock signal 2 and the phase difference 1, the sending unit synchronizes the clock signal 2 and stores the phase difference in the cache table corresponding to the sending unit; when the sending unit of the second transceiver device When receiving the clock signal 4 and the phase difference 2, the sending unit synchronizes the clock signal 4, and updates the phase difference 1 corresponding to the first transceiver device in the cache table to the phase difference 2.
  • the second transceiver device sends data to the first transceiver device
  • the second phase interpolator in the sending unit of the second transceiver device adjusts the clock signal 4 according to the phase difference 2 to obtain a clock signal 5, and uses the clock signal 5 to send data to the first transceiver device.
  • a transceiver device transmits data, wherein the clock signal 5 is synchronized with the clock signal of the first transceiver device.
  • the embodiment of the present application provides another transceiver circuit and transceiver device for clock synchronization, which can be used without occupying the interface resources of the transceiver device In the case of resources, clock synchronization between transceiver devices is realized.
  • the transceiver circuit includes: a clock adjustment module 23, a low-pass filter 21, and a first phase-locked loop 22; wherein, the first input terminal 231 of the clock adjustment module 23 is coupled to the transceiver circuit input end, the first output end 232 of the clock adjustment module 23 is connected to the input end 211 of the low-pass filter 21, and the output end 212 of the low-pass filter 21 is connected to the input end 221 of the first phase-locked loop 22, and the first phase-locked loop
  • the output end 222 of the ring 22 is connected to the second input end 233 of the clock adjustment module 23 .
  • the low-pass filter 21 is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal at a moment on the transceiver circuit;
  • the first phase-locked loop 22 is used to output the first clock signal according to the frequency difference;
  • the adjustment module 23 is used to determine the first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and adjust the first clock signal according to the first phase difference to obtain the second clock signal, the second The clock signal is synchronized with the clock signal of the first transceiver device; and the receiving clock signal of the transceiver circuit is updated to a second clock signal, and the second clock signal is used for receiving data from the first transceiver device.
  • the above-mentioned low-pass filter 21 is specifically used to determine the current receiving clock signal of the transmitting and receiving circuit according to the phase difference between the current receiving clock signal of the transmitting and receiving circuit output by the clock adjustment module 23 and the receiving clock signal of the transmitting and receiving circuit at a previous moment.
  • the method for determining the frequency difference specifically includes: based on the relationship that the phase difference is an integral of the frequency difference, calculating the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal of the transceiver circuit at a previous moment according to the phase difference.
  • first phase-locked loop 22 is specifically used to control the output of the first phase-locked loop 22 at a previous moment according to the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal of the transceiver circuit at a previous moment.
  • the frequency of the clock signal is adjusted, for example, when the above-mentioned phase difference is a positive number, the frequency of the clock signal output by the first phase-locked loop 22 at a moment is reduced, wherein the amount of reduction is the above-mentioned frequency difference; when When the above-mentioned phase difference is a negative number, increase the frequency of the clock signal output by the first phase-locked loop 22 at a previous moment, wherein the increased amount is the above-mentioned frequency difference; and then obtain the first clock signal.
  • the first clock signal is synchronized with the frequency of the current receiving clock of the transceiver circuit.
  • the frequency difference may be expressed in the form of a frequency control word, which is used to indicate the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal of the transceiver circuit at a previous moment.
  • the first clock signal is adjusted according to the phase difference to obtain the second clock signal.
  • the first clock signal is adjusted according to the phase difference to obtain the second clock signal.
  • the low-pass filter in the transceiver circuit can determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the previous moment of the transceiver circuit, and convert the frequency The difference is sent to the first phase-locked loop; the first phase-locked loop adjusts and outputs the first clock signal to the receiving clock signal of the transceiver circuit at a moment according to the frequency difference, and then realizes the clock signal output by the first phase-locked loop at a moment Synchronization with the frequency of the current receiving clock signal of the transceiver circuit; then, the clock adjustment module determines the first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and according to the first phase difference pair The first clock signal is adjusted to obtain a second clock signal, and the second clock signal is synchronized with the clock signal of the first transceiver device.
  • the transceiver circuit for clock synchronization provided by the embodiment of the present application does not need to set up a master clock device for providing a reference clock signal, so there is no need to occupy the interface resources of the transceiver device during the clock synchronization process. That is to say, the transceiver circuit for clock synchronization provided in the embodiment of the present application can realize clock synchronization between transceiver devices without occupying interface resources of the transceiver devices.
  • the clock adjustment module 23 specifically includes: a phase detection module 30 and a first phase interpolator 31; the first input terminal 301 of the phase detection module 30 is coupled to the clock adjustment module The first input end 231 of the phase detection module 30, the first output end 302 of the phase detection module 30 is coupled to the first output end 232 of the clock adjustment module 23, and the second output end 303 of the phase detection module 30 is connected to the first phase interpolator 31.
  • An input terminal 311, the second input terminal 312 of the first phase interpolator 31 is coupled to the second input terminal 233 of the clock adjustment module 23, the output terminal 313 of the first phase interpolator 31 is connected to the second input module of the phase detection module 30 304.
  • the phase detection module 30 is used to determine the first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; the first phase interpolator 31 is used to calculate the first phase difference according to the first phase difference The first clock signal is adjusted to obtain the second clock signal.
  • both the first output terminal 302 and the second output terminal 303 of the above-mentioned phase detection module 30 are used to output the phase difference, and the form of the phase difference output by the first output terminal 302 of the phase detection module 30 can be a phase code word , the phase codeword is used to indicate the phase difference between the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit.
  • the transceiver circuit for clock synchronization may further include: an analog-to-digital converter 24, and the input end 241 of the analog-to-digital converter 24 is coupled to the transceiver circuit The input end of the circuit and the output end 242 of the analog-to-digital converter are connected to the input end 231 of the clock adjustment module 23 .
  • the analog-to-digital converter 24 is configured to convert the clock signal of the first transceiver device from an analog signal to a digital signal.
  • the processing of the clock signal is usually processed in the form of a digital signal. Therefore, after the transceiver circuit obtains the clock signal (the clock signal is an analog signal) of the first transceiver device, the analog-to-digital converter 24 converts The clock signal of the first transceiver device is converted from an analog signal to a digital signal, and then the clock signal in the form of a digital signal is input to the clock adjustment module 23 .
  • the transceiver circuit for clock synchronization may further include a component or module for synchronizing the sending clock signal of the transceiver circuit, that is, when the transceiver circuit receives the data sent by the first transceiver device, Not only the receiving clock signal of the transceiver circuit is synchronized with the clock signal of the first transceiver device, but also the sending clock signal of the transceiver circuit is synchronized with the clock signal of the first transceiver circuit.
  • the transceiver circuit for clock synchronization may further include: a second phase interpolator 25, the first phase interpolator 25 of the second phase interpolator 25
  • the input terminal 251 is connected to the output terminal 222 of the first phase-locked loop 22, the second input terminal 252 of the second phase interpolator 25 is connected to the second output terminal 234 of the clock adjustment module 23, and the output terminal 303 of the phase detection module 30 is also connected to the clock The second output terminal 234 of the adjustment module 23 is coupled.
  • the second phase interpolator 25 is used to adjust the first clock signal according to the second phase difference output by the second output terminal 234 of the clock adjustment module 23 to obtain a third clock signal, which is the same as the first clock signal.
  • the clock signal of the transceiver device is synchronized; and the sending clock signal of the transceiver circuit is updated to a third clock signal, and the third clock signal is used to send data to the first transceiver device.
  • the first clock signal is adjusted according to the second phase difference to obtain the third clock signal.
  • the first clock signal is adjusted according to the second phase difference to obtain the third clock signal.
  • the transceiving device corresponding to the transceiving circuit provided in the embodiment of the present application includes a transmitting unit and a receiving unit. It should be understood that the clock adjustment module 23 in the above-mentioned transceiver circuit is set on the receiving unit, and the above-mentioned second phase interpolator 25 is set on the sending unit.
  • the second phase interpolator 25 After the second phase interpolator 25 acquires the above-mentioned first clock signal and the second phase difference, it will synchronize the first clock signal, and store the second phase difference in the corresponding In the cache table, as long as the transceiver circuit sends data to the first transceiver device, the second phase interpolator 25 adjusts the first clock signal according to the second phase difference to obtain a third clock signal, which is used for Send data to the first transceiver device.
  • the phase detection module 30 in the above-mentioned clock adjustment module 23 filters the phase difference , and then the first phase interpolator 31 adjusts the first clock signal according to the filtered second phase difference (that is: a more accurate phase difference); meanwhile, the phase difference stored in the buffer table corresponding to the second phase interpolator 25 is also is the filtered second phase difference.
  • the transceiver circuit for clock synchronization may further include: a second phase interpolator 25 and a second phase-locked loop 26,
  • the input end 261 of the second phase-locked loop 26 is connected to the output end 212 of the low-pass filter 21, and the output end 262 of the second phase-locked loop 26 is connected to the first input end 251 of the second phase interpolator 25, and the second phase interpolator
  • the second input end 252 of the clock adjustment module 23 is connected to the second output end 234 of the clock adjustment module 23
  • the output end 303 of the phase detection module 30 is also coupled to the second output end 234 of the clock adjustment module 23 .
  • the second phase-locked loop 26 is used for outputting the fourth clock signal according to the frequency difference between the current receiving clock signal of the sending circuit and the receiving clock signal of the last moment of the sending and receiving circuit; the second phase interpolator 25 is used for According to the phase difference output by the second output terminal 234 of the clock adjustment module 23, the fourth clock signal is adjusted to obtain the fifth clock signal, which is synchronized with the clock signal of the first transceiver device; and the transmission of the transceiver circuit The clock signal is updated to a fifth clock signal, and the fifth clock signal is used to send data to the first transceiver device.
  • the above-mentioned fourth clock signal and the first clock signal both output clock signals according to the frequency difference between the current receiving clock signal of the transmitting circuit and the receiving clock signal of the transmitting and receiving circuit at a moment, so the above-mentioned fourth clock signal and The first clock signal is the exact same clock signal.
  • an embodiment of the present application provides a transceiver device, which includes a transceiver circuit as shown in any one of FIGS. 9 to 13 , and clock synchronization between transceiver devices with this structural feature can be realized based on the transceiver circuit.
  • the clock adjustment module in the second transceiver device according to the clock signal corresponding to the first data and the current reception clock signal of the second transceiver device , to determine the phase difference 1 of these two clock signals; the clock adjustment module adjusts the phase and frequency of the clock signal output at a moment on the first phase-locked loop according to the phase difference 1, and obtains the clock signal 1, wherein the clock signal 1 and The clock signal of the first transceiver device is synchronized; at this time, the clock adjustment module updates the current receiving clock signal of the second transceiver device to clock signal 1; in addition, the clock adjustment module sends the phase difference 1 to the sending unit of the second transceiver device and low pass filter.
  • the low-pass filter determines the frequency difference 1 between the clock signal corresponding to the first data and the current receiving clock signal (receiving clock signal before updating) of the second transceiver device according to the phase difference 1, and sends the frequency difference 1 to the first PLL.
  • the first phase-locked loop adjusts the frequency of the clock signal output at a moment on the first phase-locked loop according to the frequency difference 1 to obtain a clock signal 2, wherein the clock signal 2 is synchronized with the frequency of the clock signal 1, and the first phase-locked loop Send the clock signal 2 to the sending unit and the receiving unit of the second transceiver device, so that when the first transceiver device sends the second data to the second transceiver device, the clock adjustment module adjusts the clock signal 2 according to the phase difference 2, and then A clock signal corresponding to the second data is recovered.
  • the first transceiver device sends the second data to the second transceiver device, due to the influence of external factors, the phase of the clock signal for sending the data may be shifted; therefore, the first transceiver device sends the second data to the second transceiver device.
  • the clock adjustment module in the second transceiver device synchronizes The current receiving clock signal (ie: clock signal 1) determines the phase difference 2 of these two clock signals; the clock adjustment module adjusts the phase and frequency of the clock signal 2 output at a moment on the first phase-locked loop according to the phase difference 2 , to obtain the clock signal 3, what needs to be explained here is: the frequency of the clock signal 3 and the first transceiver device is synchronous, therefore, the frequency adjustment of the clock signal 3 by the clock adjustment module according to the phase difference 2 is negligibly small; then , the clock adjustment module updates the current receiving clock signal (that is: clock signal 1) of the second transceiver device to clock signal 3, and in addition, the clock adjustment module sends the phase difference 2 to the sending unit and low-pass filter of the second transceiver device According to the phase difference 2, the low-pass filter determines the frequency difference 2 between
  • the first phase-locked loop adjusts the frequency of the clock signal 2 output at a moment on the first phase-locked loop according to the frequency difference 2 to obtain a clock signal 4, wherein the clock signal 4 is synchronized with the frequency of the clock signal 3, and the first phase-locked loop
  • the ring transmits this clock signal 4 to the transmitting unit and the receiving unit of the second transceiving device.
  • the sending unit of the second transceiver device When the sending unit of the second transceiver device receives the clock signal 2 and the phase difference 1, the sending unit synchronizes the clock signal 2 and stores the phase difference in the cache table corresponding to the sending unit; when the sending unit of the second transceiver device When receiving the clock signal 4 and the phase difference 2, the sending unit synchronizes the clock signal 4, and updates the phase difference 1 corresponding to the first transceiver device in the cache table to the phase difference 2.
  • the second transceiver device sends data to the first transceiver device
  • the second phase interpolator in the sending unit of the second transceiver device adjusts the clock signal 4 according to the phase difference 2 to obtain a clock signal 5, and uses the clock signal 5 to send data to the first transceiver device.
  • a transceiver device transmits data, wherein the clock signal 5 is synchronized with the clock signal of the first transceiver device.
  • Figure 15 is a schematic flow diagram of the transceiving circuit provided in the embodiment of the present application when synchronizing the clock signal of the opposite end.
  • the second transceiving device periodically sends random codes to the first transceiving device.
  • the random code may be the first data or the second data in the above embodiment, or other non-service data, so that the receiving clock signal of the first transceiver device is synchronized with the sending clock signal of the second transceiver device.
  • the first transceiver device adjusts the phase of the current receiving clock signal of the first transceiver device according to the phase difference between the received clock signal and the clock signal corresponding to the service data, and implements the first transceiver device.
  • the received clock signal is synchronized with the clock signal corresponding to the service data, so that the first transceiver device obtains the service data sent by the second transceiver device according to the synchronized receive clock signal.
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage medium includes: flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk, and other various media capable of storing program codes.

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

Circuit d'émission-réception, comprenant : un module de réglage d'horloge (A), un détecteur de phase/fréquence (B) et une première boucle à verrouillage de phase (C), une première extrémité d'entrée du module de réglage d'horloge (A) est couplée à une extrémité d'entrée du circuit d'émission-réception, une première extrémité de sortie du module de réglage d'horloge (A) est connectée à une première extrémité d'entrée du détecteur de phase/fréquence (B), une extrémité de sortie du détecteur de phase/fréquence (B) est connectée à une extrémité d'entrée de la première boucle à verrouillage de phase (C), et une extrémité de sortie de la première boucle à verrouillage de phase (C) est connectée à une seconde extrémité d'entrée du module de réglage d'horloge (A) et à une seconde extrémité d'entrée du détecteur de phase/fréquence (B); le détecteur de phase/fréquence (B) est utilisé pour déterminer la différence de fréquence entre le signal d'horloge reçu actuel du circuit d'émission-réception et un signal d'horloge émis par la première boucle à verrouillage de phase (C) au moment précédent; la première boucle à verrouillage de phase (C) est utilisée pour délivrer en sortie un premier signal d'horloge en fonction de la différence de fréquence; et le module de réglage d'horloge (A) est utilisé pour déterminer la différence de phase entre un signal d'horloge d'un premier dispositif d'émission-réception et le signal d'horloge actuel du circuit d'émission-réception, ajuster le premier signal d'horloge en fonction de la différence de phase, de manière à obtenir un second signal d'horloge, qui est synchronisé avec le signal d'horloge du premier dispositif d'émission-réception, et mettre à jour le signal d'horloge reçu du circuit d'émission-réception pour passer au second signal d'horloge, qui est utilisé pour recevoir des données provenant du premier dispositif d'émission-réception.
PCT/CN2021/109946 2021-07-31 2021-07-31 Circuit d'émission-réception et dispositif d'émission-réception pour synchronisation d'horloge WO2023010234A1 (fr)

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PCT/CN2021/109946 WO2023010234A1 (fr) 2021-07-31 2021-07-31 Circuit d'émission-réception et dispositif d'émission-réception pour synchronisation d'horloge
CN202180099154.9A CN117480743A (zh) 2021-07-31 2021-07-31 一种用于时钟同步的收发电路及收发设备

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20030081147A1 (en) * 2001-11-01 2003-05-01 Sony Corporation And Sony Electronics, Inc. Apparatus and method for implementing a unified clock recovery system
CN101489290A (zh) * 2008-01-15 2009-07-22 瑞昱半导体股份有限公司 接收装置、信号处理系统以及信号接收方法
CN103957003A (zh) * 2014-04-23 2014-07-30 华为技术有限公司 一种时间数字转换器、频率跟踪装置及方法
CN112118063A (zh) * 2019-06-21 2020-12-22 华为技术有限公司 一种时钟同步装置、光发射器、光接收器及方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030081147A1 (en) * 2001-11-01 2003-05-01 Sony Corporation And Sony Electronics, Inc. Apparatus and method for implementing a unified clock recovery system
CN101489290A (zh) * 2008-01-15 2009-07-22 瑞昱半导体股份有限公司 接收装置、信号处理系统以及信号接收方法
CN103957003A (zh) * 2014-04-23 2014-07-30 华为技术有限公司 一种时间数字转换器、频率跟踪装置及方法
CN112118063A (zh) * 2019-06-21 2020-12-22 华为技术有限公司 一种时钟同步装置、光发射器、光接收器及方法

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