WO2023009297A1

WO2023009297A1 - Method and apparatus for operating a tactical data link terminal

Info

Publication number: WO2023009297A1
Application number: PCT/US2022/036581
Authority: WO
Inventors: Yoshen HOU
Original assignee: Viasat, Inc.
Priority date: 2021-07-28
Filing date: 2022-07-08
Publication date: 2023-02-02

Abstract

According to techniques disclosed herein, a Tactical Data Link (TDL) terminal uses a first clock that runs during a sleep mode for initial realignment of a second clock that is used for synchronous operation with respect to a TDL network during active-mode operation of the TDL terminal. For example, implementation of the first clock via low-power circuitry and characterization of the relative error or drift of the first clock with respect to the second clock allows the TDL terminal to adjust the phase of the second clock upon transitioning back to active-mode operation, for accurate realignment of the second clock with the TDL network timing.

Description

METHOD AND APPARATUS FOR OPERATING A TACTICAL DATA LINK

TERMINAL

TECHNICAL FIELD

[0001] Subject matter presented in this document involves tactical data link terminals, such as a Link 16 terminal, and corresponding methods of operation.

BACKGROUND

[0002] Tactical Data Links or “TDLs” support military operations by providing secure and jam-resistant means of communication between various items of equipment. Link 16 is one example of a TDL and is a Time Division Multiple Access (TDMA) digital data link that operates in radiofrequency (RF) spectrum from 960 MHz to 1,215 MHz. Link 16 provides secure, jam-resistant, and relatively high-speed transfer of tactical data among joined entities. Here, “entity” refers to a weapons platform or other item of equipment communicating in a Link 16 network, or, more generally, to the military units operating such equipment. See the standards document NATO STANAG 5516 for Link 16 specifications.

[0003] Originally developed in the 1970s to support air interdiction missions, Link 16 terminals find increasingly diverse deployment, in everything from fighter and reconnaissance aircraft, ground vehicles, surface vessels, operational centers, and bases. For example, deployment of gateways and satellite-based interconnections extend TDL networks in various Beyond-Line-of-Sight (BLoS) applications. However, the increasingly diverse deployment scenarios, such as the use of handheld or otherwise portable TDL terminals by dismounted ground warfighters, raise numerous design and operational challenges.

[0004] As one example, operation by a TDL terminal in a Link 16 network assumes continuous reception monitoring by the TDL terminal. Further, TDL terminals participating in a Link 16 network must maintain tight synchronization, which requires recurring radio activity by the TDL terminal. While continuous operation by a TDL terminal integrated into a shipboard or vehicular power system may not represent a significant power draw, such operation poses serious practical issues in the context of battery-powered and other power-constrained TDL terminals·

SUMMARY

[0005] According to techniques disclosed herein, a Tactical Data Link (TDL) terminal uses a first clock that runs during sleep or inactive modes for initial realignment of a second clock that is used for synchronous operation with respect to a TDL network during active-mode operation of the TDL terminal. For example, implementation of the first clock via low-power circuitry and characterization of the relative error or drift of the first clock with respect to the second clock allows the TDL terminal to adjust the phase of the second clock upon transitioning back to active-mode operation, for accurate realignment of the second clock with the TDL network timing.

[0006] An example embodiment comprises a method of operation by a TDL terminal, where the method includes a communications processor of the TDL terminal determining timing error of a first time-slot clock relative to a second time-slot clock. The first time-slot clock is maintained by a system controller of the TDL terminal that operates during both active and sleep modes of the TDL terminal, and the second time-slot clock is maintained by the communications processor. The communications processor operates during the active mode and maintains fine synchronization of the second time-slot clock with time-slot boundaries of a TDL network, based on receiving messages transmitted by one or more other TDL terminals in the TDL network. As part of the method, the communications processor transfers control information to the system controller for transitioning the TDL terminal into the sleep mode, with the control information indicating a current time slot count for the TDL network and indicating a future time slot as a wake-up time. Correspondingly, the method further includes the system controller incrementing the time slot count according to the first time-slot clock while the TDL terminal is in the sleep mode, and transitioning the TDL terminal back to the active mode in response to reaching the wake-up time, and the communications processor initially reestablishing fine synchronization of the second time-slot clock, based on realigning the second time-slot clock with the first time-slot clock according to an extrapolated clock phase that is based on the timing error of the first time- slot clock.

[0007] Another embodiment comprises a communications processor configured to determine a timing error of a first time-slot clock relative to a second time-slot clock. The first time-slot clock is maintained by a system controller of the TDL terminal that operates during both active and sleep modes of the TDL terminal. The second time-slot clock is maintained by the communications processor, which operates only during the active mode and maintains fine synchronization of the second time-slot clock with time-slot boundaries of a TDL network, based on receiving messages transmitted by one or more other TDL terminals in the TDL network. The communications processor is configured to transfer control information to the system controller for transitioning the TDL terminal into the sleep mode, the control information indicating a current time slot count for the TDL network and indicating a future time slot as a wake-up time. The system controller is configured to increment the time slot count according to the first time- slot clock while the TDL terminal is in the sleep mode and transition the TDL terminal back to the active mode in response to reaching the wake-up time, and, with respect to the TDL terminal transitioning back to the active mode. Correspondingly, the communications processor is further configured to reestablish fine synchronization of the second time-slot clock initially, based on realigning the second time-slot clock with the first time-slot clock according to an extrapolated clock phase that is based on the timing error of the first time-slot clock.

[0008] Of course, the present invention is not limited to the above features and advantages. Indeed, those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a Tactical Data Link (TDL) terminal according to an example embodiment, shown in context with other TDL terminals acting together as participants in a TDL network.

[0010] Figure 2 is a block diagram of a typical frame and time-slot structure used in a TDL network.

[0011] Figure 3 is a block diagram of example details of a TDL terminal·

[0012] Figure 4 is a logic flow diagram of a method of operation by a TDL terminal, according to an example embodiment.

[0013] Figures 5 and 6 are block diagrams of further example details of a TDL terminal.

[0014] Figures 7 and 8 are timing diagram depicting sequential states and operations of a

TDL terminal transitioning from active mode to sleep mode and back to active mode, according to example embodiments.

[0015] Figures 9 and 10 are diagrams illustrating example bootup times for a communication processor with respect to transitioning from a sleep state to an active state.

DETAILED DESCRIPTION

[0016] Figure 1 illustrates a Tactical Data Link (TDL) terminal 10 that uses a first clock that runs during sleep or inactive modes for initial realignment of a second clock that is used for synchronous operation with respect to a TDL network 12 during active-mode operation of the TDL terminal 10. For example, implementation of the first clock via low-power circuitry and characterization of the relative error or drift of the first clock with respect to the second clock during active-mode operation of the TDL terminal 10 allows the TDL terminal 10 to adjust the phase of the second clock upon transitioning back to active-mode operation, for accurate realignment of the second clock with the TDL network timing.

[0017] Put simply, the TDL terminal 10 makes advantageous use of a low-power sleep clock to track elapsed time while sleeping through periods when it does not need to monitor for radio messages from other TDL terminals 14 in the TDL network 12, and then, upon transitioning back to active operation, uses the characterized drift or error of the sleep clock to realign its communications clock with time-slot boundaries of the TDL network 12. As such, the TDL terminal 10 recovers fine synchronization with the TDL network 12 upon reentering active mode, without requiring the exchange of Round Trip Timing (RTT) messages with another TDL terminal 14 in the TDL network 12 that is acting as the Network Time Reference (NTR). Of course, the TDL terminal 10 may subsequently exchange RTT messages with the NTR, to maintain or further refine its synchronization state.

[0018] In an example context, the TDL network 12 is a Link 16 network, which uses time slots of 7.8125 ms as its basic unit of time. Each twenty-four hour day is divided into 112.5 epochs, with each epoch being 12.8 minutes in duration. Each epoch is divided into 98,304 time slots, yielding the 7.8125 ms time-slot duration. The time slots are divided into three sets: Set A, Set B, and Set C. Each set of time slots in one epoch contains 32,768 time slots, set A contains time slots A0 - A32,767, set B contains time slots B0 - B32,767, and so on. Each epoch is organized as a set of 64 frames 16, yielding the frame duration of 12 seconds in duration. Each frame 16 thus contains 1,536 time slots — i.e., 512 time slots belonging to each of sets A, B, and C. The circular arrangement of frames 16 depicted in Figure 1 is suggestive of one epoch, and Figure 2 illustrates the time-slot composition of one frame 16 within the succession of frames 16 included in any given epoch.

[0019] A conventional TDL terminal achieves “coarse” synchronization with the NTR in a Link 16 network based on successfully receiving a net entry message and achieves “fine” synchronization based on successfully exchanging RTT messages with the NTR. “Fine” synchronization refers to alignment between the time slot boundaries at the terminal and at the NTR. More broadly, “fine synchronization” as used herein refers to a state of synchronization that satisfies the applicable limit(s) on synchronization error. Because a TDL terminal must be in a state of fine synchronization to transmit in a Link 16 network, each terminal participating in the network maintains a measure of how accurately it knows the system time, with that measure referred to as the "Time Quality" or "TQ" of the terminal, and with "TQ15" being the highest level of time quality.

[0020] Figure 3 illustrates details for the TDL terminal 10 according to an example embodiment. The TDL terminal 10 includes a system controller 20 with an associated first time- slot clock 22 that is based on a first crystal oscillator (XO) 24, a battery 26, power supply circuitry 28, and a communications processor 30 that is associated with a second time-slot clock 32 based on a second XO 34. Further, the TDL terminal 10 includes radio transceiver circuitry 36 — i.e., radio transmitter circuitry and radio receiver circuitry for transmitting and receiving messages in a TDL network. The radio transceiver circuitry 36 is associated with one or more transmit/receive antennas 38.

[0021] The communications processor 30, which may comprise fixed circuitry or programmatically-configured circuitry or a mix of both, and which may comprise more than one integrated circuit, performs radio signal waveform processing and other processing used to carry on radio communications during the active mode. All such processing may be referred to as “communications processing,” with the active mode of the TDL terminal 10 being understood as normal, ongoing communications processing by the communications processor 30.

[0022] However, during the inactive mode — hereafter referred to as the sleep mode — communications processing is suspended. That is, the communications processor 30 is idle or powered off during the sleep mode. Other power savings may be implemented; for example, the radio transceiver circuitry 36 may also be powered off during the sleep mode. As an advantageous aspect of the TDL terminal 10, the system controller 20, which is characterized by low-power operation, tracks time during operation of the TDL terminal 10 during the sleep mode and initiates transition of the TDL terminal 10 back to the active mode based on that time tracking. “Low-power” in this context means low in comparison to the level of power consumption associated with active-mode operation.

[0023] For example, the system controller 20 comprises fixed circuitry or programmatically- configured circuitry or a mix of both, and it consumes less power than the circuitry comprising the communications processor 30. For example, the system controller 20 comprises a low-power microcontroller that operates in a low-frequency mode and requires relatively few microamps of current to operate.

[0024] The first time-slot clock 22, which is maintained by the system controller 20, runs during the active mode and during the sleep mode, and the second time-slot clock 32 runs during the active mode. The communications processor 30 is configured to determine a timing error of the first time-slot clock 22 relative to the second time-slot clock 32, which is maintained by the communications processor 30 and is active only during the active mode. For example, while in the active mode, the communications processor 30 relies on RTT message exchanges with the NTR in the TDL network 12 to adjust the phase or other attributes of the second time-slot clock 32 and correspondingly track or otherwise assess the drift or other error characteristics of the first time-slot clock 22 with respect to the second time-slot clock 32.

[0025] According to one or more embodiments, for any given transitioning of the TDL terminal 10 from the active mode to the sleep mode, the communications processor 30 is configured to transfer control information to the system controller 20 for transitioning the TDL terminal 10 into the sleep mode. The control information indicates a current time slot count for the TDL network 12 and indicates a future time slot as a wake-up time. In this regard, the communications processor 30 necessarily keeps track of the time slot count — the running time slot index — during the active mode as part of its communications processing.

[0026] Correspondingly, the system controller 20 is configured to increment the time slot count according to the first time-slot clock 22 while the TDL terminal 10 is in the sleep mode and transition the TDL terminal 10 back to the active mode in response to reaching the wake-up time. With respect to the TDL terminal 10 transitioning back to the active mode, the communications processor 30 is further configured to reestablish fine synchronization of the second time-slot clock 32 initially, based on realigning the second time-slot clock 32 with the first time-slot clock 22 according to an extrapolated clock phase that is based on the timing error of the first time-slot clock 22.

[0027] For example, during active mode operation, the communications processor 30 exchanges RTT messages with the NTR in the TDL network 12 to refine or maintain the fine synchronization state of the second time-slot clock 32. Further, the communications processor 30 includes circuitry to detect the phase offset of the first time-slot clock 22 relative to the second time-slot clock 32. The communications processor 30 tracks the phase offset over time and determines a characteristic phase drift of the first time-slot clock 22 relative to the second time- slot clock 32. Thus, with the second time-slot clock 32 being in fine synchronization with the NTR of the TLD network 12, the communications processor 30 can cooperate with the system controller 20 to bring the first time-slot clock 22 into alignment with the second time-slot clock 32 or otherwise note the phase offset between the two clocks 22 and 32. Then, based on knowing that the two clocks 22 and 32 were in phase alignment or offset by a known phase amount at the time of entering the sleep mode, and based on further knowing the duration of the sleep mode and the characteristic phase drift of the first time-slot clock 22, the communications processor 30 can calculate — i.e., predict — what the phase offset ought to be between the two clocks upon the resumption of active-mode operation.

[0028] Adjusting the phase of the second time-slot clock 32 according to the predicted phase offset can be understood as reestablishing the fine synchronization of the second time-slot clock 32 for communications processing, without need for exchanging RTT messages with the NTR of the TDL network 12. Of course, the reestablished fine synchronization may be considered as an “initial” synchronization and the TDL terminal 10 may subsequently send RTT messages to maintain fine synchronization. However, as a distinct advantage, sleep mode does not result in a loss of fine synchronization.

[0029] For determining the phase offset and drift of the first time-slot clock 22, the communications processor 30 in one or more embodiments is configured to track the phase offset and drift via a Kalman filter implemented via the communications processor 30. With respect to the communications processor 30 initially reestablishing fine synchronization of the second time-slot clock 32 upon transitioning back to the active mode, the communications processor 30 in one or more embodiments is configured to operate in an idle state during which the radio transceiver circuitry 36 of the TDL terminal 10 is powered, but no TDL network transmissions are performed. Further, with the communications processor 30 maintaining fine synchronization of the second time-slot 32 during any particular window of operation in the active mode, the communications processor 30 in one or more embodiments is configured to adjust the phase of the second time-slot clock 32 according to Time-of- Arrival (TO A) measurements, based on the TDL terminal 10 receiving messages transmitted by the one or more other TDL terminals 14 in the TDL network 12 during the particular window of operation in the active mode.

[0030] In one or more embodiments, the communications processor 30 is configured to decide whether to initiate transitioning of the TDL terminal 10 into the sleep mode in dependence on whether a calculated duration of the sleep mode exceeds a first threshold. For example, the communications processor 30 remains in the active mode in response to determining that the time remaining before the TDL terminal 10 is next required to be active is less than a first threshold. Further, in one or more embodiments, the communications processor 30 or the system controller 20 is configured to decide whether the communications processor 30 is to be held in reset or powered off during an interval of sleep mode, in dependence on whether the calculated duration of the sleep mode exceeds a second threshold. [0031] Such operation can be understood as controlling the aggressiveness of power reduction during sleep mode in dependence on the duration of the sleep interval. For example, the system controller 20 merely holds the communications processor 30 in reset or other idle configuration during sleep intervals that are shorter than a defined duration but removes power from the communications processor 30 during sleep intervals that are longer than the defined duration.

[0032] For example, in one or more embodiments, the system controller 20 is configured to control voltage- supply circuitry of the TDL terminal 10 to remove power from radio transceiver circuitry 36 of the TDL terminal 10 during the sleep mode. For reference, see the power supply circuitry 28 depicted in Figure 1 , which in one or more embodiments is responsive to control signaling from the system controller 20, to remove or shut down power to the radio transceiver circuitry 36. In one or more embodiments, the system controller 20 is configured to control the voltage- supply circuitry, to remove power from the communications processor 30 during the sleep mode; however, as noted, the system controller 20 may or may not remove power from the communications processor 30, in dependence on the duration of sleep-mode operation.

[0033] One advantage of such decision making flows from the differences in initialization time of the communications processor 30 for “warm” boots versus “cold” boots. That is, leaving the communications processor 30 powered but idle during a sleep interval allows faster resumption of normal operations by the communications processor 30, as compared to powering it down and then powering it back up. The faster recovery means sleep operation can be extended closer to the time slot by which the communications processor 30 must have resumed normal operations.

[0034] In at least one embodiment, with respect to each frame 16 in a succession of frames 16 defined by the TDL network 12, with each frame 16 comprising a defined number of time slots, the communications processor 30 is configured to configure the system controller 20 such that the TDL terminal 10 enters the active mode to monitor a same time slot per frame as a “contention” time slot and, absent detection of activity in any particular contention time slot, the TDL terminal 10 transitions back to the sleep mode until a defined wake-up time in advance of the next contention time slot. In other words, in an example scenario where the TDL terminal 10 is obligated to monitor a contention time slot in each frame 16, the TDL terminal 10 may simply wake up in advance of the contention time slot, reestablish fine synchronization with the time slot boundaries of the TDL network 12 based on its sleep-mode time tracking, and then go back to sleep if no network activity is detected. [0035] With respect to preparing for transition into the sleep mode, the communications processor 30 in one or more embodiments is configured to determine a future time slot of the TDL network 12 as the wake-up time by identifying a next active time slot for the TDL terminal 10 and selecting the future time slot according to an initialization offset that provides a window in advance of the next active time slot. This window accounts for the time needed for transitioning the TDL terminal 10 back to the active mode and completing the initial reestablishment of fine synchronization of the second time-slot clock 32. The future time slot may be determined as the wake-up time based on a time slot assignment for the TDL terminal 10 in the TDL network 12.

[0036] Figure 4 depicts an example method 400 of operation by a TDL terminal 10, where the method 400 includes a communications processor 30 of the TDL terminal 10 determining (Block 402) timing error of a first time-slot clock 22 relative to a second time-slot clock 32, e.g., determining a characteristic phase drift of the first time-slot clock 22 relative to the second time- slot clock 32. Here, the first time-slot clock 22 is maintained by a system controller 20 of the TDL terminal 10 that operates during both active and sleep modes of the TDL terminal, and the second time-slot clock 32 is maintained by the communications processor 30, which operates only during the active mode and, while in the active mode, maintains fine synchronization of the second time-slot clock 32 with time-slot boundaries of a TDL network 12, based on receiving messages transmitted by one or more other TDL terminals 14 in the TDL network 10.

[0037] The method 400 further includes the communications processor 30 transferring (Block 404) control information to the system controller 20 for transitioning the TDL terminal 10 into the sleep mode, the control information indicating a current time slot count for the TDL network 12 and indicating a future time slot as a wake-up time. Such operation occurs in advance of any given transition from active mode into sleep mode. Correspondingly, the method 400 includes the system controller 20 incrementing (Block 406) the time slot count according to the first time-slot clock 22 while the TDL terminal 10 is in the sleep mode and transitioning the TDL terminal 10 back to the active mode in response to reaching the wake-up time. Still further, the method 400 includes the communications processor 30 initially reestablishing (Block 408) fine synchronization of the second time-slot clock 32, based on realigning the second time-slot clock 32 with the first time-slot clock 22 according to an extrapolated clock phase that is based on the timing error of the first time-slot clock 22. [0038] The method 400 in one or more embodiments includes the communications processor 30 deciding whether to initiate transitioning of the TDL terminal 10 into the sleep mode in dependence on whether a calculated duration of the sleep mode exceeds a first threshold.

[0039] The method 400 may include the communications processor 30 deciding whether the communications processor 30 is to be held in reset or powered off during the sleep mode, in dependence on whether the calculated duration of the sleep mode exceeds a second threshold. [0040] In at least one embodiment, the method 400 comprises the TDL terminal 10 entering the active mode to monitor a same time slot per frame as a contention time slot and, absent detection of activity in any particular contention time slot, the TDL terminal 10 transitioning back to the sleep mode until a defined wake-up time in advance of the next contention time slot. [0041] Determining a future time slot of the TDL network 12 as a wake-up time comprises, for example, the communications processor 30 identifying a next active time slot for the TDL terminal 10 and selecting the future time slot according to an initialization offset that provides a window in advance of the next active time slot, for transitioning the TDL terminal 10 back to the active mode and completing the initial reestablishment of fine synchronization of the second time-slot clock 32.

[0042] Determining the timing error of the first time-slot clock 22 comprises, for example, determining a phase offset and drift of the first time-slot clock 22 relative to the second time-slot clock 32, while the second time-slot clock 32 is maintained by the communications processor 30 in fine synchronization. As a particular example, determining the phase offset and drift of the first time-slot clock 22 comprises tracking the phase offset and drift via a Kalman filter implemented via the communications processor 30.

[0043] With respect to determining a future time slot as the wake-up time for any given sleep period, the method 400 in one or more embodiments includes determining the wake-up time based on a time slot assignment for the TDL terminal 10 in the TDL network 12. The method 400 may also include the system controller 20 toggling a RESET signal, for resetting the communications processor 30 in conjunction with the TDL terminal 10 transitioning back to the active mode from any given period of sleep-mode operation. The method 400 may also include the system controller 20 controlling voltage- supply circuitry, to remove power from radio transceiver circuitry 36 and/or the communications processor 30 during the sleep mode. For example, the power supply circuitry 28 shown in Figure 3 may include one or more power supplies that can be disabled, or supply voltages may be coupled through gating transistors that are switched on or off via discrete output signaling from the system controller 20, which, as noted, may be a low-power microprocessor and may have digital I/O for controlling which portions of the TDL terminal 10 are powered.

[0044] With the above examples and variations in mind and with reference to the further example details depicted in Figure 5, a TDL terminal 10 according to the teachings disclosed herein incorporates a low-power microprocessor chip or other low-power control circuitry as a system controller 20. The system controller 20 is operative to perform deep power shutdown for durations corresponding to unused time slots in a TDL network 12 or, more broadly, corresponding to times during which the TDL terminal 10 does not need to monitor for transmissions or otherwise perform radio operations.

[0045] The system controller 20 in one or more embodiments is powered by a non- interrupted supply (e.g., 1.8 volts) from a battery 26 and directly controls supply voltage switching regulators 40 without itself being powered off. Such regulators 40 provide power to radio transceiver circuitry 36 and/or the communications processor 30. In an example embodiment, the communications processor 30 is instantiated via firmware as a soft-core process in a Field Programmable Gate Array (FPGA) and it performs the waveform processing and real time radio control and communications operations. See, as one example, the illustrated signal processor 42 and waveform and control processor 44, which may be firmware-based processing circuitry realized in the FPGA. A communication link, e.g., a 16-bit or other width parallel data bus, interconnects the system controller 20 with the communications processor 30 in one or more embodiments for inter-processor communication.

[0046] The system controller 20 in one or more embodiments is clocked by a first time-slot clock 22, based on a crystal oscillator 24 operating at 32.768kHz, for example. This first time- slot clock 22 can be an independent clock source isolated from a second time-slot clock 32 used by the communications processor 30. To provide a basis for the communications processor 30 reestablishing fine synchronization of the second time-slot clock 32 upon the TDL terminal 10 exiting from sleep and reentering active-mode operation, the system controller 20 in one or more embodiments uses its first time-slot clock 22 to count TDL network time slots while the TDL terminal 10 sleeps — e.g., the first time-slot clock 22 is a 128 Hz clock derived by dividing the 32.768 kHz frequency of the first XO 24 by 256. Using this approach allows the system controller 20 to maintain the time quality (TQ) at the TDL terminal 10 while the TDL terminal 10 sleeps, with minimal degradation and without significant power consumption in comparison to the power draw of the terminal during active-mode operation. [0047] Figure 6 illustrates further example details regarding the functional modules instantiated via underlying processing circuitry comprising the respective system controller 20 and the communications processor 30. A nano- or micro-powered switching supply 50 provides operating power to the system controller 20 during sleep mode and inactive mode, without interruption. A battery supply switching service 52 — a logical circuit — implemented in the system controller 20 generates control signals for sleep-mode power gating for the communications processor 30 and/or the radio transceiver circuitry 36, which is not shown in Figure 6. Further, a timer 54 operates as a sleep slot clock, i.e., the system controller 20 incorporates circuitry to form the first time-slot clock 22 based on the first XO 24.

[0048] The timer 54 outputs the sleep clock signal to the communications processor 30, for error characterization relative to the second time-slot clock 32 maintained by the communications processor 30. The system controller 20 further includes a system time inter service module 56 that outputs a clock freeze and resets signals to the communications processor 30, as part of its sleep control operations. The clock freeze signal suspends clocked switching of logic circuitry comprised in the communications processor 30, resulting in a substantial reduction in power consumption. Finally, an inter-processor communications function 58 handles the exchange of control information and data with the communications processor 30. [0049] The waveform and control processor 44 portion of the communications processor 30 implements a sleep scheduler function 60 that identifies sleep opportunities, calculates potential sleep durations, and makes decisions regarding initiation of the sleep mode. A system time tracking filter 62 can be understood as being part of the earlier-illustrated second time-slot clock 32, which is based on the second XO 34, and which is maintained in fine synchronization with the NTR of the TDL network 12 during the active mode. Correspondingly, the system time signal output from the filter 62 can be understood as the clock signal of the second time-slot clock 32.

[0050] A clock phase offset detector function 64 determines the phase difference between the first time-slot clock 22 and second time-slot clock 32 — i.e., between the respective clock signals output by the first and second time-slot clocks 22 and 32. A tracking filter function 66 tracks the phase difference and determines the characteristic phase drift of the first time-slot clock 22 relative to the second time-slot clock 32. The filter function 66 is a Kalman-based tracking filter, for example.

[0051] Figure 7 depicts an example timing sequence of events. When the communications processor 32 is actively maintaining fine synchronization of the second time-slot clock 32 through either RTT or passive sync processes associated with the TDL network 12, the waveform and control processor 44 keeps the TDL epoch of slot boundaries, which may be, for example, 128 Hz. That is, the clock signal output from the second time-slot clock 32, e.g., a 128 Hz clock signal, is phase-aligned to the TDL time reference epochs.

[0052] Regarding the respective states of the system controller 20 and the communications processor 30, the “SLOT/CLOCK SYNC” state of the system controller 20 may be understood as including operations in which the system controller 20 evaluates the first time-slot clock 22 against an absolute time reference. For example, assume that the first time-slot clock has a nominal clock frequency of 32.768 kHz. The system controller 20 may observe the number of clock edges occurring between Global Positioning System (GPS) epochs — 1 second intervals — and use that observation to track elapsed time during the sleep mode. That is, the observation allows the system controller 20 translate clock cycles of the first time slot clock 22 into an elapsed time- slot count referenced to the TDL network 12.

[0053] As for the “TIME REALIGNMENT INITIATION” state of the system controller 20, in one or more embodiments, the system controller 20 provides the communications processor 30 with information needed by the communications processor 20 to slew its second time-slot clock 32, for initial restoration of fine synchronization coming out of sleep. In at least one example, the communications processor 30 transfers a value indicating the characteristic phase drift to the system controller 20 in conjunction with the communications processor 30 entering the sleep mode, and the system controller 20 returns that value to the communications processor 30 in conjunction with the communications processor 30 returning to the active mode.

[0054] It is estimated to take about three time slots in the context of Link 16 time slots to wake up the communications processor 30 and it can take a few more time slots to re-establish fine synchronization by extrapolating the correct phase of the second time-slot clock 32 from the phase of the first time-slot clock 22 upon exiting from the sleep mode.

[0055] Figure 8 depicts a timing sequence similar to that shown in Figure 7. However,

Figure 8 illustrates power-gating control, which is used in one or more embodiments. That is, the system controller 20 in one or more embodiments controls circuitry within the TDL terminal 10 to remove supply voltage from one or more circuits during sleep mode, such as the communications processor 30 and/or the radio transceiver circuitry 36.

[0056] As noted earlier, the TDL network 12 may use designated “contention access” time slots as “activity indicators,” meaning that the TDL terminal 10 need only monitor contention access slots for activity and, with respect to any given contention access slot, return to the sleep mode upon detecting no activity. In more detail, all transmissions in the TDL network 12 can be preceded with a transmission in the contention access slots for activity indication. The participating terminals can awake to detect their assigned slots in the next multiple seconds, e.g., in a next frame. Collision and bad receptions in the contention slots do not degrade receive quality because participants need only to detect activity of contention slots to determine whether to wake up and receive the next TDL frame.

[0057] More broadly, a TDL terminal 10 using the techniques described herein may advantageously use a low-power sleep mode with respect to essentially any contiguous block of time slots for which the TDL terminal 10 is not obligated to perform radio operations. A consideration for power shutdown during sleep, such as shown in Figure 8, is the length of time for startup. For example, as depicted in Figure 9, the startup time of the communications processor 30 may be about 10 milliseconds (ms) for a warm boot (powered during sleep but with the second time-slot clock 32 held frozen). As depicted in Figure 10, however, the startup time for the communications processor 30 may be in the range of 300 ms for a cold boot (powered down during sleep). In some embodiments, the TDL network 12 may be configured so that assigned slots are collocated to increase power saving and extend the duration of sleep opportunities.

[0058] Notably, modifications and other embodiments of the disclosed invention(s) will come to mind to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention(s) is/are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of this disclosure. Although specific terms may be employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

CLAIMS What is claimed is:

1. A method of operation by a Tactical Data Link (TDL) terminal, the method comprising: a communications processor of the TDL terminal determining timing error of a first time- slot clock relative to a second time-slot clock, the first time-slot clock maintained by a system controller of the TDL terminal that operates during both active and sleep modes of the TDL terminal, and the second time-slot clock maintained by the communications processor, which operates only during the active mode and maintains fine synchronization of the second time-slot clock with time-slot boundaries of a TDL network, based on receiving messages transmitted by one or more other TDL terminals in the TDL network; the communications processor transferring control information to the system controller for transitioning the TDL terminal into the sleep mode, the control information indicating a current time slot count for the TDL network and indicating a future time slot as a wake-up time; the system controller incrementing the time slot count according to the first time-slot clock while the TDL terminal is in the sleep mode, and transitioning the TDL terminal back to the active mode in response to reaching the wake-up time; and the communications processor initially reestablishing fine synchronization of the second time-slot clock, based on realigning the second time-slot clock with the first time- slot clock according to an extrapolated clock phase that is based on the timing error of the first time-slot clock.

2. The method according to claim 1 , further comprising the communications processor deciding whether to initiate transitioning of the TDL terminal into the sleep mode in dependence whether a calculated duration of the sleep mode exceeds a first threshold.

3. The method according to claim 2, further comprising deciding whether the communications processor is to be held in reset or powered off during the sleep mode, in dependence on whether the calculated duration of the sleep mode exceeds a second threshold.

4. The method according to any one of claims 1-3, wherein, with respect to each frame in a succession of frames of the TDL network, with each frame comprising a defined number of time slots, the method comprises the TDL terminal entering the active mode to monitor a same time slot per frame as a contention time slot and, absent detection of activity in any particular contention time slot, the TDL terminal transitioning back to the sleep mode until a defined wake- up time in advance of the next contention time slot.

5. The method according to any one of claims 1-4, wherein determining the future time slot of the TDL network as the wake-up time comprises identifying a next active time slot for the TDL terminal and selecting the future time slot according to an initialization offset that provides a window in advance of the next active time slot, for transitioning the TDL terminal back to the active mode and completing the initial reestablishment of fine synchronization of the second time-slot clock.

6. The method according to any one of claims 1-5, wherein determining the timing error of the first time-slot clock comprises determining a phase offset and drift of the first time-slot clock relative to the second time-slot clock, while the second time-slot clock is maintained by the communications processor in fine synchronization.

7. The method according to claim 6, wherein determining the phase offset and drift of the first time-slot clock comprises tracking the phase offset and drift via a Kalman filter implemented via the communications processor.

8. The method according to any one of claims 1-7, wherein, with respect to the communications processor initially reestablishing fine synchronization of the second time-slot clock, the communications processor operates in an idle state during which the radio transceiver circuitry of the TDL terminal is powered, but no TDL network transmissions are performed.

9. The method of according to any one of claims 1-8, wherein, with respect to the communications processor maintaining fine synchronization of the second time-slot during any particular window of operation in the active mode, the method comprises the communications processor adjusting the phase of the second time-slot clock according to Time-of- Arrival (TOA) or Round-Trip-Time (RTT) calculations, based on receiving messages transmitted by the one or more other TDL terminals in the TDL network during the particular window of operation in the active mode.

10. The method according to any one of claims 1-9, wherein determining the future time slot as the wake-up time is based on a time slot assignment for the TDL terminal in the TDL network.

11. The method according to any one of claims 1-10, further comprising toggling a RESET signal by the system controller, for resetting the communications processor in conjunction with the TDL terminal transitioning back to the active mode.

12. The method according to any one of claims 1-11, further comprising the system controller controlling voltage- supply circuitry, to remove power from radio transceiver circuitry of the TDL terminal during the sleep mode.

13. The method according to any one of claims 1-12, further comprising the system controller controlling voltage- supply circuitry, to remove power from the communications processor during the sleep mode.

14. The method according to any one of claims 1-13, further comprising the system controller observing the number of clock edges of the first time-slot clock occurring between Global Positioning System (GPS) epochs and using that observation during the sleep mode to translate clock cycles of the first time slot clock into an elapsed time-slot count referenced to the TDL network.

15. A Tactical Data Link (TDL) terminal comprising: a communications processor configured to: determine a timing error of a first time-slot clock relative to a second time-slot clock, the first time-slot clock maintained by a system controller of the TDL terminal that operates during both active and sleep modes of the TDL terminal, and the second time-slot clock maintained by the communications processor, which operates only during the active mode and maintains fine synchronization of the second time-slot clock with time-slot boundaries of a TDL network, based on receiving messages transmitted by one or more other TDL terminals in the TDL network; and transfer control information to the system controller for transitioning the TDL terminal into the sleep mode, the control information indicating a current time slot count for the TDL network and indicating a future time slot as a wake-up time; wherein the system controller is configured to increment the time slot count according to the first time-slot clock while the TDL terminal is in the sleep mode, and transition the TDL terminal back to the active mode in response to reaching the wake-up time, and, with respect to the TDL terminal transitioning back to the active mode, the communications processor is further configured to reestablish fine synchronization of the second time-slot clock initially, based on realigning the second time-slot clock with the first time-slot clock according to an extrapolated clock phase that is based on the timing error of the first time-slot clock.

16. The TDL terminal according to claim 15, wherein the communications processor is configured to decide whether to initiate transitioning of the TDL terminal into the sleep mode in dependence whether a calculated duration of the sleep mode exceeds a first threshold.

17. The TDL terminal according to claim 16, wherein the communications processor or the system controller is configured to decide whether the communications processor is to be held in reset or powered off during the sleep mode, in dependence on whether the calculated duration of the sleep mode exceeds a second threshold.

18. The TDL terminal according to any one of claims 15-17, wherein, with respect to each frame in a succession of frames of the TDL network, with each frame comprising a defined number of time slots, the communications processor is configured to configure the system controller such that the TDL terminal enters the active mode to monitor a same time slot per frame as a contention time slot and, absent detection of activity in any particular contention time slot, the TDL terminal transitions back to the sleep mode until a defined wake-up time in advance of the next contention time slot.

19. The TDL terminal according to any one of claims 15-18, wherein the communications processor is configured to determine the future time slot of the TDL network as the wake-up time by identifying a next active time slot for the TDL terminal and selecting the future time slot according to an initialization offset that provides a window in advance of the next active time slot, for transitioning the TDL terminal back to the active mode and completing the initial reestablishment of fine synchronization of the second time-slot clock.

20. The TDL terminal according to any one of claims 15-19, wherein the communications processor is configured to determine the timing error of the first time-slot clock by determining a phase offset and drift of the first time-slot clock relative to the second time-slot clock, while the second time-slot clock is maintained by the communications processor in fine synchronization.

21. The TDL terminal according to claim 20, wherein, to determine the phase offset and drift of the first time-slot clock, the communications processor is configured to track the phase offset and drift via a Kalman filter implemented via the communications processor.

22. The TDL terminal according to any one of claims 15-21, wherein, with respect to the communications processor initially reestablishing fine synchronization of the second time-slot clock, the communications processor is configured to operate in an idle state during which a radio transceiver circuitry of the TDL terminal is powered, but no TDL network transmissions are performed.

23. The TDL terminal according to any one of claims 15-22, wherein, with respect to the communications processor maintaining fine synchronization of the second time-slot during any particular window of operation in the active mode, the communications processor is configured to adjust the phase of the second time-slot clock according to Time-of- Arrival (TOA) or Round- Trip-Time (RTT) calculations, based on the TDL terminal receiving messages transmitted by the one or more other TDL terminals in the TDL network during the particular window of operation in the active mode.

24. The TDL terminal according to any one of claims 15-23, wherein the communications processor is configured to determine the future time slot as the wake-up time based on a time slot assignment for the TDL terminal in the TDL network.

25. The TDL terminal according to any one of claims 15-24, wherein the system controller is configured to toggle a RESET signal, for resetting the communications processor in conjunction with the TDL terminal transitioning back to the active mode.

26. The TDL terminal according to any one of claims 15-25, wherein the system controller is further configured to control voltage- supply circuitry of the TDL terminal, to remove power from radio transceiver circuitry of the TDL terminal during the sleep mode.

27. The TDL terminal according to any one of claims 15-26, wherein the system controller is configured to control the voltage-supply circuitry, to remove power from the communications processor during the sleep mode.

28. The TDL terminal according to any one of claims 15-27, wherein the system controller is configured to observe the number of clock edges of the first time-slot clock occurring between Global Positioning System (GPS) epochs and use that observation during the sleep mode to translate clock cycles of the first time slot clock into an elapsed time-slot count referenced to the TDL network.