WO2023006106A1

WO2023006106A1 - Array substrate, display panel, and method for manufacturing array substrate

Info

Publication number: WO2023006106A1
Application number: PCT/CN2022/109234
Authority: WO
Inventors: 李源规; 唐波玲; 李荣荣
Original assignee: 惠科股份有限公司
Priority date: 2021-07-30
Filing date: 2022-07-29
Publication date: 2023-02-02
Also published as: CN113629116A; CN113629116B

Abstract

An array substrate (200), a display panel (100), and a method for manufacturing the array substrate (200). The array substrate (200) comprises a substrate (210) and a plurality of pixel units, the plurality of pixel units are disposed on the substrate (210), each pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a driving thin film transistor (220) and an active light-emitting array (230); the driving thin film transistors (220) and the active light-emitting arrays (230) are adjacently disposed on the substrate (210), and the driving thin film transistors (220) are connected to the active light-emitting arrays (230). In this way, the manufacturing process is reduced, thereby reducing the manufacturing cost.

Description

Array substrate, display panel and method for manufacturing array substrate

This application claims the priority of the Chinese patent application with the application number CN202110872016.1 and the application name "Array Substrate, Display Panel and Array Substrate Manufacturing Method" submitted to the China Patent Office on July 30, 2021, the entire content of which is passed References are incorporated in this application.

technical field

The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a method for manufacturing the array substrate.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

With the wide application of display panels, users' demand for display panels is getting higher and higher. Therefore, the competition in the display panel manufacturing industry is also becoming more and more fierce. The display panel has developed from a liquid crystal display panel to a QNED (Quantum-dot Nano-rod Electroluminescent Diode, Quantum-dot Nano-rod Electroluminescent Diode) display panel and other types of display panels.

At present, QNED display panels or improved display panels based on QNED display panels are mostly formed by using active light-emitting arrays and driving circuits through different processes, that is, after forming the driving circuits, the active light-emitting arrays are then fabricated. This method will double the manufacturing process, resulting in high manufacturing costs, low production efficiency, and weak product competitiveness.

Contents of the invention

In view of the purpose of the present application is to provide an array substrate, a display panel and a method for manufacturing the array substrate, the driving thin film transistor and the active light-emitting array are formed by sharing the manufacturing process, reducing the manufacturing process and thus reducing the manufacturing cost.

The present application discloses an array substrate, the array substrate includes a substrate and a plurality of pixel units, the plurality of pixel units are arranged on the substrate, each of the pixel units includes a plurality of sub-pixels, the sub-pixels The pixel includes a driving thin film transistor and an active light emitting array; the driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor is connected to the active light emitting array.

The present application discloses a display panel, including an array substrate, the array substrate includes a substrate and a plurality of pixel units, a plurality of the pixel units are arranged on the substrate, each of the pixel units includes a plurality of sub-pixels , the sub-pixel includes a driving thin film transistor and an active light emitting array; the driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor is connected to the active light emitting array; The array substrate is also provided with a color conversion layer, the color conversion layer is disposed on the side of the substrate away from the thin-film encapsulation layer, the color conversion layer includes a light-transmitting area and a light-shielding area, and the light-shielding area corresponds to the The driving thin film transistor is set, and the light-transmitting area is set corresponding to the active light-emitting array.

The present application discloses a method for fabricating an array substrate, which is used to fabricate an array substrate. The array substrate includes a substrate and a plurality of pixel units, and a plurality of pixel units are arranged on the substrate. Each pixel The unit includes a plurality of sub-pixels, and the sub-pixels include a driving thin film transistor and an active light emitting array; the driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor and the active light emitting array Lighting array connection; includes:

providing a substrate, dividing the substrate into at least a driving region and a light emitting region;

forming an insulating layer covering the driving region and the light emitting region on the substrate;

Depositing a first conductive material on the insulating layer, and etching the first conductive material, forming a gate electrode corresponding to the driving region, and forming a first electrode and a second electrode opposite to each other corresponding to the light emitting region;

forming an active light-emitting layer between the first electrode and the second electrode;

A driving thin film transistor is formed at a position corresponding to the gate electrode in the driving region, and an active light-emitting array is formed at a position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain an array substrate.

Compared with the scheme in which the active light-emitting array and the driving circuit are formed through different processes, resulting in doubling the manufacturing process and high manufacturing costs, the array substrate of the present application, by arranging the driving thin film transistor and the active light-emitting array adjacently on the substrate, is relatively Compared with the overlapping arrangement of the driving thin film transistor and the active light-emitting array, the thickness of the array substrate can be reduced, and the thickness of the array substrate can be reduced; at the same time, the connection between the driving thin film transistor and the active light-emitting array is used to connect the driving thin film transistor and the active light-emitting array. The metal layer between the active light-emitting arrays is manufactured by the same process, which makes the continuity of the metal layer between the driving thin film transistor and the active light-emitting array better, and avoids the quality difference caused by different manufacturing processes. During electrical connection, there is a risk of disconnection or short circuit, which improves the stability of the array substrate. In addition, the driving thin film transistor and other film layers in the active light-emitting array can also share the process, which greatly reduces the number of processes, such as exposure, development, deposition and etching, and further reduces the manufacturing cost of the array substrate and improves production. Efficiency and production capacity, thereby improving the competitiveness of products.

Description of drawings

The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and explain the principle of the present application together with the text description. Apparently, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without any creative effort. In the attached picture:

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the present application;

Fig. 2 is the sectional schematic diagram along A-A ' direction of Fig. 1 of the present application;

FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present application;

4 is a schematic diagram of the manufacturing process of the array substrate according to the first embodiment of the present application;

5 is a schematic diagram of the manufacturing process of the array substrate according to the second embodiment of the present application;

6 is a schematic diagram of the manufacturing process of the array substrate according to the third embodiment of the present application;

Fig. 7 is a schematic cross-sectional view of the change of the film layer along the direction A-A' corresponding to Fig. 1 in the manufacturing process of the third embodiment of the present application.

Detailed ways

It should be understood that the terminology and specific structural and functional details disclosed herein are representative only for describing specific embodiments, but the application can be embodied in many alternative forms and should not be construed as merely Be limited by the examples set forth herein.

In the description of the present application, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating relative importance, or implicitly indicating the quantity of indicated technical features. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of these features; "plurality" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, possible presence or addition of one or more other features, integers, steps, operations, units, components and/or combinations thereof.

Also, Center, Horizontal, Top, Bottom, Left, Right, Vertical, Horizontal, Top, Bottom, Inner, Outer The terms indicating the orientation or positional relationship are described based on the orientation or relative positional relationship shown in the drawings, and are only for the convenience of describing the simplified description of the application, rather than indicating that the referred device or element must have a specific orientation. , are constructed and operate in a particular orientation and therefore are not to be construed as limiting the application.

In addition, unless otherwise clearly specified and limited, the terms "mounted", "connected" and "connected" should be interpreted in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , can also be an electrical connection; it can be a direct connection, an indirect connection through an intermediary, or an internal communication between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the present application. FIG. 2 is a schematic cross-sectional view of FIG. The array substrate 200 includes a substrate 210 and a plurality of pixel units, the plurality of pixel units are arranged on the substrate 210, each of the pixel units includes a plurality of sub-pixels, and the sub-pixels include a driving thin film transistor 220 and an active light emitting array 230 , the driving thin film transistor 220 and the active light emitting array 230 are adjacently disposed on the substrate 210 , and the driving thin film transistor 220 is connected to the active light emitting array 230 .

Compared with the scheme in which the active light-emitting array and the driving circuit are formed through different processes, resulting in doubling of the manufacturing process and high manufacturing costs, the present application uses the array substrate 200 by arranging the driving thin film transistor 220 and the active light-emitting array 230 adjacently on the substrate. On the bottom 210, compared with the way in which the driving thin film transistor 220 and the active light emitting array 230 are overlapped up and down, the thickness of the array substrate 200 can be reduced, and the thickness of the array substrate 200 can be realized; at the same time, the driving thin film transistor 220 and the active light emitting array 230 The metal layer used to connect the driving thin film transistor 220 and the active light emitting array 230 is manufactured by the same process, so that the continuity of the metal layer between the driving thin film transistor 220 and the active light emitting array 230 is better, and different manufacturing processes are avoided. Due to the difference in manufacturing quality, when the driving thin film transistor 220 is electrically connected to the active light-emitting array 230 , there is a risk of disconnection or short circuit, which improves the stability of the array substrate 200 . In addition, the driving thin film transistor 220 and other film layers in the active light-emitting array 230 can also share a process, which greatly reduces the number of processes, such as exposure, development, deposition and etching, and further reduces the manufacturing cost of the array substrate 200. , Improve production efficiency and production capacity, thereby improving the competitiveness of products.

Specifically, the active light emitting array 230 includes an insulating layer 223, a first electrode 231, a second electrode 232, a nano light emitting diode 233, a first interlayer dielectric layer 225, a first contact electrode 234, a second interlayer dielectric layer 228 and a second contact electrode 235, the insulating layer 223 is disposed on the substrate 210; the first electrode 231 is disposed on the insulating layer 223; the second electrode 232 is disposed on the insulating layer 223 , arranged at intervals from the first electrode 231; the nano light-emitting diode 233 is arranged on the insulating layer 223, and is located between the first electrode 231 and the second electrode 232; between the first layer The dielectric layer 225 is disposed on the first electrode 232, the second electrode 232 and the nano light-emitting diode 233; the first contact electrode 234 is disposed on the first interlayer dielectric layer 225, located in the Between the first electrode 231 and the nano light emitting diode 233, and communicate with one of the poles of the first electrode 231 and the nano light emitting diode 233; the second interlayer dielectric layer 228 is arranged on the first on the contact electrode 234, and cover the exposed surface of the first interlayer dielectric layer 225; the second contact electrode 235 is arranged on the second interlayer dielectric layer 228, and is located between the second electrode 232 and the between the nano light emitting diodes 233 , and communicate with the second electrode 232 and the other of the two poles of the nano light emitting diodes 233 that is not connected.

In this embodiment, a plurality of nano light emitting diodes 233 are generally provided; a plurality of nano light emitting diodes 233 are arranged in alignment between the first electrode 231 and the second electrode 232 respectively, and the plurality of nano light emitting diodes 233 and the first electrode 231 Not in direct contact with the second electrode 232, one end of each nano light-emitting diode 233 communicates with the first electrode 231 through the first contact electrode 234, and the other end communicates with the second electrode 232 through the second contact electrode 235 to realize signal transmission, On the one hand, the first electrode 231 and the second electrode 232 play the role of making the alignment of the multiple nano-light emitting diodes 233 accurate, preventing the disorderly arrangement of the multiple nano-light-emitting diodes 233 during the inkjet printing process, resulting in adjacent nano-light-emitting diodes 233 There is a risk of short circuit; on the other hand, the first electrode 231 and the second electrode 232 communicate with the first contact electrode 234 and the second contact electrode 235 respectively, which can also improve the signal stability between the multiple nano-LEDs 233 .

In the actual application process of the array substrate 200, the driving thin film transistor 220 may have a bottom gate structure or a top gate structure. This application takes the driving thin film transistor 220 as an example with a top gate structure. Layer 221, semiconductor layer 222, gate electrode 224, source electrode 226 and drain electrode 227, the buffer medium layer 221 is arranged between the substrate 210 and the insulating layer 223; the semiconductor layer 222 is located in the insulating layer layer 223 and the buffer dielectric layer 221; the gate electrode 224 is disposed between the insulating layer 223 and the first interlayer dielectric layer 225, and corresponds to the position of the semiconductor layer 222, the gate The orthographic area of the electrode 224 on the substrate 210 is smaller than the orthographic area of the semiconductor layer 222; the source electrode 226 is arranged between the first interlayer dielectric layer 225 and the second interlayer dielectric layer 228 and connected to the semiconductor layer 222; the drain electrode 227 is disposed between the first interlayer dielectric layer 225 and the second interlayer dielectric layer 228, and is disposed opposite to the source electrode 226, and communicate with the semiconductor layer 222; wherein, the gate electrode 224 shares the same manufacturing process as the first electrode 231 and the second electrode 232; the source electrode 226, the drain electrode 227 and the first electrode A contact electrode 234 is fabricated by the same manufacturing process, and the drain electrode 227 is connected to the first contact electrode 234 .

In this embodiment, the driving thin film transistor 220 adopts a top-gate structure, and there is no overlapping area between the source electrode 226 and the drain electrode 227 and the gate electrode 224, or there is a small overlapping area, which greatly suppresses or reduces the gate electrode 224. The parasitic capacitance generated between the electrode 224 and the source electrode 226, and/or the gate electrode 224 and the drain electrode 227 avoids undesirable phenomena caused by capacitive effects, such as the flicker phenomenon that occurs when the display panel displays a picture, so that the thin film transistor 220 is driven Also has better stability.

Moreover, the gate electrode 224 of the driving thin film transistor 220 and the first electrode 231 and the second electrode 232 of the active light-emitting array 230 share the same manufacturing process, and the source electrode 226, the drain electrode 227 and the first contact electrode 234 share the same manufacturing process, and the leakage The electrode 226 communicates with the first contact electrode 234, and each metal layer is manufactured by the same process, which ensures the continuity of the metal layer and the uniformity of each position. Manufacturing process, the subsequent connection of the driving thin film transistor 220 and the active light-emitting array 230 together will result in poor connection effects, and improve the stability of the array substrate 200; on the other hand, the metal of the driving thin-film transistor 220 and the active light-emitting array 230 Layers share the same manufacturing process, which can also reduce the number of manufacturing processes for each film layer, improve production efficiency, and reduce manufacturing costs.

Furthermore, the light emitted by the nano-light emitting diode 233 in the array substrate 200 may be emitted along the substrate extending direction to the nano-light emitting diode 233, or may be emitted along the extending direction of the nano-light emitting diode 233 to the substrate. In this application, the nano-light emitting diode 233 The emitted light is emitted along the extending direction of the nano light-emitting diode 233 to the substrate 210 as an example, the array substrate 200 also includes a planarization layer 229, a reflective layer 236 and a thin film encapsulation layer 240, and the planarization layer 229 is arranged on the array on the substrate 220, and located on the side of the driving thin film transistor 220 and the active light-emitting array 230 away from the substrate 210; side, and corresponds to the position of the active light-emitting array 230; the thin film encapsulation layer 240 is disposed on the side of the reflective layer 236 away from the planarization layer 229, and is used for encapsulating the array substrate 200; the The substrate 210 is provided with a transparent area corresponding to the reflective layer 236 .

In this embodiment, a planarization layer 229 is provided on the driving thin film transistor 220 and the active light-emitting array 230, and the planarization layer 229 includes a light-transmitting material so as to guide light effectively so that the light energy emitted by the nano-LEDs 233 can be directed to the planarization layer. 229, a reflective layer 236 is set at the position corresponding to the active light-emitting array 230 on the planarization layer 229, and a light-transmitting area is set at the position corresponding to the reflective layer 236 on the substrate 210, so that the light emitted by the nano light-emitting diode 233 is reflected by the reflective layer 236 from the issued from the substrate 210. At the same time, a thin-film encapsulation layer 240 is provided on the reflective layer 236 to encapsulate the array substrate 200. The thin-film encapsulation layer 240 covers the driving thin-film transistor 220 and the active light-emitting array 230 at the same time, and the same manufacturing process can be used for the driving thin-film transistor 220 and the active light-emitting array 230. Simultaneous encapsulation reduces the number of encapsulations, reduces manufacturing costs, avoids quality differences caused by different manufacturing processes, and ensures the flatness of the array substrate 200. At the same time, it improves the production efficiency of the array substrate 200 and increases production capacity.

In order to improve the utilization rate of the light emitted by the active light-emitting array 230, the planarization layer 229 is provided with a dome structure corresponding to the position of the active light-emitting array 230, and the orthographic projection of the dome structure on the substrate 210 completely covers all The orthographic projection of the first electrode 231, the second electrode 232 and the nano light-emitting diode 233 on the substrate 210; the reflective layer 236 is arranged on the dome structure, and the reflective layer 236 is on the The orthographic projection area on the substrate 210 is greater than or equal to the orthographic projection area of the dome structure.

In this embodiment, a dome structure is set at the position where the planarization layer 229 corresponds to the active light-emitting array 230. Compared with other positions, the planarization layer 229 at the dome structure is thicker and can guide more light to gather to the dome structure. The concentration is better, and the orthographic projection of the dome structure on the substrate 210 is set to completely cover the orthographic projection of the first electrode 231, the second electrode 232 and the nano-light emitting diode 233 on the substrate 210, so that the nano-light emitting diode 233 emits The light utilization rate is higher.

At the same time, the reflective layer 236 is arranged on the dome structure, and the orthographic projection area of the reflective layer 236 on the substrate 210 is set to be greater than or equal to the orthographic projection area of the dome structure, so that the light emitted by the nano light-emitting diode 233 is transmitted through the planarization layer 229. Over time, the light outside the dome structure can also return to the bottom of the substrate 210 through the reflective layer 236, so that the light can be reflected by the reflective layer 236 to the greatest extent, and the utilization rate of light can be improved. In addition, setting the area of the orthographic projection of the reflective layer 236 on the substrate 210 to be equal to the area of the orthographic projection of the dome structure can increase the utilization rate of light while making the uniformity of light better, and in this embodiment, the For the radian of the dome structure, it is best to turn the light emitted by the nano-LEDs 233 into parallel light after reflection.

Generally, the active light-emitting array 230 needs to emit light, and also needs to trigger the switch that drives the thin film transistor 220 to work. Therefore, the switching thin film transistor 270 is also arranged on the substrate 210, and the array substrate 200 also includes a scanning line 250, a data line 260 and a capacitor 280. The capacitor 280 is arranged between the switching thin film transistor 270 and the driving thin film transistor 220, one end of the capacitor 280 is connected to the switching thin film transistor 270, and the other end is connected to the driving thin film transistor 220, and the switching thin film transistor 270 controls the opening and closing of the driving thin film transistor 220 closure.

Fig. 3 is a schematic diagram of a display panel according to an embodiment of the present application. With reference to Fig. 3, it can be seen that the present application also discloses a display panel 100, including the array substrate 200 in any embodiment of the present application, and the array substrate 200 is also provided with a color conversion layer 300, the color conversion layer 300 is disposed on the side of the substrate 210 away from the thin-film encapsulation layer 240, the color conversion layer 300 includes a light-transmitting area and a light-shielding area, and the light-shielding area corresponds to the drive film The transistor 220 is set, and the light-transmitting area is set corresponding to the active light-emitting array 230 .

In this embodiment, the display panel 100 is used as a QNED display panel, and the array substrate 200 is provided with a color conversion layer 300 on the side of the substrate 210 away from the thin film encapsulation layer 240. The color conversion layer 300 is provided with a light-shielding area corresponding to the driving thin film transistor 220 to prevent driving Light leakage occurs at the thin film transistor 220; a light-transmitting area is set corresponding to the active light-emitting array 230, so that the light reflected by the active light-emitting array 230 is completely transmitted, and is converted by the color conversion layer 300, so as to realize the display target display screen, so that the display The display effect of the panel 100 is better. The color conversion layer 300 may be disposed on the substrate 210 in an adhesive manner, or may be fabricated on the substrate 210 by other processes.

Certainly, the color conversion layer 300 may not be disposed on the array substrate 200 , but may be separately fabricated on a substrate, and may be disposed in a box-to-box manner with the array substrate 200 .

Among them, the driving thin film transistor 220 and the active driving array 230 of the array substrate 200 are produced in the same manufacturing process, which reduces the number of process steps, and can also reduce the thickness of the array substrate 200, further realizing the thinning of the display panel 100, thereby improving the display performance. Competitiveness of the panel 100.

Generally, in actual use, the nano light emitting diode 233 can emit blue light, white light or light of other colors. This application takes the nano light emitting diode 233 emitting blue light as an example, and the array substrate 200 includes red pixels, green pixels and blue pixels. Pixel; the nano light emitting diode 233 includes a blue light nano light emitting diode; the color conversion layer 300 includes a sub-color conversion layer 310 of multiple colors, and the sub-color conversion layer 310 is arranged in the light-transmitting region; the sub-color The conversion layer 310 includes a red sub-color conversion layer and a green sub-color conversion layer, the red sub-color conversion layer and the green sub-color conversion layer are both provided with quantum dots, and the sub-color conversion layer 310 corresponds to the blue pixel The hollow setting, the red sub-color conversion layer corresponds to the red pixel setting; the green sub-color conversion layer corresponds to the green pixel setting.

In this embodiment, the nano light emitting diode 233 is a blue light nano light emitting diode, the color conversion layer 300 includes a sub-color conversion layer 310 of multiple colors, the sub-color conversion layer 310 is arranged in the light-transmitting area, and the sub-color conversion layer 310 includes a red sub-color The conversion layer and the green sub-color conversion layer, and the sub-color conversion layer 310 is corresponding to the blue pixel hollow setting, the red sub-color conversion layer is corresponding to the red pixel setting, the green sub-color conversion layer is corresponding to the green pixel setting, and the green sub-color conversion layer is corresponding to the green pixel setting. The sub-color conversion layers are all provided with quantum dots, through which the blue light emitted by the nano light-emitting diodes 233 of the array substrate 200 is converted into red light and green light to realize image display. At this time, the display panel 100 serves as a quantum dot nanorod electroluminescent diode display panel. Of course, the sub-color conversion layer 310 can also be provided with other substances that can convert blue into red or green, or use nano light-emitting diodes 233 of different colors, such as white or red, etc., to achieve display images as well.

Therefore, the sub-color conversion layer 310 can be arranged corresponding to the position of the reflective layer 236, so that all the light energy reflected by the reflective layer 236 is converted by the quantum dots 310, so as to realize the maximum utilization of light. The color conversion layer 300 also includes a black matrix 320. The black matrix 320 is disposed in the light-shielding area as a light-blocking film, and is mainly used to prevent color mixing of light between adjacent light-transmitting areas, and to block the driving thin film transistor 220 on the array substrate 200. To prevent light leakage, the black matrix 320 can be disposed on the color conversion layer 300 except for the sub-color conversion layer 310 to improve the display effect of the display panel 100 .

Wherein, the size of the sub-color conversion layer 310 in this embodiment is smaller than or equal to the size of the dome structure. When it is equal to, the maximum utilization of reflected light can be ensured; and when it is smaller, the uniformity of light can be improved, because the edge of the dome structure The relative uniformity of the light reflected at the position will be poorer, and the size of the sub-color conversion layer 310 is set smaller than the size of the dome structure, so this part of light can be eliminated, thereby improving the uniformity of light.

Further, the display panel 100 further includes a polarizing layer 330, the polarizing layer 330 is arranged on the side of the color conversion layer 300 away from the array substrate 200, the polarizing layer 330 can be attached by means of glue or double-sided tape, etc. Attached to the surface of the color conversion layer 300 , through the polarizing layer 330 , the light emitted through the color conversion layer 300 is emitted in a direction perpendicular to the color conversion layer 300 , improving the display effect of the display panel 100 .

Fig. 4 is a schematic diagram of the manufacturing process of the array substrate according to the first embodiment of the present application. With reference to Fig. 4, it can be seen that, as the first embodiment of the present application, a method for manufacturing an array substrate is disclosed, including steps:

S1. Provide a substrate, and divide the substrate into at least a driving region and a light emitting region;

S2, forming an insulating layer covering the driving region and the light emitting region on the substrate;

S3. Depositing a first conductive material on the insulating layer, and etching the first conductive material, forming a gate electrode corresponding to the driving region, and forming a first electrode and a second electrode opposite to each other corresponding to the light emitting region;

S4, forming an active light-emitting layer between the first electrode and the second electrode;

S5 , forming a driving thin film transistor at a position corresponding to the gate electrode in the driving region, and forming an active light-emitting array at a position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain an array substrate.

Compared with the solution of forming an active light-emitting array after the driving circuit is laid, resulting in doubling of the manufacturing process and high manufacturing cost, this application adopts the same process in the manufacturing process of the array substrate to drive the thin film transistor in the driving area. At the same time as the gate electrode of the light-emitting area, the first electrode and the second electrode of the active light-emitting array in the light-emitting area are formed, which saves at least one process and reduces manufacturing costs; at the same time, the process of forming the driving thin film transistor and other layers in the active light-emitting array can also be used. The same process is completed, which greatly reduces the number of process processes, such as exposure, development, deposition and etching processes, further reduces the manufacturing cost of array substrates, improves production efficiency, increases product productivity, and thus improves product competitiveness. .

In this embodiment, in step S1, a substrate is firstly provided as the substrate for manufacturing the array substrate, the substrate may be a glass substrate, and the substrate is divided into the driving area A1 and the light emitting area A2; then in step S2, on the substrate The entire driving area and light emitting area, using CVD (Chemical Vapor Deposition) method to form an insulating layer, the insulating layer can be an inorganic insulating layer or an organic insulating layer, including any silicon nitride (SiNx) or silicon oxide (SiOx) One, it can be composed of at least one of SiNx layer or SiOx layer, that is, the insulating layer can be made of SiNx layer or SiOx layer single-layer structure, or a multilayer structure consisting of two or more layers of SiNx layer or SiOx layer The specific material of the insulating layer is selected according to the material of the gate electrode.

In step S3, the first conductive material is deposited on the insulating layer, and the first conductive material is etched and patterned, the gate electrode of the driving thin film transistor is formed corresponding to the driving region, and the first electrode and the first electrode of the active driving array are formed corresponding to the light emitting region. The second electrode, and the first electrode and the second electrode are arranged oppositely, and the gate electrode, the first electrode and the second electrode can be made of at least one or at least two materials of materials such as copper, aluminum, molybdenum and titanium or indium tin oxide. A mixed single-layer structure can also be a composite layer structure of two or more layers formed by at least one or at least two of materials such as copper, aluminum, molybdenum, titanium or indium tin oxide. Of course, other materials can also be used. After step S3 is completed, proceed to step S4 to form an active light-emitting layer between the first electrode and the second electrode; next step S5, form a driving thin film transistor at the position corresponding to the gate electrode in the driving region, and in the light-emitting region An active light-emitting array is formed at a position corresponding to the active light-emitting layer, so as to obtain an array substrate.

The driving thin film transistor of this application can adopt a top-gate structure or a bottom-gate structure. For a clearer illustration, the design scheme using a top-gate structure is shown as follows:

Fig. 5 is a schematic diagram of the manufacturing process of the array substrate according to the second embodiment of the present application. Referring to Fig. 5, it can be known that in the actual application process of the array substrate, the driving thin film transistor is mainly used to drive the active light-emitting array to emit light, and the driving thin film transistor can be a bottom gate structure, it can also be a top-gate structure. Compared with the bottom-gate structure, the overlapping area between the gate electrode and the source electrode and the drain electrode in the top-gate structure is less, which can reduce the gate electrode and the source electrode, and/or the gate electrode and the drain electrode. The parasitic capacitance generated between them can more stably ensure the performance of the driving thin film transistor. Optionally, this application takes the driving thin film transistor as an example with a top gate structure, and the insulating layer covering the driving region and the light emitting region is formed on the substrate The step S2 includes:

S21. Depositing a buffer dielectric material on the substrate to form a buffer dielectric layer;

S22. Depositing a semiconductor layer material on the buffer medium layer, and etching the semiconductor layer material, partially etching the corresponding driving region to form a semiconductor layer, and completely etching the corresponding light emitting region;

S23 , forming an insulating layer covering the driving region and the light emitting region on the semiconductor layer.

Wherein, before forming the insulating layer, a buffer dielectric material is first deposited on the substrate to form a buffer dielectric layer. The buffer dielectric layer may be composed of a multilayer structure of more than two layers, and is composed of at least one of a SiNx layer or a SiOx layer; Deposit a semiconductor layer material on the buffer dielectric layer, etch and pattern it, and form a semiconductor layer corresponding to the driving region. The semiconductor layer can be an oxide semiconductor or polysilicon, and the orthographic projection area of the gate electrode on the substrate is smaller than that of the semiconductor layer. The area of the orthographic projection on the substrate; and the fabrication of the insulating layer on the semiconductor layer.

Fig. 6 is a schematic diagram of the manufacturing process of the array substrate according to the third embodiment of the present application, and Fig. 7 is a schematic cross-sectional schematic diagram of the change of the film layer along the direction AA' corresponding to Fig. 1 in the manufacturing process of the third embodiment of the present application, combined with Fig. 5 - Fig. 7. As the third embodiment of the present application, in order to reduce the number of processes of the array substrate, the driving thin film transistor is formed at the position corresponding to the gate electrode in the driving region, and the active light-emitting array is formed at the position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain The step S5 of array substrate comprises:

S511, forming nano light emitting diodes on the active light emitting layer by printing inkjet;

S512, depositing a first interlayer dielectric layer material on the nano light emitting diode, and etching the first interlayer dielectric layer material to form a first interlayer dielectric layer, the first via hole and the second via hole located on both sides of the gate electrode a hole, and a first contact hole between the first electrode and the nano light emitting diode;

S513, depositing a second conductive material on the first interlayer dielectric layer, and etching the second conductive material to form a source electrode located in the first via hole, a drain electrode located in the second via hole, and a source electrode located in the first contact hole The first contact electrode, and the drain electrode is connected to the first contact electrode;

S514, depositing a second interlayer dielectric layer material on the source electrode, the drain electrode and the first contact electrode, and etching the second interlayer dielectric layer material to form a second interlayer dielectric layer, and a second contact hole between the nano light-emitting diodes;

S515, depositing a third conductive material on the second interlayer dielectric layer, and etching the third conductive material to form a second contact electrode connecting the second electrode and the nano light emitting diode through the second contact hole;

S516. Deposit a planarization layer material on the second contact electrode, and etch the planarization layer material to obtain a planarization layer corresponding to a flat driving region and forming a dome structure corresponding to a light emitting region;

S517, forming a reflection layer corresponding to the dome structure on the planarization layer;

S518 , forming a thin film encapsulation layer on the reflective layer to form a driving thin film transistor in the driving region, and forming an active light emitting array at a position corresponding to the active light emitting layer in the light emitting region, so as to obtain an array substrate.

In step S511, a plurality of nano light-emitting diode devices are mixed into the luminescent solvent, and ink-jet equipment is used to spray a plurality of nano-light-emitting diodes into the light-emitting area by printing and ink-jet, and a plurality of nano-light-emitting diodes are sprayed into the light-emitting area by using diffusion and alignment technology. The diodes are arranged in an array and arranged between the first electrode and the second electrode; after completion, proceed to step S512, depositing a first interlayer dielectric layer material on the nano light-emitting diodes, and etching it to form a first interlayer dielectric layer , and are located on both sides of the gate electrode, and penetrate the first interlayer dielectric layer, the insulating layer to the first via hole and the second via hole on the surface of the semiconductor layer, and the first contact hole located between the first electrode and the nano light emitting diode , the first interlayer dielectric layer can be made of at least one of SiNx layer or SiOx layer, can be made by SiNx layer or SiOx layer single-layer structure, and can also be made of two or more layers of SiNx layer or SiOx layer. Layer structure fabrication, that is, the material of the first interlayer dielectric layer can be the same as that of the insulating layer, and the first interlayer dielectric layer and the insulating layer are etched in the same process to form the first interlayer dielectric layer penetrating through the surface of the semiconductor layer. The via hole and the second via hole reduce the process, thereby reducing the manufacturing cost.

Of course, the first interlayer dielectric layer can also be made of other materials. In order to prevent different etching rates of different materials during the etching process of the same process, the first interlayer dielectric layer and the insulating layer form the first via hole and the second via hole. When the via hole is undercut at the junction of the two layers, the first interlayer dielectric layer and the insulating layer can be etched separately, and the first via hole and the second via hole can be formed by using two etching processes to prevent the undercut angle from causing Disconnection problem, improve the stability of the array substrate.

In step S513, a second conductive material is deposited on the first interlayer dielectric layer, and the second conductive material is etched by an etching process, and patterned to form source electrodes and drain electrodes located at intervals in the driving region, and Connected to the drain electrode and located in the first contact electrode of the light-emitting region, the first electrode, the nano light-emitting diode and the drain electrode are connected through the first contact electrode. The source electrode, the drain electrode and the first contact electrode can be made of copper, aluminum, molybdenum and A single-layer structure in which at least one or at least two materials of titanium or indium tin oxide are mixed, or at least one or at least two of copper, aluminum, molybdenum, and titanium or indium tin oxide are used Of course, the composite layer structure of two or more layers can also be made of other electrode metal materials.

After step S513 is completed, proceed to step S514, deposit a layer of second interlayer dielectric layer material on the source electrode, drain electrode and first contact electrode, and etch the second interlayer dielectric layer material to form a second interlayer dielectric layer , and between the second electrode and the nano light-emitting diode, and through the second interlayer dielectric layer and the second contact hole of the first interlayer dielectric layer, the second interlayer dielectric layer can be made of at least one of the SiNx layer or the SiOx layer One or more than one structure can be made by SiNx layer or SiOx layer single-layer structure, and can also be made by a multi-layer structure made of two or more layers of SiNx layer or SiOx layer, that is, the second interlayer dielectric layer and the first The material of the interlayer dielectric layer can be selected to be the same, and the first interlayer dielectric layer and the second interlayer dielectric layer are etched simultaneously to form a second contact hole penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer. Of course, the material of the second interlayer dielectric layer and the first interlayer dielectric layer can also be selected to be different, and the first interlayer dielectric layer and the second interlayer dielectric layer are respectively etched, and two etching processes are adopted to prevent the second contact The hole generates an undercut corner at the junction of the second interlayer dielectric layer and the first interlayer dielectric layer.

In step S515, a third conductive material is deposited on the second interlayer dielectric layer, and it is etched, and patterned to form a second contact electrode, and the connection between the second electrode and the nano light-emitting diode is realized through the second contact electrode. connected, the second contact electrode can adopt at least one single-layer structure of copper, aluminum, molybdenum and titanium or indium tin oxide or a mixture of at least two materials, or it can use copper, aluminum, molybdenum and titanium or oxide The two-layer or more than two-layer composite layer structure formed by at least one or at least two materials such as indium tin can of course also be made of other electrode metal materials.

Step S516 is performed after the formation of the second contact electrode. Corresponding to the driving area and the light emitting area, a nozzle or spin coating process is used to use an organic insulating substance with strong light transmittance on the second contact electrode, and a half-tone exposure process is used to form The corresponding drive area is flat, and a planarization layer with a dome-shaped curved surface pattern structure is formed on the upper part of the corresponding light-emitting area. The dome structure is set on the upper part corresponding to the nano light-emitting diode, along the second contact electrode extending direction to the planarization layer, and protrudes from the drive area. The hemispherical surface structure of the planarization layer, the orthographic projection of the dome structure completely covers the nano light-emitting diodes, the first electrode, the second electrode, the first contact electrode and the second contact electrode, so that the dome structure covers a plurality of nano light-emitting diodes, which plays the role of The function of converging light emitted by a plurality of nano light-emitting diodes improves the utilization rate of light.

Step S517 Deposit a layer of metal material on the dome structure of the planarization layer in the corresponding light-emitting area, and etch and pattern the metal material to form a reflective layer. The orthographic projection of the reflective layer can be set to be greater than or equal to the orthographic projection of the dome structure, Make the light emitted by the nano light-emitting diode fully reflected, and return to the bottom of the reflective layer; after forming the reflective layer, proceed to step S518, using CVD deposition method and nozzle printing method to form a thin film encapsulation layer on the reflective layer, and the thin film encapsulation layer covers The reflective layer, and the exposed surface of the planarization layer in the driving area and the light emitting area, the thin film encapsulation layer can be made of an organic insulating material and an inorganic film (at least one of SiNx, SiOx, SiON or a composite layer of at least two or more) The multi-layer encapsulation layer forms the array substrate after the encapsulation is completed.

In addition, in order to improve the stability of the array substrate and prevent the problem of undercut corners during the fabrication process, during the fabrication of the array substrate, in step S512, when etching the first interlayer dielectric layer, not only the first interlayer dielectric layer corresponding to the driving region is formed A via hole and a second via hole, and simultaneously form a corresponding light emitting region, a first contact hole located between the first electrode and the nano light emitting diode and a second contact hole located between the second electrode and the nano light emitting diode; step S514 When etching the second interlayer dielectric layer, corresponding to the second contact hole position, the second interlayer dielectric layer above the second contact hole position is etched to form a third contact hole, and at the same time, the gap between the nano light emitting diode and the second electrode is exposed. For the second contact hole, the second contact hole and the third contact hole are etched twice, so that at the contact hole, the side transition between the first interlayer dielectric layer and the second interlayer dielectric layer is smoother The second electrode and the nano light emitting diode are exposed through the second contact hole and the third contact hole, and the second electrode and the nano light emitting diode are connected through the subsequently formed second contact electrode.

The contact hole between the second electrode and the nano light-emitting diode is formed through two process steps, that is, the second contact hole and the third contact hole, which can reduce the possibility of problems such as undercut corners formed between two or more dielectric layer structures characteristics, avoiding disconnection of the second contact electrode, and improving the connection performance between the second electrode and the nano-LED; at the same time, the first contact hole and the second contact hole are formed in the same process, which can also reduce a photomask process and reduce manufacturing costs. cost.

Of course, when the first contact hole and the second contact hole are formed in the same process, the second contact electrode and the first contact electrode can also be formed in the same process, that is, when step S513 is performed, the first interlayer dielectric layer is deposited on the first interlayer dielectric layer. Two conductive materials, and when etching the second conductive material, simultaneously form the source electrode at the position of the first via hole, the drain electrode at the position of the second via hole, the first contact electrode at the position of the first contact hole, and the second contact hole The second contact electrode at the position, and the drain electrode is connected to the first contact electrode, and there is no connection between the first contact electrode and the second contact electrode, so that at least two photomasks and one etching process can be reduced, and the manufacturing cost can be reduced.

In addition, when the first contact electrode and the second contact electrode are formed in the same process, the step of forming the second interlayer dielectric layer can also be omitted, and the planarization can be performed directly on the source electrode, the drain electrode, the first contact electrode and the second contact electrode. The production of the chemical layer can also reduce one deposition and photomask process, and further reduce the production cost.

Usually the active light-emitting array needs to emit light, and also needs to trigger the switch that drives the thin film transistor to work. Therefore, the substrate is also divided into a switch area, and the switch area is formed with a switch thin film transistor. The switch thin film transistor and the drive thin film transistor are formed through the same process. The switching thin film transistor and the driving thin film transistor are manufactured in the same process, that is, the switching thin film transistor, the driving thin film transistor and the active light-emitting array are manufactured in the same process, which reduces the separate forming process of each film layer of the switching thin film transistor, reduces the number of times of process doubling, and saves At least two processes of deposition, exposure, etching, etc., reduce the manufacturing cost and further improve the production efficiency.

It should be noted that the limitations of the steps involved in this plan are not considered as limiting the order of the steps without affecting the implementation of the specific plan. The steps written in the front can be executed first. It can also be performed later, or even at the same time, as long as the solution can be implemented, it should be considered as belonging to the protection scope of the present application.

It should be noted that the inventive concept of the present application can form a lot of embodiments, but the space of the application documents is limited, and it is impossible to list them one by one. The technical features can be combined arbitrarily to form a new embodiment, and the original technical effect will be enhanced after each embodiment or technical feature is combined.

The technical scheme of the present application can be widely used in various display panels, such as QNED (Quantum-dot Nano-rod Electroluminescent Diode, quantum dot nano-rod electroluminescent diode) display panel, OLED (Organic Light-Emitting Diode, organic light-emitting diode) The display panel, of course, can also be other types of display panels, and the above solution can be applied to all of them.

The above content is a further detailed description of the present application in conjunction with specific optional implementation modes, and it cannot be deemed that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field described in this application, without departing from the concept of this application, some simple deduction or replacement can also be made, which should be regarded as belonging to the protection scope of this application.

Claims

An array substrate, including a substrate and a plurality of pixel units, a plurality of pixel units are arranged on the substrate, each of the pixel units includes a plurality of sub-pixels, and the sub-pixels include driving thin film transistors and active light emitting array;

The driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor is connected to the active light emitting array.
The array substrate according to claim 1, wherein the active light emitting array comprises:

an insulating layer disposed on the substrate;

a first electrode disposed on the insulating layer;

a second electrode disposed on the insulating layer and spaced apart from the first electrode;

a nano light emitting diode, disposed on the insulating layer, and located between the first electrode and the second electrode;

a first interlayer dielectric layer disposed on the first electrode, the second electrode and the nano light emitting diode;

A first contact electrode, disposed on the first interlayer dielectric layer, located between the first electrode and the nano light emitting diode, and connected to one of the two poles of the first electrode and the nano light emitting diode ;

a second interlayer dielectric layer disposed on the first contact electrode and covering the exposed surface of the first interlayer dielectric layer; and

The second contact electrode is arranged on the second interlayer dielectric layer, is located between the second electrode and the nano light emitting diode, and communicates with the second electrode and the two poles of the nano light emitting diode that are not covered. Connected to another one.
The array substrate according to claim 2, wherein the driving thin film transistor comprises:

a buffer dielectric layer disposed between the substrate and the insulating layer;

a semiconductor layer located between the insulating layer and the buffer medium layer;

A gate electrode, arranged between the insulating layer and the first interlayer dielectric layer, and corresponding to the position of the semiconductor layer, the orthographic area of the gate electrode on the substrate is smaller than that of the semiconductor layer orthographic area;

a source electrode, disposed between the first interlayer dielectric layer and the second interlayer dielectric layer, and communicated with the semiconductor layer;

a drain electrode disposed between the first interlayer dielectric layer and the second interlayer dielectric layer, opposite to the source electrode, and communicated with the semiconductor layer;

Wherein, the gate electrode and the first electrode and the second electrode share the same manufacturing process; the source electrode, the drain electrode and the first contact electrode share the same manufacturing process, and the drain electrode and the The first contact electrodes are connected.
The array substrate according to claim 1, wherein the array substrate further comprises a planarization layer, a reflective layer and a thin film encapsulation layer, the planarization layer is disposed on the array substrate and located between the driving thin film transistor and the The active light-emitting array is away from the side of the substrate; the reflective layer is arranged on the side of the planarization layer away from the array substrate, and corresponds to the position of the active light-emitting array; the thin film encapsulation layer is arranged on the side of the reflective layer away from the planarization layer, for packaging the array substrate;

The substrate is provided with a transparent area corresponding to the reflective layer.
The array substrate according to claim 4, wherein the planarization layer is provided with a dome structure corresponding to the position of the active light-emitting array, and the orthographic projection of the dome structure on the substrate completely covers the first electrode , the orthographic projection of the second electrode and the nano light-emitting diode on the substrate; the reflective layer is arranged on the dome structure, and the orthographic projection area of the reflective layer on the substrate is larger than Equal to the orthographic projection area of the dome structure.
The array substrate according to claim 1, wherein a switching thin film transistor is further arranged on the substrate, and the array substrate further includes a scanning line, a data line and a capacitor; the capacitor is arranged between the switching thin film transistor and the Between the driving thin film transistors, one end of the capacitor is connected to the switching thin film transistor, and the other end is connected to the driving thin film transistor.
The array substrate according to claim 4, wherein the thin film encapsulation layer covers both the driving thin film transistor and the active light emitting array.
The array substrate according to claim 5, wherein the thickness of the planarization layer corresponding to the dome structure is greater than the thickness of the planarization layer except for the dome structure.
A display panel, including an array substrate, the array substrate includes a substrate and a plurality of pixel units, the plurality of pixel units are arranged on the substrate, each of the pixel units includes a plurality of sub-pixels, the sub-pixels The pixel includes a driving thin film transistor and an active light emitting array; the driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor is connected to the active light emitting array;

The array substrate is also provided with a color conversion layer, the color conversion layer is disposed on the side of the substrate away from the thin-film encapsulation layer, the color conversion layer includes a light-transmitting area and a light-shielding area, and the light-shielding area corresponds to The driving thin film transistor is set, and the light-transmitting area is set corresponding to the active light-emitting array.
The display panel according to claim 9, wherein the array substrate comprises red pixels, green pixels and blue pixels; the nano light emitting diodes comprise blue light nano light emitting diodes;

The color conversion layer includes sub-color conversion layers of multiple colors, and the sub-color conversion layer is arranged in the light-transmitting region; the sub-color conversion layer includes a red sub-color conversion layer and a green sub-color conversion layer, the Both the red sub-color conversion layer and the green sub-color conversion layer are provided with quantum dots, the sub-color conversion layer corresponds to the blue pixel hollow setting, and the red sub-color conversion layer corresponds to the red pixel setting; The green sub-color conversion layer corresponds to the green pixel setting.
The display panel according to claim 9, wherein the display panel comprises a polarizing layer, and the polarizing layer is disposed on a side of the color conversion layer away from the array substrate.
The display panel according to claim 10, wherein the color conversion layer further comprises a black matrix, and the black matrix is disposed in the light-shielding area.
The display panel according to claim 10, wherein the sub-color conversion layer is arranged correspondingly to the reflective layer.
The display panel of claim 10, wherein a size of the sub-color conversion layer is smaller than or equal to a size of the dome structure.
The display panel according to claim 11, wherein the polarizing layer is attached to the surface of the color conversion layer by means of glue or double-sided tape.
A method for fabricating an array substrate, used for fabricating an array substrate, the array substrate includes a substrate and a plurality of pixel units, the plurality of pixel units are arranged on the substrate, and each of the pixel units includes a plurality of sub-substrates A pixel, the sub-pixel includes a driving thin film transistor and an active light emitting array; the driving thin film transistor and the active light emitting array are adjacently arranged on the substrate, and the driving thin film transistor is connected to the active light emitting array; include:

providing a substrate, dividing the substrate into at least a driving region and a light emitting region;

forming an insulating layer covering the driving region and the light emitting region on the substrate;

Depositing a first conductive material on the insulating layer, and etching the first conductive material, forming a gate electrode corresponding to the driving region, and forming a first electrode and a second electrode opposite to each other corresponding to the light emitting region;

forming an active light-emitting layer between the first electrode and the second electrode;

A driving thin film transistor is formed at a position corresponding to the gate electrode in the driving region, and an active light-emitting array is formed at a position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain an array substrate.
The method for manufacturing an array substrate according to claim 16, wherein the step of forming an insulating layer covering the driving region and the light emitting region on the substrate comprises:

Depositing a buffer dielectric material on the substrate to form a buffer dielectric layer;

Depositing a semiconductor layer material on the buffer medium layer, and etching the semiconductor layer material, partially etching the corresponding driving region to form a semiconductor layer, and completely etching the corresponding light emitting region;

forming an insulating layer covering the driving region and the light emitting region on the semiconductor layer;

The step of forming a driving thin film transistor at a position corresponding to the gate electrode in the driving region, and forming an active light-emitting array at a position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain an array substrate includes:

Form nano light-emitting diodes on the active light-emitting layer by printing inkjet;

Depositing a first interlayer dielectric layer material on the nano light-emitting diode, and etching the first interlayer dielectric layer material to form a first interlayer dielectric layer, a first via hole and a second via hole located on both sides of the gate electrode, and a first contact hole located between the first electrode and the nano light emitting diode;

Deposit a second conductive material on the first interlayer dielectric layer, and etch the second conductive material to form a source electrode located in the first via hole, a drain electrode located in the second via hole, and a second conductive material located in the first contact hole. a contact electrode, and the drain electrode is connected to the first contact electrode;

Depositing a second interlayer dielectric layer material on the source electrode, drain electrode and first contact electrode, and etching the second interlayer dielectric layer material to form a second interlayer dielectric layer, and a second contact hole between the diodes;

depositing a third conductive material on the second interlayer dielectric layer, and etching the third conductive material to form a second contact electrode connecting the second electrode and the nano light emitting diode through the second contact hole;

depositing a planarization layer material on the second contact electrode, and etching the planarization layer material to obtain a planarization layer corresponding to a flat driving region and forming a dome structure corresponding to a light emitting region;

On the planarization layer, a reflective layer corresponding to the dome structure is formed; and

A thin-film encapsulation layer is formed on the reflective layer to form a driving thin-film transistor in the driving area, and an active light-emitting array is formed in a position corresponding to the active light-emitting layer in the light-emitting area to obtain an array substrate.
The method for manufacturing an array substrate according to claim 16, wherein, in the step of providing the substrate and dividing the substrate into at least a driving area and a light emitting area, the substrate is further divided into a switch area, and the switch A switching thin film transistor is formed in the region, and the switching thin film transistor and the driving thin film transistor are formed through the same process.
The method for manufacturing an array substrate according to claim 16, wherein the step of forming an insulating layer covering the driving region and the light emitting region on the substrate comprises:

Depositing a buffer dielectric material on the substrate to form a buffer dielectric layer;

Depositing a semiconductor layer material on the buffer medium layer, and etching the semiconductor layer material, partially etching the corresponding driving region to form a semiconductor layer, and completely etching the corresponding light emitting region;

forming an insulating layer covering the driving region and the light emitting region on the semiconductor layer;

The step of forming a driving thin film transistor at a position corresponding to the gate electrode in the driving region, and forming an active light-emitting array at a position corresponding to the active light-emitting layer in the light-emitting region, so as to obtain an array substrate includes:

Form nano light-emitting diodes on the active light-emitting layer by printing inkjet;

Depositing a first interlayer dielectric layer material on the nano light-emitting diode, and etching the first interlayer dielectric layer material to form a first interlayer dielectric layer, a first via hole and a second via hole located on both sides of the gate electrode, a first contact hole located between the first electrode and the nano light emitting diode, and a second contact hole located between the second electrode and the nano light emitting diode;

Deposit a second conductive material on the first interlayer dielectric layer, and etch the second conductive material to form a source electrode located in the first via hole, a drain electrode located in the second via hole, and a second conductive material located in the first contact hole. a contact electrode, and the drain electrode is connected to the first contact electrode;

Depositing a second interlayer dielectric layer material on the source electrode, the drain electrode and the first contact electrode, and etching the second interlayer dielectric layer material, corresponding to the position of the second contact hole, etching and removing the first layer above the position of the second contact hole The second interlayer dielectric layer forms the third contact hole, and at the same time exposes the second contact hole between the nano light emitting diode and the second electrode, so as to form the second interlayer dielectric layer, and the contact hole between the second electrode and the nano light emitting diode ;

depositing a third conductive material on the second interlayer dielectric layer, and etching the third conductive material to form a second contact electrode connecting the second electrode and the nano light emitting diode through the contact hole;

depositing a planarization layer material on the second contact electrode, and etching the planarization layer material to obtain a planarization layer corresponding to a flat driving region and forming a dome structure corresponding to a light emitting region;

On the planarization layer, a reflective layer corresponding to the dome structure is formed; and

A thin-film encapsulation layer is formed on the reflective layer to form a driving thin-film transistor in the driving area, and an active light-emitting array is formed in a position corresponding to the active light-emitting layer in the light-emitting area to obtain an array substrate.