WO2023004661A1

WO2023004661A1 - Semiconductor arrangement

Info

Publication number: WO2023004661A1
Application number: PCT/CN2021/109129
Authority: WO
Inventors: Juergen Hoegerl; Ruoyang DU
Original assignee: Huawei Technologies Co.,Ltd.
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2023-02-02
Also published as: CN117751447A

Abstract

A semiconductor arrangement comprises at least one power module for electric power conversion. A first mold body is arranged between a first module side and a second module side of the power module. At least one semiconductor chip is embedded within the first mold body. The first module side comprises an upper metal layer forming an upper heat dissipation surface of the at least one power module. The second module side comprises a lower metal layer forming a lower heat dissipation surface of the at least one power module. A second mold body is encapsulating the at least one power module. An upper cavity is formed in the second mold body to form an upper cooling channel. A lower cavity is formed in the second mold body to form a lower cooling channel. A respective contact area of the upper metal layer and the lower metal layer with the second mold body comprises a rough surface structure that enables a sealed connection between the respective contact area and the second mold body.

Description

Semiconductor arrangement

TECHNICAL FIELD

The present disclosure relates to the field of low cost and high-efficient direct water cooling for molded power modules that may be used in automotive and industrial devices. For example, the present disclosure relates to a semiconductor arrangement with a cooling channel for cooling the semiconductor arrangement by a flow of cooling medium.

BACKGROUND

In automotive and industrial applications, in particular automotive inverter systems, efficient cooling is the key to improve performance and lifetime. The more efficient the thermal paths are inside such a cooling system from die surface to cooling media (e.g. water glycol mixture) , the more power can be handled by the system for a given active chip area. Basic simulations for double side cooled power modules have shown that the so called “direct water cooling” concept is providing the best performance. The concept assumes that the cooling media is in direct contact with the package’s own heat dissipating areas, thereby requiring an efficient sealing of the cooling media. Currently, all cooling solutions are based on seal ring or adhesion concepts independently which kind of power modules are used. Seal rings, however, are subject of leakage and bonded structures have issues during hot and cold test. From experience those sealings are affected by potential fails as seal rings my brake and direct material contact is often affected by delamination caused by the CTE (coefficient of thermal expansion) mismatch between the elements combined with non-adequate adhesion properties or even residues on the surfaces. Hence, there is a need for a cooling concept realizing “direct water cooling” at an optimum cost level in conjunction with a high reliability such as automotive level reliability.

SUMMARY

Devices and methods according to this disclosure allow to provide a solution for a semiconductor arrangement with a cooling concept without the above described disadvantages. Thus, a solution for an efficient direct water cooling for molded power modules is provided. Note that the term direct water cooling used herein also includes direct cooling by other liquid cooling media such as water glycol mixture, for example.

The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

A basic idea of this disclosure is a seal ring free direct cooling concept for producing direct cooled power modules, in particular double side cooled modules, including the forming of a “second mold body” in combination with mechanical interlock for adhesion within the crucial sealing regions. When forming a second mold body, an exemplary number of three modules, e.g. half bridges, are put side aside and connected with the so called “second mold body” . Those three modules then form a so-called “six-pack” required to drive a 3-phase motor.

Another idea of this disclosure is the concept of a turbulence structure, in particular a non-uniform turbulence structure. Such a turbulence structure may be clamped between cooler areas of the modules and cover plates (top and bottom) to enable balanced chip temperatures, e.g. within a certain range of 5 degrees Celsius, for example, throughout the complete six-pack arrangement. This temperature balancing is essential for an even current flow of cooling media through the three modules and improves performance and reliability significantly. In this concept, non-uniform turbulence inserts can be clamped between cooler areas and cover plates (top and bottom) which ensure such kind of contact and such a spreading performance that the chip temperature can be maintained within a certain temperature range, e.g. within 5 degrees Celsius, even at full load.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

CTE coefficient of thermal expansion

DBA direct bonded aluminum

US bonding ultra-sonic bonding

ALD atomic layer deposition

According to a first aspect, the disclosure relates to a semiconductor arrangement, comprising: at least one power module for electric power conversion, the at least one power module comprising a first module side and a second module side opposing the first module side, wherein a first mold body is arranged between the first module side and the second module side; at least one semiconductor chip which is embedded within the first mold body; wherein the first module side comprises an upper metal layer forming an upper heat dissipation surface of the at least one power module, and wherein the second module side comprises a lower metal layer forming a lower heat dissipation surface of the at least one power module; and a second mold body comprising a first body side and a second body side opposing the first body side, the second mold body encapsulating the at least one power module, wherein an upper cavity is formed in the second mold body above the upper metal layer to form an upper cooling channel and wherein a lower cavity is formed in the second mold body below the lower metal layer to form a lower cooling channel, wherein a respective contact area of the upper metal layer and the lower metal layer with the second mold body comprises a rough surface structure that enables a sealed connection between the respective contact area and the second mold body.

The rough surface structure provides the technical effect that the upper metal layer and the lower metal layer comprise an undercut structure that can claw into the soft material of the second mold body, e.g. made of a thermoplastic. These sharp edges of the rough surface structure of upper/lower metal layer clawing into the second mold body provide the tight or sealed connection by mechanic adhesion, e.g. in the manner of a Velcro fastener.

In an exemplary implementation of the semiconductor arrangement, a hole is formed in the second mold body, wherein the upper cooling channel and the lower cooling channel are fluidly connected, and wherein the upper cooling channel and the lower cooling channel are formed to enable a flow of cooling medium through the upper cooling channel and the lower cooling channel.

This provides the advantage of efficient cooling of the semiconductor arrangement by direct water cooling. Of course any other liquid can be used for cooling, e.g. a water glycol mixture.

The hole may be, for example, a through-hole through the second mold body to connect the upper cooling channel with the lower cooling channel.

Alternatively, the hole may be a single-side hole for connecting the upper cooling channel, while another single-side hole can be used for connecting the lower cooling channel, for example.

The second mold body may comprise one or more through-holes and/or one or more single-side holes, for example.

In an exemplary implementation of the semiconductor arrangement, the semiconductor arrangement comprises: a top cover plate covering the first body side of the second mold body and the upper cavity; and a bottom cover plate covering the second body side of the second mold body and the lower cavity.

This provides the advantage that the top and bottom cover plates can be used to seal the power module (s) within the semiconductor arrangement in order to protect them against environmental influences.

In an exemplary implementation of the semiconductor arrangement, the top cover plate comprises a cooling medium inlet and a cooling medium outlet configured to enable cooling medium flow through the upper cooling channel and the lower cooling channel.

This provides the advantage of efficient cooling. Cooling media can be guided by the inlet to flow through the cooling channels of the power modules to the outlet and thereby cool down the temperature of the semiconductor chips within the power modules.

The bottom cover plate may be formed analogously, i.e. having the same functionality:

The bottom cover plate may comprise a cooling medium inlet and a cooling medium outlet configured to enable cooling medium flow through the upper cooling channel and the lower cooling channel.

In an exemplary implementation of the semiconductor arrangement, a respective contact area of the top cover plate and the bottom cover plate with the second mold body comprises a metallization with a rough surface structure that enables a sealed connection between the respective contact area and the second mold body.

The rough surface structure of the metallization of top/bottom cover plate provides the same technical effect as described above with respect to the power module substrate with the second mold body, i.e., that the metallization of top/bottom cover plate comprise an undercut structure that can claw into the soft material of the second mold body, e.g. made of a thermoplastic. These sharp edges of the rough surface structure of the metallization of top/bottom cover plate clawing into the second mold body provide the tight or sealed connection by mechanic adhesion, e.g. in the manner of a Velcro fastener.

In an exemplary implementation of the semiconductor arrangement, the metallization of the respective contact area of the top cover plate and the bottom cover plate comprises an Aluminum metallization.

This provides the advantage that Aluminum is a very efficient thermal conductor which enables an efficient cooling of the semiconductor arrangement.

In an exemplary implementation of the semiconductor arrangement, the at least one power module comprises: a multi-layered upper substrate comprising an Aluminum surface forming the upper metal layer; and/or a multi-layered lower substrate comprising an Aluminum surface forming the lower metal layer.

This provides the advantage that the power module can be placed on a upper and/or lower substrate which is covered by a good thermal conductor which Aluminum surface provides for a good thermal dissipation.

In an exemplary implementation of the semiconductor arrangement, the multi-layered upper substrate and/or the multi-layered lower substrate comprise a ceramic layer between an Aluminum layer forming the Aluminum surface and a Copper or Aluminum layer.

This provides the advantage that the ceramic layer provides for a good electrical insulation and the roughened Aluminum surface provides for a good adhesion with the second mold body.

In an exemplary implementation of the semiconductor arrangement, the multi-layered upper substrate comprises a ceramic layer between an upper Copper layer and a lower Copper layer, wherein a bonded Aluminum layer is placed on the upper Copper layer, the bonded Aluminum layer forming the Aluminum surface of the upper metal layer.

The bonded Aluminum layer may be advantageously applied by bonding or alternatively foil can already be roughened prior o attachment, at least on the side towards the second mold body.

The multi-layered lower substrate may be formed analogously as the multi-layered upper substrate, i.e.: The multi-layered lower substrate may comprise a ceramic layer between an upper Copper layer and a lower Copper layer, wherein a bonded Aluminum layer may be placed on the lower Copper layer, the bonded Aluminum layer forming the Aluminum surface of the lower metal layer.

In an exemplary implementation of the semiconductor arrangement, the upper metal layer and/or the lower metal layer are covered by an adhesion layer.

This provides the advantage that adhesion between power module and second mold body can be improved when using such thin adhesion layer.

In an exemplary implementation of the semiconductor arrangement, the adhesion layer comprises an atomic layer deposited Aluminum Oxide layer.

This provides the advantage that the adhesion layer can be very thin.

The Aluminum Oxide layer may comprise an Al2O3 layer, for example.

In an exemplary implementation of the semiconductor arrangement, the adhesion layer covers the upper metal layer, the lower metal layer and the first mold body of the at least one power module.

This provides the advantage that the adhesion layer can seal the power module.

In an exemplary implementation of the semiconductor arrangement, the semiconductor arrangement comprises: a turbulence structure arranged within the upper cooling channel between the upper heat dissipation surface of the at least one power module and the top cover plate.

By using such a turbulence structure, cooling of the power modules can be efficiently realized. The turbulence of the cooling medium by the turbulence structure results in a similar junction temperatures and similar cooling conditions for all the semiconductor chips of the power modules.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure is clamped or jammed between the upper metal layer and the top cover plate.

This provides the advantage that the turbulence structure can be easily attached between the upper metal layer of the power modules and the top cover plate of the semiconductor arrangement.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure comprises a non-uniform turbulence structure.

This provides the advantage that the non-uniformity results in a better mixture of the cooling medium and a more uniform cooling of all semiconductor chips.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure is made of a compressible material.

This provides the advantage of an easy attachment of the turbulence structure and hence efficient production of the whole semiconductor arrangement.

The (upper) non-uniform turbulence structure may be arranged within the upper cooling channel above the upper heat dissipation surface of the at least one power module. The upper non-uniform turbulence structure may be formed to enable a non-uniform flow of cooling medium through the upper cooling channel to keep a junction temperature of all semiconductor chips of the at least one power module within a predefined temperature range.

A lower turbulence structure may be formed analogously to the upper turbulence structure:

The semiconductor arrangement may comprise a lower turbulence structure arranged within the lower cooling channel between the lower heat dissipation surface of the at least one power module and the bottom cover plate.

The lower turbulence structure may be clamped or jammed between the lower metal layer and the bottom cover plate.

The lower turbulence structure may comprise a non-uniform lower turbulence structure.

The lower turbulence structure may be made of a compressible material.

The lower non-uniform turbulence structure may be arranged within the lower cooling channel below the lower heat dissipation surface of the at least one power module. The lower non-uniform turbulence structure may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel to keep a junction temperature of all semiconductor chips of the at least one power module within a predefined temperature range.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure comprises a first block of rib structures designed according to a first geometry and a second block of rib structures designed according to a second geometry.

This provides the advantage that the non-uniformity can be easily implemented by forming two different geometries of rib structures.

In an exemplary implementation of the semiconductor arrangement, the rib structures of the first block and the rib structures of the second block are arranged in rows, wherein a number of rows is different for the first block and the second block.

This provides the advantage that the different number of rows results in a non-homogeneous flow of cooling medium resulting in an efficient cooling.

In an exemplary implementation of the semiconductor arrangement, a length of the rib structures is different for the first block and the second block.

This provides the advantage that the different length of the rib structures results in a non-homogeneous flow of cooling medium resulting in an efficient cooling.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure is formed as an insert clamped between the upper heat dissipation surface of the at least one power module and the top cover plate.

This provides the advantage that the insert can be easily clamped within the semiconductor arrangement.

In an exemplary implementation of the semiconductor arrangement, the insert is made of Aluminum.

This provides the advantage of a good thermal dissipation due to Aluminum.

In an exemplary implementation of the semiconductor arrangement, the bonded Aluminum layer comprises a turbulence structure.

This provides the advantage that the turbulence structure can be directly provided at the bonded Aluminum layer. The bonded Aluminum layer can have a roughened structure for a good adhesion with the substrate of the power module and at the same time have the turbulence structure at its reverse side for an efficient thermal dissipation.

In an exemplary implementation of the semiconductor arrangement, the turbulence structure comprises a first block of fins or pins designed according to a first geometry and a second block of fins or pins designed according to a second geometry.

This provides the advantage that the non-uniformity can be easily implemented by forming two different geometries of fin or pin structures.

The turbulence structure may be arranged within the upper cooling channel above the bonded Aluminum layer that forms the upper heat dissipation surface of the at least one power module. The turbulence structure may be formed to enable a non-uniform flow of cooling medium through the upper cooling channel to keep a junction temperature of all semiconductor chips of the at least one power module within a predefined temperature range.

A lower turbulence structure may be formed analogously to the (upper) turbulence structure as described above: This lower turbulence structure may be arranged within the lower cooling channel below the bonded Aluminum layer that forms the lower heat dissipation surface of the at least one power module. The lower turbulence structure may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel to keep a junction temperature of all semiconductor chips of the at least one power module within a predefined temperature range.

According to a second aspect, the disclosure relates to a method for producing a semiconductor arrangement, the method comprising: forming at least one power module for electric power conversion, the at least one power module comprising a first module side and a second module side opposing the first module side; the forming of the at least one power module comprising: arranging a first mold body between the first module side and the second module side of the at least one power module; embedding at least one semiconductor chip within the first mold body; arranging an upper metal layer at the first module side, the upper metal layer forming an upper heat dissipation surface of the at least one power module; arranging a lower metal layer at the second module side, the lower metal layer forming a lower heat dissipation surface of the at least one power module; forming a second mold body comprising a first body side and a second body side opposing the first body side, the second mold body encapsulating the at least one power module; forming an upper cavity in the second mold body above the upper metal layer to form an upper cooling channel; and forming a lower cavity in the second mold body below the lower metal layer to form a lower cooling channel, wherein a respective contact area of the upper metal layer and the lower metal layer with the second mold body comprises a rough surface structure that enables a sealed connection between the respective contact area and the second mold body.

Such a method provides the advantage that the semiconductor arrangement can be easily produced.

The advantages of the method are the same as those for the corresponding implementation forms of the semiconductor arrangement and vice versa.

According to a third aspect, the disclosure relates to a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the method according to the second aspect described above.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 100;

Fig. 2 shows a 3-dimensional view of an exemplary semiconductor arrangement 200 with a second mold body 120, the semiconductor arrangement 200 including an exemplary number of three power modules 110;

Fig. 3 shows a 3-dimensional view of the semiconductor arrangement 200 with top cover plate 130 mounted on the second mold body 120;

Fig. 4 shows a 3-dimensional view of an exemplary power module 110 including a chip arrangement with an exemplary number of 12 semiconductor chips 112;

Fig. 5 shows a 3-dimensional view of the first module side 111a of the power module 110 embedded in a mold body 113;

Fig. 6 shows a 3-dimensional view of three power modules 110 arranged in a row to be embedded in the second mold body 120;

Fig. 7 shows a schematic diagram illustrating a cross section of the semiconductor arrangement 100 designed according to a first adhesion variant;

Fig. 8 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 800 designed according to a second adhesion variant;

Fig. 9 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 900 designed according to a third adhesion variant;

Fig. 10a shows a sectional view of the semiconductor arrangement 200 with second mold body 120 and three power modules 110;

Fig. 10b shows a sectional view of the semiconductor arrangement 200 with embedded turbulence structures 1001 and non-mounted top cover and

bottom plates

130, 140;

Fig. 10c shows a sectional view of the semiconductor arrangement 200 with embedded turbulence structures 1001 and mounted top and

bottom plates

130, 140;

Fig. 11a shows a 3-dimensional view of the semiconductor arrangement 200 with second mold body 120 and mounted top and

bottom plates

130, 140;

Fig. 11b shows a sectional view of the semiconductor arrangement 200 with cooling medium 1100 flowing through the upper 122a and lower 122b cooling channels and the turbulence structures 1001;

Fig. 12 shows a 3-dimensional view of a cooling plate 1200 including a metal layer 1210 with

exemplary turbulence structures

1201, 1202;

Fig. 13 shows a 3-dimensional view of the semiconductor arrangement 200 with

turbulence structures

1201, 1202 mounted on the power modules 110;

Fig. 14 shows a 3-dimensional view of the semiconductor arrangement 200 with an exemplary position of the chips 112 within the complete arrangement; and

Fig. 15 shows a 3-dimensional view of an exemplary cooling plate 1500 mounted on the power modules 110 to form the semiconductor arrangement 200.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

The semiconductor arrangements, devices and systems described herein may, for example, be implemented in automotive, industrial or consumer electronic applications, e.g. for driving loads, converting power, etc. However, the semiconductor arrangements, devices and systems described herein may also be implemented in wireless communication schemes, e.g. communication schemes according to 5G or WiFi, e.g. for Internet of Things, etc. The described semiconductor arrangements, devices and systems may include integrated circuits and/or power semiconductors and may be manufactured according to various technologies. For example, the semiconductor arrangements, devices and systems may be utilized in power and/or logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, etc.

In this disclosure, double side cooling (DSC) packages are described although the concepts of this disclosure can also be applied to single side cooling (SSC) packages. The single side cooling (SSC) package is covered with an insulating mold. Therefore, the heat dissipation path of the package is mainly its bottom (e.g. drain or collector) side cooling plate. On the other side, the double side cooling (DSC) package has a top (e.g. source or emitter) side cooling plate in addition to the bottom side plate. These cooling plates contribute in reducing the thermal resistance. As heat is removed from both, the top and bottom surfaces, a double side cooling package utilizes the heat sink efficiently. These double side cooling packages are designed for high-efficient cooling to achieve the highest level of energy that can be switched with such a system.

In this disclosure, power modules with semiconductor chips are described. These power modules may include MOSFET transistors or IGBTs, for example. The power modules may be produces based on Silicon-Nitride semiconductor technology or Silicon semiconductor technology.

Fig. 1 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 100.

The semiconductor arrangement 100 comprises at least one power module 110 for electric power conversion, the at least one power module comprising a first module side 111a and a second module side 111b opposing the first module side 111a. A first mold body 113 is arranged between the first module side 111a and the second module side 111b.

In this schematic diagram only a single power module 110 is visible. However, the semiconductor arrangement 100 may include any number of power modules, for example a number of three power modules 110 as shown in Figures 2, 3 and 6.

The semiconductor arrangement 100 comprises at least one semiconductor chip 112 which is embedded within the first mold body 113.

In this schematic diagram only a single semiconductor chip 112 is visible. However, the semiconductor arrangement 100 may include any number of semiconductor chips 112, for example a number of twelve semiconductor chips 112 per power module 110 as shown in Figures 4 and 14.

The first module side 111a comprises an upper metal layer 114a forming an upper heat dissipation surface of the at least one power module 110. The second module side 111b comprises a lower metal layer 114b forming a lower heat dissipation surface of the at least one power module 110.

The semiconductor arrangement 100 comprises a second mold body 120 comprising a first body side 121a and a second body side 121b opposing the first body side 121a. The second mold body 120 is encapsulating the at least one power module 110.

An upper cavity 122a is formed in the second mold body 120 above the upper metal layer 114a to form an upper cooling channel 122a. A lower cavity 122b is formed in the second mold body 120 below the lower metal layer 114b to form a lower cooling channel 122b.

A

respective contact area

124a, 124b of the upper metal layer 114a and the lower metal layer 114b with the second mold body 120 comprises a rough surface structure that enables a sealed connection between the

respective contact area

124a, 124b and the second mold body 120.

A hole 123 (not shown in Figure 1 but in Figure 2) may be formed in the second mold body 120. The upper cooling channel 122a and the lower cooling channel 122b may be fluidly connected, and the upper cooling channel 122a and the lower cooling channel 122b may be formed to enable a flow of cooling medium through the upper cooling channel 122a and the lower cooling channel 122b.

The semiconductor arrangement 100 may comprise a top cover plate 130 covering the first body side 121a of the second mold body 120 and the upper cavity 122a.

The semiconductor arrangement 100 may comprise a bottom cover plate 140 covering the second body side 121b of the second mold body 120 and the lower cavity 122b.

The top cover plate 130 may comprise a cooling medium inlet 131a and a cooling medium outlet 131b which may be configured to enable cooling medium flow through the upper cooling channel 122a and the lower cooling channel 122b.

The bottom cover plate 140 may be formed analogously, i.e. having the same functionality:

The bottom cover plate 140 may comprise a cooling medium inlet and a cooling medium outlet configured to enable cooling medium flow through the upper cooling channel 122a and the lower cooling channel 122b.

A

respective contact area

125a, 125b of the top cover plate 130 and the bottom cover plate 140 with the second mold body 130 may comprise a metallization with a rough surface structure that enables a sealed connection between the

respective contact area

125a, 125b and the second mold body 120.

The rough surface structure of the metallization of top/bottom cover plate provides the same technical effect as described above for the

contact areas

124a, 124b, i.e., that the metallization of top/bottom cover plate comprise an undercut structure that can claw into the soft material of the second mold body, e.g. made of a thermoplastic. These sharp edges of the rough surface structure of the metallization of top/bottom cover plate clawing into the second mold body provide the tight or sealed connection by mechanic adhesion, e.g. in the manner of a Velcro fastener.

The metallization of the

respective contact area

125a, 125b of the top cover plate 130 and the bottom cover plate 140 may comprise an Aluminum metallization, for example.

The at least one power module 110 may comprise: a multi-layered upper substrate 115 comprising an Aluminum surface forming the upper metal layer 114a.

The at least one power module 110 may comprise a multi-layered lower substrate 116 comprising an Aluminum surface forming the lower metal layer 114b.

The multi-layered upper substrate 115 and/or the multi-layered lower substrate 116 may comprise a

ceramic layer

115b, 116b between an

Aluminum layer

115a, 116a forming the Aluminum surface and a Copper or

Aluminum layer

115c, 116c, e.g. as shown in Figure 7.

The multi-layered upper substrate 115 may comprise a

ceramic layer

815b, 816b between an

upper Copper layer

815a, 816c and a

lower Copper layer

815c, 816a, e.g. as shown in Figure 8. A bonded Aluminum layer 810 may be placed on the upper Copper layer 815a. This bonded Aluminum layer 810 may form the Aluminum surface of the upper metal layer 114a, e.g. as shown in Figure 8.

The multi-layered lower substrate 116 may be formed analogously as the multi-layered upper substrate 115, i.e.: The multi-layered lower substrate 116 may comprise a ceramic layer 816b between an upper Copper layer 816c and a lower Copper layer 816a, wherein a bonded Aluminum layer 820 may be placed on the lower Copper layer 816a, the bonded Aluminum layer 820 forming the Aluminum surface of the lower metal layer 114b, e.g. as shown in Figure 8.

The upper metal layer 114a and/or the lower metal layer 114b may be covered by an

adhesion layer

910, 920, respectively, e.g. as shown in Figure 9.

The

adhesion layer

910, 920 may comprise an atomic layer deposited Aluminum Oxide layer.

The Aluminum Oxide layer may comprise an Al2O3 layer, for example.

The

adhesion layer

910, 920 as shown in Figure 9 may cover the upper metal layer 114a, the lower metal layer 114b and the first mold body 113 of the at least one power module 110.

The semiconductor arrangement 100 may comprise a turbulence structure 1001 arranged within the upper cooling channel 122a between the upper heat dissipation surface of the at least one power module 110 and the top cover plate 130, e.g. as shown in Figures 10b and 10c.

The turbulence structure 1001 may be clamped or jammed between the upper metal layer 114a and the top cover plate 130.

The turbulence structure 1001 may comprise a

non-uniform turbulence structure

1201, 1202, e.g. as shown in Figure 12.

The turbulence structure 1001 may be made of a compressible material.

The (upper) non-uniform turbulence structure may be arranged within the upper cooling channel 122a above the upper heat dissipation surface of the at least one power module 110. The upper non-uniform turbulence structure may be formed to enable a non-uniform flow of cooling medium through the upper cooling channel 122a to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

A lower turbulence structure may be formed analogously to the upper turbulence structure. I.e., the semiconductor arrangement 100 may comprise a lower turbulence structure arranged within the lower cooling channel 122b between the lower heat dissipation surface of the at least one power module 110 and the bottom cover plate 140. The lower turbulence structure may be clamped or jammed between the lower metal layer 114b and the bottom cover plate 140. The lower turbulence structure may comprise a non-uniform lower turbulence structure. The lower turbulence structure may be made of a compressible material. The lower non-uniform turbulence structure may be arranged within the lower cooling channel 122b below the lower heat dissipation surface of the at least one power module 110. The lower non-uniform turbulence structure may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel 122b to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

The turbulence structure 1001 may comprises a first block of rib structures 1201 designed according to a first geometry and a second block of rib structures 1202 designed according to a second geometry, e.g. as shown in Figure 12.

The rib structures of the first block 1201 and the rib structures of the second block 1202 may be arranged in rows. A number of rows can be different for the first block 1201 and the second block 1202.

A length of the rib structures may be different for the first block 1201 and the second block 1202.

The turbulence structure 1001 may be formed as an insert clamped between the upper heat dissipation surface of the at least one power module 110 and the top cover plate 130, e.g. as shown in Figure 13.

The insert may be made of Aluminum.

The bonded

Aluminum layer

810, 820 shown in Figure 8 may comprise a turbulence structure 1500, e.g. as shown in Figure 15.

This turbulence structure 1500 may comprise a non-uniform turbulence structure, e.g. as shown in Figure 15.

For example, the turbulence structure 1500 may comprise a first block of fins or pins 1501 designed according to a first geometry and a second block of fins or pins 1502 designed according to a second geometry, e.g. as shown in Figure 15.

The turbulence structure 1500 may be arranged within the upper cooling channel 122a above the bonded Aluminum layer 810 (shown in Figure 8) that forms the upper heat dissipation surface of the at least one power module 110. The turbulence structure 1500 may be formed to enable a non-uniform flow of cooling medium through the upper cooling channel 122a to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

A lower turbulence structure 1500 may be formed analogously to the (upper) turbulence structure 1500 as described above and shown in Figure 15. I.e., this lower turbulence structure may be arranged within the lower cooling channel 122b below the bonded Aluminum layer 820 (shown in Figure 8) that forms the lower heat dissipation surface of the at least one power module 110. The lower turbulence structure 1500 may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel 122b to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

Fig. 2 shows a 3-dimensional view of an exemplary semiconductor arrangement 200 with a second mold body 120, the semiconductor arrangement 200 including an exemplary number of three power modules 110.

The three power modules 110 are embedded in the second mold body 120 according to the schematic representation of Figure 1. An exemplary number of two holes 123 that may be through-holes are placed in the second mold body 120 to provide an input and output for the cooling medium. The power modules 110 include a lead frame 117 for externally connecting the semiconductor chips 112 of the power modules 110.

The second mold body 120 can be applied, for example, by a so called transfer molding process. In this process, the power modules 110 may be clamped in a mold chase forming the area around the module (negative shape of second mold body) . The second mold body 120 may consist either of a duroplast material or a thermoplastic material which can be transferred under temperature and pressure in the cavities of the mold chase. This can be performed in such a way that the three power modules 110 are fixed together and flow areas, i.e. the upper cooling channel 122a and the lower cooling channel 122b as shown in Figure 1, on each side of the double side cooled modules 110 are formed. The shape can be chosen in such way that the

flow channels

122a, 122b have access to one inlet and one outlet point 123, for example. Of course, more than one inlet and more than one outlets may be implemented in the second mold body 120.

The shape can also be chosen in such manner that the cooling areas of the outer cooler areas of the module (top and bottom) , i.e. upper metal layer 114a and lower metal layer 114b as shown in Figure 1, have access to the cooling medium. The cooling medium may comprise of a water and glycol mixture, for example in a relation of 1: 1.

The outer Cu areas may be covered with additional layer (e.g. Nickel) to prevent base Cu material from corrosion and those layers are usually not the nest layer for adhesion (e.g. forming of Nickel Oxide) .

In order to ensure reliable adhesion within the whole system the adhesion concept as described in this disclosure is not based on pure chemical adhesion but based on mechanical adhesion. This new adhesion concept affects the construction of the power module 110 as well as the construction of the second mold body 120. The new concept of mechanical adhesion is based on the insight that a highly efficient adhesion can be reached by pressing a roughened Aluminum surface into a softened thermoplastic material.

Fig. 3 shows a 3-dimensional view of the semiconductor arrangement 200 with top cover plate 130 mounted on the second mold body 120.

In this representation of the semiconductor arrangement 200, the top cover plate 130 and the bottom cover plate 140 are mounted on the second mold body 120 shown in Figure 2. One inlet 131a and one outlet 131b for the cooling medium is placed above the hole 123 of the second mold body 120 as shown in Figure 2, respectively. Of course, there may be more than one inlet 131a and one outlet 131b. In another implementation, the inlet 131a and the outlet 131b may be placed at different sides of the semiconductor arrangement 200, for example inlet 131a in the top cover plate 130 and outlet 131b in the bottom cover plate 140 or vice versa.

Fig. 4 shows a 3-dimensional view of an exemplary power module 110 including a chip arrangement with an exemplary number of 12 semiconductor chips 112.

The chips may be placed on a bottom substrate 116, e.g. a printed circuit board. The bottom substrate 116 may comprise a multi-layer substrate, e.g. Cupper-ceramic-Cupper layers. A number of spacers 401 may be placed on the multi-layer bottom substrate 116. A lead frame 117 may connect the semiconductor chips 112 to external.

The power module 110 with all or at least a part of its semiconductor chips 112 may form a switching circuit, e.g. comprising a first switch and a second switch connected in series. The first switch may be connected between a first terminal P and a third terminal AC. The second switch may be connected between a second terminal N and the third terminal AC. For example, the switching circuit may switch a DC voltage between first and second terminals P and N to an AC voltage at the third terminal AC. The first switch may implement a high-side switch, for example. The second switch may implement a low-side switch, for example. Both switches may implement a half bridge or part of a full H-bridge.

The first switch may be implemented by a field effect transistor (FET) having a drain terminal, a source terminal and a gate terminal and a diode connected in parallel to the FET. Alternatively, an insulated gate bipolar transistor (IGBT) may be used instead of the FET.

Fig. 5 shows a 3-dimensional view of the first module side 111a of the power module 110 embedded in a mold body 113. In this view, the outer cooling area 111a of top substrate 115 can be seen. The semiconductor chips 112 shown in Figure 4 are embedded in the mold body 113 of the power module 110. A leadframe 117 as shown in Figure 1 is arranged on both sides of the power module 100. One AC pin 117a is arranged on one side of the power module 110 together with other pins 117b. Three other AC pins 117a are arranged on the opposite side of the power module 110.

As described above, the power module 110 may form a switching circuit, e.g. comprising a first switch and a second switch connected in series. The first switch may be connected between any of the leadframe pins 117a. The second switch may be connected between any of the leadframe pins 117a.

Fig. 6 shows a 3-dimensional view of three power modules 110 arranged in a row to be embedded in the second mold body 120.

This row of three power modules 110 may be embedded in the second mold body 120 and covered by top cover plate 130 and bottom cover plate 140 to form the

semiconductor arrangement

100, 200 as shown in Figures 1 to 3.

Fig. 7 shows a schematic diagram illustrating a cross section of the semiconductor arrangement 100 designed according to a first adhesion variant. This semiconductor arrangement 100 corresponds to the semiconductor arrangement described above with respect to Figure 1.

The at least one power module 110 may comprise a multi-layered upper substrate 115 comprising an Aluminum surface forming the upper metal layer 114a. The at least one power module 110 may comprise a multi-layered lower substrate 116 comprising an Aluminum surface forming the lower metal layer 114b.

ceramic layer

115b, 116b between an

Aluminum layer

115a, 116a forming the Aluminum surface and a Copper or

Aluminum layer

115c, 116c.

The straight forward approach for the adhesion promotion is to have roughened Aluminum surfaces 701 on all

crucial interfaces

124a, 134b, 125a, 125b. This means that not only the two

cover plates

130, 140 are made of Aluminum which has seen chemical roughening process, but also the two outer

heat spreading areas

115, 116 of the power module 110. This can be achieved, for example, by using substrates with Aluminum surface, e.g. using a so called direct bonded Aluminum (DBA) as substrate.

A derivate of this variant can be a hybrid substrate with Aluminum on the outer layer (to be roughened for adhesion and inert per default towards corrosion caused by the cooling liquid) and Cu (Copper) on the inner side, which results in excellent thermal and electrical conductivity.

Fig. 8 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 800 designed according to a second adhesion variant. This semiconductor arrangement 800 may correspond to the semiconductor arrangement 100 described above with respect to Figure 1 with some changes in the structure as described below.

The multi-layered upper substrate 115 may comprise a

ceramic layer

815b, 816b between an

upper Copper layer

815a, 816c and a

lower Copper layer

815c, 816a. A bonded Aluminum layer 810 may be placed on the upper Copper layer 815a. This bonded Aluminum layer 810 may form the Aluminum surface of the upper metal layer 114a.

The multi-layered lower substrate 116 may be formed analogously as the multi-layered upper substrate 115, i.e.: The multi-layered lower substrate 116 may comprise a ceramic layer 816b between an upper Copper layer 816c and a lower Copper layer 816a, wherein a bonded Aluminum layer 820 may be placed on the lower Copper layer 816a, the bonded Aluminum layer 820 forming the Aluminum surface of the lower metal layer 114b.

The semiconductor arrangement 800 is an efficient alternative to the semiconductor arrangement 100 described above. A DSC module may be used and then an Aluminum foil can be applied towards the outer cooler area of the module, e.g. by bonding or ultra-sonic welding. After the foil is attached it can be roughened or the foil is already roughened prior to the attachment, at least on the side towards the second mold body.

Fig. 9 shows a schematic diagram illustrating a cross section of an exemplary semiconductor arrangement 900 designed according to a third adhesion variant. This semiconductor arrangement 900 may correspond to the semiconductor arrangement 100 described above with respect to Figure 1 with some changes in the structure as described below.

adhesion layer

910, 920 as shown in Figure 9. The

adhesion layer

910, 920 may comprise an atomic layer deposited Aluminum Oxide layer. The Aluminum Oxide layer may comprise an Al2O3 layer, for example.

The

adhesion layer

910, 920 may cover the upper metal layer 114a, the lower metal layer 114b and the first mold body 113 of the at least one power module 110.

In this third adhesion variant, an

adhesion layer

910, 920 such as a thin Al2O3 layer, e.g. by ALD (atomic layer deposition) can be deposited. The

adhesion layer

910, 920 can be roughened by cooking in distilled water so that dendrites are growing on top of this layer.

The complete module 110 can be covered. This

nonconductive layer

910, 920 also improves the adhesion of the power module mold body 113 towards the second mold body 120. This third variant can be combined with the above described first and second variants in order to upgrade the mold body 113 towards the second mold body 120.

Fig. 10a shows a sectional view of the semiconductor arrangement 200 with second mold body 120 and three power modules 110. The semiconductor arrangement 200 may correspond to the semiconductor arrangement 200 as described above with respect to Figures 2 to 9.

With the upgraded power modules 110 and upgraded covers the semiconductor arrangement 200 is constructed and mounted. The second mold body 120 can be formed by a thermoplastic material around the three power modules 110 forming a carrier structure, the cooling channels on top and bottom and the guidance towards single inlet and single outlet point. The partly overlap of the second mold body 120 towards to the roughened Aluminum on the top and bottom cooler area ensures a long lasting and reliable adhesion and therefore proper isolation of the contact area between the power modules 110 and the second mold body 120.

bottom plates

130, 140.

The semiconductor arrangement 200 may comprise a turbulence structure 1001 arranged within the upper cooling channel 122a between the upper heat dissipation surface of the at least one power module 110 and the top cover plate 130. The turbulence structure 1001 may be clamped or jammed between the upper metal layer 114a and the top cover plate 130. The turbulence structure 1001 may comprise a

non-uniform turbulence structure

1201, 1202, e.g. as shown in Figure 12. The turbulence structure 1001 may be made of a compressible material.

A lower turbulence structure may be formed analogously to the upper turbulence structure 1001. I.e., the semiconductor arrangement 200 may comprise a lower turbulence structure 1001 arranged within the lower cooling channel 122b between the lower heat dissipation surface of the at least one power module 110 and the bottom cover plate 140. The lower turbulence structure may be clamped or jammed between the lower metal layer 114b and the bottom cover plate 140. The lower turbulence structure may comprise a non-uniform lower turbulence structure. The lower turbulence structure may be made of a compressible material. The lower non-uniform turbulence structure may be arranged within the lower cooling channel 122b below the lower heat dissipation surface of the at least one power module 110. The lower non-uniform turbulence structure may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel 122b to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

bottom plates

130, 140.

The semiconductor arrangement 200 shown in Fig. 10c is produced by pressing the top and cover plates with their roughened side towards the second mold body 120. By heating the top and cover plates the thermoplastic of the second mold body 120 is locally melting and the covers can interlock with the second mold body 120. Thus, a long lasting and reliable adhesion and therefore proper isolation between the covers and the second mold body 120 can be achieved.

Prior to this step the turbulence structure 1001, e.g. made of aluminum can be placed on the cooler areas of power modules and clamped between the cooler areas of the module and the covers.

bottom plates

130, 140. The semiconductor arrangement 200 may correspond to the semiconductor arrangement 200 described above with respect to Figure 10c.

As described above, the turbulence structure 1001 (not seen in this external 3-dimensioinal view) , e.g. made of aluminum, is arranged on the cooler areas of the power modules 110 and clamped between the cooler areas of the module and the covers.

Fig. 11b shows a sectional view of the semiconductor arrangement 200 with cooling medium 1100 flowing through the upper 122a and lower 122b cooling channels and the turbulence structures 1001. The semiconductor arrangement 200 may correspond to the semiconductor arrangement 200 described above with respect to Figure 10c.

The cooling medium 1100 (e.g. water) flows through from the inlet 131a via upper cooling channel 122a and lower cooling channel 122b to the outlet 131b. The cooling medium flow is separated into two partial flows passing the upper cooling channel 122a and the lower cooling channel 122b, respectively.

As seen in Figure 11b, the cooler can be equipped with one water inlet 131a and one water outlet 131b and the flow inside the cooler is shown in Figure 11b, where half of the cooling water 1100 may be used for cooling the top side of the module 110 and half of the cooling water may be used for cooling the bottom side of the module 110. Of course, the water can also be guided via another ratio, e.g. a third of the water flowing through the upper cooling channel and two thirds of the water flowing through the lower cooling channel or any other relation of water flow may be used as well.

exemplary turbulence structures

1201, 1202.

The

semiconductor arrangement

100, 200 as described above may comprise a turbulence structure 1200 that may correspond to the turbulence structure 1001 described above with respect to Figures 10 and 11. The turbulence structure 1200 may be arranged within the upper cooling channel 122a between the upper heat dissipation surface of the at least one power module 110 and the top cover plate 130, e.g. as shown in Figures 10b and 10c.

The turbulence structure 1200 may be clamped or jammed between the upper metal layer 114a and the top cover plate 130, e.g. a shown in Figure 10c.

The turbulence structure 1200 may comprise a

non-uniform turbulence structure

1201, 1202.

The turbulence structure 1200 may be made of a compressible material.

The (upper) non-uniform turbulence structure 1200 may be arranged within the upper cooling channel 122a above the upper heat dissipation surface of the at least one power module 110. The upper non-uniform turbulence structure 1200 may be formed to enable a non-uniform flow of cooling medium through the upper cooling channel 122a to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

A lower turbulence structure 1200 may be formed analogously to the upper turbulence structure 1200. I.e., the semiconductor arrangement 100 may comprise a lower turbulence structure 1200 arranged within the lower cooling channel 122b between the lower heat dissipation surface of the at least one power module 110 and the bottom cover plate 140. The lower turbulence structure 1200 may be clamped or jammed between the lower metal layer 114b and the bottom cover plate 140. The lower turbulence structure may comprise a non-uniform

lower turbulence structure

1201, 1202. The lower turbulence structure 1200 may be made of a compressible material. The lower non-uniform turbulence structure 1200 may be arranged within the lower cooling channel 122b below the lower heat dissipation surface of the at least one power module 110. The lower non-uniform turbulence structure 1200 may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel 122b to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

The turbulence structure 1200 may comprises a first block of rib structures 1201 designed according to a first geometry and a second block of rib structures 1202 designed according to a second geometry. For example, the

ribs

1201, 1202 may be corrugated and formed as squares or triangles or sine-waves or any other geometry. The first geometry is different from the second geometry.

The turbulence structure 1200 may be formed as an insert clamped between the upper heat dissipation surface of the at least one power module 110 and the top cover plate 130. For example, the insert may be made of Aluminum.

The ideal case within an inverter system is that all chips do run at similar junction temperature which does correspond with even current flow through the 3 modules 110 and vice versa. As the modules 110 dissipate most of their heat towards the bottom of the module 110 and the cooling water temperature is increasing from module to module the chip temperatures will increase from module to module.

An excellent counter measure are non-uniform turbulence structures 1200 as shown in Figure 12 which influence the contact area from the module to the turbulence structure 1200, the spreading area from the turbulence structure 1200 towards the cooling water and the speed of the cooling water.

The usage of independent inserts made of aluminum may be implemented. The inserts can be quite easily produced, e.g. by stamping and may be clamped between the cooler areas of the module 110 and the

cover plate

130, 140. The clamping can be ensured by the geometry of the turbulence structures 1200, since the covers sink (or move) a little bit into the second mold body 120 when they are hot pressed.

Fig. 13 shows a 3-dimensional view of the semiconductor arrangement 200 with

turbulence structures

1201, 1202 mounted on the power modules 110. The semiconductor arrangement 200 may correspond to the semiconductor arrangement 200 shown in Figures 2 to 4 in which turbulence structures 1200 are placed as described above with respect to Figures 10 and 11.

The non-uniform turbulence structures 1200 may be present on the complete area of the cooler areas or only above the chips underneath. The geometries of the blocks of

rib structures

1201, 1202 may be different for the first power module 110, the second power module 110 and the third power module 110 and may be also different for top and bottom cooler area. The geometry of the second mold body 120 may be non-uniform on the inlet and outlet or on top and bottom.

Fig. 14 shows a 3-dimensional view of the semiconductor arrangement 200 with an exemplary position of the chips 112 within the complete arrangement.

The semiconductor arrangement 200 comprises an exemplary number of three power modules 110, each power module 110 comprising an exemplary number of twelve semiconductor chips 112.

Simulations have shown that by using such an implementation with 3 power modules and 12 chips 112 per power module the chip to chip temperature can be maintained within a range of about 5 degrees Celsius even when all chips are running on full load (here 100 W per chip) . The pressure drop of the cooler can be maintained in a range of about 100 mbar.

A further advantage can be realized, i.e. lower junction temperatures at similar power dissipation and cooling conditions, when the module internal layers are made of sinter technology instead of solder technology.

Simulations have shown that sintered and soldered designs have quite similar temperature non-uniformity through various chips: -5.7 ℃ to 5.9 ℃, correspondingly. In the simulations, sintered design provides decreasing of maximum chip temperature by about 12℃, from 152℃ to 140℃ for the chip with the highest temperature. For the sintered design, a heat flow through bottom slightly decreases from around 64%to 61%of the total heat flow.

The bonded

Aluminum layer

810, 820 shown in Figure 8 may comprise a turbulence structure 1500 as shown in Figure 15. This turbulence structure 1500 may comprise a non-uniform turbulence structure as shown in the left part of Figure 15.

The turbulence structure 1500 may comprise a first block of fins or pins 1501 designed according to a first geometry and a second block of fins or pins 1502 designed according to a second geometry. Both geometries may be different as shown in Figure 15.

A lower turbulence structure 1500 may be formed analogously to the (upper) turbulence structure 1500. I.e., this lower turbulence structure may be arranged within the lower cooling channel 122b below the bonded Aluminum layer 820 (shown in Figure 8) that forms the lower heat dissipation surface of the at least one power module 110. The lower turbulence structure 1500 may be formed to enable a non-uniform flow of cooling medium through the lower cooling channel 122b to keep a junction temperature of all semiconductor chips 112 of the at least one power module 110 within a predefined temperature range.

The aluminum foil to be attached with bonding or ultrasonic welding may already incorporate

turbulence structures

1501, 1502 as shown in Figure 15. Those structures may be designed in such manner to ensure sufficient contact area. The structures may have a fin or

pin structure distribution

1501, 1502 as shown in Figure 15.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include" , "have" , "with" , or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise" . Also, the terms "exemplary" , "for example" and "e.g. " are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected” , along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

A semiconductor arrangement (100) , comprising:

at least one power module (110) for electric power conversion, the at least one power module comprising a first module side (111a) and a second module side (111b) opposing the first module side (111a) , wherein a first mold body (113) is arranged between the first module side (111a) and the second module side (111b) ;

at least one semiconductor chip (112) which is embedded within the first mold body (113) ;

wherein the first module side (111a) comprises an upper metal layer (114a) forming an upper heat dissipation surface of the at least one power module (110) , and wherein the second module side (111b) comprises a lower metal layer (114b) forming a lower heat dissipation surface of the at least one power module (110) ; and

a second mold body (120) comprising a first body side (121a) and a second body side (121b) opposing the first body side (121a) , the second mold body (120) encapsulating the at least one power module (110) , wherein an upper cavity (122a) is formed in the second mold body (120) above the upper metal layer (114a) to form an upper cooling channel (122a) and wherein a lower cavity (122b) is formed in the second mold body (120) below the lower metal layer (114b) to form a lower cooling channel (122b) ,

wherein a respective contact area (124a, 124b) of the upper metal layer (114a) and the lower metal layer (114b) with the second mold body (120) comprises a rough surface structure that enables a sealed connection between the respective contact area (124a, 124b) and the second mold body (120) .
The semiconductor arrangement (100) of claim 1,

wherein a hole (123) is formed in the second mold body (120) , wherein the upper cooling channel (122a) and the lower cooling channel (122b) are fluidly connected, and wherein the upper cooling channel (122a) and the lower cooling channel (122b) are formed to enable a flow of cooling medium through the upper cooling channel (122a) and the lower cooling channel (122b) .
The semiconductor arrangement (100) of claim 1 or 2, comprising:

a top cover plate (130) covering the first body side (121a) of the second mold body (120) and the upper cavity (122a) ; and

a bottom cover plate (140) covering the second body side (121b) of the second mold body (120) and the lower cavity (122b) .
The semiconductor arrangement (100) of claim 3,

wherein the top cover plate (130) comprises a cooling medium inlet (131a) and a cooling medium outlet (131b) configured to enable cooling medium flow through the upper cooling channel (122a) and the lower cooling channel (122b) .
The semiconductor arrangement (100) of claim 3 or 4,

wherein a respective contact area (125a, 125b) of the top cover plate (130) and the bottom cover plate (140) with the second mold body (130) comprises a metallization with a rough surface structure that enables a sealed connection between the respective contact area (125a, 125b) and the second mold body (120) .
The semiconductor arrangement (100) of claim 5,

wherein the metallization of the respective contact area (125a, 125b) of the top cover plate (130) and the bottom cover plate (140) comprises an Aluminum metallization.
The semiconductor arrangement (100) of any of the preceding claims, wherein the at least one power module (110) comprises:

a multi-layered upper substrate (115) comprising an Aluminum surface forming the upper metal layer (114a) ; and/or

a multi-layered lower substrate (116) comprising an Aluminum surface forming the lower metal layer (114b) .
The semiconductor arrangement (100) of claim 7,

wherein the multi-layered upper substrate (115) and/or the multi-layered lower substrate (115) comprise a ceramic layer (115b) between an Aluminum layer (115a) forming the Aluminum surface and a Copper or Aluminum layer (115c) .
The semiconductor arrangement (100) of claim 7,

wherein the multi-layered upper substrate comprises a ceramic layer (815b) between an upper Copper layer (815a) and a lower Copper layer (815c) ,

wherein a bonded Aluminum layer (810) is placed on the upper Copper layer (815a) , the bonded Aluminum layer forming the Aluminum surface of the upper metal layer (114a) .
The semiconductor arrangement (100) of any of the preceding claims,

wherein the upper metal layer (114a) and/or the lower metal layer (114b) are covered by an adhesion layer (910, 920) .
The semiconductor arrangement (100) of claim 10,

wherein the adhesion layer (910, 920) comprises an atomic layer deposited Aluminum Oxide layer.
The semiconductor arrangement (100) of claim 10 or 11,

wherein the adhesion layer (910, 920) covers the upper metal layer (114a) , the lower metal layer (114b) and the first mold body (113) of the at least one power module (110) .
The semiconductor arrangement (100) of any of claims 3 to 6, comprising:

a turbulence structure (1001, 1200) arranged within the upper cooling channel (122a) between the upper heat dissipation surface of the at least one power module (110) and the top cover plate (130) .
The semiconductor arrangement (100) of claim 13,

wherein the turbulence structure (1001, 1200) is clamped or jammed between the upper metal layer (114a) and the top cover plate (130) .
The semiconductor arrangement (100) of claim 13 or 14,

wherein the turbulence structure (1001, 1200) comprises a non-uniform turbulence structure.
The semiconductor arrangement (100) of any of claims 13 to 15,

wherein the turbulence structure (1001, 1200) is made of a compressible material.
The semiconductor arrangement (100) of any of claims 13 to 16,

wherein the turbulence structure (1001, 1200) comprises a first block of rib structures (1201) designed according to a first geometry and a second block of rib structures (1202) designed according to a second geometry.
The semiconductor arrangement (100) of claim 17,

wherein the rib structures of the first block (1201) and the rib structures of the second block (1202) are arranged in rows, wherein a number of rows is different for the first block and the second block.
The semiconductor arrangement (100) of claim 17 or 18,

wherein a length of the rib structures is different for the first block (1201) and the second block (1202) .
The semiconductor arrangement (100) of any of claims 13 to 19,

wherein the turbulence structure (1001, 1200) is formed as an insert clamped between the upper heat dissipation surface of the at least one power module (110) and the top cover plate (130) .
The semiconductor arrangement (100) of claim 20,

wherein the insert is made of Aluminum.
The semiconductor arrangement (100) of claim 9,

wherein the bonded Aluminum layer comprises a turbulence structure.
The semiconductor arrangement (100) of claim 22,

wherein the turbulence structure comprises a non-uniform turbulence structure.
The semiconductor arrangement (100) of claim 22 or 23,

wherein the turbulence structure comprises a first block of fins or pins designed according to a first geometry and a second block of fins or pins designed according to a second geometry.