WO2022268358A1 - Procédé de fonctionnement d'un système d'entraînement, et système d'entraînement comprenant une pluralité d'onduleurs - Google Patents

Procédé de fonctionnement d'un système d'entraînement, et système d'entraînement comprenant une pluralité d'onduleurs Download PDF

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Publication number
WO2022268358A1
WO2022268358A1 PCT/EP2022/025258 EP2022025258W WO2022268358A1 WO 2022268358 A1 WO2022268358 A1 WO 2022268358A1 EP 2022025258 W EP2022025258 W EP 2022025258W WO 2022268358 A1 WO2022268358 A1 WO 2022268358A1
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WO
WIPO (PCT)
Prior art keywords
inverter
voltage
width modulation
inverters
pulse width
Prior art date
Application number
PCT/EP2022/025258
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German (de)
English (en)
Inventor
Georg Pfeiffer
Original Assignee
Sew-Eurodrive Gmbh & Co. Kg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sew-Eurodrive Gmbh & Co. Kg filed Critical Sew-Eurodrive Gmbh & Co. Kg
Priority to EP22733290.5A priority Critical patent/EP4360208A1/fr
Publication of WO2022268358A1 publication Critical patent/WO2022268358A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P5/00—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors
    • H02P5/74—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors controlling two or more ac dynamo-electric motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation

Definitions

  • the invention relates to a method for operating a drive system and a drive system having a plurality of inverters.
  • a method for controlling a voltage intermediate circuit is known from DE 102016 008 951 A1.
  • a method for operating an electric drive system is known from DE 102018210244 A1.
  • the invention is therefore based on the object of developing a drive system in which the service life is to be increased.
  • the object is achieved with the method according to the features specified in claim 1 and with the drive system according to the features specified in claim 12 .
  • the drive system has several, in particular more than two, inverters, in particular and a data bus, with a respective electric motor being fed from the AC voltage-side connection of the respective inverter, wherein the DC voltage-side connections of the respective inverters are connected in parallel to one another and this parallel circuit is connected to the DC voltage-side connection of a rectifier, in particular a controllable and/or regenerative rectifier, in particular by means of busbars, the respective inverter having respective semiconductor switches controlled according to a respective pulse width modulation, wherein the inverters are designed as bus users of a data bus to which a module designed as a master is also connected, in particular with the module comprising the rectifier, with each inverter being assigned a respective bus address in a first method step, in particular during initialization or commissioning of the drive system, and then, in a second method step, each inverter is given a time offset of the first switching edge, which is related to a synchronization
  • the advantage here is that the first switching edges take place at different points in time and the resulting leakage currents, which reduce the service life of the Y capacitors, are thus reduced. Thus, the service life is increased.
  • each inverter has half-bridges which are connected in parallel and are fed from the DC voltage and are each designed as a series connection of at least two controllable semiconductor switches, the semiconductor switches of the respective inverter being driven with pulse-width-modulated drive signals according to the pulse-width modulation of the inverter and their polarity.
  • the motor can be provided with the current voltage required for speed control or torque control.
  • the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed, in particular the upper switch being connected to the upper Potential of the voltage present at the DC voltage-side connection of the inverter is connected, and the lower switch is connected to the lower potential of the voltage present at the DC voltage-side connection of the inverter.
  • the inverters are arranged in a row along the data bus, with the first method step starting from the master, in particular successively, each inverter allocating a bus address to the inverter that follows it in the series until an inverter fails to allocate a further one bus address recognizes itself as the last in the series and then.
  • the advantage here is that central address assignment is possible. It is thus also possible for the master to transmit the start times, i.e. the respective time offsets to the time base, to the respective inverter. Before that, the master is able to optimally determine the time offsets. Instead of a master, however, a central controller can also be connected to the data bus and the address assignment can be carried out by this, as can the optimal determination of the time offsets mentioned and their transmission to the inverters designed as bus users.
  • the time offsets transmitted to the inverters of the drive system are regularly spaced from the synchronization signal, ie in particular are evenly distributed over the duration of a pulse width modulation period.
  • the advantage here is that the leakage currents triggered at the respective start time are distributed as evenly as possible and the load on the Y capacitors is therefore as low as possible, ie the service life is increased.
  • two of the inverters each form a pair and a respective time offset is assigned to the respective pair, with the polarity of the pulse width modulation of a first inverter in the pair being inverse to the polarity of the pulse width modulation of the other inverter in the pair, in particular with each pair having one of different time offsets are assigned to the other pairs associated time offsets.
  • the advantage here is that the two inverters in a pair may have the same time offset, but different polarity, so that the equalizing currents triggered by the individual inverters in the pair essentially cancel each other out.
  • the Y-capacitors are thus loaded as little as possible and the service life is therefore as long as possible.
  • the respective inverter l_i can provide a maximum power P_i to the electric motor M_i fed by this inverter l_i, with the time interval between the starting time t_i of the respective inverter l_i and increases strictly monotonously at the next starting point in time (t_i+1 and/or t_i-1) of another inverter (l_i+1 and/or l_i-1).
  • the advantage here is that in the case of inverters with different power ratings, the start times are distributed within a pulse width modulation period after the synchronization signal in such a way that the leakage currents, in particular the time integral of the leakage currents or their mean value formed over a pulse width modulation period, is as small as possible.
  • i runs through the numbers from 1 to n, where n is the number of inverters in the drive system.
  • the DC voltage is made available at the DC voltage-side connection of a mains-fed rectifier, in particular an AC/DC converter, in particular with the rectifier being supplied, in particular at its AC voltage-side connection, from an AC voltage network, in particular with three-phase voltage
  • the DC-side connection of the rectifier is connected in parallel to the DC-side connection of the first inverter and to the DC-side connection of the second inverter.
  • a mains filter is arranged on the AC voltage-side connection of the rectifier, in particular on the mains-side rectifier, which has Y-capacitors, in particular for interference suppression.
  • the pulse width modulation signals of the first inverter are asynchronous to the pulse width modulation signals of a second inverter, in particular they are not synchronized.
  • the advantage here is that a better distribution of the load over time can be achieved.
  • the pulse width modulation periods of the first and second inverters start asynchronously and/or not at the same time.
  • the advantage here is that the load from compensating currents, ie leakage currents, can be reduced.
  • the first switching edge of a control signal for an upper semiconductor switch of the first inverter is inverted within each pulse width modulation period and/or occurs inversely to the first switching edge of a control signal for an upper semiconductor switch of the second inverter.
  • one of the controllable semiconductor switches that is to say the upper semiconductor switch, of a respective half-bridge is connected to the upper potential of the DC voltage.
  • one of the controllable semiconductor switches that is to say the lower semiconductor switch, of a respective half-bridge is connected to the lower potential of the DC voltage.
  • the inverter is easy to produce.
  • the upper switch of a first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of a second half-bridge of the second inverter is closed and the lower switch of this second half-bridge of the second inverter open.
  • the polarity can be defined in a simple manner.
  • the synchronization signal in particular the synchronization signal having synchronization pulses, is modulated onto busbars which connect the DC voltage-side connections of the inverters to one another and to the DC voltage-side connection of the rectifier, or the synchronization signal, in particular the synchronization signal having synchronization pulses, is timed by the master as a broadcast telegram is sent recurrently to all inverters by means of the data bus, in particular the start times t_i of the pulse width modulation of the respective inverters l_i being delayed as a function of the synchronization signal as a time base by the respective time offset.
  • the advantage here is that the synchronization can be carried out without any particular effort.
  • the polarity of the pulse width modulation of a first of the inverters differs from the polarity of the pulse width modulation of a second of the inverters, in particular such that the pulse width modulation of the drive signals for the controllable semiconductor switches of the first of the inverters is clocked counter-synchronously to the pulse width modulation of the drive signals for the controllable semiconductor switches the second the inverter is running.
  • Y-capacitors are arranged on the DC voltage-side connection of the rectifier, on the AC voltage-side connection of the rectifier, on a mains filter connected to the AC voltage-side connection of the rectifier and/or on the electric motor.
  • connection of the inverters on the DC voltage side is connected in parallel.
  • the advantage here is that a single rectifier provides all inverters with a DC voltage.
  • only a single mains filter arranged on the mains side of the rectifier is necessary for the supply of all inverters.
  • a drive system with inverters (l_1, l_2, l_n) is shown schematically in FIG.
  • FIG. 1 A time-delayed operation of the inverters (L_1, L_2, L_n) of the drive system is shown schematically in FIG.
  • the drive system has inverters (l_1, l_2, l_n) whose DC voltage-side connection is connected in parallel to one another and is supplied from the DC voltage-side connection of a rectifier, which is connected to the AC voltage network AC at its AC voltage-side connection via a line filter.
  • connection of the rectifier on the DC voltage side makes a DC voltage available to each inverter (l_1, l_2, l_n) via a DC link busbar.
  • the connections on the DC side of the inverters (l_1, l_2, l_n) are connected in parallel for this purpose.
  • FIG. 1 the same representation is shown for the first inverter l_1 as for the second inverter l_2; however, these inverters can also be designed in different ways, in particular with different rated powers.
  • the mains filter (L_1, CY_2) has Y capacitors CY_2, in particular for interference suppression.
  • a respective electric motor M is fed from each AC voltage-side connection of the respective inverter (l_1, l_2, l_n), in particular with a respective three-phase voltage system provided by the respective inverter (l_1, l_2, l_n), the electric motors M preferably being designed as three-phase motors.
  • the supply lines of the respective electric motor are also provided with capacitors, in particular Y-capacitors, so that each phase line is connected to electrically ground via a respective capacitor (CS_1, CS_2, CS_n).
  • the respective electric motor M is also connected via a respective capacitor (CM_1,
  • CM_2, CM_n connected to electrical ground.
  • Each of the inverters (l_1, l_2, l_n) has three series circuits connected in parallel, each series circuit having two controllable semiconductor switches arranged in series. A respective phase voltage is thus made available to the electric motor at the connection node of the two controllable semiconductor switches of a respective series connection.
  • connection of the inverter on the AC voltage side is preferably three-phase, so that each inverter (l_1, l_2) has three of these series connections and thus three phase voltages are made available to the motor.
  • Each inverter (l_1, l_2) has an electronic circuit in the form of signal electronics, which generates pulse-width-modulated drive signals for the controllable semiconductor switches of the inverter (l_1, l_2).
  • the synchronization signal is transmitted to each of the inverters (l_1, l_2, l_n) from a central unit.
  • Each inverter (l_1, l_2, l_n) is assigned a respective time period (t1, t2, tn) at which the pulse width modulation period of its drive signals begins.
  • These time periods (t1, t2, tn) are either different or, if two of the inverters have the same time period, have different polarity. This means that the first switching edge of the upper controllable semiconductor switch of the first of the two inverters with the same time period is inverted to the first switching edge of the upper controllable semiconductor switch of the other of the two inverters with the same time period. In the case of these inverted control signals, the polarity of the pulse width modulated control signal is therefore different.
  • the advantage here is that compensating currents, in particular leakage currents, are reduced and the mains filter on the rectifier on the mains side, together with its Y capacitors, thus has a longer service life.
  • the period of time (t1, t2, tn) is therefore a time offset to a synchronization signal that serves as a time base for all inverters.
  • the first switching edges are different inverters arranged at different points in time. The exception to this is a respective pair of inverters whose pulse width modulation periods are synchronous in time but have different polarity.
  • Each electric motor M is supplied with a three-phase voltage system, ie with three phase voltages, by the respective inverter assigned to it.
  • the pulse width modulation ratio is specified within a respective pulse width modulation period in order to generate a respective phase voltage value by the first inverter l_1.
  • the lower semiconductor switch of the respective series circuit assigned to the respective phase voltage is closed and the upper semiconductor switch of this series circuit is opened.
  • connection for the phase voltage is connected to the lower potential of the DC voltage, ie the intermediate circuit voltage U_z.
  • the lower semiconductor switch is opened and the upper one is closed, so that the connection for the phase voltage is now connected to the upper potential of the DC voltage, with this lasting half the period.
  • the second inverter l_2 is operated with switching edges that are inverted relative to the first inverter l_1.
  • Figure 2 is an example
  • Pulse width modulation ratio of 50% selected.
  • the upper semiconductor switch of the series circuit is closed and the lower semiconductor switch of the series circuit is opened at the beginning of the pulse width modulation period.
  • the connection for the phase voltage of the second inverter 2 associated with this series connection is connected to the upper potential of the DC voltage, that is to say the intermediate circuit voltage U_z.
  • the upper semiconductor switch is opened and the lower one is closed, so that the connection for the phase voltage is now connected to the lower potential of the DC voltage, with this lasting half the period.
  • the respective switching edge is shifted to plus + or minus in time, i.e. shifted forward or backward in time within the pulse width modulation period.
  • the semiconductor switches of the half-bridge of the first inverter l_1 do not switch exactly at the same time as the half-bridge of the second inverter l_2 if a different pulse width modulation ratio is specified there.
  • compensating currents in the intermediate circuit ie between the DC voltage-side connections of the inverters (l_1, l_2), are at least reduced or even completely avoided.
  • This advantage according to the invention is particularly important if very long cables are used from the AC voltage-side connection of the respective inverter (l_1, l_2) to the respective electric motor. This is because the cables and motors then have high ground capacitances, so that a common mains filter, which is arranged on the mains-fed rectifier that makes the direct voltage available, is exposed to high leakage currents.
  • the pulse width modulation has a positive polarity. If the first switching edge jumps to the lower potential within the pulse width modulation period, the pulse width modulation has a negative polarity.
  • a synchronization signal SYNC is transmitted to both inverters (l_1, l_2).
  • the signal electronics of the first inverter l_1 is preferably connected to the signal electronics of the second inverter l_2 via a data bus connection.
  • this data bus connection is wired, in particular in a shielded cable.
  • the synchronization signal is modulated onto the DC voltage-side connection of the inverters (l_1, l_2), ie in particular onto the intermediate circuit connection or intermediate circuit busbar. Since the upper potential of the DC voltage-side connection of the first inverter l_1 is preferably connected to the upper potential of the DC voltage-side connection of the second inverter l_2 by means of is connected to a busbar in order to enable the passage of a strong current, the synchronization signal is therefore modulated onto the current present in the busbar.
  • the medium-frequency or high-frequency synchronization signal is coupled to the power rail in the first inverter l_1 via a capacitance; the signal is also decoupled in the second inverter l_2 via a capacitance.
  • an inductive and therefore safe and potential-free coupling and decoupling would be possible, but this leads to a higher effort.
  • this inversion of the polarity corresponds to a time offset by a fraction, in particular half or, in the case of a symmetrical method, a quarter of the pulse width modulation period T.
  • a respective time offset is assigned to further inverters.
  • Pairs of the inverters are thus preferably formed, with the pulse width modulation methods of the inverters of a respective pair having different, ie in particular inverted, polarity from one another.
  • Each pair and, in the case of an odd number of inverters, the remaining inverters that are not assigned to any pair are assigned a respective time offset.
  • These time offsets are not equal to each other. In particular, the time offsets do not only differ by half or a quarter of the pulse width modulation duration, so that the different time offset does not simply mean an inverted polarity.
  • the described inversion of the pulse width modulation signal in the second inverter 2 is only operated as long as the absolute value of the difference between the two pulse width modulation ratios is less than 50%. If this 50% is exceeded, the inversion is canceled and a synchronous pulse width modulation signal is used.
  • the quotient of the two pulse width modulation ratios can also be used as a criterion. If this quotient exceeds the amount 1, the inversion described above is applied and otherwise not.
  • the compensating currents can be reduced even if the operating points of the two inverters (l_1, l_2) are very different. This is the case, for example, when the first inverter l_1 generates a high phase voltage, i.e. in particular a potential close to the upper potential of the DC voltage, and the second inverter l_2 generates a low phase voltage, i.e. in particular a potential close to the lower potential of the DC voltage .
  • An example of a high phase voltage is 0.9 U_z and an example of a low phase voltage is 0.1 * U_z.
  • a second drive system has a data bus, via which a supply module designed as a master is connected to inverters for data exchange.
  • the supply module has a mains-fed rectifier, from the connection on the DC voltage side of which the named inverters are fed.
  • the DC-side connections of the inverters are connected in parallel to the DC-side connection of the rectifier.
  • the rectifier is designed to be regenerative, in particular as an AC/DC converter, which rectifies electrical power from the AC voltage supply network when the power of the drive system is predominantly motor and makes it available to the inverters on the DC voltage-side connection as intermediate circuit voltage, and when the power of the drive system is predominantly regenerative, electrical power from the DC voltage side Connection of the rectifier feeds back into the AC voltage network.
  • an AC/DC converter which rectifies electrical power from the AC voltage supply network when the power of the drive system is predominantly motor and makes it available to the inverters on the DC voltage-side connection as intermediate circuit voltage, and when the power of the drive system is predominantly regenerative, electrical power from the DC voltage side Connection of the rectifier feeds back into the AC voltage network.
  • the supply module designed as a master first assigns the bus addresses to the inverters designed as bus users and arranged serially with respect to the data bus.
  • the master assigns a first bus address to the first inverter in the serial arrangement, viewed from the master.
  • the master a Generates a voltage signal that signals to the first inverter, i.e. one that is directly connected to an electrical line, that it takes over the bus address contained in the next broadcast telegram sent by the master as its own bus address.
  • the first inverter then also generates a voltage signal for the second inverter, so that the bus address contained in the next broadcast telegram is adopted by the second inverter. This procedure for address assignment is continued up to the last inverter designed as a bus participant.
  • the master After or upon completion of the address assignment, the master sends a specified time offset, in particular a specified polarity, of the pulse width modulation to a respective bus user.
  • the master therefore calculates in advance which inverter gets which time offset and allocates the time offsets centrally.
  • the nominal power is determined by the respective inverter after the address has been assigned to the bus subscribers and the time offset is then assigned depending on this, so that the power consumption fluctuates as little as possible over time, i.e. evenly distributed over the pulse width modulation period if possible is.
  • the second inverter has two connections on the AC voltage side, so that a second electric motor and a third electric motor can each be supplied with a pulse width modulated voltage.
  • the same polarity and the same time offset are used for the two pulse width modulations, since the two pulse width modulations are carried out in the same device, ie within the same housing.
  • a mains filter is arranged between the AC voltage supply network, which is preferably designed as a three-phase voltage network, and the AC voltage-side connection of the rectifier of the supply module.
  • This mains filter has three capacitances which are electrically connected to one another at their first connection and are connected at their other connection to a respective phase of the AC voltage-side connection of the rectifier of the supply module.
  • a star point is thus formed at the respective first connection. This star point is galvanically connected to a protective conductor and/or to electrical earth.
  • a voltage divider formed from two series-connected capacitances is formed on the DC voltage-side connection of the rectifier, the connection node of which, in particular the potential created by the division of the intermediate circuit voltage, is connected to the star point, in particular also to the protective conductor and/or to electrical earth. galvanically connected.
  • three further capacitances are also provided, which are electrically connected to one another at their first connection and are connected to a respective motor phase at their other connection.
  • a star point is also formed at the first connection, which is electrically connected to the aforementioned star point.
  • the inverter in turn has three half-bridges supplied in parallel with one another from the DC voltage present at the connection of the inverter on the DC voltage side
  • Each of the half-bridges has a series circuit made up of an upper and a lower controllable semiconductor switch.

Abstract

L'invention se rapporte à un procédé de fonctionnement d'un système d'entraînement, comprenant une pluralité d'onduleurs, un moteur électrique respectif étant alimenté à partir de la borne côté tension alternative de l'onduleur respectif, les bornes côté tension continue des onduleurs respectifs étant connectées en parallèle les unes aux autres et ledit circuit parallèle étant connecté à la borne côté tension continue d'un redresseur, l'onduleur respectif comportant des commutateurs à semi-conducteurs respectifs qui sont entraînés conformément à une modulation en largeur d'impulsion respective, les onduleurs étant conçus en tant qu'abonnés de bus dans un bus de données auquel est également connecté un module conçu en tant que maître. Dans une première étape de procédé, une adresse de bus respective est attribuée à chaque onduleur puis, dans une seconde étape de procédé, un décalage temporel du premier bord de commutation, c'est-à-dire un temps de démarrage (t_i), de sa modulation en largeur d'impulsion, lequel décalage temporel est associé à un signal de synchronisation, étant attribué à chaque onduleur.
PCT/EP2022/025258 2021-06-22 2022-06-01 Procédé de fonctionnement d'un système d'entraînement, et système d'entraînement comprenant une pluralité d'onduleurs WO2022268358A1 (fr)

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EP22733290.5A EP4360208A1 (fr) 2021-06-22 2022-06-01 Procédé de fonctionnement d'un système d'entraînement, et système d'entraînement comprenant une pluralité d'onduleurs

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DE102021003174.1 2021-06-22

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