WO2022260692A1 - Procédé de réduction du bruit de télégraphe aléatoire dans une mémoire non volatile par regroupement et criblage de cellules de mémoire - Google Patents

Procédé de réduction du bruit de télégraphe aléatoire dans une mémoire non volatile par regroupement et criblage de cellules de mémoire Download PDF

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Publication number
WO2022260692A1
WO2022260692A1 PCT/US2021/052249 US2021052249W WO2022260692A1 WO 2022260692 A1 WO2022260692 A1 WO 2022260692A1 US 2021052249 W US2021052249 W US 2021052249W WO 2022260692 A1 WO2022260692 A1 WO 2022260692A1
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Prior art keywords
memory cell
volatile memory
cell group
memory cells
programming
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PCT/US2021/052249
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English (en)
Inventor
Viktor Markov
Alexander Kotov
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Silicon Storage Technology, Inc.
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Filing date
Publication date
Priority claimed from US17/482,095 external-priority patent/US11769558B2/en
Application filed by Silicon Storage Technology, Inc. filed Critical Silicon Storage Technology, Inc.
Priority to CN202180098698.3A priority Critical patent/CN117396964A/zh
Priority to EP21795158.1A priority patent/EP4352728A1/fr
Priority to KR1020237039966A priority patent/KR20230163580A/ko
Priority to TW111117773A priority patent/TWI834164B/zh
Publication of WO2022260692A1 publication Critical patent/WO2022260692A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • the present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations.
  • Non-volatile memory devices are well known in the art. See for example U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration, and which is incorporated herein by reference for all purposes.
  • Fig. 1 of the present application illustrates a split gate memory cell 10 with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12.
  • the source region 14 can be referred to as a source line SL (because it commonly is connected to other source regions for other memory cells in the same row or column), and the drain region 16 is commonly connected to a bit line by a bit line contact 28.
  • a channel region 18 of the substrate is defined between the source/drain regions 14/16.
  • a floating gate 20 is disposed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and partially vertically over and insulated from the source region 14).
  • a control gate 22 is disposed vertically over and insulated from the floating gate 20.
  • a select gate 24 is disposed vertically over and insulated from (and controls the conductivity of) a second portion of the channel region 18.
  • An erase gate 26 is disposed vertically over and insulated from the source region 14 and is laterally adjacent to the floating gate 20.
  • a plurality of such memory cells can be arranged in rows and columns to form a memory cell array.
  • Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26 and/or source and drain regions 14/16, to program the split gate memory cell 10 (i.e., inject electrons onto the floating gate), to erase the split gate memory cell 10 (i.e., remove electrons from the floating gate), and to read the split gate memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 to determine the programming state of the floating gate 20).
  • Split gate memory cell 10 can be operated in a digital manner, where the split gate memory cell 10 is set to one of only two possible states: a programmed state and an erased state.
  • the split gate memory cell 10 is erased by placing a high positive voltage on the erase gate 26, and optionally a negative voltage on the control gate 22, to induce tunneling of electrons from the floating gate 20 to the erase gate 26 (leaving the floating gate 20 in a more positively charged state - the erased state).
  • Split gate memory cell 10 can be programmed by placing positive voltages on the control gate 22, erase gate 26, select gate 24 and source region 14, and a current on drain region 16.
  • Split gate memory cell 10 can be read by placing positive voltages on the select gate 24 (turning on the portion of channel region 18 under the select gate 24) and drain region 16 (and optionally on the erase gate 26 and/or the control gate 22), and sensing current flow through the channel region 18. If the floating gate 20 is positively charged (i.e. split gate memory cell 10 is erased), the split gate memory cell 10 will turn on, and electrical current will flow from drain region 16 to source region 14 (i.e.
  • the split gate memory cell 10 is sensed to be in its erased “1” state based on sensed current flow). If the floating gate 20 is negatively charged (i.e. split gate memory cell 10 is programmed), the portion of channel region 18 under the floating gate 20 is turned off, thereby preventing appreciable current flow (i.e., the split gate memory cell 10 is sensed to be in its programmed “0” state based on no, or minimal, current flow).
  • Table 1 provides non-limiting examples of erase, program and read voltages for typical digital operation of the split gate memory cell, where Vcc is power supply voltage or another positive voltage such as 2.5 V. Table 1
  • Split gate memory cell 10 can alternately be operated in an analog manner where the memory state (i.e. the amount of charge, such as the number of electrons, on the floating gate 20) of the split gate memory cell 10 can be tuned to anywhere from a fully erased state (minimum number of electrons on the floating gate 20) to a fully programmed state (maximum number of electrons on the floating gate 20), or just to a portion of this range by varying one or several programming voltages, for example, one can use various control gate 22 (CG) programming voltages for analog programming.
  • CG control gate 22
  • the split gate memory cell 10 could be operated as an MLC (multilevel cell) where it is configured to be programmed to one of many discrete values (such as 16 or 64 different values).
  • MLC multilevel cell
  • the programming voltages are applied for a limited time, or as a series of pulses, until the desired programming state is achieved.
  • intervening read operations between programming pulses can be used to determine if the desired programming state has been achieved (in which case programming ceases) or has not been achieved (in which case programming continues).
  • split gate memory cell 10 operated in an analog manner or as an MLC may be more sensitive to noise and read current instabilities which can adversely affect the accuracy of the split gate memory cell 10.
  • One source of read current instability in analog non-volatile memory devices is the capture and emission of electrons by oxide traps located at the interface and near-interface between the gate oxide and memory cell channel region.
  • the gate oxide is the insulation layer that separates the floating gate 20 from the channel region 18 of substrate 12. When an electron is captured on an interface trap, it reduces the channel conductivity during a read operation, and thus increases the threshold voltage Vt of the split gate memory cell 10 (i.e., the minimum voltage on the control gate 22 needed to turn on the channel region 18 of the split gate memory cell 10 to produce a predetermined target current,
  • RTN produced by a single interface trap is characterized by two states: a lower Vt state (and higher read current state) when an electron is emitted from the interface trap and a higher Vt state (and lower read current state) when an electron is captured by the interface trap.
  • the instability of the split gate memory cell 10 during read can be characterized either by the threshold voltage Vt, i.e. the control gate voltage corresponding to the predetermined target current or by memory cell current under given read voltage conditions.
  • the present examples are particularly described in relation to memory cell read instability as threshold voltage Vt , however the use of memory cell current under given read voltages are specifically contemplated.
  • a memory device that includes a plurality of memory cell groups, where each of the memory cell groups includes N non-volatile memory cells, where N is an integer greater than or equal to 2; and a control circuitry.
  • the control circuitry is configured to, for each of the memory cell groups, program each of the non-volatile memory cells in the memory cell group to a particular program state, perform multiple read operations on each of the non-volatile memory cells in the memory cell group, identify one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply program all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and program the identified non-volatile memory cell in the memory cell group with user data.
  • Fig. 1 is a side cross sectional view of a conventional memory cell.
  • Fig. 2 is a diagram illustrating the components of a memory device.
  • Fig. 3 is a flow diagram showing steps for programming memory cells.
  • Fig. 4 is a flow diagram showing steps for grouping, screening and programing the memory cells.
  • the present example(s) technique for reducing the effects of RTN for arrays of non-volatile memory cells particularly those that include split gate memory cells 10 of the type of Fig. 1, although the techniques are not limited to such memory cells.
  • the non-volatile memory cells are logically divided into memory cell groups, each memory cell group comprising two or more memory cells, where each memory cell group is treated as a single cell for storing user data.
  • each memory cell group only the non-volatile memory cell exhibiting the lowest RTN is used to store user data, while the rest of the non volatile memory cells of the memory cell group are deeply programmed to effectively screen them out, i.e. so that they do not contribute to the output of the memory cell group during subsequent read operations.
  • the memory cell grouping, screening and programming are implemented as part of the configuration of the control circuitry 66, which controls the various device elements of the memory array, which can be better understood from the architecture of an example memory device as illustrated in Fig. 2.
  • the memory device includes an array 50 of the split gate memory cells 10, which can be segregated into two separate planes (Plane A 52a and Plane B 52b).
  • the split gate memory cells 10 can be of the type shown in Fig. 1, arranged in a plurality of rows and columns in the semiconductor substrate 12, and thus formed on a single chip.
  • Adjacent to the array 50 of split gate memory cells 10, and included in the memory device, are an address decoder (e.g. XDEC 54), source line drivers (e.g.
  • SLDRV 56 SLDRV 56
  • YMUX 58 column decoder
  • HVDEC 60 high voltage row decoder
  • BLINHCTL 62 bit line controller
  • Column decoder 58 includes a sense amplifier containing circuitry for measuring the currents on the bit lines during a read operation.
  • Control circuitry 66 is configured to control the various device elements to implement each operation (program, erase, read) on selected split gate memory cells 10 of the array 50 as described herein.
  • Charge pump CHRGPMP 64 provides the various voltages used to read, program and erase the selected split gate memory cells 10 of the array 50 under the control of control circuitry 66.
  • the control circuitry 66 is configured to operate the memory device to program, erase and read the selected split gate memory cells 10 of the array 50.
  • control circuitry 66 can be provided with access to the incoming user data which is data to be programmed to the memory cells, along with program, erase and read commands provided on the same or different lines. Data read from the array 50, i.e. from selected split gate memory cells 10 of the array 50, is provided as outgoing data.
  • the control circuitry 66 includes, or is provided access to, a separate memory such as random access memory (RAM) 70 for storing voltage values as described further below.
  • RAM random access memory
  • Control circuitry 66 implements the memory cell grouping, screening and programming described herein.
  • control circuitry 66 may be loaded with software, i.e. non-transitory electronically readable instructions, or firmware, to perform the methods described below in relation to Figs. 3-4, thereby being configured.
  • Control circuity 66 may be implemented by a microcontroller, dedicated circuitry, a processor, or a combination thereof.
  • the split gate memory cells 10 of the array 50 are logically divided into memory cell groups 80 of N cells in each memory cell group 80, where N is an integer greater than or equal to two.
  • Memory cell programming involves programming the memory cell to a particular programming state using programming voltage pulses, with intervening read operations to measure a threshold voltage parameter (i.e., a minimum voltage applied to the split gate memory cell 10 to achieve a predetermined level of source/drain current, referred to as a target current Itarget) for the split gate memory cell 10.
  • the threshold voltage parameter is a control gate threshold voltage Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate 22.
  • control gate threshold voltage Vtcg is the voltage placed on the control gate 22 that results in the channel region 18 being a conducting path, and therefore results in a read current through the channel of the predetermined level of source/drain current, i.e., the target current I target (e.g., 1 mA) to consider the split gate memory cell 10 turned on when the read potentials of a read operation are applied to the select gate 24 and drain region 16.
  • the control gate threshold voltage Vtcg varies as a function of programming state of the split gate memory cell 10, but it is desired that once the split gate memory cell 10 is programmed to a particular programming state, any variation of control gate threshold voltage Vtcg over time be below a predetermined amount.
  • Steps 1-4 in Fig. 3 which is implemented to program a split gate memory cell 10 to a specific desired programming state so that it has a target control gate threshold voltage Vtcg target that is associated with that specific desired programming state.
  • the technique begins in Step 1 with control circuitry 66 programming a selected split gate memory cell 10 of array 50.
  • the analog programming operation involves applying programming voltages to the selected split gate memory cell 10 for a limited time (i.e., in at least one pulse), which results in injecting electrons onto the floating gate 20.
  • the voltage Vcg provided from SLDRV 56, applied to the control gate 22 has a control gate program voltage Vcgp rogram .
  • Step 2 a read operation is performed by control circuitry 66 which involves applying read voltages from SLDRV 56 to the selected split gate memory cell 10, according to Table 1, and measuring, with column decoder 58 and bit line controller 62, the current flowing through the channel region 18 of the selected split gate memory cell 10, I re ad.
  • the voltage Vcg applied to the control gate 22 is the target control gate threshold voltage Vtcgtarget.
  • Step 3 it is determined from the read operation of Step 2 whether or not the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcg target (i.e., whether the read current I read measured by column decoder 58 and bit line controller 62 is less than or equal to the target current I target , where h ead equal to the target current I target is indicative of the control gate threshold voltage Vtcg of the memory cell reaching the target control gate threshold voltage Vtcg target ).
  • Step 4 the control gate program voltage V cgp rogram used for programming is increased relative to that used in the previous Step 1 programming of the memory cell, and then Step 1 is repeated using the increased control gate program voltage Vcgp rogram .
  • a first program voltage is applied to the gate of the memory cell
  • a second program voltage is applied to the gate of the memory cell, where the second program voltage is greater than the first program voltage.
  • Steps 1-4 are repeated, in order, by control circuitry 66, until it is determined in Step 3 that the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcgtarget (i.e., that the read current I read is less than or equal to the target current Itarget). At that point, the memory cell is considered programmed to its desired programming state (i.e. to its target control gate threshold voltage Vtcg target ).
  • control gate threshold voltage Vtcg the control gate threshold voltage Vtcg of the memory cell. If/when the electron(s) are emitted from the interface trap(s) after programming is completed, then the control gate threshold voltage Vtcg could drop by more than AVtcg max below the target control gate threshold voltage Vtcg target , where AVtcgmax is the maximum tolerable read error in terms of control gate threshold voltage Vtcg variation. A control gate threshold voltage drop by more than AVtcg max is considered to be an intolerable error during subsequent read operations.
  • Step 5 the split gate memory cells 10 of array 50 are logically divided into memory cell groups 80 of N cells in each memory cell group 80, where N is an integer greater than or equal to two.
  • the N split gate memory cells 10 in each memory cell group 80 can be adjacent to each other in the same column, or adjacent to each other in the same row, or not be adjacent to each other.
  • the N memory split gate memory cells 10 of the memory cell group 80 are programmed to a particular program state (Step 6), i.e. as described above in relation to Steps 1 - 4. Thus, steps 1 - 4 may be performed before, or after, step 5, without limitation.
  • the N split gate memory cells 10 of the memory cell group 80 are each read multiple times.
  • the split gate memory cell 10 in the memory cell group 80 with the lowest read variance is identified.
  • Read variance for each split gate memory cell 10 can be variations in read current I read and/or variations in control gate threshold voltage Vtcg exhibited between the multiple read operations performed on the split gate memory cell 10 in Step 7. It is the split gate memory cell 10 in the memory cell group 80 with the lowest variation in I read and/or in Vtcg that is identified in Step 8.
  • step 9 the split gate memory cells 10 in the memory cell group 80 not identified in Step 8, i.e. all of the other split gate memory cells in the memory cell group 80, are deeply programmed (i.e., programmed with a high number of electrons, well beyond the chosen MLC or analog operating range for storing user data, so that these deeply programmed split gate memory cells 10 do not contribute to any detected current from the memory cell group 80 (or any other memory cell group 80) during subsequent read operations of the split gate memory cell 10 in the memory cell group 80 (or in any other memory cell group 80) that is used to store user data, because the deeply programmed state of the floating gate with the high number of electrons effectively turns off the underlying channel region 18 and prevents current flow).
  • deeply programmed i.e., programmed with a high number of electrons, well beyond the chosen MLC or analog operating range for storing user data
  • Step 10 the one split gate memory cell 10 identified in Step 8 is programmed with user data (e.g., as described above with respect to Fig. 3). Step 10 may require first erasing the one split gate memory cell 10 identified in Step 8 prior to programing it with user data. Steps 6-10 are performed for each of the memory cell groups 80 in the array to be programmed with user data.
  • the other split gate memory cells 10 in the memory cell group 80 are effectively screened out, thus suppressing any RTN that might otherwise result if the split gate memory cells 10 in the memory cell group 80 exhibiting higher read variances were used to store user data and/or contribute to the data read operation.
  • the above described memory cell grouping and screening reduces the effect of RTN on analog program and reading accuracy.
  • the above described technique has many advantages. First, it effectively screens out the split gate memory cells 10 exhibiting greater RTN. Second, it avoids having to screen out all the split gate memory cells 10 in a given column or row simply because a single noisy split gate memory cell 10 is found in the column or row (i.e., by replacing the column or row with a redundancy column or row as is known in the prior art where redundant (spare) rows and/or columns are provided and utilized to replace any row or column that contains a noisy memory cell).
  • N 2 (i.e., two memory cells in each memory cell group)
  • the improved programming accuracy allows for twice as many possible program states for the one split gate memory cell 10 characterized by lower RTN
  • twice as many bits can be programmed using the one split gate memory cell 10 thus providing the same memory density as a memory array using all the split gate memory cells 10 at half the possible program states per split gate memory cell 10. Therefore, using twice as many program states per split gate memory cell 10 compared to a conventional array results in better read-out stability and reliability over time due to reduced RTN across the memory array.
  • threshold voltage Vt as viewed from any one or more gates in the split gate memory cell 10 that is not floating.
  • example(s) herein could be implemented in an array of non-volatile memory cells with fewer gates than those in Fig. 1 (e.g., no erase gate and/or control gate combined with select gate).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Procédé de programmation d'un dispositif de mémoire comprenant une pluralité de groupes de cellules de mémoire, chacun des groupes de cellules de mémoire comprenant N cellules de mémoire non volatile, N étant un nombre entier supérieur ou égal à 2. Pour chaque groupe de cellules de mémoire, le procédé consiste à : programmer chacune des cellules de mémoire non volatile dans le groupe de cellules de mémoire à un état de programme particulier, réaliser de multiples opérations de lecture sur chacune des cellules de mémoire non volatile dans le groupe de cellules de mémoire, identifier l'une des cellules de mémoire non volatile dans le groupe de cellules de mémoire qui présente une variance de lecture la plus faible pendant les multiples opérations de lecture, programmer en profondeur toutes les cellules de mémoire non volatile dans le groupe de cellules de mémoire à l'exception de la cellule de mémoire non volatile identifiée, et programmer la cellule de mémoire non volatile identifiée dans le groupe de cellules de mémoire avec des données d'utilisateur.
PCT/US2021/052249 2021-06-08 2021-09-27 Procédé de réduction du bruit de télégraphe aléatoire dans une mémoire non volatile par regroupement et criblage de cellules de mémoire WO2022260692A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202180098698.3A CN117396964A (zh) 2021-06-08 2021-09-27 通过分组和筛选存储器单元来减少非易失性存储器中的随机电报噪声的方法
EP21795158.1A EP4352728A1 (fr) 2021-06-08 2021-09-27 Procédé de réduction du bruit de télégraphe aléatoire dans une mémoire non volatile par regroupement et criblage de cellules de mémoire
KR1020237039966A KR20230163580A (ko) 2021-06-08 2021-09-27 메모리 셀들을 그룹화하고 스크리닝함으로써 비휘발성 메모리에서 랜덤 텔레그래프 잡음을 감소시키는 방법
TW111117773A TWI834164B (zh) 2021-06-08 2022-05-12 藉由對記憶體單元進行分組及篩選來減少非揮發性記憶體中的隨機電報雜訊的方法

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Application Number Priority Date Filing Date Title
US202163208093P 2021-06-08 2021-06-08
US63/208,093 2021-06-08
US17/482,095 US11769558B2 (en) 2021-06-08 2021-09-22 Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells
US17/482,095 2021-09-22

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868375B2 (en) 2007-08-06 2011-01-11 Silicon Storage Technology, Inc. Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US20190164617A1 (en) * 2017-11-29 2019-05-30 Silicon Storage Technology, Inc. High Precision And Highly Efficient Tuning Mechanisms And Algorithms For Analog Neuromorphic Memory In Artificial Neural Networks
US20210065837A1 (en) * 2019-09-03 2021-03-04 Silicon Storage Technology, Inc. Method of improving read current stability in analog non-volatile memory by screening memory cells

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868375B2 (en) 2007-08-06 2011-01-11 Silicon Storage Technology, Inc. Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US20190164617A1 (en) * 2017-11-29 2019-05-30 Silicon Storage Technology, Inc. High Precision And Highly Efficient Tuning Mechanisms And Algorithms For Analog Neuromorphic Memory In Artificial Neural Networks
US20210065837A1 (en) * 2019-09-03 2021-03-04 Silicon Storage Technology, Inc. Method of improving read current stability in analog non-volatile memory by screening memory cells

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