WO2022259314A1 - Dispositif de calcul quantique, procédé de suppression d'erreur quantique et programme - Google Patents

Dispositif de calcul quantique, procédé de suppression d'erreur quantique et programme Download PDF

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WO2022259314A1
WO2022259314A1 PCT/JP2021/021570 JP2021021570W WO2022259314A1 WO 2022259314 A1 WO2022259314 A1 WO 2022259314A1 JP 2021021570 W JP2021021570 W JP 2021021570W WO 2022259314 A1 WO2022259314 A1 WO 2022259314A1
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quantum
error
unit
quantum error
error correction
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PCT/JP2021/021570
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Japanese (ja)
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傑 遠藤
泰成 鈴木
裕己 徳永
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日本電信電話株式会社
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena

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  • the present invention relates to quantum error resilience technology in quantum information processing.
  • Quantum error resilience technology is important for its realization.
  • Quantum error resilience calculations in conventional technology use quantum error correction to represent one logical qubit using multiple physical qubits, and reduce calculation errors by providing redundancy.
  • Quantum error correction is the only known technique that can scaleably increase the size of a quantum computer, provided that the physical errors in the physical qubits for redundancy are below a certain threshold ( Non-Patent Document 1).
  • quantum error correction is a method that can scale the size of a quantum computer, it requires an extremely large number of qubits as overhead. For example, even if we could achieve an error rate of 10 percent of the qubits currently available, we would at least estimate that hundreds of thousands of qubits would be needed to solve useful problems that cannot be simulated on a classical computer. It is said that
  • the present invention has been made in view of the above points, and aims to provide a technology that enables a significant reduction in the number of quantum bits required for fault-tolerant quantum computation.
  • a computing unit that performs computation of a quantum algorithm; a quantum error correction unit that performs quantum error correction using a quantum error correction code during calculation by the calculation unit; a quantum error suppression unit that cancels decoding errors that occur in the quantum error correction by a quantum error suppression method;
  • FIG. 1 is a configuration diagram of a quantum computing device according to an embodiment of the present invention
  • FIG. 3 is a functional configuration diagram of a control device
  • FIG. 4 is a flowchart for explaining the operation of the quantum computing device
  • FIG. 4 is a diagram for explaining an outline of quantum error suppression
  • FIG. 2 is a diagram for explaining an outline of a Pauli frame
  • FIG. 4 is a diagram for explaining an outline of a Pauli frame incorporating quantum error suppression
  • It is a figure which shows the hardware structural example of a control apparatus.
  • the pseudo-probability method is used as a quantum error suppression method for canceling decoding errors and approximation errors.
  • method, subspace expansion method, etc. may be used.
  • a quantum computer performs error-tolerant quantum computation by combining a quantum error correction method and a quantum error suppression method in order to significantly reduce the number of quantum bits required for error-tolerant quantum computation.
  • the quantum error suppression method is a method of suppressing quantum computer errors without increasing the number of qubits, but the cost is that the number of measurements must be increased. Since the increase in the number of measurements increases exponentially with respect to the errors that occur in the quantum computer, the quantum error suppression method is not a scalable method. The increase in the number of measurements is acceptable and very useful.
  • quantum error correction is used to suppress calculation errors to about one or two times, and quantum error suppression is performed to suppress further calculation errors.
  • quantum error suppression is performed to suppress further calculation errors.
  • multiple H, T, and CNOT are used to approximate using the Solovay-Kitaev algorithm in order to implement arbitrary quantum gates. At that time, an approximation error occurs, but the approximation error can be suppressed by the method according to the present embodiment.
  • the Solovay-Kitaev algorithm is described in Nielsen, M. A., & Chuang, I. (2002). Quantum computation and quantum information.
  • FIG. 1 shows a configuration example of a quantum computing device 300 according to this embodiment.
  • a “quantum computing device” may also be called a “quantum computer.”
  • the quantum computing device 300 includes a control device 100 and a quantum processor 200.
  • the control device 100 transmits a control signal to the quantum processor 200 and acquires a calculation result (measurement result) from the quantum processor 200, thereby performing fault-tolerant quantum calculation.
  • the control device 100 can be realized, for example, by a classical computer.
  • “computer” means “classical computer”.
  • the quantum processor 200 configures a quantum two-level system called a physical qubit, and performs physical operations such as initialization, gate operation (unitary transformation), and measurement on the physical qubit.
  • a physical system for realizing a physical qubit is not particularly limited, and any physical system may be used.
  • superconducting circuits, ion traps, photons, quantum dots, etc. can be used as physical systems. These physical systems are described in Nielsen, M. A., & Chuang, I. (2002). Quantum computation and quantum information.
  • control device 100 The configuration and operation of the control device 100 will be mainly described below.
  • processing proceeds by transmitting a signal to the quantum processor 200 and receiving information from the quantum processor 200, but for convenience of explanation, in the following explanation, this Physical operations are not explicitly shown and are implicitly included in the operation of the controller 100 .
  • the “quantum algorithm operation” includes signal transmission to the quantum processor 200 and information reception from the quantum processor 200 .
  • quantum computation may be performed without physically operating the quantum processor 200 .
  • FIG. 2 shows an example of the functional configuration of the control device 100.
  • the control device 100 includes a calculation unit 110 , a quantum error suppression unit 120 , a quantum error correction unit 130 , an error map creation unit 140 and a storage unit 150 .
  • the function outline of each part is as follows.
  • the quantum error correction unit 130 configures a pseudo two-level system called a logical qubit from a plurality of qubits according to a quantum error correction code technique such as a stabilizer code, and encodes and decodes the qubits. Perform error correction (error correction) with a quantum error correction code technique such as a stabilizer code.
  • the operation unit 110 performs the operation of the target quantum algorithm by executing logical operations on the logical qubits in an appropriate order. Quantum error correction operations are performed by manipulating logical quantum gates on logical qubits in the encoded state.
  • the error map creation unit 140 creates an error map of decoding errors in the quantum error correction unit 130 and stores the error map in the storage unit 150. Further, the error map generator 140 calculates an error map of approximation errors that occur when the quantum gate is approximated by the Solovay-Kitaev algorithm, and stores the error map in the storage unit 150 .
  • the quantum error suppression unit 120 cancels the decoding error in the quantum error correction unit 130 based on the error map of the decoding error during the calculation by the calculation unit 110, and cancels the approximation error based on the error map of the approximation error. .
  • the quantum computing device 300 is shown as having a configuration including the quantum processor 200 and the control device 100, but this is an example.
  • the quantum computing device 300 may include a quantum processor 200 , an arithmetic unit 110 , a quantum error suppression unit 120 , a quantum error correction unit 130 , an error map creation unit 140 and a storage unit 150 .
  • the control device 100 that does not include the quantum processor 200 may be called a quantum computing device.
  • ⁇ S1 (Step 1)>
  • S1 when the error map creation unit 140 performs quantum error correction by the quantum error correction unit 130, decoding errors (errors caused by insufficient code distance) that are remaining errors due to error correction failure etc.) is calculated.
  • an error identification technique called gated set tomography is used to characterize (create) an error map.
  • the error map may be any information as long as it can identify the error occurrence state, and may be, for example, probabilistic information using the probability of error occurrence for each operation.
  • Gated set tomography is an approach that combines quantum state tomography, quantum process tomography, and POVM tomography experiments, and simultaneously estimates all of the quantum state quantum gate measurements (POVM) from the experimental data obtained. , is a method for checking the occurrence of an error.
  • Gated set tomography itself is a known technique as disclosed in Non-Patent Document 1, for example.
  • error identification method for decoding errors is not limited to gate set tomography, and other error identification methods may be used.
  • the calculation unit 110 approximates an arbitrary quantum gate from a plurality of Hs, Ts, and CNOTs by using the Solovay-Kitaev algorithm.
  • the operation of arbitrary quantum gates can be approximated by a combination of multiple simple quantum gates using the Solovay-Kitaev algorithm.
  • the error map generator 140 calculates in advance an error map of logic single gate operations caused by the Solovay-Kitaev algorithm.
  • the calculated error map is stored in the storage unit 150 .
  • An error map of approximation errors can be accurately calculated in advance using information about the target quantum gate and information about the approximated quantum gate.
  • the calculation unit 110 starts calculation of the target quantum algorithm. During the calculation, error correction is performed by encoding and decoding by the quantum error correction unit 130 . Error correction by the quantum error correction unit 130 is performed by stabilizer coding or magic-state distillation. Error correction methods such as stabilizer codes and magic state distillation are described in Nielsen, M. A., & Chuang, I. (2002). Quantum computation and quantum information.
  • the quantum error suppression unit 120 cancels decoding errors that occur during error correction by the quantum error correction unit 130 using the error map created in S1.
  • the quantum error suppression unit 120 cancels decoding errors using a pseudo-probability method, which is one of quantum error suppression techniques.
  • a pseudo-probability method which is one of quantum error suppression techniques.
  • the pseudo-probability method itself is an existing technology.
  • the pseudo-probability method is a method of canceling errors by effectively inverting the error map by operating the quantum circuit and post-processing the measurement results.
  • the pseudo-probability method according to the present embodiment when canceling a decoding error, instead of physically operating a quantum circuit, it is not necessary to physically operate a quantum processor by updating a classical memory called a Pauli frame. can also cancel errors only by classical processing.
  • a Pauli frame see L. Riesebos, X. Fu, S. Varsamopoulos, C. G. Almudever, and K. Bertels, Pauli frames for quantum computer architectures, in Proceedings of the 54th Annual Design Automation Conference 2017 (2017) pp. 1-6.
  • FIG. 4(a) shows the quantum computation without quantum error suppression for comparison with (b).
  • the calculation of the quantum circuit is repeated many times, the measurement results of each time are collected, and the average is calculated.
  • the distribution deviates from the ideal value because the implementation of the quantum circuit is imperfect, as shown in the right end of FIG. 4(a).
  • the ideal value is an expected value assumed when the quantum circuit is completely implemented without error.
  • each correction circuit is determined by random numbers, and the distribution of the random numbers (correction circuits) depends on the error map (error model) measured by the aforementioned gate-set tomography. By repeating the random number generation and operation by the correction circuit, the error map can be effectively reverse-transformed.
  • the rightmost diagram in FIG. 4(b) shows that the average of the measurement results becomes the ideal value by effectively performing the inverse transformation of the error map.
  • FIG. 5 shows an overview of a Pauli frame without quantum error suppression. Specifically, it indicates that the Pauli operation (Recover) for error correction (for recovery) estimated from the syndrome, which is the measurement result of the stabilizer, is applied. However, the recovery operation is not physically applied to the quantum processor, but stored in a classical memory called a Pauli frame. The recovery operation is updated with each gate operation. Finally, the measurement results are post-processed according to the manipulations stored in the Pauli frames.
  • FIG. 6 shows an outline of a Pauli frame when quantum error suppression (QEM) is performed by the pseudo-probability method described above in addition to the recovery operation shown in FIG.
  • QEM quantum error suppression
  • the recovery operation for error cancellation in quantum error suppression is a Pauli operation, it is stored in a Pauli frame (classical memory) without being physically applied to the quantum processor.
  • the recovery operation is updated with each gate operation. Parity is also updated.
  • the measurement results are post-processed according to the operation, parity, and quantum error suppression costs stored in the Pauli frames. Note that the post-processing for the measurement results is processing performed in S7, which will be described later.
  • the quantum error suppression unit 120 cancels the approximation error based on the error map of the approximation error calculated in S2 using the pseudo-probability method during the calculation by the calculation unit 110.
  • FIG. The processing operation is the same as the cancel processing in S4.
  • the quantum error suppression unit 120 reads the measurement result from the quantum processor 200 .
  • the quantum error suppression unit 120 performs post-processing on the measurement results according to the process of the pseudo-probability method and the state of the Pauli frame, and stores the post-processed measurement results in the storage unit 150 .
  • Post-processing means, for example, correcting "1" to "0” or correcting "0" to "1".
  • ⁇ S8> S3 to S7 are repeated, and when the repetition ends, the process proceeds to S9.
  • the number of repetitions may be determined in advance, or may be repeated until the average value of the measurement results converges to a certain value.
  • the quantum error suppression unit 120 outputs the average value of the measurement results obtained by repeating S3 to S7 as the measurement result with calculation errors suppressed. Further, the quantum error suppressing unit 120 may store the measurement result with the calculation error suppressed in the storage unit 150 .
  • the control device 100 can be implemented, for example, by causing a computer to execute a program.
  • This computer may be a physical computer or a virtual machine on the cloud.
  • control device 100 can be realized by executing a program corresponding to the processing performed by the control device 100 using hardware resources such as a CPU and memory built into the computer.
  • the above program can be recorded in a computer-readable recording medium (portable memory, etc.), saved, or distributed. It is also possible to provide the above program through a network such as the Internet or e-mail.
  • FIG. 7 is a diagram showing a hardware configuration example of the computer.
  • the computer of FIG. 7 has a drive device 1000, an auxiliary storage device 1002, a memory device 1003, a CPU 1004, an interface device 1005, a display device 1006, an input device 1007, an output device 1008, etc., which are interconnected by a bus BS.
  • a program that implements the processing in the computer is provided by a recording medium 1001 such as a CD-ROM or memory card, for example.
  • a recording medium 1001 such as a CD-ROM or memory card
  • the program is installed from the recording medium 1001 to the auxiliary storage device 1002 via the drive device 1000 .
  • the program does not necessarily need to be installed from the recording medium 1001, and may be downloaded from another computer via the network.
  • the auxiliary storage device 1002 stores installed programs, as well as necessary files and data.
  • the memory device 1003 reads and stores the program from the auxiliary storage device 1002 when a program activation instruction is received.
  • the CPU 1004 implements functions related to the control device 100 according to programs stored in the memory device 1003 .
  • the interface device 1005 is used as an interface for connecting to the network and the quantum processor 200 .
  • a display device 1006 displays a GUI (Graphical User Interface) or the like by a program.
  • An input device 1007 is composed of a keyboard, a mouse, buttons, a touch panel, or the like, and is used to input various operational instructions.
  • the output device 1008 outputs the calculation result.
  • the number of qubits used for encoding must be increased. It can reduce the required qubits. For example, if the error rate of a physical qubit is about 10% of the error threshold, and the experimenter can estimate the decoding error with an accuracy of 10% of the decoding error, the code distance can be reduced by about 2. If the original code distance is 11, the number of qubits can be reduced by about 33%.
  • Quantum computing device a computation unit that performs computation of the quantum algorithm; a quantum error correction unit that performs quantum error correction using a quantum error correction code during calculation by the calculation unit; a quantum error suppression unit that cancels decoding errors that occur in the quantum error correction by a quantum error suppression method; Quantum computing device with (Section 2) 2.
  • the quantum error suppression unit cancels the decoding error using a pseudo-probability method as the quantum error suppression method based on an error map of decoding errors created in advance by gated set tomography.
  • quantum computing device (Section 3) 3.
  • the quantum computing device according to claim 1 or 2, wherein the quantum error suppression unit cancels, by the quantum error suppression method, an approximation error caused by approximating a certain quantum gate from a plurality of quantum gates by the Solovay-Kitaev algorithm. . (Section 4) Any one of the first to third terms, wherein the quantum error suppression unit stores the gate operation used when canceling the decoding error in a memory, and uses it for post-processing of the measurement result obtained from the quantum processor. Quantum computing device according to the paragraph.
  • (Section 5) A quantum error suppression method performed by a quantum computing device, an operation step for performing an operation of a quantum algorithm; A quantum error correction step of performing quantum error correction using a quantum error correction code during the calculation by the calculation step; a quantum error suppression step of canceling decoding errors that occur in the quantum error correction by a quantum error suppression method; A quantum error suppression method comprising: (Section 6) A program for causing a computer to function as each unit in the quantum computing device according to any one of items 1 to 4.
  • Control device 110 Operation unit 120 Quantum error suppression unit 130 Quantum error correction unit 140 Error map creation unit 150 Storage unit 200 Quantum processor 300 Quantum computing device 1000 Drive device 1001 Recording medium 1002 Auxiliary storage device 1003 Memory device 1004 CPU 1005 interface device 1006 display device 1007 input device 1008 output device

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Abstract

Un dispositif informatique quantique comprend : une unité de calcul qui calcule un algorithme quantique ; une unité de correction d'erreur quantique qui corrige une erreur quantique à l'aide d'un code de correction d'erreur quantique pendant le calcul par l'unité de calcul ; et une unité de suppression d'erreur quantique qui annule, par un procédé de suppression d'erreur quantique, une erreur de décodage générée pendant la correction d'erreur quantique.
PCT/JP2021/021570 2021-06-07 2021-06-07 Dispositif de calcul quantique, procédé de suppression d'erreur quantique et programme WO2022259314A1 (fr)

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Citations (3)

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US20060010187A1 (en) * 2004-05-14 2006-01-12 Brown Kenneth R Arbitrarily accurate composite pulse sequences
US20200119748A1 (en) * 2018-10-12 2020-04-16 Dennis Lucarelli System and methods for quantum post-selection using logical parity encoding and decoding
US20200175409A1 (en) * 2018-12-03 2020-06-04 International Business Machines Corporation Implementation of error mitigation for quantum computing machines

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20060010187A1 (en) * 2004-05-14 2006-01-12 Brown Kenneth R Arbitrarily accurate composite pulse sequences
US20200119748A1 (en) * 2018-10-12 2020-04-16 Dennis Lucarelli System and methods for quantum post-selection using logical parity encoding and decoding
US20200175409A1 (en) * 2018-12-03 2020-06-04 International Business Machines Corporation Implementation of error mitigation for quantum computing machines

Non-Patent Citations (1)

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Title
YASUNARI SUZUKI; SUGURU ENDO; KEISUKE FUJII; YUUKI TOKUNAGA: "Quantum error mitigation as a universal error-minimization technique: applications from NISQ to FTQC eras", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 18 October 2021 (2021-10-18), 201 Olin Library Cornell University Ithaca, NY 14853, XP091063291 *

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