WO2022257935A1 - 相变存储单元、相变存储器、电子设备及制备方法 - Google Patents

相变存储单元、相变存储器、电子设备及制备方法 Download PDF

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WO2022257935A1
WO2022257935A1 PCT/CN2022/097453 CN2022097453W WO2022257935A1 WO 2022257935 A1 WO2022257935 A1 WO 2022257935A1 CN 2022097453 W CN2022097453 W CN 2022097453W WO 2022257935 A1 WO2022257935 A1 WO 2022257935A1
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phase
layer
change memory
electrode layer
change
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PCT/CN2022/097453
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English (en)
French (fr)
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陈鑫
李响
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华为技术有限公司
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Priority to EP22819533.5A priority Critical patent/EP4343869A1/en
Priority to KR1020247000956A priority patent/KR20240019331A/ko
Publication of WO2022257935A1 publication Critical patent/WO2022257935A1/zh
Priority to US18/533,855 priority patent/US20240114808A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of semiconductor storage, in particular to a phase-change memory unit, a phase-change memory, electronic equipment and a preparation method.
  • Phase-change memory uses phase-change materials as storage media. Phase-change materials can undergo reversible transitions between crystalline and amorphous states. Phase-change memory uses the corresponding high and low resistivity of phase-change materials in amorphous and crystalline states. To realize the storage of data "0" and "1", the choice of phase change material has an important influence on the read and write speed of phase change memory.
  • the related technology provides a superlattice phase-change material, which is formed by alternately stacking multiple layers of GeTe thin films and multi-layer Sb 2 Te 3 thin films, which is beneficial to improve the read and write speed of phase change memory.
  • Te elements and Sb elements migrate to different electric field directions, so that Sb-rich regions and Te-rich regions are formed inside the phase change materials, which is not conducive to the development of superlattice phase change materials. Repeated erasing and writing will easily reduce its cycle life.
  • the present disclosure provides a phase-change memory unit, a phase-change memory array, a phase-change memory, electronic equipment and a preparation method, which can solve the above-mentioned technical problems.
  • an embodiment of the present disclosure provides a phase-change memory unit, the phase-change memory unit comprising: a phase-change film, the phase-change film comprising: a phase-change material layer and a heterojunction layer, the The phase change material layer is in contact with the heterojunction layer;
  • the phase change material layer is formed using a phase change material, and the heterojunction layer is formed using a heterojunction material;
  • the lattice mismatch between the heterojunction material and the phase change material is less than or equal to 20%; the contact crystal planes of the heterojunction material and the phase change material have the same lattice angle; and, The melting point of the heterojunction material is greater than the melting point of the phase change material.
  • the phase-change memory cell provided by the embodiment of the present disclosure uses a heterojunction layer, and the heterojunction layer is formed of a heterojunction material. Since the lattice mismatch between the heterojunction material and the phase-change material is less than or equal to 20%, and , the contact crystal planes of the heterojunction material and the phase change material have the same lattice angle, so that the phase change material layer can be crystallized on the interface of the heterojunction layer by epitaxial growth, so that the heterojunction layer can As a crystallization template of the phase change material layer, it accelerates the crystallization speed of the phase change material, increases the phase change speed of the phase change material, and thus increases its operating speed.
  • the heterojunction layer Since the melting point of the heterojunction material is higher than that of the phase change material, when the phase change material layer undergoes a phase change, the heterojunction layer will maintain a stable crystal structure, effectively preventing the element migration of the phase change material in the direction of the electric field, and reducing the The small diffusion between the phase change material and the electrode is beneficial to improve the cycle life of the phase change material layer.
  • the phase-change film includes a layer of phase-change material and a layer of heterojunction, which not only avoids the interface problems and unstable operation that are prone to occur at the multilayer interface, but also makes the phase-change memory Cells are more conducive to designing common constrained structures.
  • the phase-change storage unit adopting a single-layer phase-change material layer and a single-layer heterojunction layer has a simple structure, a correspondingly simple preparation method, and is easy to realize. Specifically, compared with the complex multilayer superlattice structure, the preparation process of the phase change thin film 1 is easier to control accurately, thereby improving the device yield.
  • the electrical operation of the phase-change thin film 1 of single-layer structure is easier to control, and can obtain more stable resistance distribution (and the multilayer superlattice structure is easier to occur the element diffusion between the phase-change layers, resulting in the cyclic operation life of the device reduce).
  • the crystal structure of the phase change material used in the phase change material layer is similar to that of the heterojunction material used in the heterojunction layer, or at least the crystal form of the contact crystal plane between the phase change material and the heterojunction material Similar to each other, so that the two can obtain a higher degree of lattice matching, so that the heterojunction material can be used as the crystallization template of the phase change material.
  • the length difference between the a-axis of the heterojunction material and the a-axis of the phase change material is less than Or equal to 20%.
  • the a-axis length of the heterojunction material is defined as a
  • the The a-axis length of the phase change material is defined as a
  • the difference between a and ⁇ 2a 2 is less than or equal to 20%.
  • the thickness of the phase change material layer is 2nm-100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm and so on.
  • the thickness of the phase change material layer 101 can be determined according to the corresponding operating voltage or operating current when the phase change occurs.
  • the thickness of the heterojunction layer is 2nm-20nm, such as 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 12nm, 15nm, 17nm, 18nm, 19nm and so on.
  • the aforementioned thickness range of the heterojunction layer can effectively prevent element diffusion between the phase change material layer and the electrode.
  • the phase change material is doped or undoped Ge-Te binary compound, Sb-Te binary compound, Bi-Te binary compound, Ge-Sb-Te ternary compound , Ga-Sb binary compound, one of Sb;
  • the heterojunction material is an M-Te compound, wherein M is a transition metal element.
  • the heterojunction material can be TiTe 2 (titanium ditelluride), ZrTe 3 (zirconium telluride), PdTe 2 (palladium ditelluride), CdTe (cadmium telluride), MoTe 2 (molybdenum ditelluride), MnTe 2 (manganese telluride), IrTe 2 (iridium telluride), RnTe (radon telluride), PtTe 2 (platinum ditelluride), Pt 2 Te 3 (platinum tritelluride), ScTe (scandium telluride), Sc 2 Te 3 (scandium tritelluride), NiTe 2 (nickel ditelluride), TaTe 2 (tantalum ditelluride), ZnTe (zinc telluride).
  • the M is Ti, Zr, Pd, Cd, Mo, Mn, Ir, Rn, Pt, Sc, Ni, Ta, or Zn.
  • the phase change material is a doping material
  • the doping element is selected from C, N, Si, B, Sc, Ti, Y, Zr, Hf, V, Ta, W, Cu, At least one of Zn and In.
  • phase change materials and heterojunction materials are used in combination, as long as the degree of lattice mismatch between the phase change materials and heterojunction materials used in combination is less than or equal to 20%, the combination of heterojunction materials and phase change materials The materials have the same lattice angle in the plane, and the melting point of the phase change material used in combination is lower than that of the heterojunction material.
  • the phase change memory cell further includes: a bottom electrode layer, a top electrode layer, and an insulating dielectric layer;
  • the phase change film is located between the bottom electrode layer and the top electrode layer;
  • the insulating dielectric layer is used to provide insulation and isolation for the phase change memory unit.
  • the phase change memory cell further includes: an intermediate electrode layer and a gate layer;
  • the first surface of the intermediate electrode layer is in contact with the phase change film, and the second surface of the intermediate electrode layer is in contact with the gate layer;
  • phase change film, the middle electrode layer and the gate layer are integrally located between the bottom electrode layer and the top electrode layer.
  • the phase-change memory cell is a restricted structure, a T-shaped structure, a U-shaped trench structure, or an L-shaped structure.
  • the phase-change memory cell has a cylindrical structure, and the phase-change memory cell further includes: an internal electrode layer and an external electrode layer;
  • the inner electrode layer, the phase change thin film, and the outer electrode layer are covered sequentially from inside to outside along the radial direction.
  • the internal electrode layer is in the shape of a solid cylinder or a ring.
  • the phase-change memory cell has a cylindrical structure, and the phase-change memory cell further includes: an internal electrode layer, an intermediate electrode layer, a gate layer, and an external electrode layer;
  • the internal electrode layer, the phase change film, the intermediate electrode layer, the gate layer, and the external electrode layer are coated sequentially from inside to outside along the radial direction.
  • the internal electrode layer is in the shape of a solid cylinder or a ring.
  • an embodiment of the present disclosure provides a phase-change memory array, and the phase-change memory array includes any one of the above-mentioned phase-change memory cells.
  • an embodiment of the present disclosure provides a phase-change memory, which includes the above-mentioned phase-change memory unit or the above-mentioned phase-change memory array.
  • the phase-change memory provided by the embodiments of the present disclosure has at least the following advantages: high stability, good repeatability, fast read and write speed, high memory density, and low cost.
  • an embodiment of the present disclosure provides an electronic device, and the electronic device includes: a processor, and the aforementioned phase-change memory;
  • the phase change memory is used to store data accessed by the processor.
  • the electronic equipment includes, but is not limited to: computers, printers, mobile phones, cameras, and the like.
  • an embodiment of the present disclosure provides a method for manufacturing a phase-change memory cell, the phase-change memory cell being the above-mentioned phase-change memory cell;
  • the preparation method of the phase change memory unit includes: preparing a phase change film
  • the preparation of the phase change thin film includes: forming a phase change material layer and a heterojunction layer respectively, and making the phase change material layer and the heterojunction layer contact.
  • the phase change material layer and the heterojunction layer are respectively formed by a thin film deposition process.
  • the thin film deposition process is an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
  • FIG. 1 is a schematic structural diagram of an exemplary phase change film provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a phase-change memory cell with a first exemplary restricted structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a phase-change memory cell with a second exemplary restricted structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a phase-change memory cell with a third exemplary restricted structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a phase-change memory cell with a fourth exemplary restricted structure provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an exemplary phase-change memory cell with a confinement structure of a gating layer designed on the basis of FIG. 5 provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a phase-change memory cell with a fifth exemplary restricted structure provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an exemplary phase-change memory cell with a confinement structure of a gating layer designed on the basis of FIG. 7 provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of an exemplary T-shaped phase-change memory cell provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an exemplary T-shaped phase-change memory cell with a gate layer designed on the basis of FIG. 9 provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of an exemplary phase-change memory cell with a U-shaped trench structure provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of an exemplary phase-change memory cell with a U-shaped groove structure of a gate layer designed on the basis of FIG. 11 provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of another exemplary phase-change memory cell with a U-shaped trench structure provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of an exemplary phase-change memory cell with a U-shaped groove structure of a gate layer designed on the basis of FIG. 13 provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of an exemplary phase-change memory cell with an L-shaped structure provided by an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of an exemplary L-shaped phase-change memory cell with a gating layer designed on the basis of FIG. 15 provided by an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of another exemplary L-shaped phase-change memory cell provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of an exemplary L-shaped phase-change memory cell with a gating layer designed on the basis of FIG. 17 provided by an embodiment of the present disclosure
  • FIG. 19 is a schematic structural diagram of an exemplary phase-change memory cell with a cylindrical structure provided by an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of another exemplary phase-change memory cell with a cylindrical structure provided by an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of an exemplary phase-change memory array provided by an embodiment of the present disclosure.
  • Fig. 22 is a schematic structural diagram of an exemplary first intermediate array provided by an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural view of a second intermediate array formed by opening holes and filling an insulating medium on the structure shown in FIG. 22;
  • Fig. 24 is a top view of another exemplary phase-change memory array provided by an embodiment of the present disclosure.
  • Fig. 25 is a side view obtained from top to bottom along the direction AB in Fig. 24;
  • Fig. 26 is a schematic diagram of a film structure formed by alternately stacking multi-layer external electrode layers and multi-layer insulating dielectric layers according to an embodiment of the present disclosure
  • Fig. 27 is a top view of yet another exemplary phase-change memory array provided by an embodiment of the present disclosure.
  • Figure 28 is a side view obtained from top to bottom along the CD direction based on Figure 27;
  • Fig. 29 is a schematic diagram of a class of application scenarios of an exemplary phase-change memory cell provided by an embodiment of the present disclosure
  • FIG. 30 is a schematic diagram of another application scenario of an exemplary phase-change memory cell provided by an embodiment of the present disclosure.
  • Phase-change memory is a solid-state semiconductor non-volatile memory, which has the advantages of high-speed reading, high erasable times, non-volatility, small component size, and low power consumption. It is widely used in semiconductor memory and other products. Phase-change memory uses phase-change materials as storage media. Phase-change materials can undergo reversible transitions between crystalline and amorphous states. Phase-change memory uses the corresponding high and low resistivity of phase-change materials in amorphous and crystalline states. The difference to realize the storage of data "0" and "1".
  • the working process of phase change memory includes: SET process and RESET process.
  • the SET process refers to: apply a wide and weak electric pulse to heat the phase change material, so that the temperature of the phase change material rises to between the crystallization temperature and the melting temperature, and the phase change material crystallizes into an ordered state, forming a A crystalline state with low resistivity to realize the storage of data "0".
  • the RESET process refers to applying a narrow and strong electric pulse to heat the phase change material, so that the temperature of the phase change material rises above the melting temperature, melts into a disordered state, and then undergoes a rapid cooling quenching process (> 10 9 K/s), the phase change material directly enters the amorphous state with higher resistivity from the molten state, so as to realize the storage of data "1".
  • phase change speed of the phase change material directly affects the read and write speed of the phase change memory.
  • the related technology provides a superlattice phase change material, which is alternately stacked by multi-layer GeTe thin films and multi-layer Sb 2 Te 3 thin films Formed, this type of superlattice phase change material has a high phase change speed.
  • phase-change memory unit which includes a phase-change film 1, as shown in Figure 1, the phase-change film 1 includes: a layer of phase-change material 101 and a layer of heterogeneous Junction layer 102 , the phase change material layer 101 is in contact with the heterojunction layer 102 .
  • the phase change material layer 101 is formed of a phase change material
  • the heterojunction layer 102 is formed of a heterojunction material, wherein (1) the lattice mismatch between the heterojunction material and the phase change material is less than or equal to 20%; (2) ) The contact crystal planes of the heterojunction material and the phase change material have the same lattice angle; (3) The melting point of the heterojunction material is greater than that of the phase change material.
  • the above-mentioned “the contact crystal plane of the heterojunction material and the phase change material have the same lattice angle” refers to the crystal plane used for contact between the phase change material layer 101 and the heterojunction layer 102. noodle.
  • the phase-change memory cell uses a heterojunction layer 102, and the heterojunction layer 102 is formed of a heterojunction material, since the lattice mismatch between the heterojunction material and the phase-change material is less than or equal to 20%. , and the contact crystal planes of the heterojunction material and the phase change material have the same lattice angle, so that the phase change material layer 101 can be crystallized on the interface of the heterojunction layer 102 by epitaxial growth, so that the heterojunction
  • the texture layer 102 can be used as a crystallization template of the phase change material layer 101 to accelerate the crystallization speed of the phase change material, increase the phase change speed of the phase change material, and thus increase its working speed.
  • the heterojunction layer 102 Since the melting point of the heterojunction material is higher than that of the phase change material, when the phase change occurs in the phase change material layer 101, the heterojunction layer 102 will maintain a stable crystal structure, effectively preventing the element migration of the phase change material in the direction of the electric field. And reduce the diffusion between the phase change material and the electrode, which is beneficial to improve the cycle life of the phase change material layer 101 .
  • the phase-change film 1 includes a layer of phase-change material 101 and a layer of heterojunction layer 102, which not only avoids the interface problems and unstable operation that are likely to occur at the multilayer interface, but also makes Phase-change memory cells are more conducive to the design of common confinement structures.
  • the phase-change memory unit adopting a single-layer phase-change material layer 101 and a single-layer heterojunction layer 102 has a simple structure, a correspondingly simple preparation method, and is easy to implement. Specifically, compared with the complex multilayer superlattice structure, the preparation process of the phase change thin film 1 is easier to control accurately, thereby improving the device yield.
  • the electrical operation of the phase-change thin film 1 of single-layer structure is easier to control, and can obtain more stable resistance distribution (and the multilayer superlattice structure is easier to occur the element diffusion between the phase-change layers, resulting in the cyclic operation life of the device reduce).
  • the crystal structure of the phase change material used in the phase change material layer 101 is similar to that of the heterojunction material used in the heterojunction layer 102, or at least make the contact crystal plane of the phase change material and the heterojunction material
  • the crystal forms are similar, so that the two can obtain a higher degree of lattice matching, so that the heterojunction material can be used as the crystallization template of the phase change material.
  • the lattice mismatch between the phase change material and the heterojunction material is less than or equal to 19%, less than or equal to 18%, less than or equal to 17%, less than or equal to 16%, less than or equal to 15%, less than or equal to 14% or less, 13% or less, 12% or less, 11% or less, 10% or less, 9% or less, 8% or less, 9% or less, 7% or less %, less than or equal to 6%, less than or equal to 5%, etc., so that the phase change material can obtain a faster crystallization rate.
  • the lattice mismatch between the phase change material and the heterojunction material is less than or equal to 10%, there is a smaller difference in lattice constant between the phase change material and the heterojunction material, which can be the crystallization of the phase change material.
  • both the heterojunction material and the phase change material are hexagonal materials.
  • a-axis length b-axis length ⁇ c-axis length, and the gap between the a-axis and the b-axis The angle is 120°, and the included angle between the a-axis and the c-axis and the included angle between the b-axis and the c-axis are both 90°.
  • the length difference between the a-axis of the heterojunction material and the a-axis of the phase-change material is less than or equal to 20% (the length difference here is also the above-mentioned lattice mismatch).
  • the heterojunction material is a hexagonal material
  • the phase change material is a cubic material.
  • the a-axis length of the heterojunction material is defined as a 1
  • the a-axis length of the phase change material is defined as a 2
  • the heterojunction material is a hexagonal system material
  • the phase change material is a cubic system
  • ⁇ 2 1.4142135623731.
  • the thickness of the phase change material layer 101 in the phase change film 1 ranges from 2nm to 100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm and so on.
  • the thickness of the phase change material layer 101 can be determined according to the corresponding operating voltage or operating current when the phase change occurs.
  • the thickness range of the heterojunction layer 102 in the phase change film 1 is 2nm-20nm, such as 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 12nm, 15nm, 17nm, 18nm, 19nm, etc.
  • the aforementioned thickness range of the heterojunction layer 102 can effectively prevent element diffusion between the phase change material layer 101 and the electrodes.
  • the thickness of the phase-change material layer 101 and the thickness of the heterojunction layer 102 are within the above-mentioned ranges, so that the phase-change memory cell can be applied to various types of phase-change memories and obtain a wider adjustment range.
  • the phase change material is doped or undoped Ge-Te binary compound, Sb-Te binary compound (such as Sb 2 Te 3 ), Bi-Te binary compound, Ge-Te binary compound, One of Sb-Te ternary compound, Ga-Sb binary compound, and Sb.
  • the phase-change material may not be doped with any other elements, or may be doped with other elements.
  • the doped elements are selected from C, N, Si, B, Sc, At least one of Ti, Y, Zr, Hf, V, Ta, W, Cu, Zn, In.
  • the atomic percentage content of the doping element in the phase change material is less than or equal to 20%, such as 15%, 12%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3% , 2%, 1%, etc.
  • the heterojunction material compatible with these phase change materials is an M-Te compound, wherein M is a transition metal element, for example, M is Ti, Zr, Pd, Cd, Mo, Mn, Ir, Rn, Pt, Sc, Ni, Ta, or Zn.
  • M is a transition metal element, for example, M is Ti, Zr, Pd, Cd, Mo, Mn, Ir, Rn, Pt, Sc, Ni, Ta, or Zn.
  • the heterojunction material can be TiTe 2 (titanium ditelluride), ZrTe 3 (zirconium telluride), PdTe 2 (palladium ditelluride), CdTe (cadmium telluride), MoTe 2 (molybdenum ditelluride ), MnTe 2 (manganese telluride), IrTe 2 (iridium telluride), RnTe (radon telluride), PtTe 2 (platinum ditelluride), Pt 2 Te 3 (platinum tritelluride), ScTe (telluride scandium), Sc 2 Te 3 (scandium tritelluride), NiTe 2 (nickel ditelluride), TaTe 2 (tantalum ditelluride), ZnTe (zinc telluride).
  • the above-mentioned heterojunction material has a stable crystal structure, which can effectively prevent the element diffusion of the phase change material in the direction of the electric field. At the same time, the lattice mismatch between the heterojunction material and the phase change material is less than or equal to 20%.
  • the phase change material layer 101 can use the heterojunction material layer 102 as a crystal growth template, it is beneficial to significantly reduce the crystallization time and increase the phase change speed of the phase change material.
  • the use of the heterojunction layer 102 is also required not to affect the identification of high and low resistances of the phase change material layer 101 to ensure data accuracy.
  • the thickness of the heterojunction layer 102 is thin, there is no higher requirement for the conductivity of the heterojunction material, because the thinner heterojunction layer 102 generally does not affect the resistance of the phase change material layer 101 Identification: When the thickness of the heterojunction layer 102 is relatively thick, a conductive heterojunction material can be used to ensure that the identification of high and low resistance values of the phase change material layer 101 is not affected and the accuracy of data is ensured.
  • phase change materials and heterojunction materials are used in combination, as long as the degree of lattice mismatch between the phase change materials and heterojunction materials used in combination is less than or equal to 20%, the combination of heterojunction materials and phase change materials The materials have the same lattice angle in the plane, and the melting point of the phase change material used in combination is lower than that of the heterojunction material.
  • phase-change thin film 1 which includes a single-layer phase-change material layer 101 formed of a binary compound Sb 2 Te 3 , and a single-layer heterojunction formed of a compound ScTe Layer 102.
  • the phase change material layer 101 and the heterojunction layer 102 are respectively formed, and the phase change material layer 101 and the heterojunction layer 102 are brought into contact.
  • the process includes: first forming a phase change material layer 101, and then forming a heterojunction layer 102 on the phase change material layer 101; or, first forming a heterojunction layer 102, and then forming a phase change material layer on the heterojunction layer 102 101.
  • the phase change material layer 101 is formed by a thin film deposition process using the phase change material as described above.
  • the heterojunction material as described above is used to form the heterojunction layer 102 through a thin film deposition process.
  • the film deposition process applicable to the embodiments of the present disclosure includes but not limited to the following: atomic layer deposition (atomic layer deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD) ), for example, Plasma Enhanced Chemical Vapor Deposition (PECVD) process, magnetron sputtering, electron beam evaporation, etc.
  • ALD atomic layer deposition
  • PVD Physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • magnetron sputtering magnetron sputtering
  • electron beam evaporation etc.
  • Magnetron sputtering is a kind of physical vapor deposition process, which has the advantages of easy control, large coating area, strong adhesion, and wide range of preparation objects.
  • the embodiments of the present disclosure can use the magnetron sputtering process to form a phase change Material layer 101 and heterojunction layer 102.
  • the sputtering gas used in the magnetron sputtering process includes but is not limited to: at least one of argon Ar, krypton Kr, xenon Xe, neon Ne, and nitrogen N2 . Due to the low price of argon, it is easy to obtain, Argon gas Ar can be selected as the working gas for magnetron sputtering.
  • the phase change film 1 can be formed by magnetron sputtering process, but also the bottom electrode layer 21 and top electrode layer 22 can be formed by magnetron sputtering process.
  • radio frequency magnetron sputtering is used, and the temperature of the substrate, that is, the temperature of the sample stage is 150° C.-350° C., for example, 200° C., 250° C., 300° C. and so on.
  • the electrode layer direct current power sputtering is used, and the substrate temperature is 20°C-40°C, for example, 25°C, 30°C, 35°C, etc.
  • phase-change memory cell provided by the embodiment of the present disclosure is based on the use of any one of the above-mentioned phase-change thin films 1, so that the phase-change memory cell has at least the following advantages:
  • the lattice mismatch between the phase change material and the heterojunction material is less than or equal to 20%, in particular, less than or equal to 10%, so that the phase change material layer 101 can grow from the heterojunction layer 102 by epitaxy Crystallization at the interface of the phase change material, and the use of the heterojunction layer 102 as a crystal growth template is beneficial to significantly reduce the crystallization time, increase the phase change speed of the phase change material, and further increase the read and write speed of the phase change memory.
  • phase change material layer 101 undergoes a phase change
  • the heterojunction layer 102 will maintain a stable crystal structure, which effectively prevents the phase change material from forming elements in the direction of the electric field. Migration is beneficial to improve the cycle life of the phase change material, and further improve the cycle life of the phase change memory unit.
  • the embodiments of the present disclosure provide such a phase-change memory unit.
  • FIG. It includes a bottom electrode layer 21, a top electrode layer 22, and an insulating dielectric layer 3; wherein, the phase change film 1 is located between the bottom electrode layer 21 and the top electrode layer 22; the insulating dielectric layer 3 is used to provide insulation isolation for the phase change memory cell , that is, when multiple phase-change memory cells are used at the same time, the insulating dielectric layer 3 is used to isolate the multiple phase-change memory cells from each other.
  • the phase-change material layer 101 and the heterojunction layer 102 are stacked in the vertical direction, which includes: the phase-change material layer 101 is located on the upper layer, and the heterojunction layer 102 is located on the lower layer; and, the phase-change material layer 101 is located in the lower layer, and the heterojunction layer 102 is located in the upper layer.
  • the arrangement of the insulating medium layer 3 can be adaptively designed according to the specific structure of the phase change memory unit, as long as the insulating medium layer 3 can be used to isolate the phase change memory unit where it is located.
  • the substrate can be used to provide support for the entire structure of the phase-change memory unit, and the phase-change memory unit is applied on the substrate so that the bottom electrode layer 21 is located on the surface of the substrate.
  • the direction of the phase-change memory cell close to the substrate is defined as the bottom direction
  • the direction of the phase-change memory cell away from the substrate is defined as the top direction.
  • the material of the substrate may be a common substrate material in the field.
  • the material of the substrate includes but is not limited to: silicon dioxide, silicon carbide, silicon wafer, sapphire, diamond, and the like.
  • organic solvents such as ethanol and/or acetone can be used to clean the surface of the substrate to remove impurities such as organic matter, oxides and metal ions on the surface of the substrate.
  • the substrate can be dried in an oven at 60°C-90°C to obtain a fully dry and clean substrate.
  • the top electrode layer 22 and the bottom electrode layer 21 can be prepared by common electrode materials in the field, and the electrode materials need to meet the following requirements: the melting point is higher than that of the phase-change material, and it is not easy to oxidation etc.
  • the materials of the top electrode layer 22 and the bottom electrode layer 21 include but are not limited to: titanium tungsten TiW (such as Ti 3 W 7 ), tungsten W, aluminum Al, titanium nitride TiN, titanium Ti, tantalum Ta, silver Ag, platinum Pt, carbon C, copper Cu, ruthenium Ru, gold Au, cobalt Co, chromium Cr, nickel Ni, iridium Ir, palladium Pd, rhodium Rh, etc.
  • the above electrode materials can be deposited into the top electrode layer 22 or the bottom electrode layer 21 by using such as Physical Vapor Deposition (Physical Vapor Deposition, PVD) process (such as magnetron sputtering).
  • Physical Vapor Deposition Physical Vapor Deposition, PVD
  • PVD Physical Vapor Deposition
  • the functions of the insulating dielectric layer 3 include at least the following: (1) forming an insulating accommodation hole so that the phase-change material layer 101 and/or the phase-change material layer 101 in the phase-change film 1
  • the junction layer 102 is confined in the insulating accommodating hole to reduce the heat required for the phase change, which is beneficial to reduce the power consumption of the phase change memory; (2) it can avoid the short circuit between the bottom electrode layer 21 and the top electrode layer 22 .
  • the insulation and heat insulation materials used for the insulating medium layer 3 include but are not limited to: silicon nitride Si 3 N 4 , silicon dioxide SiO 2 and the like.
  • the above insulating and heat insulating material may be deposited as the insulating dielectric layer 3 by using a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, for example, a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process.
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the above-mentioned phase-change memory cell further includes: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is in contact with the phase-change film 1, and the second surface of the intermediate electrode layer 23 The surface is in contact with the gate layer 4 ; the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are integrally located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the material of the intermediate electrode layer 23 includes but not limited to the following: titanium tungsten TiW (such as Ti 3 W 7 ), tungsten W, aluminum Al, titanium nitride TiN, titanium Ti, tantalum Ta, silver Ag, platinum Pt, Carbon C, copper Cu, ruthenium Ru, gold Au, cobalt Co, chromium Cr, nickel Ni, iridium Ir, palladium Pd, rhodium Rh, etc.
  • the middle electrode layer 23 can be deposited by a process such as magnetron sputtering.
  • phase-change memory cells provided by the embodiments of the present disclosure can be designed in various structures.
  • the structures of such phase-change memory cells include but are not limited to the following: (1) restricted structure; (2) T-shaped structure; (3) U-shaped groove structure; (4) L-shaped structure, etc., which are described as examples below:
  • an embodiment of the present disclosure provides a phase-change memory cell with a confinement structure. As shown in FIG. The electrode layer 21 and the substrate are in sequential contact (the substrate is not shown in the figure). That is, the bottom electrode layer 21 is formed on the top surface of the substrate, the phase change film 1 is formed on the top surface of the bottom electrode layer 21 , and the top electrode layer 22 is formed on the top surface of the phase change film 1 .
  • the insulating dielectric layer 3 is at least coated on the side of the phase change film 1, for example, as shown in Figure 2, the insulating dielectric layer 3 is coated on the outside of the phase change film 1, the bottom electrode layer 21 and the top electrode layer 22 at the same time; Alternatively, as shown in FIG. 3 , the insulating dielectric layer 3 is coated on the outside of the phase change film 1 and the bottom electrode layer 21 , and the tops of the insulating dielectric layer 3 and the phase change film 1 are connected to the top electrode layer 22 .
  • the phase-change thin film 1 includes: a phase-change material layer 101 and a heterojunction layer 102 stacked up and down, wherein the phase-change material layer 101 and the heterojunction layer 102 can be arbitrarily used as an upper layer or a lower layer.
  • the heterojunction layer 102 can be located between the phase change material layer 101 and the top electrode layer 22, or the phase change material layer 101 can also be located at the heterojunction layer 102 and top electrode layer 22 (not shown).
  • the phase change material layer 101 and the heterojunction layer 102 have the same structure and size, for example, they are all cylindrical structures with the same diameter.
  • the phase change material layer 101 and the heterojunction layer 102 have the same structure but different sizes, such as truncated cone structures of different sizes.
  • the heterojunction layer 102, the phase change material layer 101, and the bottom electrode layer 21 are stacked in sequence and are all in the shape of a truncated cone, and the radial direction of the two
  • the size gradually increases; as shown in Figure 5, along the direction from top to bottom, the top electrode layer 22, the heterojunction layer 102, the phase change material layer 101, and the bottom electrode layer 21 are stacked in sequence and are all in the shape of a truncated cone, and , the radial dimensions of the three gradually increase.
  • phase-change memory unit of the above-mentioned restricted structure it can be prepared by the following method:
  • Step 1101 Provide a cleaned substrate, and form a bottom electrode layer 21 on the surface of the substrate.
  • Step 1102 Form an insulating dielectric layer 3 on the surface of the substrate and the bottom electrode layer 21, so that the insulating dielectric layer 3 covers the bottom electrode layer 21 and the substrate and is deposited to a certain thickness. Then, the insulating dielectric layer 3 is etched to etch away the portion of the insulating dielectric layer 3 corresponding to the insulating accommodation hole, and expose the bottom electrode layer 21 to form the insulating accommodation hole on the insulating dielectric layer 3 .
  • Step 1103 According to the preparation method of the phase change film 1, the phase change film 1 is formed in the insulating accommodation hole.
  • the phase change material layer 101 is formed on the bottom electrode layer 21 in the insulating accommodation hole, and then the heterojunction layer 102 is continuously formed on the phase change material layer 101 in the accommodation hole to obtain the phase change thin film 1 .
  • Step 1104 Form a top electrode layer 22 on the top surfaces of the phase change film 1 and the insulating dielectric layer 3 to obtain a phase change memory cell.
  • phase-change memory cell with the above-mentioned restricted structure can also be designed with a gating layer, and the structure of the phase-change memory cell designed with a gating layer is described as an example below:
  • phase-change memory unit of this confinement type structure comprises top electrode layer 22, phase change
  • the phase change memory unit may also include: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is in contact with the phase change thin film 1, and the first surface of the intermediate electrode layer 23 is in contact with the phase change thin film 1.
  • the two surfaces are in contact with the gate layer 4 ; the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are integrally located between the bottom electrode layer 21 and the top electrode layer 22 .
  • top electrode layer 22 For example, as shown in Figure 6, along the direction from top to bottom, top electrode layer 22, heterojunction layer 102, phase change material layer 101, middle electrode layer 23, gate layer 4, bottom electrode layer 21 Cascade settings one by one.
  • the phase-change memory cell designed with the gate layer 4 in addition to the gate layer 4 and the middle electrode layer 23, the arrangement of the top electrode layer 22 and the phase-change film 1 can still be referred to above, and will not be repeated here. a description.
  • the preparation method of the phase-change memory cell with a restricted structure further includes: according to the specific arrangement of the gate layer 4 and the intermediate electrode layer 23 in the phase-change memory cell, adapting The gate layer 4 and the intermediate electrode layer 23 are formed accordingly.
  • step 1101 and step 1102 are performed sequentially as described above, and then step 1103 is changed so that step 1103 includes: first forming the gate layer 4 on the bottom electrode layer 21 in the insulating accommodation hole, and then sequentially The middle electrode layer 23, the phase-change material layer 101, and the heterojunction layer 102 are deposited, so that the gate layer 4, the middle electrode layer 23 and the phase-change thin film 1 are laminated and filled in the insulating accommodation hole.
  • step 1104 is performed, and step 1104 can be as described above.
  • an embodiment of the present disclosure provides a phase-change memory cell with a confinement structure. From the top to the bottom, the top electrode layer 22 , the phase-change film 1 , and the bottom electrode layer 21 are sequentially in contact. That is, the bottom electrode layer 21 is formed on the top surface of the substrate, the phase change film 1 is formed on the top surface of the bottom electrode layer 21 , and the top electrode layer 22 is formed on the top surface of the phase change film 1 .
  • the phase change material layer 101 and the heterojunction layer 102 in the phase change film 1 are covered inside and outside, for example, the heterojunction layer 102 is covered on the bottom and side of the phase change material layer 101, And the heterojunction layer 102 is even with the top surface of the phase change material layer 101 .
  • the phase-change material layer 101 covers the bottom and sides of the heterojunction layer 102 , and the phase-change material layer 101 is flat with the top surface of the heterojunction layer 102 (not shown in the figure).
  • the phase-change thin film 1 may have a cylindrical structure or a truncated conical structure.
  • the insulating dielectric layer 3 is at least coated on the side of the phase change film 1, for example, as shown in Figure 7, the insulating dielectric layer 3 is coated on the outside of the phase change film 1 and the bottom electrode layer 21, and the insulating dielectric layer 3 The top is in contact with the bottom of the top electrode layer 22 ; or, the insulating dielectric layer 3 is wrapped around the phase change film 1 , and the insulating dielectric layer 3 is also located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the phase-change memory cell with a restricted structure involved in this example may further include: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is connected to the phase-change thin film 1 contact, the second surface of the middle electrode layer 23 is in contact with the gate layer 4; For example, along the direction from top to bottom, the top electrode layer 22 , the phase change film 1 , the middle electrode layer 23 , the gate layer 4 , and the bottom electrode layer 21 are sequentially stacked.
  • phase-change memory unit of the above-mentioned restricted structure it can be prepared by the following method:
  • Step 1201 Provide a cleaned substrate, and form a bottom electrode layer 21 on the surface of the substrate.
  • Step 1202 Form an insulating dielectric layer 3 on the surface of the substrate and the bottom electrode layer 21, so that the insulating dielectric layer 3 covers the bottom electrode layer 21 and the substrate and is deposited to a certain thickness. Then the insulating dielectric layer 3 is etched to etch away the part corresponding to the insulating accommodation hole on the insulating dielectric layer 3 and expose the bottom electrode layer 21 , so that the insulating accommodation hole can be formed in the insulating dielectric layer 3 .
  • Step 1203 According to the preparation method of the phase change film 1, the phase change film 1 is formed in the insulating accommodation hole.
  • the heterojunction layer 102 is formed on the bottom electrode layer 21 in the insulating accommodating hole, and then the heterojunction layer 102 is etched to form a groove on the heterojunction layer 102, and the groove is continuously formed.
  • a phase-change material layer 101 is formed inside, so that the heterojunction layer 102 covers the bottom and sides of the phase-change material layer 101 to obtain a phase-change thin film 1 .
  • Step 1204 Form a top electrode layer 22 on the top surfaces of the phase change film 1 and the insulating dielectric layer 3 to obtain a phase change memory unit.
  • the preparation method of the phase-change memory cell with a restricted structure further includes: according to the specific arrangement of the gate layer 4 and the intermediate electrode layer 23 in the phase-change memory cell, adapting The gate layer 4 and the intermediate electrode layer 23 are formed accordingly.
  • step 1201 and step 1202 are performed sequentially as shown above, and then, an adaptive improvement is made when performing step 1203, so that step 1203 includes: first forming the gate layer 4 on the bottom electrode in the insulating accommodation hole layer 21 , and then continue to form an intermediate electrode layer 23 on the gate layer 4 . Then, continue to form the heterojunction layer 102 on the intermediate electrode layer 23 in the insulating accommodation hole, etch the heterojunction layer 102, form a groove on the heterojunction layer 102, and continue to form the heterojunction layer 102 in the groove. phase change material layer 101 to obtain a phase change thin film 1 . Finally, step 1204 is performed, and step 1204 can be as described above.
  • an embodiment of the present disclosure provides a phase-change memory cell with a T-shaped structure.
  • the phase-change memory cell with a T-shaped structure includes: a phase-change film 1 , a bottom electrode layer 21 , a top electrode layer 22 , and an insulating medium layer 3 .
  • the insulating medium layer 3 is located on the substrate, and the insulating medium layer 3 has a through hole, and the bottom electrode layer 21 is located in the through hole; the top electrode layer 22, the phase change film 1, and the insulating medium layer 3 are in sequential contact, and, The phase change film 1 is also connected to the bottom electrode layer 21 , and the bottom electrode layer 21 cooperates with the phase change film 1 to form a T-shaped structure.
  • the bottom electrode layer 21 is formed in the through hole of the insulating medium layer 3
  • the phase change film 1 is formed on the top surface of the bottom electrode layer 21 and the insulating medium layer 3 at the same time
  • the top electrode layer 22 is formed on the top surface of the phase change film 1. top surface.
  • the phase-change thin film 1 includes a phase-change material layer 101 and a heterojunction layer 102 stacked up and down, wherein the phase-change material layer 101 and the heterojunction layer 102 can be arbitrarily used as an upper layer or a lower layer.
  • the heterojunction layer 102 can be located between the phase change material layer 101 and the top electrode layer 22 , or the phase change material layer 101 can also be located between the heterojunction layer 102 and the top electrode layer 22 .
  • the structure and size of the phase change material layer 101 , the heterojunction layer 102 , and the top electrode layer 22 are the same, for example, they are cylindrical structures with the same diameter.
  • the thickness of the phase-change material layer 101 can be 20nm-150nm
  • the thickness of the heterojunction layer 101 can be 4nm-20nm
  • the thickness of the top electrode layer 22 can be 50nm-150nm. 300nm.
  • phase-change memory cell with the T-shaped structure shown in FIG. 9 can be prepared by the following method:
  • a substrate comprising a bottom electrode layer 21 and an insulating medium layer 3 is provided, and the material of the bottom electrode layer 21 may be W.
  • the substrate is alternately cleaned with acetone and ethanol to remove various impurities such as organic matter, oxides and metal ions on the surface, and baked in an oven at 80° C. for 20 minutes to fully dry it.
  • a phase change material layer 101 with a thickness of 8 nm, a heterojunction layer 102 with a thickness of 50 nm, and a top electrode layer 22 with a thickness of 50 nm were grown sequentially by magnetron sputtering.
  • the film layers above the insulating dielectric layer 3 are etched by photolithography and etching processes until the insulating dielectric layer 3 is exposed, so as to physically isolate the parts of the phase-change memory cells on top of different bottom electrode layers 21 .
  • both the bottom electrode layer 21 and the top electrode layer 22 are made of TiN, and the working parameters of magnetron sputtering are: the sputtering power supply is DC power supply, and the sputtering background vacuum is 8 ⁇ 10 -5 Pa -2 ⁇ 10 -4 Pa, the sputtering gas is Ar, and the sputtering gas pressure is 3 mTorr to 6 mTorr.
  • the magnetron sputtering parameters for the heterojunction layer 101 and the phase change material layer 102 are: the substrate temperature during sputtering is 150-300°C; wherein, the heterojunction layer 101 uses a ScTe target, and the sputtering power is 10W-20W ; The phase change material layer uses Sb 2 Te 3 target material, and the sputtering power is 7W-30W.
  • the magnetron sputtering parameters for the top electrode layer 22 are as follows: the substrate temperature is 20-40° C., the TiN target is used, and the sputtering power is 50W-250W.
  • the etching process involved in this example is reactive ion etching.
  • the T-shaped phase-change memory cell involved in this example may also include: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is connected to the phase-change thin film 1 contact, the second surface of the middle electrode layer 23 is in contact with the gate layer 4; For example, along the direction from top to bottom, the top electrode layer 22 , the phase change film 1 , the middle electrode layer 23 , the gate layer 4 , and the bottom electrode layer 21 are sequentially stacked.
  • phase change memory unit For this type of phase change memory unit, it can be prepared by the following methods:
  • Step 201 forming an insulating dielectric layer 3 on the substrate, etching the insulating dielectric layer 3 to form a through hole, filling and forming a bottom electrode layer 21 in the through hole, and making the insulating dielectric layer 3 and the bottom electrode layer 21 The top surface is flat.
  • Step 202 According to the preparation method of the phase change film, the phase change film 1 is formed on the top surfaces of the insulating dielectric layer 3 and the bottom electrode layer 21 . That is, according to the distribution order of the phase change material layer 101 and the heterojunction layer 102 in the phase change film 1, the phase change material layer 101 and the heterojunction layer 102 are sequentially formed on the top surfaces of the insulating dielectric layer 3 and the bottom electrode layer 21 , to obtain the phase change film 1.
  • Step 203 continue to form the top electrode layer 22 on the top surface of the phase change film 1 to obtain a phase change memory cell.
  • the preparation method of the T-shaped phase-change memory cell further includes: arrangement to adaptively deposit the gate layer 4 and the intermediate electrode layer 23 .
  • step 201 After step 201 is performed sequentially as shown above, then, an adaptive improvement is made when performing step 202, so that step 202 includes: forming a gate layer 4 on the top surface of the insulating dielectric layer 3 and the bottom electrode layer 21 , and then continue to form the intermediate electrode layer 23 on the gate layer 4 , and form the phase change film 1 on the intermediate electrode layer 23 .
  • step 203 can be performed as described above.
  • the embodiments of the present disclosure provide a phase-change memory cell with a U-shaped trench structure.
  • the phase-change memory cell of the U-shaped trench structure The storage unit includes: a phase change film 1 , a bottom electrode layer 21 , a top electrode layer 22 , and an insulating medium layer 3 . From the top to the bottom direction, the top electrode layer 22, the phase change film 1, and the bottom electrode layer 21 are in sequential contact, that is to say, the bottom electrode layer 21 is formed on the top surface of the substrate, and the phase change film 1 is formed on the bottom electrode layer 21 , the top electrode layer 22 is formed on the top surface of the phase change film 1 .
  • There is a U-shaped groove on the insulating dielectric layer 3 and the U-shaped groove is used for accommodating the phase-change material layer 101 and/or the heterojunction layer 102 of the phase-change thin film 1 .
  • the heterojunction layer 102 of the phase change film 1 is located on the top surface of the bottom electrode layer 21, and the insulating dielectric layer 3 with a U-shaped groove is located on the heterojunction layer. 102, a part of the phase-change material layer 101 is located inside the U-shaped groove of the insulating dielectric layer 3, and is in contact with the heterojunction layer 102, the other part of the phase-change material layer 101 covers the insulating dielectric layer 3, and the top electrode layer 22 covers The top surface of the insulating dielectric layer 3.
  • the phase-change memory cell of this U-shaped groove structure may also include: an intermediate electrode layer 23 and a gate layer 4, and the first surface of the intermediate electrode layer 23 is in contact with the phase-change film 1 In contact, the second surface of the middle electrode layer 23 is in contact with the gate layer 4 , and the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are entirely located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the heterojunction layer 102 , the middle electrode layer 23 , the gate layer 4 , and the bottom electrode layer 21 are sequentially stacked.
  • phase change memory unit For this type of phase change memory unit, it can be prepared by the following methods:
  • Step 311 Provide a cleaned substrate, form a bottom electrode layer 21 on the surface of the substrate, and spread the bottom electrode layer 21 on the top surface of the substrate.
  • Step 312 forming the heterojunction layer 102 on the surface of the bottom electrode layer 21 so that the heterojunction layer 102 covers the top surface of the bottom electrode layer 21 .
  • Step 313 forming an insulating dielectric layer 3 on the heterojunction layer 102, so that the insulating dielectric layer 3 covers the top surface of the heterojunction layer 102, and after the insulating dielectric layer 3 is deposited to a certain thickness, the insulating dielectric layer 3 is Etching is to etch away the part corresponding to the U-shaped groove on the insulating dielectric layer 3 and expose the heterojunction layer 102 , so that the U-shaped groove can be formed in the insulating dielectric layer 3 .
  • Step 314 Form the phase change material layer 101 , make the phase change material layer 101 fill the U-shaped trench and continue to deposit a certain thickness, so that the phase change material layer 101 is spread on the insulating medium layer 3 .
  • Step 315 Form a top electrode layer 22 on the top surface of the phase change material layer 101 to obtain a phase change memory cell.
  • the preparation method of this type of phase-change memory cell further includes: according to the specific arrangement of the gate layer 4 and the intermediate electrode layer 23 in the phase-change memory cell, adapting The gate layer 4 and the intermediate electrode layer 23 are selectively deposited.
  • step 311 is performed sequentially as described above, and then an adaptive improvement is made when performing step 312, so that step 312 includes: first forming a gate layer 4 on the surface of the bottom electrode layer 21, and then continuing to gate The middle electrode layer 23 is formed on the layer 4 , and the heterojunction layer 102 is formed on the surface of the middle electrode layer 23 , so that the heterojunction layer 102 covers the top surface of the middle electrode layer 23 .
  • step 313-step 315 is performed sequentially according to the above, and step 313-step 315 can be as shown above.
  • the insulating dielectric layer 3 with a U-shaped groove is located on the bottom electrode layer 21, and the heterojunction layer 102 of the phase change film 1 includes: a middle groove portion and The side tiling part, wherein the middle groove part has a U-shaped blind groove (ie, the bottom is closed).
  • the middle groove portion of the heterojunction layer 102 is located in the U-shaped groove of the insulating dielectric layer 3 , and the bottom surface of the middle groove portion is in contact with the bottom electrode layer 21 .
  • the side tile part of the heterojunction layer 102 is located on the top surface of the insulating dielectric layer 3, and the phase change material layer 101 is located between the heterojunction layer 102 and the top electrode layer 22, that is, part of the phase change material layer 101 Filling in the U-shaped blind groove of the heterojunction layer 102 , another part of the phase change material layer 101 is located on the top surface of the side flat part of the heterojunction layer 102 .
  • the phase-change memory cell of this U-shaped groove structure may further include: an intermediate electrode layer 23 and a gate layer 4, and the first surface of the intermediate electrode layer 23 is in contact with the phase-change film 1 In contact, the second surface of the middle electrode layer 23 is in contact with the gate layer 4 , and the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are entirely located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the heterojunction layer 102, the middle electrode layer 23, the gate layer 4, and the bottom electrode layer 21 are sequentially stacked, wherein the middle electrode layer 23 has a part of the top surface connected to the heterojunction layer. layer 102 , and another part of the top surface is also in contact with the insulating dielectric layer 3 .
  • phase change memory unit For this type of phase change memory unit, it can be prepared by the following methods:
  • Step 321 Provide a cleaned substrate, and form a bottom electrode layer 21 on the surface of the substrate so that the bottom electrode layer 21 covers the top surface of the substrate.
  • Step 322 Form an insulating medium layer 3 on the surface of the bottom electrode layer 21 so that the insulating medium layer 3 covers the top surface of the bottom electrode layer 21 .
  • the insulating dielectric layer 3 is deposited to a certain thickness, the insulating dielectric layer 3 is etched, and the part corresponding to the U-shaped groove on the insulating dielectric layer 3 is etched away, and the bottom electrode layer 21 is exposed, so that the A U-shaped groove is formed in the insulating dielectric layer 3 .
  • Step 323 forming a heterojunction layer 102 on the insulating dielectric layer 3, so that the heterojunction layer 102 covers the top surface of the insulating dielectric layer 3, and after the heterojunction layer 102 is deposited to a certain thickness, the heterojunction layer 102 to etch away the portion of the heterojunction layer 102 corresponding to the U-shaped blind groove, so that the U-shaped blind groove can be formed in the heterojunction layer 102 .
  • Step 324 Form the phase-change material layer 101 , make the phase-change material layer 101 fill the U-shaped blind groove and continue to deposit a certain thickness, so that the phase-change material layer 101 is spread on the heterojunction layer 102 .
  • Step 325 Form a top electrode layer 22 on the top surface of the phase change material layer 101 to obtain a phase change memory cell.
  • the preparation method of the phase-change memory cell further includes: according to the specific arrangement of the gate layer 4 and the intermediate electrode layer 23 in the phase-change memory cell, to adaptively deposit the gate layer 4 and the middle electrode layer 23 .
  • step 321 is performed sequentially as described above, and then an adaptive improvement is made when performing step 322, so that step 322 includes: first forming a gate layer 4 on the surface of the bottom electrode layer 21, and then continuing to form a gate layer 4 on the surface of the gate layer 21.
  • the intermediate electrode layer 23 is formed on the layer 4, and the insulating medium layer 3 is formed on the surface of the intermediate electrode layer 23, so that the insulating medium layer 3 covers the top surface of the intermediate electrode layer 23.
  • the insulating dielectric layer 3 is deposited to a certain thickness, the insulating dielectric layer 3 is etched to etch away the part corresponding to the U-shaped groove on the insulating dielectric layer 3 and expose the middle electrode layer 23 .
  • step 323-step 325 is performed sequentially according to the above, and step 323-step 325 can be as shown above.
  • the embodiments of the present disclosure provide a phase-change memory cell with an L-shaped structure.
  • the phase-change memory cell with an L-shaped structure It includes: a phase change film 1 , a bottom electrode layer 21 , a top electrode layer 22 , and an insulating medium layer 3 .
  • There is an L-shaped hole on the insulating dielectric layer 3 and the L-shaped hole is used for accommodating the phase-change material layer 101 and/or the heterojunction layer 102 .
  • the phase-change material layer 101 is positioned in the L-shaped hole on the insulating medium layer 3 (that is, the phase-change material layer 101 is an L-shaped hole adapted to the L-shaped hole. structure), the top and bottom surfaces of the phase change material layer 101 and the insulating dielectric layer 3 are flat. In this case, along the direction from top to bottom, the top electrode layer 22 , the heterojunction layer 102 , the phase change material layer 101 and the insulating medium layer 3 as a whole, and the bottom electrode layer 21 are sequentially stacked.
  • the phase-change memory cell with an L-shaped structure may further include: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is in contact with the phase-change film 1, The second surface of the middle electrode layer 23 is in contact with the gate layer 4 , and the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are entirely located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the bottom electrode layer 21, the gate layer 4, and the middle electrode layer 23 are stacked in sequence, and the phase-change material layer 101 and the insulating medium layer 3 are integrally located on the top surface of the middle electrode layer 23. superior.
  • phase-change memory unit of this L-shaped structure it can be prepared by the following method:
  • Step 411 Provide a cleaned substrate, form a bottom electrode layer 21 on the surface of the substrate, and spread the bottom electrode layer 21 on the top surface of the substrate.
  • Step 412 forming a phase-change material layer 101 on the surface of the bottom electrode layer 21 , and etching the phase-change material layer 101 so that the phase-change material layer 101 has an L-shaped structure.
  • Step 413 continue to form the insulating dielectric layer 3 on the bottom electrode layer 21, make the insulating dielectric layer 3 cover the top surface of the bottom electrode layer 21 and fill in the L-shaped groove of the phase change material layer 101, and make the insulating dielectric layer 3 and the top surface of the phase change material layer 101.
  • Step 414 forming a heterojunction layer 102 on the top surfaces of the insulating dielectric layer 3 and the phase change material layer 101 , so that the heterojunction layer 102 is laid on the top surfaces of the insulating dielectric layer 3 and the phase change material layer 101 .
  • Step 415 forming the top electrode layer 22 on the top surface of the heterojunction layer 102 to obtain the phase change memory cell.
  • the preparation method of the phase-change memory cell further includes: A specific arrangement is used to adaptively deposit the gate layer 4 and the middle electrode layer 23 .
  • step 411 is performed sequentially, and then, when step 412 is performed, an adaptive improvement is made, so that step 412 includes: first forming a gate layer 4 on the surface of the bottom electrode layer 21, and continuing to form a gate layer 4 on the surface of the gate layer.
  • step 412 includes: first forming a gate layer 4 on the surface of the bottom electrode layer 21, and continuing to form a gate layer 4 on the surface of the gate layer.
  • Form an intermediate electrode layer 23 on the intermediate electrode layer 23 form a phase-change material layer 101 on the surface of the intermediate electrode layer 23, and etch the phase-change material layer 101, so that the phase-change material layer 101 has an L-shaped structure.
  • step 413-step 415 is performed sequentially according to the above, and step 413-step 415 can be as shown above.
  • both the phase change material layer 101 and the heterojunction layer 102 are designed as an L-shaped structure, and one of the phase change material layer 101 and the heterojunction layer 102 Seat in another L-shaped groove.
  • the phase-change material layer 101 is seated in the L-shaped groove of the heterojunction layer 102
  • the phase-change material layer 101 and the heterojunction layer 102 constitute a phase-change film 1 with an L-shaped structure
  • the phase-change film 1 seated in the L-shaped hole on the insulating medium layer 3 so that the phase change film 1 and the insulating medium layer 3 are entirely located between the top electrode layer 22 and the bottom electrode layer 21 .
  • the phase-change memory cell with an L-shaped structure may further include: an intermediate electrode layer 23 and a gate layer 4, the first surface of the intermediate electrode layer 23 is in contact with the phase-change film 1, The second surface of the middle electrode layer 23 is in contact with the gate layer 4 , and the phase change film 1 , the middle electrode layer 23 and the gate layer 4 are entirely located between the bottom electrode layer 21 and the top electrode layer 22 .
  • the bottom electrode layer 21, the gate layer 4, and the middle electrode layer 23 are stacked in sequence, and the whole formed by the phase change film 1 and the insulating medium layer 3 is located on the top surface of the middle electrode layer 23.
  • phase-change memory unit of this L-shaped structure it can be prepared by the following method:
  • Step 421 Provide a cleaned substrate, and form a bottom electrode layer 21 on the surface of the substrate so that the bottom electrode layer 21 covers the top surface of the substrate.
  • Step 422 Form a heterojunction layer 102 on the surface of the bottom electrode layer 21, and etch the heterojunction layer 102, so that the heterojunction layer 102 has an L-shaped structure, and continue to form the phase change material layer 101 to make the phase change
  • the material layer 101 fills and seats the L-shaped groove on the heterojunction layer 102 , and then, the phase-change material layer 101 is etched, so that the phase-change material layer 101 also forms an L-shaped structure accordingly.
  • Step 423 continue to form the insulating dielectric layer 3 on the bottom electrode layer 21, so that the insulating dielectric layer 3 covers the top surface of the bottom electrode layer 21 and fills in the L-shaped groove of the phase change material layer 101, finally making the insulating dielectric layer 3 , the top surfaces of the phase change material layer 101 and the heterojunction layer 102 are flat.
  • Step 424 Form the top electrode layer 22 on the top surfaces of the insulating dielectric layer 3, the phase change material layer 101 and the heterojunction layer 102 to obtain the phase change memory cell.
  • the preparation method of the phase-change memory cell further includes: according to the specific arrangement of the gate layer 4 and the intermediate electrode layer 23 in the phase-change memory cell , to adaptively deposit the gate layer 4 and the middle electrode layer 23 .
  • step 421 is performed sequentially as shown above, and then, an adaptive improvement is made when performing step 422 and step 423, so that step 422 includes: first forming a gate layer 4 on the surface of the bottom electrode layer 21, and continuing to The intermediate electrode layer 23 is formed on the gate layer 4 , the heterojunction layer 102 is formed on the surface of the intermediate electrode layer 23 , and the heterojunction layer 102 is etched to make the heterojunction layer 102 into an L-shaped structure. Then, continue to form the phase-change material layer 101, so that the phase-change material layer 101 fills the L-shaped groove on the heterojunction layer 102, and then etch the phase-change material layer 101, so that the phase-change material layer 101 also becomes L-shaped accordingly. type structure.
  • Step 423 includes: continue to form the insulating dielectric layer 3 on the intermediate electrode layer 23, make the insulating dielectric layer 3 cover the top surface of the intermediate electrode layer 23 and fill in the L-shaped groove of the phase change material layer 101, and finally make the insulating dielectric layer 3 The top surfaces of layer 3, phase change material layer 101 and heterojunction layer 102 are flat. Finally, proceed to step 424 as described above.
  • an embodiment of the present disclosure provides a phase-change memory cell with a cylindrical structure, which includes: a phase-change film 1, an internal electrode layer 24 and the outer electrode layer 25; the inner electrode layer 24, the phase change thin film 1, and the outer electrode layer 25 are coated sequentially from inside to outside along the radial direction.
  • the raw material composition of the internal electrode layer 24 and the external electrode layer 25 may be the same as that of the above-mentioned bottom electrode layer 21 and top electrode layer 22 .
  • the phase change material layer 101 covers the outside of the heterojunction layer 102, that is, the heterojunction layer 102 covers the outside of the internal electrode layer 24 along the circumferential direction.
  • the phase-change material layer 101 covers the outside of the heterojunction layer 102 along the circumferential direction, and the external electrode layer 25 covers the outside of the phase-change material layer 101 along the circumferential direction.
  • the heterojunction layer 102 wraps the phase change material layer 101 outside, that is, the phase change material layer 101 wraps the outside of the internal electrode layer 24 along the circumferential direction, and the heterojunction layer 102 Covering the phase change material layer 101 in the circumferential direction, the external electrode layer 25 covers the heterojunction layer 102 in the circumferential direction (not shown in the figure).
  • the internal electrode layer 24 located at the center of the phase-change memory cell may be in the shape of a solid cylinder, or may be in the shape of a ring as shown in FIG. 19 .
  • the shape of the internal electrode layer 24 is arbitrarily selected according to the process conditions during preparation. No matter which shape is selected for the internal electrode layer 24, when it is used in a phase-change memory array, when the structural steps shown in Figure 23 are carried out, the The obtained array structure is also the same.
  • phase-change memory cell with a cylindrical structure involved in the above example take the phase-change material layer 101 wrapped on the outside of the heterojunction layer 102 as an example to illustrate the preparation method of the phase-change memory cell with this structure, which is as follows Shown:
  • Step 511 Provide a cleaned substrate, form an external electrode layer 25 with a certain thickness on the surface of the substrate, and spread the external electrode layer 25 on the top surface of the substrate.
  • Step 512 Etching the outer electrode layer 25 to form a ring structure, and then forming a heterojunction layer 102 on the inner wall of the outer electrode layer 25, and the formed heterojunction layer 102 is also a ring structure.
  • Step 513 Polish the inner wall of the heterojunction layer 102, and then form a phase change material layer 101 on the inner wall of the heterojunction layer 102, and the formed phase change material layer 101 is also a ring structure.
  • Step 514 Polish the inner wall of the phase change material layer 101, and then form an internal electrode layer 24 on the inner wall of the phase change material layer 101, wherein the internal electrode layer 24 can be formed into a ring structure, or can be formed into a solid cylinder shape structure (that is, it only needs to fill the round hole of the phase change material layer 101).
  • step 1512 is changed so that the phase change material is formed on the inner wall of the outer electrode layer 25 layer 101 , change step 1513 to form the heterojunction layer 102 on the inner wall of the phase change material layer 101 , and change step 1514 to form the inner electrode layer 24 on the inner wall of the heterojunction layer 102 .
  • the embodiment of the present disclosure provides another phase-change memory cell with a cylindrical structure.
  • the phase-change memory cell includes: a phase-change film 1, an internal electrode Layer 24, middle electrode layer 23, gate layer 4 and outer electrode layer 25; Wherein, inner electrode layer 24, phase change thin film 1, middle electrode layer 23, gate layer 4, outer electrode layer 25 are arranged radially from the inside To the outside in order to cover.
  • the phase change material layer 101 covers the outside of the heterojunction layer 102, that is, the heterojunction layer 102 covers the outside of the internal electrode layer 24 along the circumferential direction, and the phase change material layer 101 covers the outside of the internal electrode layer 24 along the circumferential direction.
  • the circumferential direction is wrapped around the outside of the heterojunction layer 102
  • the intermediate electrode layer 23 is wrapped around the outside of the phase change material layer 101 along the circumferential direction
  • the gate layer 4 is wrapped around the outside of the middle electrode layer 23 along the circumferential direction
  • the outer electrode layer 25 covers the outside of the middle electrode layer 23 along the circumferential direction.
  • the heterojunction layer 102 wraps the phase change material layer 101 outside, that is, the phase change material layer 101 wraps the outside of the internal electrode layer 24 along the circumferential direction, and the heterojunction layer 102 Covering the outside of the phase change material layer 101 along the circumferential direction, the intermediate electrode layer 23 covering the outside of the heterojunction layer 102 along the circumferential direction, and the gate layer 4 covering the outside of the intermediate electrode layer 23 along the circumferential direction Externally, the outer electrode layer 25 covers the outside of the middle electrode layer 23 along the circumferential direction.
  • the internal electrode layer 24 located at the center of the phase-change memory cell may be in the shape of a solid cylinder, or may be in the shape of a ring.
  • phase-change memory cell with a cylindrical structure involved in the above example take the phase-change material layer 101 wrapped on the outside of the heterojunction layer 102 as an example to illustrate the preparation method of the phase-change memory cell with this structure, which is as follows Shown:
  • Step 521 Provide a cleaned substrate, and form an external electrode layer 25 with a certain thickness on the surface of the substrate, so that the external electrode layer 25 is spread on the top surface of the substrate.
  • Step 522 Etching the outer electrode layer 25 to form a ring structure, and then forming a heterojunction layer 102 on the inner wall of the outer electrode layer 25, and the formed heterojunction layer 102 is also a ring structure.
  • Step 523 Polish the inner wall of the heterojunction layer 102, and then form a phase change material layer 101 on the inner wall of the heterojunction layer 102, and the formed phase change material layer 101 is also a ring structure.
  • Step 524 Polish the inner wall of the phase change material layer 101, and then form the intermediate electrode layer 23 on the inner wall of the phase change material layer 101, and the formed intermediate electrode layer 23 is also a ring structure.
  • Step 525 Polish the inner wall of the intermediate electrode layer 23, and then form a gate layer 4 on the inner wall of the intermediate electrode layer 23, and the formed gate layer 4 is also a ring structure.
  • Step 526 Polish the inner wall of the gate layer 4, and then form the internal electrode layer 24 on the inner wall of the gate layer 4, wherein the internal electrode layer 24 can be formed into a ring structure, or can be formed into a solid cylindrical structure (That is, it only needs to fill the round hole of the phase change material layer 101).
  • step 522 is changed to form a phase change on the inner wall of the outer electrode layer 25
  • change step 523 to form the heterojunction layer 102 on the inner wall of the phase change material layer 101
  • change step 524 to form the intermediate electrode layer 23 on the inner wall of the heterojunction layer 102 .
  • the preparation method of the phase-change memory unit includes: preparing the phase-change thin film 1, and preparing the phase-change thin film 1 further includes: respectively forming the phase-change material layer 101 and the heterojunction layer 102, and make the phase change material layer 101 and the heterojunction layer 102 contact.
  • the process includes: first forming a phase change material layer 101, and then forming a heterojunction layer 102 on the phase change material layer 101; or, first forming a heterojunction layer 102, and then forming a phase change material layer on the heterojunction layer 102 101.
  • the phase change material layer 101 is formed by a thin film deposition process using the phase change material as described above.
  • the heterojunction material as described above is used to form the heterojunction layer 102 through a thin film deposition process.
  • the thin film deposition processes applicable to the embodiments of the present disclosure include but are not limited to the following: atomic layer deposition (atomic layer deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), for example, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, magnetron sputtering, electron beam evaporation, etc.
  • atomic layer deposition atomic layer deposition
  • PVD Physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • magnetron sputtering magnetron sputtering
  • electron beam evaporation etc.
  • Magnetron sputtering is a kind of physical vapor deposition process, which has the advantages of easy control, large coating area, strong adhesion, and wide range of preparation objects.
  • the embodiments of the present disclosure can use the magnetron sputtering process to form a phase change Material layer 101 and heterojunction layer 102.
  • an embodiment of the present disclosure further provides a phase-change memory array, which includes: any one of the above-mentioned phase-change memory cells 100 .
  • the structures of the plurality of phase-change memory cells 100 included in the phase-change memory array are the above-mentioned restricted structure, T-shaped structure, U-shaped trench structure or L-shaped structure.
  • FIG. 21 shows a corresponding phase change memory array when the phase change memory unit 100 is a confinement structure.
  • a single phase-change memory cell 100 shown in FIG. 21 it can be prepared by the following method:
  • a substrate including a metal layer as the bit line layer 300 is provided, and the material of the metal layer may be W.
  • the substrate containing the bit line layer 300 is alternately cleaned with acetone and ethanol to remove various impurities such as organic matter, oxides and metal ions on the surface, and baked in an oven at 80° C. for 20 minutes to fully dry it.
  • the bottom electrode 21 , the gate layer 4 , the middle electrode layer 23 , the phase change material layer 101 , the heterojunction layer 102 , and the top electrode layer 22 are grown sequentially by magnetron sputtering.
  • Each film layer above the bit line layer 300 is etched by photolithography and etching processes until the bit line layer 300 is exposed.
  • the insulating dielectric layer 3 is deposited through a PECVD process until it completely covers each film layer.
  • the material of the insulating dielectric layer 3 is selected from Si 3 N 4 .
  • the excess insulating dielectric layer 3 is removed through a polishing process until the top electrode layer 22 is exposed, and finally a metal layer is grown on the top electrode layer 22 as the word line layer 200 .
  • both the bottom electrode layer 21 and the top electrode layer 22 are made of TiN, and the working parameters of magnetron sputtering are: the sputtering power supply is DC power supply, and the sputtering background vacuum is 8 ⁇ 10 -5 Pa ⁇ 2 ⁇ 10 -4 Pa, the sputtering gas is Ar, and the sputtering gas pressure is 3mTorr ⁇ 6mTorr.
  • the magnetron sputtering parameters for the heterojunction layer 101 and the phase change material layer 102 are: the substrate temperature during sputtering is 150-300°C; wherein, the heterojunction layer 101 uses a ScTe target, and the sputtering power is 10-20W ; The phase change material layer uses Sb 2 Te 3 target material, and the sputtering power is 7W-30W.
  • the magnetron sputtering parameters for the top electrode layer 22 are as follows: the substrate temperature is 20-40° C., the TiN target is used, and the sputtering power is 50W-250W.
  • the etching process involved in this example is reactive ion etching.
  • the phase change memory array includes a word line layer 200 , a bit line layer 300 , a plurality of word lines 400 and a plurality of bit lines 500 in addition to the above-mentioned plurality of phase change memory cells 100 .
  • phase-change memory cells 100 are arranged in an array, for example, any adjacent four phase-change memory cells 100 form a rectangular shape, and the top electrode layer 22 of each phase-change memory cell 100 is connected to a word line layer 200, each The bottom electrode layer 21 of a phase change memory cell 100 is connected to the bit line layer 300 .
  • Multiple word lines 400 are arranged sequentially in rows, multiple bit lines 500 are sequentially arranged in columns, multiple rows of word lines 400 and multiple rows of bit lines 500 cooperate to form an array suitable for multiple phase change memory cells 100 .
  • Each phase-change memory cell 100 is located in a matrix subunit composed of word lines 400 and bit lines 500, and the top electrode layer 22 of each phase-change memory cell 100 is connected to the word line layer 200 and the bit line 500 of the corresponding column.
  • the bottom electrode layer 21 of each phase change memory cell 100 is connected to the word line 400 of the corresponding row through the bit line layer 300 connected thereto.
  • a plurality of word lines 400 arranged in rows are connected to the row selection circuit A1, and the row selection circuit A1 can be driven by the row voltage control circuit B1; a plurality of bit lines 500 arranged in columns are connected It is connected with the column selection circuit A2, and the column selection circuit A2 can be driven by the column voltage control circuit B2.
  • the read-write circuit C is connected to the row voltage control circuit B1 or the column voltage control circuit B2 respectively, so that the read-write circuit C controls the row voltage via the row voltage control circuit B1 or the column voltage control circuit B2 by receiving the command from the processor.
  • the selection circuit A1 or the column selection circuit A2 performs read and write operations on the selected phase-change memory cell 100 .
  • the multiple phase-change memory cells 100 included in the phase-change memory array are the phase-change memory cells 100 of the above-mentioned cylindrical structure, and these phase-change memory cells 100 are located on the same layer, see FIGS. 22-23 ,
  • the external electrode layers 25 of these phase-change memory cells 100 are connected to each other to form an integral electrode substrate 250 , that is, the electrode substrate 250 can be shared by multiple phase-change memory cells 100 .
  • the phase-change memory array includes, in addition to the above-mentioned plurality of phase-change memory cells 100, a plurality of insulating dielectrics 600, a plurality of first metal connecting columns 700, A plurality of second metal connection pillars 800 , a plurality of word lines 400 and a plurality of bit lines 500 .
  • phase-change memory cells 100 are arranged in an array, for example, any three adjacent phase-change memory cells 100 can form an equilateral triangle.
  • the insulating medium 600 is strip-shaped, such as a rectangular strip-shaped structure. Any insulating medium 600 runs through a plurality of phase-change memory cells 100 in the same row.
  • the internal electrode layer 24 is a ring-shaped structure. Viewed from the radial direction , the width of the insulating medium 600 is equal to or slightly larger than the diameter of the inner ring of the inner electrode layer 24 . Viewed from the axial direction, the top surface and the bottom surface of the insulating medium 600 are level with the top and bottom surfaces of the phase change memory cell 100 .
  • any phase-change memory cell 100 is correspondingly connected to a first metal connecting column 700, the first metal connecting column 700 is, for example, cylindrical, and the bottom of the first metal connecting column 700 is fixed on the insulating medium 600 at the corresponding position.
  • the bottom of a metal connecting post 700 is also connected to the internal electrode layer 24 of the corresponding phase change memory cell 100 (realized by making the diameter of the first metal connecting post 700 larger than the width of the insulating medium 600, and at the same time, the first metal connecting post 700 The diameter is smaller than the outer diameter of the heterojunction layer 102 to prevent the heterojunction layer 102 from short-circuiting).
  • phase-change memory cells 100 in the same column correspond to one bit line 500 , and the bit line 500 is connected to the top of the first metal connection pillar 700 on the phase-change memory cells 100 in the same column.
  • a plurality of second metal connecting posts 800 are, for example, cylinders
  • a plurality of second metal connecting pillars 800 are arranged in a row, and each word line 400 is connected to the top of one second metal connecting pillar 800 .
  • phase-change memory array with a single-layer phase-change memory unit 100 can be prepared by the following method:
  • a first intermediate array is provided.
  • a plurality of phase-change memory cells 100 are arranged in an array, so that any adjacent three phase-change memory cells 100 form an equilateral triangle.
  • the phase change memory cell 100 may not include the gate layer 4 , or may include the gate layer 4 .
  • the phase change memory cell 100 does not include the gate layer 4 as an example to illustrate the preparation method of the phase change memory array.
  • holes are opened on the first intermediate array to form multiple rows of filling holes, and then an insulating medium 600 is filled in each row of filling holes to form a second intermediate array.
  • the width of the filling hole is equal to or slightly larger than the diameter of the inner ring of the inner electrode layer 24 , and viewed from the axial direction, the filling hole runs through the top and bottom of the first middle array.
  • a plurality of first metal connection columns 700 are formed on the second intermediate array, so that the bottoms of the first metal connection columns 700 are fixed on the insulating medium 600, and at the same time, the bottoms of the first metal connection columns 700 are also connected to the corresponding phase
  • the internal electrode layer 24 of the variable memory cell 100 is connected.
  • a strip metal layer is connected to the top of the first metal connecting pillar 700 in the same row as the bit line 500 .
  • Second metal connecting posts 800 are respectively formed on the regions isolated by the insulating medium 600 on the external electrode layer 25, and a plurality of second metal connecting posts 800 are arranged in a row, and then, on top of the plurality of second metal connecting posts 800
  • Another strip-shaped metal layer is connected as the word line 400 to finally form the above-mentioned phase-change memory array, and the structure of the phase-change memory array can also refer to FIG. 25 .
  • phase-change memory cells 100 are selected through word line 400 and bit line 500 to perform read and write operations, erase operations are performed by applying narrow and high nanosecond-level electrical pulses, and erase operations are performed by wide and low nanosecond-level electrical pulses.
  • the last low voltage is used to read the resistance state after the operation; when the phase change memory cell 100 cooperates with the gate layer 4, it can prevent the influence of the leakage current of the erase operation on the adjacent phase change memory cell 100.
  • phase-change memory cells 100 located on different layers, that is to say, the phase-change memory array includes multi-layer phase-change memory sub-arrays, wherein the multi-layer phase-change memory sub-arrays are distributed sequentially along the direction from top to bottom and form steps, An insulating medium layer 3 is used to separate adjacent two phase-change memory sub-arrays.
  • Embodiments of the present disclosure refer to this type of phase-change memory array as a three-dimensional stacking memory array.
  • phase-change memory sub-array in each layer is the same as that of the above-mentioned phase-change memory array in which the phase-change memory unit 100 is located in the same layer, and will not be elaborated here.
  • the preparation method is as follows:
  • the multi-layer outer electrode layers 25 and the multi-layer insulating dielectric layers 3 are stacked alternately, and the outer electrode layers 25 and the insulating dielectric layers 900 are stacked and arranged in a direction from top to bottom, and distributed in steps, so that each The outer electrode layers 25 of each layer are used as electrode substrates 250 .
  • a plurality of phase-change memory cells 100 are formed on each layer of the external electrode layer 25 , that is, on each layer of the electrode substrate 250 , thereby forming a multi-layer first intermediate array.
  • the structure of the first intermediate array is the same as that of the above-mentioned first intermediate array, and will not be repeated here.
  • each layer of the first intermediate array is processed to finally form a multi-layer phase change memory sub-array.
  • the second metal connection pillars 800 are respectively formed on the regions separated by the insulating medium 600 on the corresponding outer electrode layer 25 at the steps of different layers, and the strip metal layers are connected one by one as the word line 400, finally forming A three-dimensional stacked memory array with multilayer phase change memory sub-arrays as shown in FIG. 28 .
  • phase-change memory cells 100 are selected through word line 400 and bit line 500 to perform read and write operations, erase operations are performed by applying narrow and high nanosecond-level electrical pulses, and erase operations are performed by wide and low nanosecond-level electrical pulses.
  • the last low voltage is used to read the resistance state after the operation; when the phase change memory cell 100 cooperates with the gate layer 4, it can prevent the influence of the leakage current of the erase operation on the adjacent phase change memory cell 100.
  • variable storage unit 100 realizes the effect of three-dimensional high-density storage without increasing the storage area to the greatest extent.
  • an embodiment of the present disclosure also provides a phase change memory, which includes a plurality of any one of the above phase change memory cells.
  • the phase-change memory involved in the embodiments of the present disclosure can be regarded as a phase-change memory chip.
  • the phase-change memory provided by the embodiments of the present disclosure has at least the following advantages: high stability, good repeatability, fast read and write speed, high memory density, and low cost.
  • phase-change memory including a phase-change memory unit, which includes: a communication-connected phase-change memory 1001, a dynamic random access memory 2001, a cache 3001, a processor 4001, and a solid-state hard disk 5001, When applied, the phase change memory 1001 and the dynamic random access memory 2001 can be used as a hybrid memory.
  • phase-change memory unit comprises: the phase-change memory 1001 of communication connection, cache 3001, processor 4001 and solid-state hard disk 5001, when applying, phase-change memory 100 alone as memory.
  • the structure of the phase change memory involved in the embodiments of the present disclosure includes but is not limited to: 1R structure, 1T1R structure, or 1D1R structure.
  • phase change memory including the phase change memory unit involved in the embodiments of the present disclosure can cooperate with the dynamic random access memory, and can even replace the dynamic random access memory as the memory, which is beneficial to increase the density of the memory (for example, it can reach 4F 2 High density), easy to perform 3-dimensional integration with gate devices, compatible with CMOS process, reduce memory cost, and avoid the power consumption problem caused by the continuous refresh of dynamic random access memory.
  • an embodiment of the present disclosure further provides a storage device, the storage device includes a controller and any phase-change memory described above, and the controller is used to store data in the phase-change memory core.
  • the controller reads and writes the data stored in the storage device, and communicates interactively with the external interface.
  • the storage device may be configured to store various types of data, such data may be contact data, phonebook data, messages, pictures, videos, etc., and may also be instructional data.
  • the storage devices involved in the embodiments of the present disclosure may be configured in various types, for example, including but not limited to: memory, hard disk, magnetic disk, optical disk, and so on.
  • an embodiment of the present disclosure further provides an electronic device, where the electronic device includes a processor, and the above-mentioned phase-change memory or the above-mentioned storage device, where the phase-change memory is used to store data accessed by the processor.
  • the electronic equipment includes, but is not limited to: computers, mobile phones, printers, cameras, music playback equipment, digital broadcasting equipment, messaging equipment, game control equipment, medical equipment, fitness equipment, personal digital assistants, etc.
  • a plurality includes two or more, and each refers to each of the corresponding plurality, any refers to any one of the corresponding plurality.

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Abstract

本申请公开了相变存储单元、相变存储器、电子设备及制备方法，属于半导体存储技术领域。该相变存储单元包括：相变薄膜，该相变薄膜包括：一层相变材料层和一层异质结层，所述相变材料层与所述异质结层相接触；所述相变材料层采用相变材料形成，所述异质结层采用异质结材料形成；所述异质结材料与所述相变材料的晶格失配度小于或等于20％；所述异质结材料与所述相变材料的接触晶面具有相同的晶格夹角；以及，所述异质结材料的熔点大于所述相变材料的熔点。该相变存储单元具有结构简单，操作可靠性强，稳定性强，读写速度快，使用寿命长等优点。

Description

相变存储单元、相变存储器、电子设备及制备方法
本申请要求于2021年06月11日提交的申请号为202110655982.8、发明名称为“相变存储单元、相变存储器、电子设备及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储技术领域，特别涉及相变存储单元、相变存储器、电子设备及制备方法。
背景技术
相变存储器以相变材料作为存储介质，相变材料能够在晶态和非晶态之间进行可逆转变，相变存储器利用相变材料在非晶态和晶态时对应的高、低电阻率的差异来实现数据“0”和“1”的存储，相变材料的选择对于相变存储器的读写速度具有重要的影响。
相关技术提供了一种超晶格相变材料，其由多层GeTe薄膜和多层Sb 2Te 3薄膜交替叠合而成，利于提高相变存储器的读写速度。但是，该超晶格相变材料在作业过程中，Te元素和Sb元素向不同的电场方向迁移，使得相变材料内部形成富Sb区域和富Te区域，这样不利于超晶格相变材料的反复擦写，容易降低其循环寿命。
公开内容
鉴于此，本公开提供了相变存储单元、相变存储阵列、相变存储器及电子设备及制备方法，能够解决上述技术问题。
具体而言，包括以下的技术方案：
一方面，本公开实施例提供了一种相变存储单元，所述相变存储单元包括：相变薄膜，所述相变薄膜包括：一层相变材料层和一层异质结层，所述相变材料层与所述异质结层相接触；
所述相变材料层采用相变材料形成，所述异质结层采用异质结材料形成；
所述异质结材料与所述相变材料的晶格失配度小于或等于20％；所述异质结材料与所述相变材料的接触晶面具有相同的晶格夹角；以及，所述异质结材料的熔点大于所述相变材料的熔点。
本公开实施例提供的相变存储单元使用了异质结层，异质结层采用异质结材料形成，由于异质结材料与相变材料的晶格失配度小于或等于20％，并且，异质结材料与相变材料的接触晶面具有相同的晶格夹角，这样，相变材料层可以通过外延生长的方式在异质结层的界面上进行结晶，使得异质结层能够作为相变材料层的结晶模板，加速相变材料的结晶速度，提高相变材料的相变速度，从而增加其作业速度。由于异质结材料的熔点大于相变材料的熔点，在相变材料层发生相变时，异质结层会保持稳定的晶体结构，有效阻止相变材料在电场方向上的元素迁移，并减小相变材料与电极之间的扩散，利于提高相变材料层的循环寿命。
另外，该相变存储单元中，相变薄膜包括一层相变材料层和一层异质结层，这不仅避免了多层界面容易出现的界面问题和操作不稳定问题，还使得相变存储单元更利于设计成常见的限制型结构。采用单层相变材料层和单层异质结层的相变存储单元，其结构简单，制备方法也相应简单，易于实现。具体而言，相比于复杂的多层超晶格结构，该相变薄膜1的制备工艺更加容易精确控制，从而提升器件良率。同时，单层结构的相变薄膜1的电学操作更易于控制，可以获得更加稳定的电阻分布(而多层超晶格结构更容易出现相变层之间的元素扩散，导致器件的循环操作寿命降低)。
本公开实施例中，相变材料层使用的相变材料与异质结层使用的异质结材料的晶体结构类似，或者，至少使相变材料与异质结材料的接触晶面的晶型相似，以使两者获得更高的晶格匹配度，进而使得异质结材料能够作为相变材料的结晶模板。
在一些可能的实现方式中，所述异质结材料与所述相变材料均为六方晶系材料时，所述异质结材料的a轴与所述相变材料的a轴的长度差小于或等于20％。
在一些可能的实现方式中，所述异质结材料为六方晶系材料，且所述相变材料为立方晶系材料时，将所述异质结材料的a轴长度定义为a，将所述相变材料的a轴长度定义为a，a与√2a 2的差小于或等于20％。
在一些可能的实现方式中，所述相变材料层的厚度为2nm-100nm，例如为10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm等。对于相变材料层101的厚度，可以根据其发生相变时对应的操作电压或者操作电流的大小来确定。
所述异质结层的厚度为2nm-20nm，例如为2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、12nm、15nm、17nm、18nm、19nm等。异质结层的上述厚度范围能够满足有效阻止相变材料层与电极之间的元素扩散。
在一些可能的实现方式中，所述相变材料为掺杂或者未掺杂的Ge-Te二元化合物、Sb-Te二元化合物、Bi-Te二元化合物、Ge-Sb-Te三元化合物、Ga-Sb二元化合物、Sb中的一种；
所述异质结材料为M-Te化合物，其中，M为过渡金属元素。异质结材料可以为TiTe 2(二碲化钛)、ZrTe 3(碲化锆)、PdTe 2(二碲化钯)、CdTe(碲化镉)、MoTe 2(二碲化钼)、MnTe 2(碲化锰)、IrTe 2(碲化铱)、RnTe(碲化氡)、PtTe 2(二碲化铂)、Pt 2Te 3(三碲化二铂)、ScTe(碲化钪)、Sc 2Te 3(三碲化二钪)、NiTe 2(二碲化镍)、TaTe 2(二碲化钽)、ZnTe(碲化锌)。
在一些可能的实现方式中，所述M为Ti、Zr、Pd、Cd、Mo、Mn、Ir、Rn、Pt、Sc、Ni、Ta、或者Zn。
在一些可能的实现方式中，所述相变材料为掺杂材料时，掺杂元素选自C、N、Si、B、Sc、Ti、Y、Zr、Hf、V、Ta、W、Cu、Zn、In中的至少一种。
上述种类的相变材料与异质结材料组合使用时，只要满足组合使用的相变材料与异质结材料的晶格失配度小于或等于20％，组合使用的异质结材料与相变材料在面内具有相同的晶格夹角，并且，组合使用的相变材料的熔点小于异质结材料的熔点即可。
在一些可能的实现方式中，所述相变存储单元还包括：底电极层、顶电极层、绝缘介质层；
所述相变薄膜位于所述底电极层和所述顶电极层之间；
所述绝缘介质层用于为所述相变存储单元提供绝缘隔离作用。
在一些可能的实现方式中，所述相变存储单元还包括：中间电极层和选通层；
所述中间电极层的第一表面与所述相变薄膜接触，所述中间电极层的第二表面与所述选通层接触；
所述相变薄膜、所述中间电极层和所述选通层整体位于所述底电极层和所述顶电极层之间。
在一些可能的实现方式中，所述相变存储单元为限制型结构、T型结构、U型沟槽结构、或者L字型结构。
在一些可能的实现方式中，所述相变存储单元为圆柱形结构，所述相变存储单元还包括：内电极层和外电极层；
所述内电极层、所述相变薄膜、所述外电极层沿径向方向由内至外依次包覆。
在一些可能的实现方式中，所述内电极层为实心圆柱状或者圆环状。
在一些可能的实现方式中，所述相变存储单元为圆柱形结构，所述相变存储单元还包括：内电极层、中间电极层、选通层和外电极层；
所述内电极层、所述相变薄膜、所述中间电极层、所述选通层、所述外电极层沿径向方向由内至外依次包覆。
在一些可能的实现方式中，所述内电极层为实心圆柱状或者圆环状。
另一方面，本公开实施例提供了一种相变存储阵列，所述相变存储阵列包括上述所述的任一项相变存储单元。
再一方面，本公开实施例提供了一种相变存储器，所述相变存储器包括上述所述的相变存储单元或者上述所述的相变存储阵列。
基于使用了上述相变存储单元，本公开实施例提供的相变存储器，至少具有以下优点：稳定性高、重复性好、读写速度快、内存密度高、成本低等。
再一方面，本公开实施例提供了一种电子设备，所述电子设备包括：处理器、上述的相变存储器；
所述相变存储器用于存储所述处理器所访问的数据。
示例地，该电子设备包括但不限于：计算机、打印机、手机、相机等。
再一方面，本公开实施例提供了一种相变存储单元的制备方法，所述相变存储单元如上述所述的相变存储单元；
所述相变存储单元的制备方法包括：制备相变薄膜；
所述制备相变薄膜包括：分别形成相变材料层和异质结层，并使所述相变材料层和所述异质结层接触。
在一些可能的实现方式中，通过薄膜沉积工艺分别形成所述相变材料层和所述异质结层。
在一些可能的实现方式中，所述薄膜沉积工艺为原子层沉积工艺、物理气相沉积工艺、化学气相沉积工艺、或者等离子体增强化学的气相沉积工艺。
附图说明
图1为本公开实施例提供的一示例性相变薄膜的结构示意图；
图2为本公开实施例提供的第一示例性限制型结构的相变存储单元的结构示意图；
图3为本公开实施例提供的第二示例性限制型结构的相变存储单元的结构示意图；
图4为本公开实施例提供的第三示例性限制型结构的相变存储单元的结构示意图；
图5为本公开实施例提供的第四示例性限制型结构的相变存储单元的结构示意图；
图6为本公开实施例提供的一示例性在图5基础上设计了选通层的限制型结构的相变存储单元的结构示意图；
图7为本公开实施例提供的第五示例性地限制型结构的相变存储单元的结构示意图；
图8为本公开实施例提供的一示例性在图7基础上设计了选通层的限制型结构的相变存储单元的结构示意图；
图9为本公开实施例提供的一示例性地T型结构的相变存储单元的结构示意图；
图10为本公开实施例提供的一示例性在图9基础上设计了选通层的T型结构的相变存储单元的结构示意图；
图11为本公开实施例提供的一示例性地U型沟槽结构的相变存储单元的结构示意图；
图12为本公开实施例提供的一示例性在图11基础上设计了选通层的U型沟槽结构的相变存储单元的结构示意图；
图13为本公开实施例提供的另一示例性地U型沟槽结构的相变存储单元的结构示意图；
图14为本公开实施例提供的一示例性在图13基础上设计了选通层的U型沟槽结构的相变存储单元的结构示意图；
图15为本公开实施例提供的一示例性地L字型结构的相变存储单元的结构示意图；
图16为本公开实施例提供的一示例性在图15基础上设计了选通层的L字型结构的相变存储单元的结构示意图；
图17为本公开实施例提供的另一示例性地L字型结构的相变存储单元的结构示意图；
图18为本公开实施例提供的一示例性在图17基础上设计了选通层的L字型结构的相变存储单元的结构示意图；
图19为本公开实施例提供的一示例性圆柱形结构的相变存储单元的结构示意图；
图20为本公开实施例提供的另一示例性圆柱形结构的相变存储单元的结构示意图；
图21为本公开实施例提供的一示例性相变存储阵列的结构示意图；
图22为本公开实施例提供的一示例性第一中间阵列的结构示意图；
图23为在图22所示结构上开孔填充绝缘介质所形成的第二中间阵列的结构示意图；
图24为本公开实施例提供的另一示例性相变存储阵列的俯视图；
图25为基于图24中沿AB方向从上至下得到的侧视图；
图26为本公开实施例提供的多层外电极层和多层绝缘介质层交替层叠形成的薄膜结构示意图；
图27本公开实施例提供的再一示例性相变存储阵列的俯视图；
图28为基于图27中沿CD方向从上至下得到的侧视图；
图29为本公开实施例提供的一示例性相变存储单元的一类应用场景示意图；
图30为本公开实施例提供的一示例性相变存储单元的另一类应用场景示意图。
附图标记分别表示：
100-相变存储单元，
1-相变薄膜，101-相变材料层，102-异质结层，
21-底电极层，22-顶电极层，23-中间电极层，
24-内电极层，25-外电极层，
3-绝缘介质层，
4-选通层，
200-字线层，300-位线层，
400-字线，500-位线，
600-绝缘介质，
700-第一金属连接柱，800-第二金属连接柱，
1001-多值相变存储器，
2001-动态随机存取存储器，
3001-缓存，
4001-处理器，
5001-固态硬盘。
具体实施方式
为使本公开的技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
相变存储器是一种固态半导体非易失性存储器，具有高速读取、高可擦写次数、非易失性、元件尺寸小、功耗低等优点，被广泛用于半导体存储器等产品。相变存储器以相变材料作为存储介质，相变材料能够在晶态和非晶态之间进行可逆转变，相变存储器利用相变材料在非晶态和晶态时对应的高、低电阻率的差异来实现数据“0”和“1”的存储。
相变存储器工作过程包括：SET过程和RESET过程。SET过程指的是：施加一个宽而弱的电脉冲对相变材料进行加热，使相变材料的温度升高至结晶温度和熔化温度之间，相变材料结晶为有序状态，形成具有较低电阻率的晶态，以实现数据“0”的存储。RESET过程指的是，施加一个窄而强的电脉冲对相变材料进行加热，使相变材料的温度升高到熔化温度以上，融化为无序状态，随后经过一个快速冷却的淬火过程(＞10 9K/s)，相变材料由熔融态直接进入具有较高电阻率的非晶态，以实现数据“1”的存储。
可见，相变材料的相变速度直接影响了相变存储器的读写速度，相关技术提供了一种超晶格相变材料，其由多层GeTe薄膜和多层Sb 2Te 3薄膜交替叠合而成，该类超晶格相变材料具有较高的相变速度。
然而，相关技术提供的超晶格相变材料，在作业过程中，Te元素和Sb元素向不同的电场方向迁移，使得相变材料内部形成富Sb区域和富Te区域，这样不利于超晶格相变材料的反复擦写，容易降低其循环寿命。
本公开实施例提供了一种相变存储单元，该相变存储单元包括相变薄膜1，如附图1所示，该相变薄膜1包括：一层相变材料层101和一层异质结层102，该相变材料层101与异质结层102相接触。
相变材料层101采用相变材料形成，异质结层102采用异质结材料形成，其中，(1)异 质结材料与相变材料的晶格失配度小于或等于20％；(2)异质结材料与相变材料的接触晶面具有相同的晶格夹角；(3)异质结材料的熔点大于相变材料的熔点。
其中，上述的“异质结材料与相变材料的接触晶面具有相同的晶格夹角”中涉及的接触晶面为相变材料层101和异质结层102两者用于接触的晶面。
本公开实施例提供的相变存储单元使用了异质结层102，异质结层102采用异质结材料形成，由于异质结材料与相变材料的晶格失配度小于或等于20％，并且，异质结材料与相变材料的接触晶面具有相同的晶格夹角，这样，相变材料层101可以通过外延生长的方式在异质结层102的界面上进行结晶，使得异质结层102能够作为相变材料层101的结晶模板，加速相变材料的结晶速度，提高相变材料的相变速度，从而增加其作业速度。由于异质结材料的熔点大于相变材料的熔点，在相变材料层101发生相变时，异质结层102会保持稳定的晶体结构，有效阻止相变材料在电场方向上的元素迁移，并减小相变材料与电极之间的扩散，利于提高相变材料层101的循环寿命。
另外，该相变存储单元中，相变薄膜1包括一层相变材料层101和一层异质结层102，这不仅避免了多层界面容易出现的界面问题和操作不稳定问题，还使得相变存储单元更利于设计成常见的限制型结构。采用单层相变材料层101和单层异质结层102的相变存储单元，其结构简单，制备方法也相应简单，易于实现。具体而言，相比于复杂的多层超晶格结构，该相变薄膜1的制备工艺更加容易精确控制，从而提升器件良率。同时，单层结构的相变薄膜1的电学操作更易于控制，可以获得更加稳定的电阻分布(而多层超晶格结构更容易出现相变层之间的元素扩散，导致器件的循环操作寿命降低)。
本公开实施例中，相变材料层101使用的相变材料与异质结层102使用的异质结材料的晶体结构类似，或者，至少使相变材料与异质结材料的接触晶面的晶型相似，以使两者获得更高的晶格匹配度，进而使得异质结材料能够作为相变材料的结晶模板。
举例来说，相变材料与异质结材料的晶格失配度小于或等于19％、小于或等于18％、小于或等于17％、小于或等于16％、小于或等于15％、小于或等于14％、小于或等于13％、小于或等于12％、小于或等于11％、小于或等于10％、小于或等于9％、小于或等于8％、小于或等于9％、小于或等于7％、小于或等于6％、小于或等于5％等，以使相变材料获得更快的结晶速度。
当相变材料与异质结材料的晶格失配度小于或等于10％时，相变材料与异质结材料两者之间存在更小的晶格常数差异，能够为相变材料的结晶提供更大的动力，进一步提高相变材料结晶时形成的晶态结构的稳定性。
在一些可能的实现方式中，异质结材料与相变材料均为六方晶系材料，对于六方晶系材料，a轴长度＝b轴长度≠c轴长度，a轴与b轴之间的夹角为120°，a轴与c轴之间的夹角和b轴与c轴之间的夹角均为90°。当异质结材料与相变材料均为六方晶系材料时，异质结材料的a轴与相变材料的a轴的长度差小于或等于20％(这里的长度差也就是上述的晶格失配度)。
在一些可能的实现方式中，异质结材料为六方晶系材料，相变材料为立方晶系材料，对于六方晶系材料，如上所述，a轴长度＝b轴长度≠c轴长度，a轴与b轴之间的夹角为120°，a轴与c轴之间的夹角和b轴与c轴之间的夹角均为90°；对于立方晶系材料，a轴长度＝b轴长度＝c轴长度，且任意相邻的两个轴相互垂直。本公开实施例将异质结材料的a轴长度定义为a 1，将相变材料的a轴长度定义为a 2，当异质结材料为六方晶系材料，且相变材料为立方晶 系材料时，使a 1与√2a 2的差小于或等于20％(这里的a 1与√2a 2的差也就是上述的晶格失配度)。其中，√2＝1.4142135623731……。
本公开实施例中，相变薄膜1中的相变材料层101的厚度范围为2nm-100nm，例如为10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm等。对于相变材料层101的厚度，可以根据其发生相变时对应的操作电压或者操作电流的大小来确定。
本公开实施例中，相变薄膜1中的异质结层102的厚度范围均为2nm-20nm，例如为2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、12nm、15nm、17nm、18nm、19nm等。异质结层102的上述厚度范围能够满足有效阻止相变材料层101与电极之间的元素扩散。
本公开实施例使相变材料层101的厚度和异质结层102的厚度在上述范围内，使得相变存储单元能够适用于多种类型的相变存储器，并获得较宽的调节范围。
在一些可能的实现方式中，相变材料为掺杂或者未掺杂的Ge-Te二元化合物、Sb-Te二元化合物(例如为Sb 2Te 3)、Bi-Te二元化合物、Ge-Sb-Te三元化合物、Ga-Sb二元化合物、Sb中的一种。
相变材料可以未掺杂有任何其他元素，也可以掺杂有其他元素，当相变材料为掺杂材料时，其中所掺杂的掺杂元素选自C、N、Si、B、Sc、Ti、Y、Zr、Hf、V、Ta、W、Cu、Zn、In中的至少一种。掺杂元素在相变材料中的原子百分含量小于或等于20％，例如为15％、12％、10％、9％、8％、7％、6％、5％、4％、3％、2％、1％等。
当相变材料选自上述种类时，与这些相变材料相适配的异质结材料为M-Te化合物，其中，M为过渡金属元素，示例地，M为Ti、Zr、Pd、Cd、Mo、Mn、Ir、Rn、Pt、Sc、Ni、Ta、或者Zn。
也就是说，异质结材料可以为TiTe 2(二碲化钛)、ZrTe 3(碲化锆)、PdTe 2(二碲化钯)、CdTe(碲化镉)、MoTe 2(二碲化钼)、MnTe 2(碲化锰)、IrTe 2(碲化铱)、RnTe(碲化氡)、PtTe 2(二碲化铂)、Pt 2Te 3(三碲化二铂)、ScTe(碲化钪)、Sc 2Te 3(三碲化二钪)、NiTe 2(二碲化镍)、TaTe 2(二碲化钽)、ZnTe(碲化锌)。
上述种类的异质结材料具有稳定的晶体结构，能够有效阻止相变材料在电场方向上的元素扩散，同时，在使异质结材料与相变材料的晶格失配度小于或等于20％的前提下，相变材料层101能够以异质结材料层102作为结晶生长模板，利于显著降低结晶时间，提高相变材料的相变速度。
另外，本公开实施例中，异质结层102的使用还要求不能影响相变材料层101的高低电阻识别，以保证数据准确性。举例来说，当异质结层102的厚度较薄时，对异质结材料的导电性不作更高的要求，因为厚度较薄的异质结层102一般不影响相变材料层101的电阻识别；当异质结层102的厚度较厚时，可以使用具有导电性的异质结材料，以确保不影响相变材料层101的高低阻值识别，保证数据的准确性。
上述种类的相变材料与异质结材料组合使用时，只要满足组合使用的相变材料与异质结材料的晶格失配度小于或等于20％，组合使用的异质结材料与相变材料在面内具有相同的晶格夹角，并且，组合使用的相变材料的熔点小于异质结材料的熔点即可。
举例来说，本公开实施例提供了这样一种相变薄膜1，其包括由二元化合物Sb 2Te 3形成的单层相变材料层101，以及，由化合物ScTe形成的单层异质结层102。
以下就本公开实施例涉及的相变薄膜1的制备方法进行示例性描述：
在形成相变薄膜1时，分别形成相变材料层101和异质结层102，并使相变材料层101和异质结层102接触。该过程包括：首先形成相变材料层101，然后在相变材料层101上形成异质结层102；或者，首先形成异质结层102，然后在异质结层102上形成相变材料层101。
在形成相变材料层101时，利用如上所述的相变材料，通过薄膜沉积工艺形成相变材料层101。在形成异质结层102时，利用如上所述的异质结材料，通过薄膜沉积工艺形成异质结层102。
示例地，本公开实施例所适用的薄膜沉积工艺包括但不限于以下：原子层沉积(atomic layer deposition，ALD)、物理气相沉积(Physical Vapour Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)，例如，等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、磁控溅射、电子束蒸发等。
磁控溅射是物理气相沉积工艺的一种，具有易于控制、镀膜面积大、附着力强、制备对象广泛等优点，示例性地，本公开实施例可以使用磁控溅射工艺来形成相变材料层101和异质结层102。
磁控溅射工艺中使用的溅射气体包括但不限于：氩气Ar、氪气Kr、氙气Xe、氖气Ne、氮气N 2中的至少一种，由于氩气价格较低，容易获得，可以选用氩气Ar作为磁控溅射工作气体。
本公开实施例中，相变薄膜1不仅能够使用磁控溅射工艺来形成，诸如底电极层21和顶电极层22也能够利用磁控溅射工艺来形成。当用于形成相变薄膜1时，采用射频磁控溅射，基板温度，也就是样品台温度为150℃-350℃，例如为200℃、250℃、300℃等。当用于形成电极层时，采用直流功率溅射，基板温度为20℃-40℃，例如为25℃、30℃、35℃等。
本公开实施例还提供的相变存储单元基于使用了上述任一种相变薄膜1，使得相变存储单元至少具有以下优点：
(1)相变材料与异质结材料的晶格失配度小于或等于20％，特别地，小于或等于10％，这样相变材料层101可以通过外延生长的方式从异质结层102的界面进行结晶，以异质结层102作为结晶生长模板，利于显著降低结晶时间，提高相变材料的相变速度，进而提高相变存储器的读写速度。
(2)相变材料的熔点小于异质结材料的熔点，相变材料层101发生相变时，异质结层102会保持稳定的晶体结构，有效阻止了相变材料在电场方向上的元素迁移，利于提高相变材料的循环寿命，进而提高相变存储单元的循环寿命。
在一些可能的实现方式中，本公开实施例提供了这样一种相变存储单元，如附图2所示，该相变存储单元除了包括上述相变薄膜1之外，该相变存储单元还包括底电极层21、顶电极层22、绝缘介质层3；其中，相变薄膜1位于底电极层21和顶电极层22之间；绝缘介质层3用于为该相变存储单元提供绝缘隔离，即，当多个相变存储单元同时使用时，利用绝缘介质层3来使得多个相变存储单元之间互相隔离。
上述相变存储单元中，相变材料层101和异质结层102沿上下方向层叠设置，这包括：相变材料层101位于上层，异质结层102位于下层；以及，相变材料层101位于下层，异质结层102位于上层。
对于绝缘介质层3的布置，可以根据相变存储单元的具体结构来适应性地进行设计，只要确保利用绝缘介质层3能够将其所在的相变存储单元隔离开即可。
本公开实施例可以利用衬底来对整个相变存储单元结构提供支撑，通过将相变存储单元施加于衬底上，使底电极层21位于衬底的表面即可。为了更清楚地描述相变存储单元的结构，本公开实施例将相变存储单元靠近衬底的方向定义为底部方向，将相变存储单元远离衬底的方向定义为顶部方向。
示例地，衬底的材质可以采用本领域常见的衬底材料，举例来说，衬底的材质包括但不限于：二氧化硅、碳化硅、硅片、蓝宝石、金刚石等。
在应用时，可以采用有机溶剂，例如乙醇和/或丙酮等将衬底的表面清洗干净，以除去衬底表面的有机物、氧化物和金属离子等杂质。清洗完毕，可以将衬底置于烘箱中于60℃-90℃下干燥，获得充分干燥且干净的衬底。
本公开实施例提供的相变存储单元中，顶电极层22、底电极层21均可以采用本领域常见的电极材料制备得到，电极材料需要满足以下要求：熔点高于相变材料的熔点，不易氧化等。举例来说，顶电极层22和底电极层21的材质包括但不限于：钨化钛TiW(例如Ti 3W 7)、钨W、铝Al、氮化钛TiN、钛Ti、钽Ta、银Ag、铂Pt、碳C、铜Cu、钌Ru、金Au、钴Co、铬Cr、镍Ni、铱Ir、钯Pd、铑Rh等。
基于上述电极材料，可以采用诸如物理气相沉积(Physical Vapour Deposition，PVD)工艺(例如磁控溅射)，将上述电极材料沉积成顶电极层22或者底电极层21。
本公开实施例提供的相变存储单元中，所涉及的绝缘介质层3的作用至少包括以下：(1)形成绝缘容置孔，使得相变薄膜1中的相变材料层101和/或异质结层102被限制在该绝缘容置孔内，以降低相变所需的热量，利于降低相变存储器的功耗；(2)能够避免底电极层21和顶电极层22发生短路。这使得绝缘介质层3所采用的绝缘隔热材料需要较高的熔点，以有效阻止相变材料的扩散，且还需要有更佳的热稳定性，以在相变材料发生相变时保持良好的绝缘隔热性能。
示例地，绝缘介质层3所采用的绝缘隔热材料包括但不限于：氮化硅Si 3N 4、二氧化硅SiO 2等。可以采用诸如化学气相沉积(Chemical Vapor Deposition，CVD)工艺，例如等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺，将上述绝缘隔热材料沉积成绝缘介质层3。
进一步地，本公开实施例提供的上述相变存储单元还包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触；相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。通过设置选通层4，作为开关使用，能够有效抑制漏电流。
示例地，中间电极层23的材质包括但不限于以下：钨化钛TiW(例如Ti 3W 7)、钨W、铝Al、氮化钛TiN、钛Ti、钽Ta、银Ag、铂Pt、碳C、铜Cu、钌Ru、金Au、钴Co、铬Cr、镍Ni、铱Ir、钯Pd、铑Rh等。基于上述电极材料，可以采用诸如磁控溅射工艺来沉积成中间电极层23。
本公开实施例提供的上述相变存储单元可以设计成多种结构，举例来说，这类相变存储单元的结构包括但不限于以下：(1)限制型结构；(2)T型结构；(3)U型沟槽结构；(4)L字型结构等，以下分别进行示例性描述：
(11)作为一种示例，本公开实施例提供了一种限制型结构的相变存储单元，如附图2所示，自顶部到底部的方向，顶电极层22、相变薄膜1、底电极层21、衬底顺次接触(衬底 未在图中示出)。也就是说，底电极层21形成于衬底的顶部表面，相变薄膜1形成于底电极层21的顶部表面，顶电极层22形成于相变薄膜1的顶部表面。
绝缘介质层3至少包覆于相变薄膜1的侧部，例如，如附图2所示，绝缘介质层3同时包覆于相变薄膜1、底电极层21和顶电极层22的外部；或者，如附图3所示，绝缘介质层3包覆于相变薄膜1和底电极层21的外部，且绝缘介质层3和相变薄膜1的顶部均和顶电极层22连接。
相变薄膜1包括：上下层叠的相变材料层101和异质结层102，其中，相变材料层101和异质结层102可以任意的作为上层或下层。举例来说，如附图2或者附图3所示，可以使异质结层102位于相变材料层101和顶电极层22之间，或者，也可以使相变材料层101位于异质结层102和顶电极层22之间(图中未示出)。
在一些示例中，如附图3所示，相变材料层101、异质结层102结构和尺寸均相同，例如，它们均为相同直径的圆柱形结构。
在一些示例中，相变材料层101、异质结层102的结构相同，但是尺寸不相同，例如为不同尺寸的圆台形结构。举例来说，如附图4所示，沿自上而下的方向，异质结层102、相变材料层101、底电极层21依次层叠且均为圆台形，并且，两者的径向尺寸逐渐增大；如附图5所示，沿自上而下的方向，顶电极层22、异质结层102、相变材料层101、底电极层21依次层叠且均为圆台形，并且，三者的径向尺寸逐渐增大。
对于上述限制型结构的相变存储单元，可以通过以下方法制备得到：
步骤1101：提供清洗干净的衬底，在衬底的表面形成底电极层21。
步骤1102：在衬底和底电极层21的表面形成绝缘介质层3，使绝缘介质层3覆盖底电极层21和衬底并沉积至一定的厚度。然后，对绝缘介质层3进行刻蚀，将绝缘介质层3上对应于绝缘容置孔的部分刻蚀掉，并暴露出底电极层21，以在绝缘介质层3上形成绝缘容置孔。
步骤1103：按照相变薄膜1的制备方法，在绝缘容置孔内形成相变薄膜1。例如，在绝缘容置孔内使相变材料层101形成于底电极层21上，然后，在容置孔内继续在相变材料层101上形成异质结层102，得到相变薄膜1。
步骤1104：在相变薄膜1、绝缘介质层3的顶部表面形成顶电极层22，得到相变存储单元。
进一步地，上述限制型结构的相变存储单元还可以设计有选通层，以下对于设计有选通层的相变存储单元的结构进行示例性描述：
附图6示出了相变薄膜1呈圆台形结构时的一种相变存储单元的结构，如附图6所示，该限制型结构的相变存储单元除了包括顶电极层22、相变薄膜1、底电极层21之外，该相变存储单元还可以包括：中间电极层23和选通层4，中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触；相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。相变薄膜1呈圆柱形结构时，中间电极层23和选通层4的布置与上述的相同，这里不再赘述。
举例来说，如附图6所示，沿由上至下的方向，顶电极层22、异质结层102、相变材料层101、中间电极层23、选通层4、底电极层21依次层叠设置。在该设计有选通层4的相变存储单元中，除了增加了选通层4和中间电极层23之外，顶电极层22、相变薄膜1的布置仍然可以参见上述，这里不再一一描述。
当相变存储单元包括选通层4时，该限制型结构相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地形成选通层4和中间电极层23。
举例来说，如上述所示依次进行步骤1101和步骤1102，然后，改变步骤1103，使得步骤1103包括：在绝缘容置孔内，首先使选通层4形成于底电极层21上，然后依次沉积中间电极层23、相变材料层101、异质结层102，这样，选通层4、中间电极层23和相变薄膜1层叠设置并填充于绝缘容置孔内。最后进行步骤1104，步骤1104如上述所示即可。
(12)示例性地，本公开实施例提供了一种限制型结构的相变存储单元，自顶部到底部的方向，顶电极层22、相变薄膜1、底电极层21顺次接触。也就是说，底电极层21形成于衬底的顶部表面，相变薄膜1形成于底电极层21的顶部表面，顶电极层22形成于相变薄膜1的顶部表面。
如附图7所示，相变薄膜1中的相变材料层101和异质结层102内外包覆设置，例如，异质结层102包覆于相变材料层101的底部和侧部，且异质结层102与相变材料层101的顶部表面持平。或者，相变材料层101包覆于异质结层102的底部和侧部，且相变材料层101与异质结层102的顶部表面持平(图中未示出)。在该示例中，相变薄膜1可以为圆柱形结构，也可以为圆台形结构。
绝缘介质层3至少包覆于相变薄膜1的侧部，例如，如附图7所示，绝缘介质层3包覆于相变薄膜1和底电极层21的外部，且绝缘介质层3的顶部与顶电极层22的底部接触；或者，绝缘介质层3包覆于相变薄膜1的外部，同时绝缘介质层3还位于底电极层21和顶电极层22之间。
进一步地，如附图8所示，该示例所涉及的限制型结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触；相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。举例来说，沿由上至下的方向，顶电极层22、相变薄膜1、中间电极层23、选通层4、底电极层21依次层叠设置。
对于上述限制型结构的相变存储单元，可以通过以下方法制备得到：
步骤1201：提供清洗干净的衬底，在衬底的表面形成底电极层21。
步骤1202：在衬底和底电极层21的表面形成绝缘介质层3，使绝缘介质层3覆盖底电极层21和衬底并沉积至一定的厚度。然后对绝缘介质层3进行刻蚀，将绝缘介质层3上对应于绝缘容置孔的部分刻蚀掉，并暴露出底电极层21，这样能够在绝缘介质层3中形成绝缘容置孔。
步骤1203：按照相变薄膜1的制备方法，在绝缘容置孔内形成相变薄膜1。例如，在绝缘容置孔内使异质结层102形成于底电极层21上，然后，对异质结层102进行刻蚀，在异质结层102上形成凹槽，继续在该凹槽内形成相变材料层101，这样，异质结层102包覆于相变材料层101的底部和侧部，得到相变薄膜1。
步骤1204：在相变薄膜1、绝缘介质层3的顶部表面形成顶电极层22，得到相变存储单元。
当相变存储单元包括选通层4时，该限制型结构相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地形成选通层4和中 间电极层23。
举例来说，如上述所示依次进行步骤1201和步骤1202，然后，在进行步骤1203时作了适应性改进，使得步骤1203包括：在绝缘容置孔内先使选通层4形成于底电极层21上，然后继续在选通层4上继续形成中间电极层23。然后，在绝缘容置孔内于中间电极层23上继续形成异质结层102，对异质结层102进行刻蚀，在异质结层102上形成凹槽，继续在该凹槽内形成相变材料层101，得到相变薄膜1。最后进行步骤1204，步骤1204如上述所示即可。
(2)在一些可能的实现方式中，本公开实施例提供了一种T型结构的相变存储单元，如附图9所示，该T型结构的相变存储单元包括：相变薄膜1、底电极层21、顶电极层22、绝缘介质层3。其中，绝缘介质层3位于衬底上，绝缘介质层3上具有通孔，底电极层21位于该通孔内；顶电极层22、相变薄膜1、绝缘介质层3顺次接触，并且，相变薄膜1还与底电极层21连接，且底电极层21与相变薄膜1配合形成T型结构。
也就是说，底电极层21形成于绝缘介质层3的通孔内，相变薄膜1同时形成于底电极层21和绝缘介质层3的顶部表面，顶电极层22形成于相变薄膜1的顶部表面。
相变薄膜1包括上下层叠的相变材料层101和异质结层102，其中，相变材料层101和异质结层102可以任意的作为上层或下层。举例来说，可以使异质结层102位于相变材料层101和顶电极层22之间，或者，也可以使相变材料层101位于异质结层102和顶电极层22之间。
在一些示例中，相变材料层101、异质结层102、顶电极层22的结构和尺寸均相同，例如，为相同直径的圆柱形结构。
对于图9所示的该T型结构的相变存储单元，相变材料层101厚度可以为20nm-150nm，异质结层101的厚度可以为4nm-20nm，顶电极层22的厚度为50nm-300nm。
在一些示例中，图9所示的该T型结构的相变存储单元可以采用以下方法制备得到：
提供一种包含有底电极层21和绝缘介质层3的的衬底，该底电极层21的材质可以为W。
通过丙酮和乙醇交替清洗该衬底，去除表面的有机物、氧化物和金属离子等各类杂质，并在烘箱中烘烤80℃下烘烤20分钟，使其充分干燥。
通过磁控溅射法依次生长厚度为8nm的相变材料层101、厚度为50nm的异质结层102、厚度为50nm的顶电极层22。
利用光刻和刻蚀工艺刻蚀绝缘介质层3上方的各膜层，直至暴露出绝缘介质层3，以便物理隔断不同底电极层21顶部的各相变存储单元部分。
在该示例中，底电极层21和顶电极层22所采用的材质均为TiN，磁控溅射的工作参数为：溅射电源为DC电源，溅射本底真空为8×10 -5Pa-2×10 -4Pa，溅射气体为Ar，溅射气压为3mTorr～6mTorr。
对于异质结层101和相变材料层102的磁控溅射参数为：溅射时候基板温度为150～300℃；其中，异质结层101使用ScTe靶材，溅射功率为10W-20W；相变材料层使用Sb 2Te 3靶材，溅射功率为7W-30W。对于顶电极层22的磁控溅射参数为：基板温度为20～40℃，使用TiN靶材，溅射功率为50W～250W。另外，本示例中涉及的刻蚀工艺为反应离子刻蚀。
进一步地，如附图10所示，该示例所涉及的T型结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触；相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶 电极层22之间。举例来说，沿由上至下的方向，顶电极层22、相变薄膜1、中间电极层23、选通层4、底电极层21依次层叠设置。
对于该类相变存储单元，可通过以下方法制备得到：
步骤201：在衬底上形成绝缘介质层3，对绝缘介质层3进行刻蚀以形成通孔，在通孔内填充并形成底电极层21，并使绝缘介质层3和底电极层21的顶部表面持平。
步骤202：按照相变薄膜的制备方法，在绝缘介质层3和底电极层21的顶部表面形成相变薄膜1。即，按照相变薄膜1中相变材料层101和异质结层102的分布顺序，在绝缘介质层3和底电极层21的顶部表面上依次形成相变材料层101和异质结层102，得到相变薄膜1。
步骤203：继续在相变薄膜1的顶部表面形成顶电极层22，得到相变存储单元。
进一步地，当该相变存储单元包括选通层4时，该T型结构的相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地沉积选通层4和中间电极层23。
举例来说，如上述所示依次进行步骤201后，然后，在进行步骤202时作了适应性改进，使得步骤202包括：在绝缘介质层3和底电极层21的顶部表面形成选通层4，然后继续在选通层4上形成中间电极层23，在中间电极层23上形成相变薄膜1。最后如上所述进行步骤203即可。
(3)在一些可能的实现方式中，本公开实施例提供了一种U型沟槽结构的相变存储单元，如附图11或者附图13所示，该U型沟槽结构的相变存储单元包括：相变薄膜1、底电极层21、顶电极层22、绝缘介质层3。自顶部到底部的方向，顶电极层22、相变薄膜1、底电极层21顺次接触，也就是说，底电极层21形成于衬底的顶部表面，相变薄膜1形成于底电极层21的顶部表面，顶电极层22形成于相变薄膜1的顶部表面。绝缘介质层3上具有U型沟槽，该U型沟槽用于容纳相变薄膜1的相变材料层101和/或异质结层102。
(3.1)在一些示例中，如附图11所示，相变薄膜1的异质结层102位于底电极层21的顶部表面上，具有U型沟槽的绝缘介质层3位于异质结层102上，相变材料层101的一部分位于绝缘介质层3的U型沟槽内部，且与异质结层102接触，相变材料层101的另一部分覆盖绝缘介质层3，顶电极层22覆盖绝缘介质层3的顶部表面。
进一步地，如附图12所示，该种U型沟槽结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触，相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。举例来说，沿由上至下的方向，异质结层102、中间电极层23、选通层4、底电极层21依次层叠设置。
对于该类相变存储单元，可通过以下方法制备得到：
步骤311：提供清洗干净的衬底，在衬底的表面形成底电极层21，使底电极层21铺于衬底的顶部表面。
步骤312：在底电极层21的表面形成异质结层102，使异质结层102铺满底电极层21的顶部表面。
步骤313：在异质结层102上形成绝缘介质层3，使绝缘介质层3铺满异质结层102的顶部表面，待绝缘介质层3沉积至一定的厚度后，对绝缘介质层3进行刻蚀，将绝缘介质层3上对应于U型沟槽的部分刻蚀掉，并暴露出异质结层102，这样能够在绝缘介质层3中形成 U型沟槽。
步骤314：形成相变材料层101，使相变材料层101填充满U型沟槽后继续沉积一定的厚度，使得相变材料层101平铺于绝缘介质层3上。
步骤315：在相变材料层101的顶部表面形成顶电极层22，得到相变存储单元。
进一步地，当相变存储单元包括选通层4时，该类相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地沉积选通层4和中间电极层23。
举例来说，如上述所示依次进行步骤311，然后，在进行步骤312时作了适应性改进，使得步骤312包括：在底电极层21的表面先形成选通层4，然后继续在选通层4上形成中间电极层23，在中间电极层23的表面形成异质结层102，使异质结层102铺满中间电极层23的顶部表面。最后按照上述依次进行步骤313-步骤315，步骤313-步骤315如上述所示即可。
(3.2)在另一些示例中，如附图13所示，具有U型沟槽的绝缘介质层3位于底电极层21上，相变薄膜1的异质结层102包括：中间凹槽部分和侧部平铺部分，其中，中间凹槽部分具有U型盲槽(即，底部为封闭式)。异质结层102的中间凹槽部分位于绝缘介质层3的U型沟槽内，且该中间凹槽部分的底部表面与底电极层21接触。异质结层102的侧部平铺部分位于绝缘介质层3的顶部表面上，相变材料层101位于异质结层102和顶电极层22之间，也就是说，部分相变材料层101填充于异质结层102的U型盲槽内，另一部分的相变材料层101位于异质结层102的侧部平铺部分的顶部表面。
进一步地，如附图14所示，该种U型沟槽结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触，相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。举例来说，沿由上至下的方向，异质结层102、中间电极层23、选通层4、底电极层21依次层叠设置，其中，中间电极层23有一部分顶部表面与异质结层102接触，另一部分顶部表面还与绝缘介质层3接触。
对于该类相变存储单元，可通过以下方法制备得到：
步骤321：提供清洗干净的衬底，在衬底的表面形成底电极层21，使底电极层21铺满衬底的顶部表面。
步骤322：在底电极层21的表面形成绝缘介质层3，使绝缘介质层3铺满底电极层21的顶部表面。待绝缘介质层3沉积至一定的厚度后，对绝缘介质层3进行刻蚀，将绝缘介质层3上对应于U型沟槽的部分刻蚀掉，并暴露出底电极层21，这样能够在绝缘介质层3中形成U型沟槽。
步骤323：在绝缘介质层3上形成异质结层102，使异质结层102铺满绝缘介质层3的顶部表面，待异质结层102沉积至一定的厚度后，对异质结层102进行刻蚀，将异质结层102上对应于U型盲槽的部分刻蚀掉，这样能够在异质结层102中形成U型盲槽。
步骤324：形成相变材料层101，使相变材料层101填充满U型盲槽后继续沉积一定的厚度，使得相变材料层101平铺于异质结层102上。
步骤325：在相变材料层101的顶部表面形成顶电极层22，得到相变存储单元。
进一步地，当该类结构的相变存储单元包括选通层4时，相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地沉积选 通层4和中间电极层23。
举例来说，如上述所示依次进行步骤321，然后，在进行步骤322时作了适应性改进，使得步骤322包括：在底电极层21的表面先形成选通层4，然后继续在选通层4上形成中间电极层23，在中间电极层23的表面形成绝缘介质层3，使绝缘介质层3铺满中间电极层23的顶部表面。待绝缘介质层3沉积至一定的厚度后，对绝缘介质层3进行刻蚀，将绝缘介质层3上对应于U型沟槽的部分刻蚀掉，并暴露出中间电极层23。最后按照上述依次进行步骤323-步骤325，步骤323-步骤325如上述所示即可。
(4)在一些可能的实现方式中，本公开实施例提供了一种L字型结构的相变存储单元，如附图15或者附图17所示，该L字型结构的相变存储单元包括：相变薄膜1、底电极层21、顶电极层22、绝缘介质层3。绝缘介质层3上具有L型孔，该L型孔用于容纳相变材料层101和/或异质结层102。
(4.1)在一些可能的实现中，如附图15所示，使相变材料层101位于绝缘介质层3上的L型孔内(即相变材料层101为与L型孔相适配的L型结构)，相变材料层101和绝缘介质层3的顶部表面和底部表面持平。在该种情形下，沿由上至下的方向，顶电极层22、异质结层102、相变材料层101与绝缘介质层3构成的整体、底电极层21依次层叠设置。
进一步地，如附图16所示，该L字型结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触，相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。举例来说，沿由下至上的方向，底电极层21、选通层4、中间电极层23依次层叠设置，相变材料层101与绝缘介质层3构成的整体位于中间电极层23的顶部表面上。
对于该L字型结构的相变存储单元，可以通过以下方法制备得到：
步骤411：提供清洗干净的衬底，在衬底的表面形成底电极层21，使底电极层21铺于衬底的顶部表面。
步骤412：在底电极层21的表面形成相变材料层101，并对相变材料层101进行刻蚀，使得相变材料层101成L型结构。
步骤413：在底电极层21上继续形成绝缘介质层3，使绝缘介质层3铺满底电极层21的顶部表面并填充于相变材料层101的L型槽内，经处理使得绝缘介质层3和相变材料层101的顶部表面持平。
步骤414：在绝缘介质层3和相变材料层101的顶部表面上形成异质结层102，使异质结层102铺于绝缘介质层3和相变材料层101的顶部表面。
步骤415：在异质结层102的顶部表面形成顶电极层22，得到该相变存储单元。
进一步地，当该L字型结构的相变存储单元包括选通层4时，该相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地沉积选通层4和中间电极层23。
举例来说，如上述所示依次进行步骤411，然后，在进行步骤412时作了适应性改进，使得步骤412包括：在底电极层21的表面先形成选通层4，继续在选通层4上形成中间电极层23，在中间电极层23的表面形成相变材料层101，并对相变材料层101进行刻蚀，使得相变材料层101成L型结构。最后按照上述依次进行步骤413-步骤415，步骤413-步骤415如上述所示即可。
(4.2)在另一些示例中，如附图17所示，相变材料层101和异质结层102均设计为L型结构，并且，相变材料层101和异质结层102中的一个座于另一个的L型槽内。举例来说，相变材料层101座于异质结层102的L型槽内，相变材料层101和异质结层102构成L型结构的相变薄膜1，并且，该相变薄膜1座于绝缘介质层3上的L型孔内，这样，相变薄膜1和绝缘介质层3整体位于顶电极层22与底电极层21之间。
进一步地，如附图18所示，该L字型结构的相变存储单元还可以包括：中间电极层23和选通层4，该中间电极层23的第一表面与相变薄膜1接触，中间电极层23的第二表面与选通层4接触，相变薄膜1、中间电极层23和选通层4整体位于底电极层21和顶电极层22之间。举例来说，沿由下至上的方向，底电极层21、选通层4、中间电极层23依次层叠设置，相变薄膜1和绝缘介质层3构成的整体位于中间电极层23的顶部表面上。
对于该L字型结构的相变存储单元，可以通过以下方法制备得到：
步骤421：提供清洗干净的衬底，在衬底的表面形成底电极层21，使底电极层21铺满衬底的顶部表面。
步骤422：在底电极层21的表面形成异质结层102，并对异质结层102进行刻蚀，使得异质结层102成L型结构，继续形成相变材料层101，使相变材料层101填充并座于异质结层102上的L型槽，然后，对相变材料层101进行刻蚀，使得相变材料层101也相应地成L型结构。
步骤423：在底电极层21上继续形成绝缘介质层3，使绝缘介质层3铺满底电极层21的顶部表面并填充于相变材料层101的L型槽内，最终使得绝缘介质层3、相变材料层101和异质结层102的顶部表面持平。
步骤424：在绝缘介质层3、相变材料层101和异质结层102的顶部表面上形成顶电极层22，得到该相变存储单元。
进一步地，当上述结构的相变存储单元进一步包括选通层4时，该相变存储单元的制备方法还进一步包括：根据选通层4和中间电极层23在相变存储单元中的具体布置，来适应性地沉积选通层4和中间电极层23。
举例来说，如上述所示依次进行步骤421，然后，在进行步骤422和步骤423时作了适应性改进，使得步骤422包括：在底电极层21的表面先形成选通层4，继续在选通层4上形成中间电极层23，在中间电极层23的表面形成异质结层102，并对异质结层102进行刻蚀，使得异质结层102成L型结构。然后，继续形成相变材料层101，使相变材料层101填充异质结层102上的L型槽，然后对相变材料层101进行刻蚀，使得相变材料层101也相应地成L型结构。使得步骤423包括：在中间电极层23上继续形成绝缘介质层3，使绝缘介质层3铺满中间电极层23的顶部表面并填充于相变材料层101的L型槽内，最终使得绝缘介质层3、相变材料层101和异质结层102的顶部表面持平。最后按照上述进行步骤424即可。
(5.1)在一些可能的实现方式中，如附图19所示，本公开实施例提供了一种圆柱形结构的相变存储单元，该相变存储单元包括：相变薄膜1、内电极层24和外电极层25；内电极层24、相变薄膜1、外电极层25沿径向方向由内至外依次包覆。其中，内电极层24和外电极层25的原料组成可以与上述的底电极层21和顶电极层22的原料组成相同。
在一些示例中，如附图19所示，相变材料层101包覆于异质结层102的外部，也就是说，异质结层102沿周向方向包覆于内电极层24的外部，相变材料层101沿周向方向包覆于异质 结层102的外部，外电极层25沿周向方向包覆于相变材料层101的外部。
在另一些示例中，异质结层102包覆于相变材料层101的外部，也就是说，相变材料层101沿周向方向包覆于内电极层24的外部，异质结层102沿周向方向包覆于相变材料层101的外部，外电极层25沿周向方向包覆于异质结层102的外部(图中未示出)。
在上述示例中，位于相变存储单元中心位置处的内电极层24可以为实心圆柱状，也可以为如附图19所示的圆环状。根据制备时的工艺条件任意的选择内电极层24的形状，无论使内电极层24选择哪种形状，在用于相变存储阵列时，进行到如附图23所示的结构步骤时，所得到的阵列结构也是相同时。
对于上述示例中涉及的圆柱形结构的相变存储单元，以相变材料层101包覆于异质结层102的外部为例，来说明该种结构的相变存储单元的制备方法，其如下所示：
步骤511：提供清洗干净的衬底，在衬底的表面形成一定厚度的外电极层25，使外电极层25铺于衬底的顶部表面。
步骤512：对外电极层25进行刻蚀，使外电极层25形成环状结构，然后，在外电极层25的内壁上形成异质结层102，形成的异质结层102也是环状结构。
步骤513：对异质结层102的内壁进行抛光，然后在异质结层102的内壁上形成相变材料层101，形成的相变材料层101也是环状结构。
步骤514：对相变材料层101的内壁进行抛光，然后在相变材料层101的内壁上形成内电极层24，其中，内电极层24可以形成为环状结构，也可以形成为实心的圆柱状结构(即，填满相变材料层101的圆孔即可)。
当异质结层102包覆于相变材料层101的外部时，所对应的相变存储单元的制备方法与上述相同，区别在于，改变步骤1512使外电极层25的内壁上形成相变材料层101，改变步骤1513使相变材料层101的内壁上形成异质结层102，改变步骤1514使异质结层102的内壁上形成内电极层24。
(5.2)在一些可能的实现方式中，如附图20所示，本公开实施例提供了另一种圆柱形结构的相变存储单元，该相变存储单元包括：相变薄膜1、内电极层24、中间电极层23、选通层4和外电极层25；其中，内电极层24、相变薄膜1、中间电极层23、选通层4、外电极层25沿径向方向由内至外依次包覆。
在一些示例中，相变材料层101包覆于异质结层102的外部，也就是说，异质结层102沿周向方向包覆于内电极层24的外部，相变材料层101沿周向方向包覆于异质结层102的外部，中间电极层23沿周向方向包覆于相变材料层101的外部、选通层4沿周向方向包覆于中间电极层23的外部，外电极层25沿周向方向包覆于中间电极层23的外部。
在另一些示例中，异质结层102包覆于相变材料层101的外部，也就是说，相变材料层101沿周向方向包覆于内电极层24的外部，异质结层102沿周向方向包覆于相变材料层101的外部，中间电极层23沿周向方向包覆于异质结层102的外部、选通层4沿周向方向包覆于中间电极层23的外部，外电极层25沿周向方向包覆于中间电极层23的外部。
在上述示例中，位于相变存储单元中心位置处的内电极层24可以为实心圆柱状，也可以为圆环状。
对于上述示例中涉及的圆柱形结构的相变存储单元，以相变材料层101包覆于异质结层102的外部为例，来说明该种结构的相变存储单元的制备方法，其如下所示：
步骤521：提供清洗干净的衬底，在衬底的表面形成一定厚度的外电极层25，使外电极层25铺于衬底的顶部表面。
步骤522：对外电极层25进行刻蚀，使外电极层25形成环状结构，然后，在外电极层25的内壁上形成异质结层102，形成的异质结层102也是环状结构。
步骤523：对异质结层102的内壁进行抛光，然后在异质结层102的内壁上形成相变材料层101，形成的相变材料层101也是环状结构。
步骤524：对相变材料层101的内壁进行抛光，然后在相变材料层101的内壁上中间电极层23，形成的中间电极层23也是环状结构。
步骤525：对中间电极层23的内壁进行抛光，然后在中间电极层23的内壁上形成选通层4，形成的选通层4也是环状结构。
步骤526：对选通层4的内壁进行抛光，然后在选通层4的内壁上形成内电极层24，其中，内电极层24可以形成为环状结构，也可以形成为实心的圆柱状结构(即，填满相变材料层101的圆孔即可)。
当异质结层102包覆于相变材料层101的外部时，所对应的相变存储单元的制备方法与上述相同，区别在于，改变步骤522，使外电极层25的内壁上形成相变材料层101，改变步骤523，使相变材料层101的内壁上形成异质结层102，改变步骤524使异质结层102的内壁上形成中间电极层23。
对于本公开实施例提供的相变存储单元的制备方法，如上所述，该相变存储单元的制备方法包括：制备相变薄膜1，制备相变薄膜1又包括：分别形成相变材料层101和异质结层102，并使相变材料层101和异质结层102接触。该过程包括：首先形成相变材料层101，然后在相变材料层101上形成异质结层102；或者，首先形成异质结层102，然后在异质结层102上形成相变材料层101。
在形成相变材料层101时，利用如上所述的相变材料，通过薄膜沉积工艺形成相变材料层101。在形成异质结层102时，利用如上所述的异质结材料，通过薄膜沉积工艺形成异质结层102。
如上所述，本公开实施例所适用的薄膜沉积工艺包括但不限于以下：原子层沉积(atomic layer deposition，ALD)、物理气相沉积(Physical Vapour Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)，例如，等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、磁控溅射、电子束蒸发等。
磁控溅射是物理气相沉积工艺的一种，具有易于控制、镀膜面积大、附着力强、制备对象广泛等优点，示例性地，本公开实施例可以使用磁控溅射工艺来形成相变材料层101和异质结层102。
再一方面，本公开实施例还提供了一种相变存储阵列，该相变存储阵列包括：上述所述的任一种相变存储单元100。
在一些示例中，该相变存储阵列中包含的多个相变存储单元100的结构为上述所述的限制型结构、T型结构、U型沟槽结构或者L字型结构。附图21示出了相变存储单元100为限制型结构时对应的相变存储阵列。
作为一种示例，对于图21所示的单个的相变存储单元100，可以通过以下方法制备得到：
提供一种包含有金属层作为位线层300的衬底，该金属层的材质可以为W。
通过丙酮和乙醇交替清洗包含该位线层300的衬底，去除表面的有机物、氧化物和金属离子等各类杂质，并在烘箱中烘烤80℃下烘烤20分钟，使其充分干燥。
通过磁控溅射法依次生长底电极21、选通层4、中间电极层23、相变材料层101、异质结层102、顶电极层22。
利用光刻和刻蚀工艺刻蚀位线层300上方的各膜层，直至暴露出位线层300。
通过PECVD工艺沉积绝缘介质层3，直至完全将各膜层完全包覆。示例地，绝缘介质层3的材质选自Si 3N 4。
通过抛光工艺将多余的绝缘介质层3去除，直到暴露出顶电极层22，最后在顶电极层22生长金属层作为字线层200。
在该示例中，底电极层21和顶电极层22所采用的材质均为TiN，磁控溅射的工作参数为：溅射电源为DC电源，溅射本底真空为8×10 -5Pa～2×10 -4Pa，溅射气体为Ar，溅射气压为3mTorr～6mTorr。
对于异质结层101和相变材料层102的磁控溅射参数为：溅射时候基板温度为150～300℃；其中，异质结层101使用ScTe靶材，溅射功率为10～20W；相变材料层使用Sb 2Te 3靶材，溅射功率为7W～30W。对于顶电极层22的磁控溅射参数为：基板温度为20～40℃，使用TiN靶材，溅射功率为50W～250W。另外，本示例中涉及的刻蚀工艺为反应离子刻蚀。
该相变存储阵列除了包括上述多个相变存储单元100之外，还包括字线层200、位线层300、多条字线400和多条位线500。
多个相变存储单元100按阵列排布，例如，任意相邻的四个相变存储单元100构成矩形形状，每一相变存储单元100的顶电极层22与一字线层200连接，每一相变存储单元100的底电极层21与一位线层300连接。
多条字线400按行依次排列，多条位线500按列依次排列，多行字线400与多行位线500配合形成与多个相变存储单元100相适配的阵列。
每一相变存储单元100位于由字线400和位线500构成的矩阵子单元内，每一相变存储单元100的顶电极层22通过与其连接的字线层200与相应列的位线500连接，每一相变存储单元100的底电极层21通过与其连接的位线层300与相应行的字线400连接。
该相变存储阵列在应用时，使成行排列的多条字线400与行选择电路A1连接，行选择电路A1又能够被行电压控制电路B1所驱动；使成列排列的多条位线500与列选择电路A2连接，列选择电路A2又能够被列电压控制电路B2所驱动。
应用时，读写电路C分别与行电压控制电路B1或者列电压控制电路B2连接，这样，读写电路C通过接收处理器的命令，经行电压控制电路B1或者列电压控制电路B2来控制行选择电路A1或者列选择电路A2，进而对被选中的相变存储单元100进行读写操作。
在另一些示例中，该相变存储阵列中包含的多个相变存储单元100为上述圆柱形结构的相变存储单元100，这些相变存储单元100位于同一层，参见图22-图23，这些相变存储单元100的外电极层25彼此连接以形成一整体式的电极基底250，也就是说，这个电极基底250可以供多个相变存储单元100共同使用。
该示例中，如附图22-附图25所示，该相变存储阵列除了包括上述多个相变存储单元100之外，还包括多个绝缘介质600、多个第一金属连接柱700、多个第二金属连接柱800、多条 字线400和多条位线500。
关于各部件的具体布置方面，多个相变存储单元100按阵列排布，例如，任意相邻的三个相变存储单元100能够构成等边三角形。
绝缘介质600为条状，例如为矩形条状结构，任一个绝缘介质600贯穿位于同一行的多个相变存储单元100，以内电极层24为环状结构举例来说，从径向方向上来看，绝缘介质600的宽度等于或者略大于内电极层24的内环直径。从轴向方向上来看，绝缘介质600的顶部表面和底部表面与相变存储单元100的顶部表面和底部表面持平。
任一相变存储单元100对应连接一个第一金属连接柱700，第一金属连接柱700例如为圆柱状，第一金属连接柱700的底部固定于相应位置处的绝缘介质600上，同时，第一金属连接柱700的底部还与对应相变存储单元100的内电极层24连接(通过使第一金属连接柱700的直径大于绝缘介质600的宽度来实现，同时，第一金属连接柱700的直径小于异质结层102的外径，以防止异质结层102短路)。
位于同一列的相变存储单元100对应一条位线500，该条位线500与同一列的相变存储单元100上的第一金属连接柱700的顶部连接。
在多个相变存储单元100共用的外电极层25上，也就是电极基底250上没有布置相变存储单元100的位置连接多个第二金属连接柱800(第二金属连接柱800例如为圆柱状)，多个第二金属连接柱800排列成一列，每一条字线400与一个第二金属连接柱800的顶部连接。
上述的具有单层相变存储单元100的相变存储阵列可以通过以下方法制备得到：
参见图22，提供第一中间阵列，在该第一中间阵列中，多个相变存储单元100按阵列排布，使得任意相邻的三个相变存储单元100构成等边三角形。相变存储单元100可以不包括选通层4，也可以包括选通层4。以下以相变存储单元100不包括选通层4举例说明该相变存储阵列的制备方法。
参见图23，在第一中间阵列上进行开孔，形成多行填充孔，然后，在每一行填充孔内均填充绝缘介质600，形成第二中间阵列。从径向方向上来看，填充孔的宽度等于或略大于内电极层24的内环直径，从轴向方向上来件，填充孔贯穿第一中间阵列的顶部和底部。
参见图24，在第二中间阵列上形成多个第一金属连接柱700，使第一金属连接柱700的底部固定于绝缘介质600上，同时，第一金属连接柱700的底部还与对应相变存储单元100的内电极层24连接。然后，在位于同一列的第一金属连接柱700的顶部连接一条状金属层来作为位线500。
在外电极层25上被绝缘介质600隔绝开的各区域上分别形成第二金属连接柱800，多个第二金属连接柱800成排列成一列，然后，在多个第二金属连接柱800的顶部连接另一条状金属层来作为字线400，最终形成上述相变存储阵列，相变存储阵列结构还可以参考图25。
应用时，通过字线400和位线500选择不同的相变存储单元100进行读写操作，通过施加窄而高的纳秒级电脉冲进行擦操作，通过宽而低的纳秒级电脉冲进行写操作，最后低电压来读取操作后的电阻状态；当在相变存储单元100与选通层4配合作用时，可以防止擦写操作的漏电流对邻近相变存储单元100的影响。
以上就相变存储阵列中多个相变存储单元100位于同一层的结构进行了阐述，在另一些示例中，如附图26-附图28所示，该相变存储阵列还可以包括多个位于不同层的相变存储单元100，也就是说，相变存储阵列包括多层相变存储子阵列，其中，多层相变存储子阵列沿 由上至下的方向依次分布并成台阶状，相邻两层相变存储子阵列之间使用绝缘介质层3隔开。本公开实施例将这种类型的相变存储阵列称为三维堆垛存储阵列。
在该三维堆垛存储阵列中，每一层相变存储子阵列的结构与上述相变存储单元100位于同一层的相变存储阵列的结构相同，在此不再一一阐述。
在制备这种包括多层相变存储子阵列的三维堆垛存储阵列时，其制备方法如下所示：
参见图26，使多层外电极层25和多层绝缘介质层3交替层叠，外电极层25和绝缘介质层900沿由上至下的方向层叠设置，并且成台阶状分布，这样，每一层的外电极层25均作为电极基底250使用。
参见图27和图28，在每一层外电极层25，即在每一层电极基底250形成多个相变存储单元100，进而形成多层第一中间阵列。第一中间阵列的结构与上述涉及的第一中间阵列结构相同，在此不再赘述。参照上述所述的方法，对每一层第一中间阵列进行处理，最终形成多层相变存储子阵列。相应地，在不同层的台阶处对应的外电极层25上被绝缘介质600隔绝开的各区域上分别形成第二金属连接柱800，并一一连接条状金属层作为字线400，最终形成如附图28所示的具有多层相变存储子阵列的三维堆垛存储阵列。
应用时，通过字线400和位线500选择不同的相变存储单元100进行读写操作，通过施加窄而高的纳秒级电脉冲进行擦操作，通过宽而低的纳秒级电脉冲进行写操作，最后低电压来读取操作后的电阻状态；当在相变存储单元100与选通层4配合作用时，可以防止擦写操作的漏电流对邻近相变存储单元100的影响。
进一步地，对于相变存储子阵列的多层设计，也就是说，通过横向增加一个微小的台阶的宽度就可以增加一层字线400，通过选择不同层的字线400来控制不同层的相变存储单元，100，在最大限度不增加存储面积的情形下，实现三维高密度存储的效果。
再一方面，本公开实施例还提供了一种相变存储器，该相变存储器包括多个上述的任一种相变存储单元。本公开实施例涉及的相变存储器可以认为是一种相变存储芯片。
基于使用了上述相变存储单元，本公开实施例提供的相变存储器，至少具有以下优点：稳定性高、重复性好、读写速度快、内存密度高、成本低等。
附图29提供了包括相变存储单元的相变存储器的一种应用场景示意图，其包括：通讯连接的相变存储器1001、动态随机存取存储器2001、缓存3001、处理器4001和固态硬盘5001，应用时，相变存储器1001和动态随机存取存储器2001能够共同作为混合内存。
附图30提供了包括相变存储单元的相变存储器的另一种应用场景示意图，其包括：通讯连接的相变存储器1001、缓存3001、处理器4001和固态硬盘5001，应用时，相变存储器100单独作为内存。
本公开实施例涉及的相变存储器的结构包括但不限于：1R结构、1T1R结构或者1D1R结构等。
本公开实施例涉及的包括相变存储单元的相变存储器，能够与动态随机存取存储器协同作用，甚至能够替代动态随机存取存储器作为内存，利于来增加内存的密度(例如，能达到4F 2的高密度)，易于和选通器件进行3维集成、和COMS工艺兼容，降低内存成本，同时避免了动态随机存取存储器不断刷新带来的功耗问题。
再一方面，本公开实施例还提供了一种存储设备，该存储设备包括控制器和上述的任一种相变存储器，控制器用于存储数据至相变存储芯器。控制器对存储设备中保存的数据进行读写，并和外部接口进行交互通讯。该存储设备可以被配置为存储各种类型的数据，这些数据可以为联系人数据，电话簿数据，消息，图片，视频等，也可以为指令性数据。
本公开实施例涉及的存储设备可以设置成各种类型，例如，这包括但不限于：内存、硬盘、磁盘、光盘等。
再一方面，本公开实施例还提供了一种电子设备，该电子设备包括处理器、以及，上述的相变存储器或者上述的存储设备，相变存储器用于存储处理器所访问的数据。
示例地，该电子设备包括但不限于：计算机、手机、打印机、相机、音乐播放设备、数字广播设备、消息收发设备、游戏控制设备、医疗设备、健身设备、个人数字助理等。
对于本公开实施例所使用的术语“每个”、“多个”及“任一”等，多个包括两个或两个以上，每个是指对应的多个中的每一个，任一是指对应的多个中的任意一个。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种相变存储单元，其特征在于，所述相变存储单元包括：相变薄膜(1)，所述相变薄膜(1)包括：一层相变材料层(101)和一层异质结层(102)，所述相变材料层(101)与所述异质结层(102)相接触；
    所述相变材料层(101)采用相变材料形成，所述异质结层(102)采用异质结材料形成；
    所述异质结材料与所述相变材料的晶格失配度小于或等于20％；所述异质结材料与所述相变材料的接触晶面具有相同的晶格夹角；以及，所述异质结材料的熔点大于所述相变材料的熔点。
  2. 根据权利要求1所述的相变存储单元，其特征在于，所述异质结材料与所述相变材料均为六方晶系材料，所述异质结材料的a轴与所述相变材料的a轴的长度差小于或等于20％。
  3. 根据权利要求1所述的相变存储单元，其特征在于，所述异质结材料为六方晶系材料，且所述相变材料为立方晶系材料，将所述异质结材料的a轴长度定义为a 1，将所述相变材料的a轴长度定义为a 2，a 1与√2a 2的差小于或等于20％。
  4. 根据权利要求1所述的相变存储单元，其特征在于，所述相变材料层(101)的厚度为2nm-100nm；
    所述异质结层(102)的厚度为2nm-20nm。
  5. 根据权利要求1所述的相变存储单元，其特征在于，所述相变材料为掺杂或者未掺杂的Ge-Te二元化合物、Sb-Te二元化合物、Bi-Te二元化合物、Ge-Sb-Te三元化合物、Ga-Sb二元化合物、Sb中的一种；
    所述异质结材料为M-Te化合物，其中，M为过渡金属元素。
  6. 根据权利要求5所述的相变存储单元，其特征在于，所述M为Ti、Zr、Pd、Cd、Mo、Mn、Ir、Rn、Pt、Sc、Ni、Ta、或者Zn。
  7. 根据权利要求5所述的相变存储单元，其特征在于，所述相变材料为掺杂材料时，掺杂元素选自C、N、Si、B、Sc、Ti、Y、Zr、Hf、V、Ta、W、Cu、Zn、In中的至少一种。
  8. 根据权利要求1-7任一项所述的相变存储单元，其特征在于，所述相变存储单元还包括：底电极层(21)、顶电极层(22)、绝缘介质层(3)；
    所述相变薄膜(1)位于所述底电极层(21)和所述顶电极层(22)之间；
    所述绝缘介质层(3)用于为所述相变存储单元提供绝缘隔离作用。
  9. 根据权利要求8所述的相变存储单元，其特征在于，所述相变存储单元还包括：中间 电极层(23)和选通层(4)；
    所述中间电极层(23)的第一表面与所述相变薄膜(1)接触，所述中间电极层(23)的第二表面与所述选通层(4)接触；
    所述相变薄膜(1)、所述中间电极层(23)和所述选通层(4)整体位于所述底电极层(21)和所述顶电极层(22)之间。
  10. 根据权利要求8或9所述的相变存储单元，其特征在于，所述相变存储单元为限制型结构、T型结构、U型沟槽结构、或者L字型结构。
  11. 根据权利要求1-7任一项所述的相变存储单元，其特征在于，所述相变存储单元为圆柱形结构，所述相变存储单元还包括：内电极层(24)和外电极层(25)；
    所述内电极层(24)、所述相变薄膜(1)、所述外电极层(25)沿径向方向由内至外依次包覆。
  12. 根据权利要求1-7任一项所述的相变存储单元，其特征在于，所述相变存储单元为圆柱形结构，所述相变存储单元还包括：内电极层(24)、中间电极层(23)、选通层(4)和外电极层(25)；
    所述内电极层(24)、所述相变薄膜(1)、所述中间电极层(23)、所述选通层(4)、所述外电极层(25)沿径向方向由内至外依次包覆。
  13. 一种相变存储阵列，其特征在于，所述相变存储阵列包括：权利要求1-12任一项所述的相变存储单元。
  14. 一种相变存储器，其特征在于，所述相变存储器包括权利要求1-12任一项所述的相变存储单元或者权利要求13所述的相变存储阵列。
  15. 一种电子设备，其特征在于，所述电子设备包括：处理器、权利要求14所述的相变存储器；
    所述相变存储器用于存储所述处理器所访问的数据。
  16. 一种相变存储单元的制备方法，其特征在于，所述相变存储单元如权利要求1-12任一项所述的相变存储单元；
    所述相变存储单元的制备方法包括：制备相变薄膜(1)；
    所述制备相变薄膜(1)包括：分别形成相变材料层(101)和异质结层(102)，并使所述相变材料层(101)和所述异质结层(102)接触。
  17. 根据权利要求16所述的相变存储单元的制备方法，其特征在于，通过薄膜沉积工艺分别形成所述相变材料层(101)和所述异质结层(102)。
  18. 根据权利要求17所述的相变存储单元的制备方法，其特征在于，所述薄膜沉积工艺为原子层沉积工艺、物理气相沉积工艺、化学气相沉积工艺、或者等离子体增强化学的气相沉积工艺。
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