WO2022257246A1 - 逻辑运算电路、差分放大电路及电子设备 - Google Patents

逻辑运算电路、差分放大电路及电子设备 Download PDF

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Publication number
WO2022257246A1
WO2022257246A1 PCT/CN2021/108500 CN2021108500W WO2022257246A1 WO 2022257246 A1 WO2022257246 A1 WO 2022257246A1 CN 2021108500 W CN2021108500 W CN 2021108500W WO 2022257246 A1 WO2022257246 A1 WO 2022257246A1
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Prior art keywords
transistor
differential
module
logic
unit
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PCT/CN2021/108500
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English (en)
French (fr)
Inventor
李世杰
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李世杰
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Priority claimed from CN202110640251.6A external-priority patent/CN113346894B/zh
Application filed by 李世杰 filed Critical 李世杰
Publication of WO2022257246A1 publication Critical patent/WO2022257246A1/zh
Priority to US18/527,506 priority Critical patent/US20240106399A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45264—Complementary cross coupled types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H03F1/0266—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45273—Mirror types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/261—Amplifier which being suitable for instrumentation applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45141—A cross coupled pair of transistors being added in the input circuit of a differential amplifier

Definitions

  • the application relates to the field of integrated circuits, in particular to a logic operation circuit, a differential amplifier circuit and electronic equipment.
  • a single signal line is used for signal transmission, and the signal changes between 0 and 1.
  • the voltage transmitted on the signal line is switched between high level and low level, and the inversion of the level needs to absorb or release a large amount of Charge, so that physical information such as circuit power consumption, electromagnetic radiation, or temperature exhibits different characteristics.
  • the data information inside the chip can be obtained, which is prone to side-channel attacks.
  • the present application provides a logic operation circuit, a differential amplifier circuit and electronic equipment to solve the problem that side channel attacks are prone to occur in the existing single signal line for signal transmission.
  • the logic operation circuit provided by this application includes at least one differential logic operation circuit, and the differential logic operation circuit includes: a logic network module, including a first logic network unit and a second logic network unit with complementary logic functions, the first logic The input signal of the network unit and the second logic network unit constitutes a differential signal, which is used to realize the preset logic function according to the input signal, and output the operation result;
  • the differential amplification module includes a first input terminal, a second input terminal, a first an output terminal and a second output terminal, the first input terminal and the second input terminal are respectively connected to the output terminals of the first logical network unit and the second logical network unit, and the first output terminal and the The second output terminal constitutes a differential output terminal for amplifying the operation result and outputting a logic operation result.
  • the differential amplification module includes: a differential amplification unit, connected to the output terminal of the logic network module, for amplifying the operation result and outputting the logic operation result; a pre-charging unit, connected to the differential amplification unit The unit connection is used to control the first output terminal and the second output terminal to be precharged to the power supply voltage during the pre-charging cycle; the current source unit is connected to the differential amplification unit and is used to give the power supply voltage during the evaluation cycle.
  • the differential amplifier unit provides a current path.
  • the differential amplification module further includes: a storage unit, connected to the output terminals of the first logical network unit and the second logical network unit, for storing information.
  • the differential amplification module further includes: an absorbing unit, connected to the storage unit, for absorbing excess charges generated when the storage unit is switched.
  • the storage unit includes: a first transistor and a second transistor; gates of the first transistor and the second transistor are connected to a clock signal, and drains are connected to the first logic network unit and the second transistor respectively.
  • the output terminal of the second logical network unit is connected, and the source is respectively connected to the first input terminal and the second input terminal.
  • the absorption unit includes: a third transistor and a fourth transistor; when the third transistor and the fourth transistor are N-channel transistors, the gate of the third transistor is connected to the source of the fourth transistor The drain is connected to the power supply voltage, the source is connected to the first input terminal; the gate of the fourth transistor is connected to the source of the third transistor, the drain is connected to the power supply voltage, and the source is connected to the first input terminal. Two input connections.
  • the gate of the third transistor is connected to the drain of the fourth transistor, the source is connected to the power supply voltage, and the drain is connected to the first input terminal ;
  • the gate of the fourth transistor is connected to the drain of the third transistor, the source is connected to the power supply voltage, and the drain is connected to the second input terminal.
  • N-channel transistors are such as N-channel MOS (Field Effect Transistor) transistors, and P-channel transistors are such as P-channel MOS transistors.
  • the differential amplification module further includes: at least one switched capacitor unit connected to the current source unit for increasing the range of the output driving voltage.
  • differential logic operation circuits are included; among the adjacent differential logic operation circuits, the output terminal of one of the differential logic operation circuits is connected to the input terminal of the other differential logic operation circuit to Implement cascading.
  • a clock buffer module connected between the differential logic operation circuits, and used to control the timing relationship between different differential logic operation circuits.
  • a differential amplification circuit comprising at least one differential module, the differential module includes a storage sub-module, a differential amplification sub-module, a pre-charging sub-module and a current source sub-module: the storage sub-module includes a differential input terminal for pre-charging Store the input differential signal during the period, and input the differential signal to the differential amplification sub-module; the differential amplification sub-module, including a differential output terminal, is connected to the storage sub-module, and is used to output a differential signal according to the differential signal Result; the pre-charging sub-module is connected with the differential amplifier sub-module, and is used to control the pre-charge of the differential output terminal to the power supply voltage during the pre-charging cycle; the current source sub-module is connected with the differential amplifier sub-module, and uses A current path is provided to the differential amplifier unit during an evaluation cycle.
  • the storage sub-module includes a differential input terminal for pre-charging Store the input differential signal during the period, and
  • it further includes: an absorbing sub-module connected to the storage sub-module for absorbing excess charges generated when the storage sub-module is switched.
  • it also includes a first differential module and a second differential module, the first input terminal of the first differential module is connected to the second output terminal of the second differential module, and the second input terminal is connected to the second differential module.
  • the first output terminal of the differential module is connected, the first output terminal is connected to the second input terminal of the second differential module, and the second output terminal is connected to the first input terminal of the second differential module.
  • a circuit for resisting side-channel attacks including the above-mentioned logic operation circuit.
  • An electronic device includes the logic operation circuit described above.
  • the above-mentioned differential amplifier circuit is also included.
  • the logic operation circuit of the present invention includes at least one differential logic operation circuit, the differential logic operation circuit includes: a logic network module and a differential amplification module, and the logic network module includes a first logic network unit and a second logic network with complementary logic functions unit, the input signals of the first logic network unit and the second logic network unit form a differential signal, and various preset logic functions can be realized through the logic network module. Since the output signal of the logic network module is weak, the logic The output result of the network module is connected to a differential amplifier module for signal amplification, and outputs the logical operation results in differential form.
  • the logic network module uses differential signals for signal transmission, the differential signals are characterized by positive and negative voltage differences between levels 0 and 1, the level change range is small, so that the physical information such as circuit power consumption, electromagnetic radiation or temperature does not change significantly, that is, no matter whether the transmitted information is 0 or 1, the physical quantities that can be captured by the outside world are the same, and it is not easy to obtain
  • the data information inside the chip prevents side channel attacks and improves data security.
  • using the logic network module can realize various logic functions, which increases the logic complexity of the circuit. Since the logic network module can be powered by a lower power supply voltage, the power consumption of the circuit is reduced; in addition, compared to using discrete devices to implement logic function, the use of dedicated logic network modules can reduce the number of components and optimize the chip area.
  • Fig. 1 is a schematic structural diagram of a logical operation circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a differential logic operation circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the circuit structure of a logical operation circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the circuit structure of a logical operation circuit according to an embodiment of the present invention.
  • 5 is a two-input XOR gate transmission calculation circuit according to an embodiment of the present invention.
  • FIG. 6 is a logic operation circuit with a switched capacitor unit according to an embodiment of the present invention.
  • FIG. 7 is a circuit diagram of cascaded differential logic operation circuits according to an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a clock buffer module according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a combination of 16bit carry-ahead adders according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a differential amplifier circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a circuit structure of a differential amplifier circuit according to an embodiment of the present invention.
  • FIG. 12 is a circuit diagram of generating a differential clock signal using a differential amplifier circuit according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a logic operation circuit according to an embodiment of the present invention.
  • the logic operation circuit 200 of this embodiment includes at least one differential logic operation circuit 100 .
  • the differential logic operation circuit 100 includes: a logic network module 1 and a differential amplification module 2 .
  • the logical network module 1 includes a first logical network unit 11 and a second logical network unit 12 with complementary logical functions, the input signal IN of the first logical network unit 11 and the input signal of the second logical network unit 12
  • the first logic network unit 11 and the second logic network unit 12 are preferably a combination of transistors, and different arrangements of transistors can be used to achieve different logic functions, such as XOR calculation, NAND calculation, 1-bit full adder, Arbitrary logic calculations such as 1-bit half adder to realize different preset logic functions.
  • the first logic network unit 11 and the second logic network unit 12 are arranged on both sides of the differential amplifier module 2, and the circuit connection mode is different from that of the DYCML (Dynamic Current Mode Logic) circuit, which includes the logic circuit in the charging and discharging unit, which can improve The complexity of the circuit.
  • DYCML Dynamic Current Mode Logic
  • the differential amplifier module 2 includes a first input terminal, a second input terminal, a first output terminal OUT and a second output terminal
  • the first input terminal of the differential amplification module 2 and the second input terminal of the differential amplification module 2 are respectively connected to the output terminals of the first logic network unit 11 and the second logic network unit 12, and the first An output terminal OUT and the second output terminal Constituting a differential output terminal, the differential amplifier module 2 is used to amplify the output operation results of the first logic network unit 11 and the second logic network unit 12 and output the logic operation result of the logic operation circuit 200 .
  • the differential amplification module 2 preferably includes: a current source unit 21, a pre-charging unit 22 and a differential amplification unit 23, and the differential amplification unit 23 is connected to the first logic network
  • the output terminal of the unit 11 and the second logic network unit 12 is used to amplify the operation result and then output the logic operation result
  • the pre-charging unit 22 is connected with the differential amplification unit 23 for controlling the pre-charging cycle
  • the first output terminal OUT and the second output terminal pre-charged to the power supply voltage VDD
  • the current source unit 21 is connected to the differential amplifier unit 23 and used to provide a current path for the differential amplifier unit 23 during the evaluation cycle.
  • the transistor M1, the transistor M2 and the capacitor C constitute the current source unit 21
  • the transistor M1 and the transistor M2 are N-channel MOS transistors
  • the gate of the transistor M1 is connected to the clock signal CLK
  • the source is connected to the drain of the transistor M2 and the capacitor C
  • One end of the transistor M2 is connected to the gate of the clock signal clock signal
  • the phase of CLK is opposite
  • the source of transistor M2 and the other end of capacitor C are grounded to GND.
  • the transistor M3 and the transistor M4 constitute the pre-charging unit 22, the transistor M3 and the transistor M4 are P-channel MOS transistors, the clock signal CLK is input to the gate of the transistor M3, the source of the transistor M3 is connected to the power supply voltage VDD, and the drain is connected to the first output The terminal OUT is connected; the clock signal CLK is input to the gate of the transistor M4, the source of the transistor M4 is connected to the power supply voltage VDD, and the drain is connected to the second output terminal connection, the pre-charging unit 22 is used to control the first output terminal OUT and the second output terminal The power supply voltage VDD is output during the precharge cycle.
  • the transistor M7 and the transistor M8 form a differential amplifier unit 23 for amplifying the operation results output by the first logic network unit 11 and the second logic network unit 12 and outputting the amplified logic operation results.
  • the transistor M7 and the transistor M8 are N-channel MOS transistors, the gate of the transistor M7 is connected to the output terminal of the first logic network unit 11, the drain is connected to the drain of the transistor M3, the source is connected to the drain of the transistor M1, and the gate of the transistor M8 The pole is connected to the output terminal of the second logic network unit 12, the drain is connected to the drain of the transistor M4, and the source is connected to the drain of the transistor M1.
  • the transistor M7 and the transistor M8 also constitute a PDN (pull-down network), which is used to connect the first output terminal OUT and the second output terminal Voltage is transmitted and amplified.
  • PDN pulse-down network
  • the logic operation circuit of this embodiment includes at least one differential logic operation circuit, the differential logic operation circuit includes: a logic network module and a differential amplification module, and the logic network module includes a first logic network unit and a second logic network unit with complementary logic functions
  • the network unit, the input signals of the first logic network unit and the second logic network unit form a differential signal, and various preset logic functions can be realized through the logic network module. Since the output signal of the logic network module is weak, it is also necessary to The output result of the logic network module is connected to a differential amplifier module for signal amplification, and outputs the result of logical operation in differential form.
  • the logic network module uses differential signals for signal transmission, the differential signals use the positive and negative voltage differences between levels to generate Representing 0 and 1, the level change is small, so that the physical information such as circuit power consumption, electromagnetic radiation or temperature does not change significantly, and it is not easy to obtain the data information inside the chip, preventing side channel attacks and improving data security.
  • the differential logic operation circuit of this embodiment sets the logic network module outside the differential amplifier module, and integrates the logic of various complex logic functions The network module is separated separately, and is connected with the differential input terminal of the differential amplifier module to realize the logic function of the logic network module, and more complex logic operations can be performed.
  • the cascode structure formed by the logic operation network and PDN inside the traditional differential circuit requires a higher power supply voltage to work, which increases the power consumption of the circuit, and the logic network module and the differential amplifier module in this embodiment are separated.
  • the logic network blocks use lower than supply voltage swings, reducing the power consumption of the circuit.
  • the differential amplification module 2 of this embodiment further includes a storage unit, which is connected to the The output terminals of the first logical network unit 11 and the second logical network unit 12 are used for information storage.
  • the differential amplifier module 2 of this embodiment further includes an absorbing unit connected to the storage unit for absorbing the The excess charge generated when a switch is switched.
  • the differential amplification module 2 of this embodiment further includes a latch unit.
  • FIG. 4 is a schematic circuit structure diagram of a logic operation circuit according to another embodiment of the present invention.
  • the differential amplification module 2 of this embodiment further includes: a latch unit, a storage unit and an absorption unit.
  • the transistor M5 and the transistor M6 are P-channel MOS transistors
  • the first transistor M9, the second transistor M10, the third transistor M11 and the fourth transistor M12 are N-channel MOS transistors
  • the transistor M5 and the transistor M6 constitute In the latch unit, the first transistor M9 and the second transistor M10 form a storage unit, and the third transistor M11 and the fourth transistor M12 form a sink unit.
  • the transistor M5 and the transistor M6 form a set of latches, the gate of the transistor M5 is connected to the drain of the transistor M4 and the transistor M6, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of the transistor M3 and the drain of the transistor M6 The gate is connected, and the source of the transistor M6 is connected to the power supply voltage VDD.
  • the latch unit is used to control the first output terminal OUT and the second output terminal during the evaluation period create a differential voltage.
  • the gate of the transistor M7 is connected to the source of the transistor M9, the drain is connected to the drain of the transistor M5, the source is connected to the drain of the transistor M1, the gate of the transistor M8 is connected to the source of the transistor M10, and the drain is connected to the transistor M6
  • the drain and the source are connected to the drain of the transistor M1.
  • the gates of the first transistor M9 and the second transistor M10 are connected to the clock signal
  • the drains are respectively connected to the output terminals of the first logic network unit 11 and the second logic network unit 12, and the sources are respectively connected to the gates of the transistor M7 and the transistor M8.
  • the first transistor M9 and the second transistor M10 control the charges stored in the gates of the transistor M7 and the transistor M8, so as to store information in the gates of the transistor M7 and the transistor M8.
  • the gate of the third transistor M11 is connected to the source of the fourth transistor M12 and the source of the second transistor M10, and the drain is connected to the power supply voltage VDD; the gate of the fourth transistor M12 is connected to the source of the third transistor M11 and the first The source of the transistor M9 is connected, and the drain is connected to the power supply voltage VDD.
  • the third transistor M11 and the fourth transistor M12 are respectively used to absorb excess charges generated by the first transistor M9 and the second transistor M10 when switching.
  • the third transistor M11 and the fourth transistor M12 are used to form a latch connection to optimize the channel charge injection effect of the first transistor M9 and the second transistor M10 .
  • Channel charge injection refers to the phenomenon that the charge in the channel region flows into or out of the MOS switch at the moment when the MOS (metal-oxide-semiconductor) device is turned on or off, changing the voltage of the corresponding node and introducing errors.
  • the optimization of the channel charge injection effect of the first transistor M9 and the second transistor M10 can improve circuit speed and reduce circuit power consumption.
  • the third transistor M11 and the fourth transistor M12 may be N-type transistors or P-type transistors.
  • the gate of the third transistor M11 is connected to the drain of the fourth transistor M12, the source is connected to the power supply voltage, and the drain is connected to the gate of the transistor M7;
  • the gate of the fourth transistor M12 is connected to the drain of the third transistor M11, the source is connected to the power supply voltage, and the drain is connected to the gate of the transistor M8.
  • the work of the logic operation circuit in Figure 4 is divided into a pre-charging cycle and an evaluation cycle, and the process is as follows:
  • the pre-charging cycle the clock signal CLK is at a low level, and the clock signal is high level
  • the transistor M3 and the transistor M4 in the precharge unit are turned on
  • the first output terminal OUT and the second output terminal The power supply voltage VDD is output
  • the first transistor M9 and the second transistor M10 are turned on
  • the output results of the first logic network unit 11 and the second logic network unit 12 are respectively stored in the gates of the transistor M7 and the transistor M8, and the third transistor M11 or
  • the fourth transistor M12 is turned on to absorb excess charges generated by the switching of the first transistor M9 or the second transistor M10.
  • the transistor M2 is turned on, so that the charge on the capacitor C is released to the ground GND.
  • the transistor M1 is turned off, and the current path between the power supply voltage VDD and the ground GND is closed.
  • the clock signal CLK is high, and the clock signal is low level
  • the transistor M3 and transistor M4 the first transistor M9, the second transistor M10, the third transistor M11, and the fourth transistor M12 in the pre-charging unit are closed, the transistor M1 in the current source unit is turned on, and the capacitor C constitutes Virtual ground, transistor M7 or transistor M8 is also turned on, the first output terminal OUT and the second output terminal A current path is formed to ground GND.
  • the transistor M5 and the transistor M6 in the latch unit will help the circuit balance, and when the output voltage drops to a certain level, the transistor M5 or the transistor M6 will be turned on so that the output voltage returns to the power supply voltage VDD again.
  • the operation of the logic operation circuit in this embodiment is divided into a pre-charging cycle and an evaluation cycle.
  • the first transistor M9 and the second transistor M10 are used to store control information to the gates of the transistors M7 and M8.
  • the function of the third transistor M11 and the fourth transistor M12 is to eliminate the harmful effect of the channel charge injection effect of the first transistor M9 and the second M10 transistor and utilize the beneficial effect.
  • the first transistor M9 and the second transistor M10 have one Low level needs to be stored, the other only stores high level, the benefits brought by the channel charge injection effect are retained in the low level gate, and the defects of the channel charge injection effect are eliminated by the third transistor M11 or the fourth transistor M12 Eliminated, so the transconductance difference of the PDN network is preserved, thus affecting the output result.
  • the function of transistor M3 and transistor M4 is to control the output level back to VDD in the pre-charging cycle, and the function of transistor M1 and transistor M2 is to flow the electrons of capacitor C into the logic network module in the evaluation cycle to perform logic operations.
  • the precharge cycle discharges capacitor C, causing electrons to be released to ground.
  • the main function of the transistor M5 and the transistor M6 is to keep the output state during the evaluation period.
  • the first output terminal OUT and the second output terminal of the logic operation circuit of this embodiment It will not be full swing, which makes the circuit consume less power and has a wider application range.
  • the current source unit 21 is a charge pump or any circuit that can realize the charge transfer function. Since the transistor M1, the transistor M2, and the capacitor C are used to provide a charge transfer path, the charge pump in the integrated circuit field can achieve the same function, so the capacitor C itself can be replaced by a common MOS in the integrated circuit field, or realized by using a MIM (metal capacitor), Or a special process is used to realize the capacitor inside the chip, or another chip is used to specifically place the capacitor, and the capacitor C is replaced by connecting to the current source unit 21 through a through hole on the chip or other bonding (bonding) wires.
  • MIM metal capacitor
  • the present invention proposes a new technical solution.
  • FIG. 5 shows a two-input XOR gate transmission calculation circuit according to another embodiment of the present invention.
  • the two-input XOR gate transmission calculation circuit in this embodiment is an instantiation formed after replacing the first logic network unit 11 and the second logic network unit 12 in FIG. 4 with preset XOR logic functions, and can complete two Input XOR function.
  • the transistor M13 and the transistor M15 constitute the first exclusive OR unit 110
  • the transistor M14 and the transistor M16 constitute the second exclusive OR unit 120
  • the transistor M13, the transistor M14, the transistor M15 and the transistor M16 are all N-channel MOS transistors
  • the transistor M13, the transistor M14, the transistor M15 and the transistor M16 are all N-channel MOS transistors, and the transistor M13
  • the gate is connected to the input signal
  • the drain is connected to the input signal B, the source is connected to the drain of the first transistor M9, the gate of the transistor M14 is connected to the input signal A, and the drain is connected to the input signal
  • the source is connected to the drain of the first transistor M9, and the gate of the transistor M14 is connected to the input signal Drain connected to input signal
  • the source is connected to the drain of the second transistor M10
  • the gate of the transistor M16 is connected to the input signal A
  • the drain is connected to the input signal B
  • the source is connected to the drain of the second transistor M10
  • this embodiment can realize the operation function of A XOR B, and can complete the storage operation together.
  • the logic operation circuit can omit the first transistor M9 and the second transistor M10 to realize a differential calculation circuit without a storage function. It should be noted that by replacing the logical network module with any network that can complete calculations, different logical calculation functions can be realized.
  • the logic operation circuit of the above embodiment can realize logic function calculation and information storage, but when cascaded with other circuits, the driving voltage range provided by the current source unit is relatively narrow. In order to increase the driving voltage range of the next stage circuit when logic operation circuits are cascaded, the present invention provides a new technical solution.
  • FIG. 6 a logic operation circuit with a switched capacitor unit according to another embodiment of the present invention.
  • the differential amplification module in the logic operation circuit with switched capacitor unit of this embodiment further includes at least one switched capacitor unit connected to the current source unit for increasing the range of the output driving voltage.
  • the switched capacitor unit includes: a transistor M17 and a transistor M18 , and the transistor M17 and the transistor M18 are N-channel transistors.
  • one end of the capacitor C in the current source unit is connected to the drain of the transistor M2, the other end of the capacitor C is connected to the drain of the transistor M18, and the gate of the transistor M17 is connected to the clock signal
  • the drain is connected to the power supply voltage VDD
  • the source is connected to the drain of the transistor M18
  • the gate of the transistor M18 is connected to the clock signal CLK
  • the source is connected to the ground GND.
  • the logic operation circuit of the above-mentioned embodiment is only a separate circuit, and the logic function realized by the circuit is relatively simple.
  • a new technical solution is further proposed on the basis of the above-mentioned embodiment, and the new technical solution It can solve the cascading problem of the logic operation circuit, increase the complexity of the circuit, and meet the timing requirements between the circuits at the same time.
  • FIG. 7 is a circuit diagram of cascaded differential logic operation circuits according to another embodiment of the present invention.
  • the logical operation circuit of this embodiment includes more than two differential logical operation circuits; among the adjacent differential logical operation circuits, the output end of one of the differential logical operation circuits is connected to the input end of the other differential logical operation circuit In order to realize cascading, the complexity of the circuit is increased. And because the timing requirements between the logic circuits are very high, in order to make the timing between the cascaded logic operation circuits meet the requirements, the logic operation circuit in this embodiment also includes: a clock buffer module, connected to the differential logic operation circuit is used to control the timing relationship between different differential logic operation circuits.
  • the logic operation circuit includes two differential logic operation circuits, a differential logic operation circuit 101 and a differential logic operation circuit 102, and the first output terminal OUT and the second output terminal of the differential logic operation circuit 101 Respectively with the input terminal IN of the differential logic operation circuit 102 and Corresponding connections are made to realize the cascade connection of the differential logic operation circuit 101 and the differential logic operation circuit 102 .
  • the logical network modules are connected according to the calculation relationship between the front and back stages, and can be connected to the next stage through the clock buffer module 103 according to the timing requirements.
  • transistor M21, transistor M24 are P-channel transistors
  • transistor M22, transistor M23 and transistor M25 are all N-channel MOS transistors
  • the gate of transistor M21 is connected to the clock signal CLK
  • the source is connected to the power supply voltage VDD
  • the drain is connected to the drain of the transistor M22
  • the gate of the transistor M22 is connected to the signal EOE (evaluation end signal)
  • the source is connected to the drain of the transistor M23
  • the gate of the transistor M23 is connected to the clock signal CLK
  • the source is grounded
  • the gate of the transistor M24 is connected to the drain of the transistor M21
  • the source is connected to the power supply voltage VDD
  • the drain is connected to the drain of the transistor M25
  • the gate of the transistor 25 is connected to the clock signal
  • the source is grounded, and the drain of the transistor M25 outputs a signal SE (start evaluation), and SE is connected to the gate of the transistor M19 in the differential logic operation circuit 102 .
  • SE start evaluation
  • connection method of the differential logic operation circuit in Fig. 7 its core technical point lies in the logic calculation module formed by N-type transistors, when the logic network module is used for calculation, the use of N-type transistors for all transistors will bring about an improvement in the power consumption delay product, Advantages over common CMOS or complementary logic.
  • the logic network module may also use P-type transistors or transmission gate logic.
  • Logical network modules can be divided, arranged and combined according to the specific calculation needs to achieve multiple functions. It should be noted that the differential logic operation circuits in Fig. 7 need the CLK signal to control the time sequence relationship, and determine when to perform evaluation and when to perform pre-charging based on the arrival of the determined clock signal.
  • the clock buffer module 103 in FIG. 7 can be omitted. If the phase difference between CLK can ensure that the timing meets the design requirements, the clock buffer module 103 in FIG. 7 can be omitted. If the differential logic operation circuits between the upper and lower stages need tight timing coordination, there is a tight timing between the logic relationship, the clock buffer module 103 in FIG. 8 needs to be used to meet timing requirements.
  • the differential logic operation circuit 101 may also be directly connected to the differential logic operation circuit 102 from a clock source. In other optional implementation manners, the differential logic can be implemented by controlling the timing relationship between different differential logic operation circuits, and connecting clocks with different phase differences between the differential logic operation circuit 101 and the differential logic operation circuit 102.
  • the timing between the operation circuit 101 and the differential logic operation circuit 102 is correct, and the differential logic operation circuit 101 and the differential logic operation circuit 102 can cooperate with each other to produce correct calculation results, which improves the accuracy of the calculation results.
  • the foregoing embodiments can realize cascade connection of logic operation circuits, and improve the logic complexity of the circuit.
  • the present invention provides an embodiment of implementing an adder by using the above-mentioned embodiment.
  • FIG. 9 a 16-bit (bit) look-ahead carry adder combination according to another embodiment of the present invention.
  • the 16bit (bit) look-ahead carry adder combination of the present embodiment is made up of four groups of 4bit look-ahead carry adders, and the 4bit look-ahead carry adder is realized using a differential logic operation circuit, and its internal logic network module is produced by a specific carry signal G and the logic decision of the carry transmission signal P, the specific calculation logic is:
  • G G3+P3G2+P3P2G1+P3P2P1G0
  • G0, G1, G2, and G3 are the carry generation signals of the 4-bit carry-ahead adder from low to high, respectively, and P0, P1, P2, and P3 are the carry transmission of the 4-bit carry-ahead adder from low to high.
  • Signal, G is the bit generation signal of the combined 16bit advanced carry adder.
  • multiple differential logic operation circuits can be used to implement an adder with more bits, which is not limited to the above examples.
  • the present invention also provides a differential amplifier circuit, which includes at least one differential module.
  • the differential amplifier circuit of this embodiment includes a differential module. Please refer to FIG. 10 .
  • the storage sub-module 31 includes a differential input terminal for storing the input differential signal during the pre-charging cycle, and inputs the differential signal to the differential amplification sub-module 32;
  • the differential amplification sub-module 32 includes a differential output terminal, Connected with the storage sub-module 31, for outputting a differential result according to the differential signal;
  • a pre-charging sub-module 33 connected with the differential amplification sub-module 32, for controlling the pre-charging of the differential output terminal during the pre-charging cycle charging to the power supply voltage;
  • the current source sub-module 34 is connected with the differential amplifier sub-module 32 and is used to provide a current path for the differential amplifier unit during the evaluation period.
  • the differential amplifier circuit of this embodiment can realize information storage by adding a storage sub-module 31 .
  • the differential module is connected with other circuit modules, which can realize the differential transmission of signals, so that the physical information such as circuit power consumption, electromagnetic radiation or temperature does not change significantly, and it is not easy to obtain the data information inside the chip, preventing side channel attacks and improving data security.
  • the integration of modules is getting higher and higher. By adding storage functions, it is convenient to connect with other modules to realize various complex logic functions.
  • the differential amplifier circuit in the above embodiment can realize information storage.
  • the present invention provides a new technical solution to optimize the storage sub-module 31 .
  • FIG. 11 is a schematic circuit structure diagram of a differential amplifier circuit according to another embodiment of the present invention.
  • the differential amplifier circuit of this embodiment also includes an absorption sub-module connected to the storage sub-module 31 for absorbing the excess charge generated by the storage sub-module 31 when the switch is switched, so as to increase the speed of the circuit and reduce the circuit power consumption.
  • the differential amplifier circuit of this embodiment includes: capacitor C1, transistor M41, transistor M42, transistor M43, transistor M44, transistor M45, transistor M46, transistor M47, transistor M48, transistor M49, transistor M50, transistor M51, transistor M52, power supply voltage VDD and ground GND.
  • the transistor M41, the transistor M42, the transistor M47, the transistor M48, the transistor M49, the transistor M50, the transistor M51, and the transistor M52 are N-channel MOS transistors
  • the transistor M43, the transistor M44, the transistor M45, and the transistor M46 are P-channel MOS transistors
  • Transistor M49 and transistor M50 form a storage sub-module
  • the gates of transistor M49 and transistor M50 are connected to a clock signal drains are connected to the differential input signals IN and
  • the sources are connected to the gates of the transistor M47 and the transistor M48 respectively.
  • the transistor M49 and the transistor M50 control the charges stored in the gates of the transistor M47 and the transistor M48, so that information is stored in the gates of the transistor M47 and the transistor M48.
  • the transistor M47 and the transistor M48 form a differential amplifier sub-module 32 for amplifying the input differential signals IN and
  • the gate of the transistor M47 is connected to the source of the transistor M49, the drain is connected to the drain of the transistor M45, the source is connected to the drain of the transistor M41, the gate of the transistor M48 is connected to the source of the transistor M50, and the drain is connected to the drain of the transistor M46 , the source is connected to the drain of the transistor M41.
  • the transistor M47 and the transistor M48 also constitute a PDN, which are respectively used to transmit and amplify the output node voltage.
  • the transistor M43 and the transistor M44 constitute the pre-charging sub-module 33, the clock signal CLK is input to the gate of the transistor M43, the source of the transistor M43 is connected to the power supply voltage VDD, and the drain is connected to the first output terminal OUT; the clock signal CLK is input to the transistor M44 The gate of the transistor M44 is connected to the power supply voltage VDD, and the drain is connected to the second output terminal connection, the pre-charge unit is used to control the first output terminal OUT and the second output terminal Output supply voltage during precharge cycle.
  • the transistor M41, the transistor M42 and the capacitor C1 constitute the current source sub-module 34, the gate of the transistor M41 is connected to the clock signal CLK, the source is connected to the drain of the transistor M42 and one end of the capacitor C1, and the gate of the transistor M42 is connected to the clock signal clock signal It constitutes an opposite signal to CLK, and the source of the transistor M42 and the other end of the capacitor C1 are grounded to GND.
  • the transistor M45 and the transistor M46 form a group of latches, forming the latch sub-module 35, the gate of the transistor M45 is connected to the drains of the transistor M44 and the transistor M46, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of the transistor M43 and the transistor The gate of the transistor M46 is connected, and the source of the transistor M46 is connected to the power supply voltage VDD.
  • the latch sub-module is used to control the first output terminal OUT and the second output terminal during the evaluation cycle create a differential voltage.
  • Transistor M51 and transistor M52 constitute an absorption sub-module, the gate of transistor M51 is connected to the source of transistor M52 and the source of transistor M50, and the drain is connected to the power supply voltage VDD; the gate of transistor M52 is connected to the source of transistor M51 and transistor M49 The source is connected to the source, the drain is connected to the power supply voltage VDD, and the transistor M51 and the transistor M52 are respectively used to absorb excess charges generated by the transistor M49 and the transistor M50 when the switch is switched.
  • the transistor M51 and the transistor M52 are used to form a latch connection to optimize the channel charge injection effect of the transistor M49 and the transistor M50.
  • Channel charge injection refers to the phenomenon that the charge in the channel region flows into or out of the MOS switch at the moment when the MOS device is turned on or off, changing the voltage of the corresponding node and introducing errors.
  • the optimization of the channel charge injection effect of the transistor M49 and the transistor M50 can improve circuit speed and reduce circuit power consumption.
  • the transistor M51 and the transistor M52 include N-type transistors and P-type transistors.
  • the gate of the transistor M51 is connected to the drain of the transistor M52, the source is connected to the power supply voltage, and the drain is connected to the gate of the transistor M47; the gate of the transistor M52 is connected to the gate of the transistor M51 The drain is connected, the source is connected to the power supply voltage, and the drain is connected to the gate of the transistor M48.
  • the operation of the differential amplifier circuit in FIG. 11 is divided into a pre-charging cycle and an evaluation cycle.
  • the principle and working process are similar to those of the differential logic operation circuit in FIG. 4 , and will not be repeated here.
  • the present invention provides the following embodiments.
  • FIG. 12 is a circuit diagram of generating a differential clock signal using a differential amplifier circuit according to another embodiment of the present invention.
  • the circuit diagram for generating a differential clock signal using a differential amplifier circuit in this embodiment includes a first differential module 321 and a second differential module 322, the first input terminal IN1 of the first differential module 321 is connected to the second differential module 322 second output connection, second input Connected to the first output terminal OUT2 of the second differential module 322, the first output terminal OUT1 is connected to the second input terminal of the second differential module 322 connection, the second output It is connected with the first input terminal IN2 of the second differential module 322, and the differential module is used to implement differential clock signals.
  • the present invention also provides a circuit for resisting side-channel attacks comprising the logic operation circuit described above.
  • a circuit for resisting side-channel attacks comprising the logic operation circuit described above.
  • physical information such as circuit power consumption, electromagnetic radiation, or temperature does not change significantly, and it is not easy to obtain data information inside the chip, preventing side channel attacks and improving data security.
  • various logic functions can be realized by using the logic network module, which increases the logic complexity of the circuit. Since the logic network module can be powered by a lower power supply voltage, the power consumption of the circuit is reduced.
  • the present invention also provides an electronic device including the above-mentioned logic operation circuit or differential amplifier circuit, such as a mobile phone, a tablet computer, a power amplifier, and the like.
  • a logic operation circuit or differential amplifier circuit such as a mobile phone, a tablet computer, a power amplifier, and the like.
  • physical information such as circuit power consumption, electromagnetic radiation, or temperature does not change significantly, and it is not easy to obtain data information inside the chip, preventing side channel attacks and improving data security.
  • various logic functions can be realized by using the logic network module, which can be used to realize more complex logic operations. Since the logic network module can be driven by a lower voltage, the power consumption of the circuit is reduced.

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Abstract

一种逻辑运算电路、差分放大电路及电子设备，逻辑运算电路（200）包括至少一差分逻辑运算电路（100），差分逻辑运算电路（100）包括：逻辑网络模块（1），包括逻辑功能互补的第一逻辑网络单元（11）和第二逻辑网络单元（12），第一逻辑网络单元（11）和第二逻辑网络单元（12）的输入信号构成差分信号，用于根据输入信号实现预设逻辑功能，并输出运算结果；差分放大模块（2），包括第一输入端、第二输入端、第一输出端和第二输出端，第一输入端和第二输入端分别与第一逻辑网络单元（11）和第二逻辑网络单元（12）的输出端连接，第一输出端和第二输出端构成差分输出端，用于对运算结果进行放大并输出逻辑运算结果。能够防止边信道攻击，提高数据的安全性，降低电路功耗。

Description

逻辑运算电路、差分放大电路及电子设备 技术领域
本申请涉及集成电路领域，具体涉及一种逻辑运算电路、差分放大电路及电子设备。
背景技术
近年来随着半导体集成电路的迅速发展，集成电路的漏洞带来的安全问题也愈加显著。边信道攻击，又称侧信道攻击，其核心思想是通过获取硬件运行时产生的各种泄漏信息分析出明文信息或密钥信息。硬件运行时产生的各种泄漏信息主要包括芯片内部电平翻转时的功耗、电磁辐射或者温度等变量，通过分析这些变量，可以捕获芯片内部的数据信息。随着移动支付的发展，越来越多的机密数据构建在芯片底层之上，尽管这些机密数据已经利用了加密算法进行保护，但是攻击者依然可以对芯片进行边信道分析从而获取内部明文、密钥等信息。另外，边信道攻击还会给各类电子设备带来重大安全隐患，尤其是AES(高级加密标准)加解密电子设备。
现有技术中使用单根信号线进行信号传输，信号在0/1之间变化，此时信号线上传输的电压在高电平和低电平之间切换，电平的翻转需要吸收或者释放大量电荷，从而使得电路功耗、电磁辐射或者温度等物理信息表现出不同特征，通过对该特征的分析，能够获得芯片内部的数据信息，容易发生边信道攻击。
技术问题
本申请提供一种逻辑运算电路、差分放大电路及电子设备，以解决现有的单根信号线进行信号传输，容易发生边信道攻击的问题。
技术解决方案
本申请提供的逻辑运算电路，包括至少一差分逻辑运算电路，所述差分逻辑运算电路包括：逻辑网络模块，包括逻辑功能互补的第一逻辑网络单元和第 二逻辑网络单元，所述第一逻辑网络单元和所述第二逻辑网络单元的输入信号构成差分信号，用于根据输入信号实现预设逻辑功能，并输出运算结果；差分放大模块，包括第一输入端、第二输入端、第一输出端和第二输出端，所述第一输入端和所述第二输入端分别与所述第一逻辑网络单元和所述第二逻辑网络单元的输出端连接，所述第一输出端和所述第二输出端构成差分输出端，用于对所述运算结果进行放大并输出逻辑运算结果。
可选的，所述差分放大模块包括：差分放大单元，连接于所述逻辑网络模块的输出端，用于放大所述运算结果后输出所述逻辑运算结果；预充电单元，与所述差分放大单元连接，用于在预充电周期时控制所述第一输出端和所述第二输出端预充电至电源电压；电流源单元，与所述差分放大单元连接，用于在求值周期时给所述差分放大单元提供电流通路。
可选的，所述差分放大模块还包括：存储单元，连接于所述第一逻辑网络单元和所述第二逻辑网络单元的输出端，用于进行信息存储。
可选的，所述差分放大模块还包括：吸收单元，与所述存储单元连接，用于吸收所述存储单元在开关切换时产生的多余电荷。
可选的，所述存储单元包括：第一晶体管和第二晶体管；所述第一晶体管和所述第二晶体管的栅极均连接时钟信号，漏极分别与所述第一逻辑网络单元和所述第二逻辑网络单元的输出端连接，源极分别连接所述第一输入端和第二输入端。
可选的，所述吸收单元包括：第三晶体管和第四晶体管；所述第三晶体管和第四晶体管为N沟道型晶体管时，第三晶体管的栅极与所述第四晶体管的源极连接，漏极接电源电压，源极与所述第一输入端连接；所述第四晶体管的栅极与所述第三晶体管的源极连接，漏极接电源电压，源极与所述第二输入端连接。所述第三晶体管和第四晶体管为P沟道型晶体管时，第三晶体管的栅极与所述第四晶体管的漏极连接，源极接电源电压，漏极与所述第一输入端连接；所述第四晶体管的栅极与所述第三晶体管的漏极连接，源极接电源电压，漏极与所述第二输入端连接。N沟道型晶体管比如N沟道MOS(场效应管)管，P 沟道型晶体管比如P沟道MOS管。
可选的，所述差分放大模块还包括：至少一开关电容单元，与所述电流源单元连接，用于增加输出驱动电压的范围。
可选的，包括两个以上所述差分逻辑运算电路；相邻所述差分逻辑运算电路中，其中一所述差分逻辑运算电路的输出端连接至另一所述差分逻辑运算电路的输入端以实现级联。
可选的，还包括：时钟缓冲模块，连接于所述差分逻辑运算电路之间，用于控制不同的所述差分逻辑运算电路之间的时序关系。
一种差分放大电路，包括至少一差分模块，所述差分模块包括存储子模块、差分放大子模块、预充电子模块和电流源子模块：存储子模块，包括差分输入端，用于在预充电周期时存储输入的差分信号，并将所述差分信号输入至所述差分放大子模块；差分放大子模块，包括差分输出端，与所述存储子模块连接，用于根据所述差分信号输出差分结果；预充电子模块，与所述差分放大子模块连接，用于在预充电周期时控制所述差分输出端预充电至电源电压；电流源子模块，与所述差分放大子模块连接，用于在求值周期时给所述差分放大单元提供电流通路。
可选的，还包括：吸收子模块，与所述存储子模块连接，用于吸收所述存储子模块在开关切换时产生的多余电荷。
可选的，还包括第一差分模块和第二差分模块，所述第一差分模块的第一输入端与所述第二差分模块的第二输出端连接，第二输入端与所述第二差分模块的第一输出端连接，第一输出端与所述第二差分模块的第二输入端连接，第二输出端与所述第二差分模块的第一输入端连接。
一种用于抵抗边信道攻击的电路，包括上述所述的逻辑运算电路。
一种电子设备，包括上述所述的逻辑运算电路。
可选的，还包括上述所述的差分放大电路。
有益效果
本发明的逻辑运算电路，包括至少一差分逻辑运算电路，所述差分逻辑运算电路包括：逻辑网络模块和差分放大模块，将逻辑网络模块包括逻辑功能互补的第一逻辑网络单元和第二逻辑网络单元，第一逻辑网络单元和所述第二逻辑网络单元的输入信号构成差分信号，通过逻辑网络模块可以实现各种预设的逻辑功能，由于逻辑网络模块输出的信号较弱，还需要将逻辑网络模块的输出结果连接到一差分放大模块进行信号放大，并输出差分形式的逻辑运算结果，由于将逻辑网络模块使用差分信号进行信号传输，差分信号采用电平之间的正负电压差来表征0和1，电平变化幅度小，从而使得电路功耗、电磁辐射或者温度等物理信息变化不明显，即无论传输的信息是0或者是1，对于外界能捕获的物理量均相同，不容易获得芯片内部的数据信息，防止了边信道攻击，提高了数据的安全性。另外，使用逻辑网络模块可实现各种逻辑功能，提高了电路的逻辑复杂性，由于逻辑网络模块可以使用较低的电源电压供电，降低了电路功耗；另外，相比于使用分立器件实现逻辑功能，使用专用的逻辑网络模块可以减少元器件数量，优化了芯片面积。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例的逻辑运算电路的结构示意图；
图2为本发明一实施例的差分逻辑运算电路的结构示意图；
图3为本发明一实施例的逻辑运算电路的电路结构示意图；
图4为本发明一实施例的逻辑运算电路的电路结构示意图；
图5为本发明一实施例的二输入异或门传输计算电路；
图6为本发明一实施例的带开关电容单元的逻辑运算电路；
图7为本发明一实施例的差分逻辑运算电路级联的电路图；
图8为本发明一实施例的时钟缓冲模块的电路图；
图9为本发明一实施例的16bit超前进位加法器组合的结构示意图；
图10为本发明一实施例的差分放大电路的结构示意图；
图11为本发明一实施例的差分放大电路的电路结构示意图；
图12为本发明一实施例的利用差分放大电路生成差分时钟信号的电路图。
本发明的实施方式
下面结合附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而非全部实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。在不冲突的情况下，下述各个实施例及其技术特征可以相互组合。
请参考图1，为本发明一个实施例的逻辑运算电路的结构示意图。
本实施例的逻辑运算电路200，包括至少一差分逻辑运算电路100。如图2所示，差分逻辑运算电路100包括：逻辑网络模块1和差分放大模块2。
逻辑网络模块1包括逻辑功能互补的第一逻辑网络单元11和第二逻辑网络单元12，所述第一逻辑网络单元11的输入信号IN和所述第二逻辑网络单元12的输入信号
Figure PCTCN2021108500-appb-000001
构成差分信号，第一逻辑网络单元11和第二逻辑网络单元12内部优选为晶体管的组合，可以采用晶体管不同排列来实现不同逻辑功能，比如异或计算、与非计算、1位全加器、1位半加器等任意逻辑计算以实现不同的预设逻辑功能。第一逻辑网络单元11和第二逻辑网络单元12设置在差分放大模块2的两侧，该电路连接方式不同于DYCML(动态电流模式逻辑)电路将逻辑电路包含在充放电单元之内，可以提高电路的复杂程度。
差分放大模块2包括第一输入端、第二输入端、第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000002
所述差分放大模块2的第一输入端和所述差分放大模块2的第二输入端分别与所述第一逻辑网络单元11和所述第二逻辑网络单元12的输出端连接，所述第一输出端OUT和所述第二输出端
Figure PCTCN2021108500-appb-000003
构成差分输出端，差分放大模 块2用于对第一逻辑网络单元11和所述第二逻辑网络单元12的输出运算结果进行放大并输出逻辑运算电路200的逻辑运算结果。
请参考图3，实施例的逻辑运算电路的电路结构示意图，差分放大模块2优选包括：电流源单元21、预充电单元22和差分放大单元23，差分放大单元23连接于所述第一逻辑网络单元11和第二逻辑网络单元12的输出端，用于放大所述运算结果后输出所述逻辑运算结果；预充电单元22，与所述差分放大单元23连接，用于在预充电周期时控制所述第一输出端OUT和所述第二输出端
Figure PCTCN2021108500-appb-000004
预充电至电源电压VDD；电流源单元21，与所述差分放大单元23连接，用于在求值周期时给所述差分放大单元23提供电流通路。具体的，晶体管M1、晶体管M2和电容C构成电流源单元21，晶体管M1和晶体管M2为N沟道MOS管，晶体管M1的栅极连接时钟信号CLK，源极连接晶体管M2的漏极和电容C的一端，晶体管M2的栅极连接时钟信号
Figure PCTCN2021108500-appb-000005
时钟信号
Figure PCTCN2021108500-appb-000006
与CLK的相位相反，晶体管M2的源极和电容C的另一端接地GND。晶体管M3和晶体管M4构成预充电单元22，晶体管M3和晶体管M4为P沟道MOS管，时钟信号CLK输入到晶体管M3的栅极，晶体管M3的源极连接电源电压VDD，漏极与第一输出端OUT连接；时钟信号CLK输入到晶体管M4的栅极，晶体管M4的源极连接电源电压VDD，漏极与第二输出端
Figure PCTCN2021108500-appb-000007
连接，预充电单元22用于控制第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000008
在预充电周期时输出电源电压VDD。晶体管M7和晶体管M8构成差分放大单元23，用于放大第一逻辑网络单元11和第二逻辑网络单元12输出的运算结果并输出放大后的逻辑运算结果。晶体管M7和晶体管M8为N沟道MOS管，晶体管M7的栅极连接第一逻辑网络单元11的输出端，漏极连接晶体管M3的漏极，源极连接晶体管M1的漏极，晶体管M8的栅极连接第二逻辑网络单元12的输出端，漏极连接晶体管M4的漏极，源极连接晶体管M1的漏极。同时，晶体管M7和晶体管M8也构成了PDN(下拉网络)，用于对第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000009
电压进行传输和放大。
本实施例的逻辑运算电路，包括至少一差分逻辑运算电路，所述差分逻辑运算电路包括：逻辑网络模块和差分放大模块，将逻辑网络模块包括逻辑功能 互补的第一逻辑网络单元和第二逻辑网络单元，第一逻辑网络单元和所述第二逻辑网络单元的输入信号构成差分信号，通过逻辑网络模块可以实现各种预设的逻辑功能，由于逻辑网络模块输出的信号较弱，还需要将逻辑网络模块的输出结果连接到一差分放大模块进行信号放大，并输出差分形式的逻辑运算结果，由于将逻辑网络模块使用差分信号进行信号传输，差分信号采用电平之间的正负电压差来表征0和1，电平变化幅度小，从而使得电路功耗、电磁辐射或者温度等物理信息变化不明显，不容易获得芯片内部的数据信息，防止了边信道攻击，提高了数据的安全性。另外，相比于现有技术中，在差分电路内部使用实现简单逻辑功能的电路，本实施例的差分逻辑运算电路将逻辑网络模块设置在差分放大模块的外部，将各种复杂逻辑功能的逻辑网络模块单独分离出来，并通过与差分放大模块的差分输入端连接以实现逻辑网络模块的逻辑功能，可以进行更复杂的逻辑运算。由于传统差分电路内部逻辑运算网络与PDN构成的共源共栅结构要求更高的电源电压才能工作，提高了电路的功耗，而本实施例中的逻辑网络模块与差分放大模块是分离的，逻辑网络模块使用低于电源电压摆幅，降低了电路的功耗。
上述实施例中的逻辑运算电路中逻辑网络模块的计算结果直接输出，无法进行存储。由于逻辑运算电路需要存储中间信息才能形成流水线用以提高计算能力，为了解决信息存储问题，在上述实施例的基础上，本实施例的差分放大模块2进一步包括存储单元，该存储单元连接于所述第一逻辑网络单元11和所述第二逻辑网络单元12的输出端，用于进行信息存储。又为了进一步优化沟道电荷注入效应，提高电路速度和降低电路功耗，本实施例的差分放大模块2进一步包括吸收单元，该吸收单元与所述存储单元连接，用于吸收所述存储单元在开关切换时产生的多余电荷。又为了使逻辑运算电路的输出稳定的差分电压，本实施例的差分放大模块2进一步包括锁存单元。
请参考图4，本发明的另一实施例的逻辑运算电路的电路结构示意图。
在图3的基础上，本实施例的差分放大模块2还包括：锁存单元、存储单元和吸收单元。
如图4所示，晶体管M5和晶体管M6为P沟道MOS管，第一晶体管M9、第二晶体管M10、第三晶体管M11与第四晶体管M12为N沟道MOS管，晶体管M5和晶体管M6构成锁存单元，第一晶体管M9和第二晶体管M10构成存储单元，第三晶体管M11和第四晶体管M12构成吸收单元。晶体管M5和晶体管M6构成一组latch(锁存器)，晶体管M5的栅极与晶体管M4和晶体管M6的漏极连接，源极连接电源电压VDD，漏极与晶体管M3的漏极和晶体管M6的栅极连接，晶体管M6的源极连接电源电压VDD。锁存单元用于在求值周期时控制第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000010
形成差分电压。此时，晶体管M7的栅极连接晶体管M9的源极，漏极连接晶体管M5的漏极，源极连接晶体管M1的漏极，晶体管M8的栅极连接晶体管M10的源极，漏极连接晶体管M6的漏极，源极连接晶体管M1的漏极。第一晶体管M9和第二晶体管M10的栅极连接时钟信号
Figure PCTCN2021108500-appb-000011
漏极分别与所述第一逻辑网络单元11和所述第二逻辑网络单元12的输出端连接，源极分别与晶体管M7和晶体管M8的栅极连接。第一晶体管M9和第二晶体管M10对于存储于晶体管M7和晶体管M8栅极的电荷进行控制，实现了将信息存储在晶体管M7和晶体管M8的栅极。第三晶体管M11的栅极与第四晶体管M12的源极和第二晶体管M10的源极连接，漏极接电源电压VDD；第四晶体管M12的栅极与第三晶体管M11的源极和第一晶体管M9的源极连接，漏极接电源电压VDD，第三晶体管M11和第四晶体管M12分别用于吸收由第一晶体管M9，第二晶体管M10在开关切换时产生的多余电荷。利用第三晶体管M11和第四晶体管M12构成latch连接以实现第一晶体管M9和第二晶体管M10沟道电荷注入效应的优化。沟道电荷注入指的是在MOS(金属-氧化物-半导体)器件导通或关断的瞬间，沟道区内的电荷流入或流出MOS开关，改变对应节点的电压，引入误差的现象。第一晶体管M9和第二晶体管M10沟道电荷注入效应的优化可以提高电路速度和降低电路功耗。第三晶体管M11和第四晶体管M12可以是N型晶体管或者P型晶体管。当第三晶体管M11和第四晶体管M12为P型晶体管时，第三晶体管M11的栅极与第四晶体管M12的漏极连接，源极接电源电压，漏极与晶体管M7的栅极连接；第四晶体管M12 的栅极与第三晶体管M11的漏极连接，源极接电源电压，漏极与晶体管M8的栅极连接。
图4中的逻辑运算电路的工作分成预充电周期和求值周期，过程如下：在预充电周期，时钟信号CLK为低电平，时钟信号
Figure PCTCN2021108500-appb-000012
为高电平，预充电单元中晶体管M3和晶体管M4导通，第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000013
输出电源电压VDD，第一晶体管M9和第二晶体管M10导通，第一逻辑网络单元11和第二逻辑网络单元12的输出结果分别存储在晶体管M7和晶体管M8的栅极，第三晶体管M11或第四晶体管M12导通，吸收第一晶体管M9或第二晶体管M10开关产生的多余电荷。此时，晶体管M2导通，使得电容C上的电荷释放到地GND。同时，晶体管M1是关闭的，电源电压VDD到地GND之间电流通路关闭。在求值周期，时钟信号CLK为高电平，时钟信号
Figure PCTCN2021108500-appb-000014
为低电平，预充电单元中晶体管M3和晶体管M4、第一晶体管M9、第二晶体管M10、第三晶体管M11、第四晶体管M12是关闭的，电流源单元中晶体管M1导通，电容C构成虚拟地，晶体管M7或者晶体管M8也导通，第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000015
到地GND形成了电流通路。由于第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000016
的电流通路有不同的阻抗，因此，会出现一个输出电压比另一个输出电压下降较快的情况。此时，锁存单元中晶体管M5和晶体管M6会帮助电路平衡，当输出电压下降到一定程度时，晶体管M5或晶体管M6会导通以使得输出电压再次回到电源电压VDD。
可见，本实施例的逻辑运算电路，工作分成预充电周期和求值周期，第一晶体管M9，第二晶体管M10作用是控制信息的存储至晶体管M7和M8的栅极。在求值周期中，第三晶体管M11，第四晶体管M12的作用是消除第一晶体管M9，第二M10晶体管的沟道电荷注入效应的有害影响，利用有益影响。由于第一晶体管M9的沟道电荷注入影响被第三晶体管M11所消除，第二晶体管M10的沟道电荷注入影响被第四晶体管M12所消除，因此第一晶体管M9，第二晶体管M10晶体管有一只需要存储低电平，另一只存储高电平，沟道电荷注入效应所带来的益处被保留在低电平栅极，沟道电荷注入效应的缺陷被第三晶体管 M11或者第四晶体管M12所消除，因此PDN网络的跨导差值被保留，从而影响输出结果。晶体管M3，晶体管M4的作用是在预充电周期控制输出电平回到VDD，晶体管M1，晶体管M2的作用是在求值周期，通过将电容C的电子流入逻辑网络模块，从而进行逻辑运算，在预充电周期对电容C进行放电，使得电子释放到地。晶体管M5，晶体管M6的主要作用是使得输出状态在求值周期得到保持。另外，本实施例的逻辑运算电路的第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000017
不会满摆幅，使得电路功耗更低，适用范围更广。
图4中的晶体管可以部分或全部为P型晶体管也可以为N型晶体管。另外，电流源单元21为电荷泵或任意可实现电荷搬运功能的电路。由于晶体管M1，晶体管M2，电容C用于提供电荷搬运通路，集成电路领域电荷泵能够实现相同功能，因此电容C本身可以用集成电路领域常见的MOS代替实现，或者利用MIM(金属电容)实现，或者特殊工艺在芯片内部来实现电容，或是通过另一颗芯片专门放置电容，通过芯片上的通孔或者其他bonding(键合)线连接至电流源单元21以替代电容C。
为了实现二输入异或门传输计算，在上述实施例的基础上，本发明提出了一种新的技术方案。
请参考图5，本发明的另一实施例的二输入异或门传输计算电路。
本实施例的二输入异或门传输计算电路是将图4中的第一逻辑网络单元11和第二逻辑网络单元12替换成了预设的异或逻辑功能之后形成的实例化，能够完成二输入异或功能。图5中晶体管M13和晶体管M15构成第一异或单元110，晶体管M14和晶体管M16构成第二异或单元120，晶体管M13、晶体管M14、晶体管M15和晶体管M16均为N沟道MOS管，晶体管M13的栅极接输入信号
Figure PCTCN2021108500-appb-000018
漏极接输入信号B，源极接第一晶体管M9的漏极，晶体管M14的栅极接输入信号A，漏极接输入信号
Figure PCTCN2021108500-appb-000019
源极接第一晶体管M9的漏极，晶体管M14的栅极接输入信号
Figure PCTCN2021108500-appb-000020
漏极接输入信号
Figure PCTCN2021108500-appb-000021
源极接第二晶体管M10的漏极，晶体管M16的栅极接输入信号A，漏极接输入信号B，源极接第二晶体管M10的漏极，输入信号A和B是异或门的两输入信号，本实施例可以实现A异或B的 运算功能，且能够存储运算一起完成。逻辑运算电路优选地可以省去第一晶体管M9和第二晶体管M10以实现没有存储功能的差分计算电路。需要说明的是，通过将逻辑网络模块替换成任意能够完成计算的网络，从而实现不同的逻辑计算功能。
上述实施例的逻辑运算电路可以实现逻辑功能的计算及信息存储，但是与其他电路级联时，电流源单元提供的驱动电压的范围较窄。为了在逻辑运算电路级联时增加下一级电路的驱动电压的范围，本发明提供了一种新的技术方案。
请参加图6，本发明的另一实施例的带开关电容单元的逻辑运算电路。
本实施例的带开关电容单元的逻辑运算电路中差分放大模块进一步包括至少一开关电容单元，与所述电流源单元连接，用于增加输出驱动电压的范围。如图6所示，开关电容单元包括：晶体管M17和晶体管M18，晶体管M17和晶体管M18为N沟道型晶体管。此时，电流源单元中的电容C的一端与晶体管M2的漏极连接，电容C的另一端与晶体管M18的漏极连接，晶体管M17的栅极连接时钟信号
Figure PCTCN2021108500-appb-000022
漏极连接电源电压VDD，源极与晶体管M18的漏极连接，晶体管M18的栅极连接时钟信号CLK，源极连接地GND。通过增加开关电容单元可以减小电容C的容量，减少电容C的面积，晶体管M1的源极输出驱动电压的范围更大。
上述实施例的逻辑运算电路仅是单独的电路，电路实现的逻辑功能相对简单，为了实现更为复杂的电路逻辑功能，在上述实施例的基础上进一步提出了新的技术方案，新的技术方案可以解决逻辑运算电路的级联问题，增加电路的复杂度，同时满足各电路之间的时序要求。
请参看图7，本发明的另一实施例的差分逻辑运算电路级联的电路图。
本实施例的逻辑运算电路包括两个以上差分逻辑运算电路；相邻所述差分逻辑运算电路中，其中一所述差分逻辑运算电路的输出端连接至另一所述差分逻辑运算电路的输入端以实现级联，增加电路的复杂度。又由于逻辑电路之间对时序的要求很高，为了使级联的逻辑运算电路之间的时序满足要求，本实施例中逻辑运算电路还包括：时钟缓冲模块，连接于所述差分逻辑运算电路之间， 用于控制不同的所述差分逻辑运算电路之间的时序关系。
具体的，如图7所示，逻辑运算电路包括两个差分逻辑运算电路，差分逻辑运算电路101和差分逻辑运算电路102，差分逻辑运算电路101的第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000023
分别与差分逻辑运算电路102的输入端IN和
Figure PCTCN2021108500-appb-000024
对应连接，以实现差分逻辑运算电路101和差分逻辑运算电路102级联。其中逻辑网络模块之间根据前后级的计算关系进行连接，根据时序需求，可以通过时钟缓冲模块103与下一级相连接。
图7中的时钟缓冲模块103如图8所示，晶体管M21、晶体管M24为P沟道型晶体管、晶体管M22、晶体管M23和晶体管M25均为N沟道MOS管，晶体管M21的栅极连接时钟信号CLK，源极接电源电压VDD，漏极连接晶体管M22的漏极，晶体管M22的栅极连接信号EOE(求值结束信号)，源极连接晶体管M23的漏极，晶体管M23的栅极连接时钟信号CLK，源极接地，晶体管M24的栅极连接晶体管M21的漏极，源极接电源电压VDD，漏极连接晶体管M25的漏极，晶体管25的栅极连接时钟信号
Figure PCTCN2021108500-appb-000025
源极接地，晶体管M25的漏极输出信号SE(开始求值)，SE与差分逻辑运算电路102中的晶体管M19的栅极连接。在预充电周期，时钟缓冲模块103的EOE节点电压为0，在求值周期开始，电容C开始充电，EOE输出高电平以给差分逻辑运算电路102提供驱动。
图7中的差分逻辑运算电路的连接方法，其核心技术要点在于N型晶体管形成的逻辑计算模块，该逻辑网络模块用于计算时，所有晶体管使用N型会带来功耗延迟积的改善，比常见CMOS或者互补逻辑更有优势。在其他实施方式中，逻辑网络模块也可使用P型晶体管或传输门逻辑。逻辑网络模块可根据具体需要的计算进行分割，排列和组合以实现多种功能。需要说明的是，图7中的各差分逻辑运算电路之间需要CLK信号来控制时间序列关系，通过确定的时钟信号到来的早晚，来决定何时进行求值，何时进行预充电。如果CLK之间的相位差能够保证时序满足设计要求，图7中的时钟缓冲模块103可以省略，若上下两级之间的差分逻辑运算电路之间需要紧密的时序配合，逻辑之间有紧密 时序关系，则需要使用图8中的时钟缓冲模块103，以满足时序要求。差分逻辑运算电路101也可直接从时钟源连接至差分逻辑运算电路102。在其他可选的实施方式中，可通过控制不同的所述差分逻辑运算电路之间的时序关系，并在差分逻辑运算电路101和差分逻辑运算电路102连接不同相位差的时钟，以实现差分逻辑运算电路101和差分逻辑运算电路102之间时序正确，差分逻辑运算电路101和差分逻辑运算电路102能够相互配合产生正确的计算结果，提高了计算结果的准确性。
上述实施例可以实现逻辑运算电路的级联，提高电路的逻辑复杂度。本发明提供了一利用上述实施例实现加法器的实施例。
请参见图9，本发明的另一实施例的16bit(比特)超前进位加法器组合。
本实施例的16bit(比特)超前进位加法器组合，由四组4bit超前进位加法器构成，4bit超前进位加法器使用差分逻辑运算电路实现，其内部逻辑网络模块由具体进位产生信号G和进位传输信号P的逻辑决定，具体计算逻辑是：
G＝G3+P3G2+P3P2G1+P3P2P1G0
其中，G0、G1、G2、G3分别为由低位到高位的4bit超前进位加法器的进位产生信号，P0、P1、P2、P3分别为由低位到高位的4bit超前进位加法器的进位传输信号，G为组合后的16bit超前进位加法器的位产生信号。
本实施例可以使用多个差分逻辑运算电路实现更多比特位的加法器，不限于以上举例内容。
本发明还提供一种差分放大电路，差分放大电路包括至少一差分模块。本实施例的差分放大电路包括一个差分模块，请参见图10，差分模块包括存储子模块31、差分放大子模块32、预充电子模块33和电流源子模块34。
存储子模块31，包括差分输入端，用于在预充电周期时存储输入的差分信号，并将所述差分信号输入至所述差分放大子模块32；差分放大子模块32，包括差分输出端，与所述存储子模块31连接，用于根据所述差分信号输出差分结果；预充电子模块33，与所述差分放大子模块32连接，用于在预充电周期时控制所述差分输出端预充电至电源电压；电流源子模块34，与所述差分放大子模 块32连接，用于在求值周期时给所述差分放大单元提供电流通路。
本实施例的差分放大电路，通过增加存储子模块31，可实现信息存储。该差分模块与其他电路模块连接，可以实现信号的差分形式传输，从而使得电路功耗、电磁辐射或者温度等物理信息变化不明显，不容易获得芯片内部的数据信息，防止了边信道攻击，提高了数据的安全性。另外，随着集成电路的功能越来越复杂，模块集成度越来越高，通过增加存储功能方便与其他模块进行连接，实现各种复杂逻辑功能。
上述实施例的差分放大电路可以实现信息存储，为了进一步提高电路速度和降低电路功耗，本发明提供了一种新的技术方案对存储子模块31进行优化。
请参见图11，本发明另一实施例的差分放大电路的电路结构示意图。
本实施例的差分放大电路还包括吸收子模块，吸收子模块与所述存储子模块31连接，用于吸收所述存储子模块31在开关切换时产生的多余电荷，以提高电路的速度，降低电路功耗。
具体的，如图11所示，本实施例的差分放大电路，包括：电容C1、晶体管M41、晶体管M42、晶体管M43、晶体管M44、晶体管M45、晶体管M46、晶体管M47、晶体管M48、晶体管M49、晶体管M50、晶体管M51、晶体管M52、电源电压VDD和接地GND。其中，晶体管M41、晶体管M42、晶体管M47、晶体管M48、晶体管M49、晶体管M50、晶体管M51、晶体管M52为N沟道MOS管，晶体管M43、晶体管M44、晶体管M45、晶体管M46为P沟道MOS管，晶体管M49和晶体管M50构成存储子模块，晶体管M49和晶体管M50的栅极连接时钟信号
Figure PCTCN2021108500-appb-000026
漏极分别与差分输入信号IN和
Figure PCTCN2021108500-appb-000027
连接，源极分别与晶体管M47和晶体管M48的栅极连接。晶体管M49和晶体管M50对于存储于晶体管M47和晶体管M48栅极的电荷进行控制，实现了将信息存储在晶体管M47和晶体管M48的栅极。
晶体管M47和晶体管M48构成差分放大子模块32，用于放大输入的差分信号IN和
Figure PCTCN2021108500-appb-000028
晶体管M47的栅极连接晶体管M49的源极，漏极连接晶体管M45的漏极，源极连接晶体管M41的漏极，晶体管M48的栅极连接晶体管M50 的源极，漏极连接晶体管M46的漏极，源极连接晶体管M41的漏极。同时，晶体管M47和晶体管M48也构成了PDN，分别用于对输出节点电压进行传输和放大。
晶体管M43和晶体管M44构成预充电子模块33，时钟信号CLK输入到晶体管M43的栅极，晶体管M43的源极连接电源电压VDD，漏极与第一输出端OUT连接；时钟信号CLK输入到晶体管M44的栅极，晶体管M44的源极连接电源电压VDD，漏极与第二输出端
Figure PCTCN2021108500-appb-000029
连接，预充电单元用于控制第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000030
在预充电周期时输出电源电压。
晶体管M41、晶体管M42和电容C1构成电流源子模块34，晶体管M41的栅极连接时钟信号CLK，源极连接晶体管M42的漏极和电容C1的一端，晶体管M42的栅极连接时钟信号
Figure PCTCN2021108500-appb-000031
时钟信号
Figure PCTCN2021108500-appb-000032
与CLK构成相反信号，晶体管M42的源极和电容C1的另一端接地GND。
晶体管M45和晶体管M46构成一组latch，构成锁存子模块35，晶体管M45的栅极与晶体管M44和晶体管M46的漏极连接，源极连接电源电压VDD，漏极与晶体管M43的漏极和晶体管M46的栅极连接，晶体管M46的源极连接电源电压VDD。锁存子模块用于在求值周期时控制第一输出端OUT和第二输出端
Figure PCTCN2021108500-appb-000033
形成差分电压。
晶体管M51和晶体管M52构成吸收子模块，晶体管M51的栅极与晶体管M52的源极和晶体管M50的源极连接，漏极接电源电压VDD；晶体管M52的栅极与晶体管M51的源极和晶体管M49的源极连接，漏极接电源电压VDD，晶体管M51和晶体管M52分别用于吸收由晶体管M49，晶体管M50在开关切换时产生的多余电荷。利用晶体管M51和晶体管M52构成latch连接以实现晶体管M49和晶体管M50沟道电荷注入效应的优化。沟道电荷注入指的是在MOS器件导通或关断的瞬间，沟道区内的电荷流入或流出MOS开关，改变对应节点的电压，引入误差的现象。晶体管M49和晶体管M50沟道电荷注入效应的优化可以提高电路速度和降低电路功耗。晶体管M51和晶体管M52包括N型晶体管和P型晶体管。当晶体管M51和晶体管M52为P型晶体管时，晶体管M51 的栅极与晶体管M52的漏极连接，源极接电源电压，漏极与晶体管M47的栅极连接；晶体管M52的栅极与晶体管M51的漏极连接，源极接电源电压，漏极与晶体管M48的栅极连接。
图11中的差分放大电路的工作分成预充电周期和求值周期，原理与工作过程与图4中的差分逻辑运算电路类似，此处不再赘述。
为了实现差分放大电路之间的级联，在上述实施例的基础上，本发明提供了下面的实施例。
请参见图12，本发明另一实施例的利用差分放大电路生成差分时钟信号的电路图。
本实施例的利用差分放大电路生成差分时钟信号的电路图，包括第一差分模块321和第二差分模块322，所述第一差分模块321的第一输入端IN1与所述第二差分模块322的第二输出端
Figure PCTCN2021108500-appb-000034
连接，第二输入端
Figure PCTCN2021108500-appb-000035
与所述第二差分模块322的第一输出端OUT2连接，第一输出端OUT1与所述第二差分模块322的第二输入端
Figure PCTCN2021108500-appb-000036
连接，第二输出端
Figure PCTCN2021108500-appb-000037
与所述第二差分模块322的第一输入端IN2连接，该差分模块用于实现差分时钟信号。
本发明还提供一种包括上述的逻辑运算电路的用于抵抗边信道攻击的电路。通过上述逻辑运算电路使得电路功耗、电磁辐射或者温度等物理信息变化不明显，不容易获得芯片内部的数据信息，防止了边信道攻击，提高了数据的安全性。另外，使用逻辑网络模块可实现各种逻辑功能，提高了电路的逻辑复杂性，由于逻辑网络模块可以使用较低的电源电压供电，降低了电路功耗。
本发明还提供一种包括上述的逻辑运算电路或差分放大电路的电子设备，例如手机、平板电脑、功放等。通过上述逻辑运算电路或差分放大电路，使得电路功耗、电磁辐射或者温度等物理信息变化不明显，不容易获得芯片内部的数据信息，防止了边信道攻击，提高了数据的安全性。另外，使用逻辑网络模块可实现各种逻辑功能，可用于实现更复杂的逻辑运算，由于逻辑网络模块可以使用较低的电压驱动，降低了电路功耗。
即，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡 是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (14)

  1. 一种逻辑运算电路，其特征在于，包括至少一差分逻辑运算电路，所述差分逻辑运算电路包括：
    逻辑网络模块，包括逻辑功能互补的第一逻辑网络单元和第二逻辑网络单元，所述第一逻辑网络单元和所述第二逻辑网络单元的输入信号构成差分信号，用于根据输入信号实现预设逻辑功能，并输出运算结果；
    差分放大模块，包括第一输入端、第二输入端、第一输出端和第二输出端，所述第一输入端和所述第二输入端分别与所述第一逻辑网络单元和所述第二逻辑网络单元的输出端连接，所述第一输出端和所述第二输出端构成差分输出端，用于对所述运算结果进行放大并输出逻辑运算结果。
  2. 如权利要求1所述的逻辑运算电路，其特征在于，所述差分放大模块包括：
    差分放大单元，连接于所述逻辑网络模块的输出端，用于放大所述运算结果后输出所述逻辑运算结果；
    预充电单元，与所述差分放大单元连接，用于在预充电周期时控制所述第一输出端和所述第二输出端预充电至电源电压；
    电流源单元，与所述差分放大单元连接，用于在求值周期时给所述差分放大单元提供电流通路。
  3. 如权利要求2所述的逻辑运算电路，其特征在于，所述差分放大模块还包括：
    存储单元，连接于所述第一逻辑网络单元和所述第二逻辑网络单元的输出端，用于进行信息存储。
  4. 如权利要求3所述的逻辑运算电路，其特征在于，所述差分放大模块还包括：
    吸收单元，与所述存储单元连接，用于吸收所述存储单元在开关切换时产生的多余电荷。
  5. 如权利要求3所述的逻辑运算电路，其特征在于，所述存储单元包括：
    第一晶体管和第二晶体管；
    所述第一晶体管和所述第二晶体管的栅极均连接时钟信号，漏极分别与所述第一逻辑网络单元和所述第二逻辑网络单元的输出端连接，源极分别连接所述第一输入端和所述第二输入端。
  6. 如权利要求4所述的逻辑运算电路，其特征在于，所述吸收单元包括：
    第三晶体管和第四晶体管；
    当所述第三晶体管和所述第四晶体管为N沟道型晶体管时，所述第三晶体管的栅极与所述第四晶体管的源极连接，漏极接电源电压，源极与所述第一输入端连接，所述第四晶体管的栅极与所述第三晶体管的源极连接，漏极接电源电压，源极与所述第二输入端连接；
    当所述第三晶体管和所述第四晶体管为P沟道型晶体管时，所述第三晶体管的栅极与所述第四晶体管的漏极连接，源极接电源电压，漏极与所述第一输入端连接；所述第四晶体管的栅极与所述第三晶体管的漏极连接，源极接电源电压，漏极与所述第二输入端连接。
  7. 如权利要求2所述的逻辑运算电路，其特征在于，所述差分放大模块还包括：
    至少一开关电容单元，与所述电流源单元连接，用于增加输出驱动电压的范围。
  8. 如权利要求1所述的逻辑运算电路，其特征在于，包括两个以上所述差分逻辑运算电路；
    相邻所述差分逻辑运算电路中，其中一所述差分逻辑运算电路的输出端连接至另一所述差分逻辑运算电路的输入端以实现级联。
  9. 如权利要求8所述的逻辑运算电路，其特征在于，还包括：
    时钟缓冲模块，连接于所述差分逻辑运算电路之间，用于控制不同的所述差分逻辑运算电路之间的时序关系。
  10. 一种差分放大电路，其特征在于，包括至少一差分模块，所述差分模块包括存储子模块、差分放大子模块、预充电子模块和电流源子模块：
    存储子模块，包括差分输入端，用于在预充电周期时存储输入的差分信号，并将所述差分信号输入至所述差分放大子模块；
    差分放大子模块，包括差分输出端，与所述存储子模块连接，用于根据所述差分信号输出差分结果；
    预充电子模块，与所述差分放大子模块连接，用于在预充电周期时控制所述差分输出端预充电至电源电压；
    电流源子模块，与所述差分放大子模块连接，用于在求值周期时给所述差分放大单元提供电流通路。
  11. 根据权利要求10所述的差分放大电路，其特征在于，还包括：
    吸收子模块，与所述存储子模块连接，用于吸收所述存储子模块在开关切换时产生的多余电荷。
  12. 根据权利要求10所述的差分放大电路，其特征在于，还包括：第一差分模块和第二差分模块，所述第一差分模块的第一输入端与所述第二差分模块的第二输出端连接，第二输入端与所述第二差分模块的第一输出端连接，第一输出端与所述第二差分模块的第二输入端连接，第二输出端与所述第二差分模块的第一输入端连接。
  13. 一种电子设备，其特征在于，包括权利要求6所述的逻辑运算电路。
  14. 如权利要求13所述的电子设备，其特征在于，还包括权利要求11所述的差分放大电路。
PCT/CN2021/108500 2021-06-08 2021-07-26 逻辑运算电路、差分放大电路及电子设备 WO2022257246A1 (zh)

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CN109327206A (zh) * 2018-09-30 2019-02-12 天津大学 功耗平坦化标准集成电路
CN110113054A (zh) * 2018-02-01 2019-08-09 爱思开海力士有限公司 串行化器以及包括其的半导体系统

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CN101924553A (zh) * 2010-09-15 2010-12-22 复旦大学 一种cmos超宽带二分频器结构
CN206237376U (zh) * 2016-12-14 2017-06-09 浙江大学城市学院 基于浮栅mos管的差分型单边沿t触发器
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