WO2022249554A1

WO2022249554A1 - Solid state imaging element and electronic device

Info

Publication number: WO2022249554A1
Application number: PCT/JP2022/004218
Authority: WO
Inventors: 智行弘
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-05-26
Filing date: 2022-02-03
Publication date: 2022-12-01
Also published as: JP2022181579A

Abstract

The present disclosure relates to a solid state imaging element and an electronic instrument configured such that performance can be further improved. Each pixel includes at least an FD part for detecting a charge generated by photoelectric conversion in a photodiode, a first transistor driven as a source follower when the voltage of the FD part increases, and a second transistor driven as a source follower when the voltage of the FD part decreases. The first transistor is used as an amplification transistor for amplifying charge, and the second transistor has a gate connected to the FD part and a drain connected to the source of the amplification transistor. The present technology can be applied to, for example, a CMOS image sensor having InGaAs photodiode pixels.

Description

Solid-state image sensor and electronic equipment

The present disclosure relates to a solid-state imaging device and electronic equipment, and more particularly to a solid-state imaging device and electronic equipment capable of further improving performance.

Conventionally, in electronic devices with imaging functions such as digital still cameras and digital video cameras, for example, solid-state imaging devices such as CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) image sensors are used. For example, in a solid-state imaging device, the charge photoelectrically converted in the photodiode is transferred to the FD (Floating Diffusion) section, and the pixel signal output via the amplification transistor according to the charge amount is AD (Analog to Digital) converted. be done.

Further, in Patent Document 1, in an imaging device in which a constant current source with a variable current value is connected to a vertical signal line that transmits a pixel signal, a change in the voltage of the vertical signal line is measured to detect the constant current source. Techniques for controlling current values are disclosed.

JP 2008-153909 A

By the way, compared to the conventional image sensor, further improvement in performance is required by improving the settling time until the voltage of the vertical signal line converges and suppressing the increase in the current value of the constant current source. ing.

The present disclosure has been made in view of such circumstances, and is intended to enable further performance improvement.

A solid-state imaging device according to one aspect of the present disclosure includes an FD section for detecting charges generated by photoelectric conversion in a photodiode, a first transistor that performs source follower driving when the voltage of the FD section increases, and the and a second transistor that performs source follower driving when the voltage of the FD section drops, and one of the first transistor and the second transistor is used as an amplification transistor that amplifies the charge. , the other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. with connected pixels.

An electronic device according to one aspect of the present disclosure includes an FD unit for detecting charges generated by photoelectric conversion in a photodiode, a first transistor that performs source follower driving when the voltage of the FD unit increases, and the FD. and at least a second transistor that performs source follower driving when the voltage of the unit drops, and one of the first transistor and the second transistor is used as an amplification transistor that amplifies the charge, The other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. and a solid-state imaging device having pixels formed by

In one aspect of the present disclosure, the pixel includes an FD unit for detecting charge generated by photoelectric conversion in the photodiode, a first transistor that performs source follower driving when the voltage of the FD unit rises, and an FD. At least a second transistor is provided for source follower driving when the voltage across the circuit drops. One of the first transistor and the second transistor is used as an amplification transistor for amplifying charge, and the other of the first transistor and the second transistor has a gate connected to the FD section. In addition, the source of the amplification transistor is connected to the drain, or the drain of the amplification transistor is connected to the source.

1 is a circuit diagram showing a configuration example of a first embodiment of a pixel included in a solid-state imaging device to which the present technology is applied; FIG. It is a circuit diagram showing a configuration example of a conventional pixel. 1 is a diagram showing basic characteristics of a transistor; FIG. FIG. 4 is a diagram showing operation timing; It is a figure which shows an example of a simulation result. It is a figure which shows an example of the planar layout of a pixel. FIG. 7 is a circuit diagram showing a configuration example of a pixel according to a second embodiment; FIG. 10 is a diagram for explaining settling improvement during layer D transfer; FIG. 11 is a circuit diagram showing a configuration example of a pixel according to a third embodiment; It is a figure explaining the settling improvement at the time of high light intensity. It is a block diagram which shows the structural example of an imaging device. FIG. 10 is a diagram showing an example of use using an image sensor;

Specific embodiments to which the present technology is applied will be described in detail below with reference to the drawings.

<First Configuration Example of Pixel>
FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of a pixel included in a solid-state imaging device to which the present technology is applied.

In the pixel 11 shown in FIG. 1, the area surrounded by the broken line is the pixel area. The pixel 11 is connected to a load MOS (Metal Oxide Semiconductor) 22 serving as a constant current source through a vertical signal line 21 , and a parasitic capacitance 23 is generated in the vertical signal line 21 .

Pixel 11 includes InGaAs photodiode 31, SN node 32, capacitor 33, discharge transistor 34, transfer transistor 35, FD node 36, capacitor 37, amplification transistor 38, selection transistor 39, reset transistor 40, and additional transistor 41. Configured. The ejection transistor 34, the transfer transistor 35, the reset transistor 40, and the additional transistor 41 are P-type transistors, and the amplification transistor 38 and the selection transistor 39 are N-type transistors. That is, in the pixel region of the pixel 11, an N-type transistor and a P-type transistor are arranged in combination.

The InGaAs photodiode 31 photoelectrically converts light in the near-infrared wavelength region and outputs the charge generated by the photoelectric conversion to the SN node 32 .

A capacitor 33 is connected to the SN node 32 , and charges generated by the InGaAs photodiode 31 are accumulated in the capacitor 33 .

The discharge transistor 34 discharges the charges accumulated in the capacitor 33 according to the discharge signal OFG supplied to the gate, and resets the potential of the SN node 32 to the reset voltage Vrst1.

The transfer transistor 35 transfers charges from the SN node 32 to the FD node 36 according to the transfer signal TRG supplied to its gate.

A capacitor 37 is connected to the FD node 36 , and charges transferred from the SN node 32 are accumulated in the capacitor 37 .

The amplification transistor 38 connects, for example, a 3.3V power supply voltage and the selection transistor 39, and turns on/off the connection according to the potential of the FD node 36 supplied to the gate.

The selection transistor 39 connects the amplification transistor 38 to the vertical signal line 21 according to the selection signal SEL supplied to the gate.

The reset transistor 40 discharges the charge accumulated in the capacitor 37 according to the reset signal RST supplied to its gate, and resets the potential of the FD node 36 to the reset voltage Vrst1.

The FD node 36 is connected to the gate of the additional transistor 41 . The drain of the additional transistor 41 is connected to the source of the amplification transistor 38 and to the vertical signal line 21 via the selection transistor 39 . The source of additional transistor 41 is connected to ground level. Therefore, the additional transistor 41 turns on/off the connection between the vertical signal line 21 and the ground level via the selection transistor 39 according to the potential of the FD node 36 .

In the pixel 11 configured as described above, the FD node 36 is used to detect the charge generated by photoelectric conversion in the InGaAs photodiode 31, and the amplification transistor 38 amplifies the charge accumulated in the FD node 36. do. The amplification transistor 38 is an N-type transistor, and is driven as a source follower when the voltage of the FD node 36 rises. The additional transistor 41 is a P-type transistor and is source follower driven when the voltage of the FD node 36 drops.

Accordingly, the pixel 11 is configured such that when the amplification transistor 38 is turned on, the additional transistor 41 is turned off, and when the amplification transistor 38 is turned off, the additional transistor 41 is turned on, according to the potential of the FD node 36 .

As a result, the pixel 11 shortens the settling time T until the voltage VSL of the vertical signal line 21 drops and converges to the reset voltage Vrst1 at the timing when the potential of the FD node 36 is reset by the reset transistor 40. can be done. For example, this settling time T can be calculated using the current I0 supplied by the load MOS 22, the capacitance Cvsl of the charge that can be stored in the parasitic capacitance 23, the transconductance gm1 of the amplifying transistor 38, and the transconductance gm2 of the additional transistor 41 as follows: is represented by the following formula (1).

Here, FIG. 2 shows a configuration example of a conventional pixel 11A in which the additional transistor 41 is not provided. In addition, in FIG. 2, the same reference numerals are given to the constituent elements common to the pixel 11 in FIG. 1, and detailed description thereof will be omitted.

The settling time T in the conventional pixel 11A configured as shown in FIG. is represented by the following equation (2).

Therefore, in order to reduce the settling time T in the configuration of the conventional pixel 11A, it is necessary to increase the current I0 supplied by the load MOS 22 or increase the transconductance gm of the amplification transistor 38. However, if the current I0 supplied by the load MOS 22 is increased, the stationary current consumption will increase.

On the other hand, in the pixel 11, since the additional transistor 41 is turned on only during transient operations, there is no steady increase in power consumption. That is, the pixel 11 can improve settling while avoiding an increase in power consumption.

Furthermore, the settling improvement in the pixel 11 will be described with reference to FIGS. 3 and 4. FIG.

Fig. 3 shows the basic characteristics of a transistor.

In a transistor as shown in A of FIG. 3, the current Ids flowing from the drain to the source changes according to the voltage difference Vgs between the gate voltage and the source voltage. For example, an enhancement-type transistor changes the current Ids as shown in FIG. 4B, and a depletion-type transistor changes the current Ids as shown in FIG. 4C.

For example, as the amplification transistor 38 and the additional transistor 41, either an enhancement type or a depletion type may be adopted. Since the depletion type has a smaller threshold voltage VTh for switching on/off of the transistor, it is possible to increase the switching sensitivity of the source follower driving, thereby enhancing the effect of shortening the settling time.

Also, the threshold voltage VTh of the amplification transistor 38 is set to be smaller than the threshold voltage VTh of the additional transistor 41 .

4A shows the operation timing of the pixel 11, and FIG. 3B shows the operation timing of the conventional pixel 11A.

As shown in FIG. 4, in both the pixel 11 and the conventional pixel 11A, the voltage VSL of the vertical signal line 21 starts to drop at the timing when the potential of the FD node 36 is reset by the reset transistor 40. Also, at this time, since the voltage VSL of the vertical signal line 21 is higher than the potential of the FD node 36, the amplification transistor 38 is off and the additional transistor 41 is on.

For example, as shown enlarged in FIG. 4B, in the conventional pixel 11A, the settling time T is increased by the current I0 supplied by the load MOS 22 during the period (AMP_OFF period) in which the amplification transistor 38 is turned off. It is determined. When the voltage VSL of the vertical signal line 21 drops below the potential of the FD node 36 as the voltage VSL of the vertical signal line 21 drops, the amplification transistor 38 is turned on. After that, during the period (AMP_ON period) in which the amplification transistor 38 is on, the settling time T is determined by the mutual conductance gm of the amplification transistor 38 .

That is, in the conventional pixel 11A, when the voltage of the FD node 36 drops, the voltage VSL of the vertical signal line 21 drops so as to follow the voltage of the FD node 36. At this time, at the instant when the voltage of the FD node 36 drops, the gate voltage of the amplification transistor 38 is lower than the source voltage of the amplification transistor 38, so the amplification transistor 38 is turned off. Therefore, the settling time T is determined by the current I0 supplied by the load MOS 22 while the amplification transistor 38 is off.

On the other hand, in the pixel 11, the current I0 supplied by the load MOS 22 and the additional transistor The settling time T is determined by the transconductance gm of 41. When the voltage VSL of the vertical signal line 21 drops below the potential of the FD node 36 as the voltage VSL of the vertical signal line 21 drops, the amplification transistor 38 is turned on, while the additional transistor 41 is turned off. . After that, during the period (AMP_ON period) in which the amplification transistor 38 is on, the settling time T is determined by the mutual conductance gm of the amplification transistor 38 .

In other words, the pixel 11 is provided with the additional transistor 41 that operates in a region where the gate voltage of the amplification transistor 38 is lower than the source voltage and the amplification transistor 38 is turned off. As a result, in the pixel 11, at the moment the voltage of the FD node 36 drops, the amplification transistor 38 is turned off while the additional transistor 41 is turned on. The voltage VSL of the vertical signal line 21 can be lowered by the flowing current. As a result, the pixel 11 can shorten the settling time T until the voltage VSL of the vertical signal line 21 converges when the voltage VSL of the vertical signal line 21 drops.

In this way, in the pixel 11, the drop of the voltage VSL of the vertical signal line 21 is assisted by the additional transistor 41 while the amplification transistor 38 is off, so that the settling time can be shortened more than the conventional pixel 11A. can be planned.

FIG. 5 is a diagram showing an example of settling time simulation results.

As shown in FIG. 5, in the pixel 11 to which this technology is applied, the simulation result shows that the settling time from the timing when the voltage of the FD node 36 drops until the voltage VSL of the vertical signal line 21 converges is 0.858 μs. I was asked. Further, in the conventional pixel 11A, a simulation result was obtained in which the settling time from the timing when the voltage of the FD node 36 dropped until the voltage VSL of the vertical signal line 21 converged was 1.125 μs. Further, a simulation result was obtained in which the current (AMPP current) flowing through the additional transistor 41 was generated as shown in FIG.

Thus, it is expected that the pixel 11 to which this technology is applied can reduce the settling time by about 25% compared to the conventional pixel 11A. By reducing the settling time in this manner, the solid-state imaging device including the pixels 11 can achieve a high frame rate.

It should be noted that FIG. 5 shows the results of a simulation performed with the LW ratio of the additional transistor 41 set to 4. By increasing the LW ratio of the additional transistor 41 (performance improvement), it is possible to further reduce the settling time. have a nature.

6 shows an example of a planar layout of the pixels 11. FIG.

As shown in FIG. 6, the pixel 11 includes, for example, an ejection transistor 34, which is a P-type transistor, a transfer transistor 35, a reset transistor 40, and an additional transistor 41 in-line, an amplification transistor 38, which is an N-type transistor, and a selection transistor 38. A planar layout in which the transistors 39 are arranged in a line can be adopted.

A solid-state imaging device including the pixels 11 configured as described above can achieve a high frame rate by shortening the settling time compared to the conventional art, and can suppress an increase in power consumption at that time. , the performance can be further improved. Also, the smaller the current of the load MOS 22, the more effectively the additional transistor 41 can improve the settling.

In addition, the pixel 11 has a configuration in which N-type transistors and P-type transistors are mixed and combined, as in the conventional pixel 11A, and adding the additional transistor 41 does not increase the number of steps. In addition, since the pixel 11 has a configuration in which the capacitor 37 is intentionally provided at the FD node 36 for capacitive division (controlling the capacitance ratio between the capacitor 33 and the capacitor 37), the additional transistor 41 can be added. The conversion efficiency is not affected by the additional capacitance. In addition, the pixel 11 has only the additional transistor 41 added to the conventional pixel 11A, so that the increase in area and current is small, and versatility to other products can be improved.

<Second Configuration Example of Pixel>
FIG. 7 is a circuit diagram showing a configuration example of a second embodiment of a pixel included in a solid-state imaging device to which the present technology is applied. In addition, in the pixel 11B shown in FIG. 7, the same reference numerals are given to the components common to the pixel 11 in FIG. 1, and detailed description thereof will be omitted.

For example, the pixel 11B has a common configuration with the pixel 11 in FIG. there is While the pixel 11 has the InGaAs photodiode 31, the pixel 11B has a PN junction type photodiode 42. FIG.

The pixel 11B configured in this manner can shorten the settling time during D-layer transfer, for example.

That is, as shown in FIG. 8, in the pixel 11B, during D layer transfer, the transfer transistor 35 is turned on according to the transfer signal TRG, and the charge transferred from the photodiode 42 causes the voltage of the FD node 36 to drop. At this time, the amplification transistor 38 is turned off and the additional transistor 41 is turned on, and the additional transistor 41 assists the voltage drop of the FD node 36, so that the settling time until the voltage of the FD node 36 converges is shortened. be able to.

In this manner, the pixel 11B is configured such that the drain of the additional transistor 41 is connected to the source of the amplification transistor 38, thereby improving the falling speed of the voltage of the FD node 36 during transfer to the D layer. It is possible to improve the settling.

<Third Configuration Example of Pixel>
FIG. 9 is a circuit diagram showing a configuration example of a third embodiment of a pixel included in a solid-state imaging device to which the present technology is applied.

A pixel 11C shown in FIG. 9 is used, for example, in an event-based vision sensor that detects movement of an object as an event. For example, an event-based vision sensor has a laminated structure in which a sensor substrate and a logic substrate are laminated. In the event-based vision sensor, the sensor substrate and the logic substrate are electrically connected via the Cu--Cu connecting portion 51 for each pixel 11C, and pixel signals are AD-converted for each pixel 11C.

As shown in FIG. 9, a photodiode 61 and N-

type transistors

62 and 63 are provided in the pixel region 52 on the sensor substrate side. Further, P-type transistors 64 to 69, N-type transistors 70 to 72,

capacitors

73 and 74, a switch 75, and a load MOS 76 are provided in the pixel AD area 53 on the logic substrate side.

For example, in the pixel 11C, the P-type transistor 69 corresponds to the amplification transistor 38 in FIG. In the pixel 11C, the N-type transistor 70 corresponds to the additional transistor 41 in FIG. 1, and assists the rise of the output of the P-type transistor 69 when the photodiode 61 detects a high amount of light.

That is, the pixel 11C is configured such that the output voltage prout of the pixel region 52 corresponding to the charge generated by the photoelectric conversion in the photodiode 61 is supplied to the gate of the P-type transistor 69 . The pixel 11C is configured such that the output voltage prout is amplified by an amplifier composed of the P-

type transistors

65 and 69, and the output voltage foout is output from the amplifier.

Then, in the pixel 11C, as shown in FIG. 10, when the illuminance increases and the output voltage prout changes from low illuminance to high illuminance, the output voltage foout increases. At this time, the P-type transistor 69 is turned off and the N-type transistor 70 is turned on, so that the settling time until the output voltage foout converges can be shortened. In other words, by configuring the pixel 11C such that the drain of the P-type transistor 69 is connected to the source of the N-type transistor 70, it is possible to improve the rising speed of the output voltage foout when detecting high illuminance. .

Thus, the pixel 11C can improve settling when the photodiode 61 detects a high amount of light.

In the pixel 11C, the threshold voltage VTh of the P-type transistor 69 is set to be smaller than the threshold voltage VTh of the N-type transistor 70.

<Configuration example of electronic device>
An imaging device including the pixels 11 of each configuration example as described above is, for example, an imaging system such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or another device with an imaging function. It can be applied to various electronic devices.

FIG. 11 is a block diagram showing a configuration example of an imaging device mounted on an electronic device.

As shown in FIG. 11, the imaging device 101 includes an optical system 102, an imaging device 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

The optical system 102 is configured with one or more lenses, guides the image light (incident light) from the subject to the imaging element 103, and forms an image on the light receiving surface (sensor section) of the imaging element 103.

As the imaging element 103, an imaging element including the pixels 11 of each configuration example described above is applied. Electrons are accumulated in the imaging element 103 for a certain period of time according to the image formed on the light receiving surface via the optical system 102 . A signal corresponding to the electrons accumulated in the image sensor 103 is supplied to the signal processing circuit 104 .

The signal processing circuit 104 performs various signal processing on the pixel signals output from the image sensor 103 . An image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to the monitor 105 for display or supplied to the memory 106 for storage (recording).

By applying the pixel 11 of each configuration example described above to the imaging apparatus 101 configured in this manner, for example, images can be captured at higher speed and with lower power consumption.

<Usage example of image sensor>
FIG. 12 is a diagram showing a usage example using the image sensor (imaging element) described above.

The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

・Devices that capture images for viewing purposes, such as digital cameras and mobile devices with camera functions. Devices used for transportation, such as in-vehicle sensors that capture images behind, around, and inside the vehicle, surveillance cameras that monitor running vehicles and roads, and ranging sensors that measure the distance between vehicles. Devices used in home appliances such as TVs, refrigerators, air conditioners, etc., to take pictures and operate devices according to gestures ・Endoscopes, devices that perform angiography by receiving infrared light, etc. equipment used for medical and healthcare purposes ・Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for personal authentication ・Skin measuring instruments for photographing the skin and photographing the scalp Equipment used for beauty, such as microscopes used for beauty ・Equipment used for sports, such as action cameras and wearable cameras for use in sports ・Cameras, etc. for monitoring the condition of fields and crops , agricultural equipment

<Configuration example combination>
Note that the present technology can also take the following configuration.
(1)
an FD (Floating Diffusion) section for detecting charges generated by photoelectric conversion in the photodiode;
a first transistor driven as a source follower when the voltage of the FD section rises;
and at least a second transistor that performs source follower driving when the voltage of the FD section drops,
one of the first transistor and the second transistor is used as an amplification transistor for amplifying the charge;
The other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. A solid-state imaging device comprising pixels.
(2)
The solid-state imaging device according to (1) above, wherein the first transistor and the second transistor are arranged in combination in a pixel region in which the elements constituting the pixels are provided.
(3)
the first transistor is used as the amplification transistor,
The solid-state imaging device according to (1) or (2) above, wherein the second transistor assists the voltage drop of the vertical signal line at the timing when the FD section is reset.
(4)
The solid-state imaging device according to (3) above, wherein a threshold voltage for switching on/off of the first transistor is lower than a threshold voltage for switching on/off of the second transistor.
(5)
the second transistor is used as the amplification transistor;
The solid-state imaging device according to (1) or (2) above, wherein the first transistor assists the rise of the output of the amplification transistor when the photodiode detects a high amount of light.
(6)
The solid-state imaging device according to (5), wherein a threshold voltage for switching on/off of the second transistor is lower than a threshold voltage for switching on/off of the first transistor.
(7)
The solid-state imaging device according to any one of (1) to (6) above, wherein either an enhancement type or a depression type is employed as the first transistor and the second transistor.
(8)
an FD (Floating Diffusion) section for detecting charges generated by photoelectric conversion in the photodiode;
a first transistor driven as a source follower when the voltage of the FD section rises;
and at least a second transistor that performs source follower driving when the voltage of the FD section drops,
one of the first transistor and the second transistor is used as an amplification transistor for amplifying the charge;
The other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. An electronic device comprising a solid-state imaging device having pixels.

It should be noted that the present embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the gist of the present disclosure. Moreover, the effects described in this specification are merely examples and are not limited, and other effects may be provided.

11 pixel, 21 vertical signal line, 22 load MOS, 23 parasitic capacitance, 31 InGaAs photodiode, 32 SN node, 33 capacitance, 34 discharge transistor, 35 transfer transistor, 36 FD node, 37 capacitance, 38 amplification transistor, 39 selection transistor , 40 reset transistor, 41 additional transistor, 42 photodiode, 51 Cu-Cu connection, 52 pixel area, 53 pixel AD area, 61 photodiode, 62 and 63 N-type transistors, 64 to 69 P-type transistors, 70 to 72 N-type transistor, 73 and 74 capacitor, 67 switch, 68 load MOS

Claims

an FD (Floating Diffusion) section for detecting charges generated by photoelectric conversion in the photodiode;
a first transistor driven as a source follower when the voltage of the FD section rises;
and at least a second transistor that performs source follower driving when the voltage of the FD section drops,
one of the first transistor and the second transistor is used as an amplification transistor for amplifying the charge;
The other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. A solid-state imaging device comprising pixels.
2. The solid-state imaging device according to claim 1, wherein the first transistor and the second transistor are arranged in combination in a pixel region in which the elements constituting the pixel are provided.
the first transistor is used as the amplification transistor,
2. The solid-state imaging device according to claim 1, wherein the second transistor assists the voltage drop of the vertical signal line at the timing when the FD section is reset.
The solid-state imaging device according to claim 3, wherein a threshold voltage for switching on/off of the first transistor is smaller than a threshold voltage for switching on/off of the second transistor.
the second transistor is used as the amplification transistor;
2. The solid-state imaging device according to claim 1, wherein the first transistor assists the rise of the output of the amplification transistor when the photodiode detects a high amount of light.
The solid-state imaging device according to claim 5, wherein a threshold voltage for switching on/off of the second transistor is smaller than a threshold voltage for switching on/off of the first transistor.
2. The solid-state imaging device according to claim 1, wherein either an enhancement type transistor or a depression type transistor is employed as the first transistor and the second transistor.
an FD (Floating Diffusion) section for detecting charges generated by photoelectric conversion in the photodiode;
a first transistor driven as a source follower when the voltage of the FD section rises;
and at least a second transistor that performs source follower driving when the voltage of the FD section drops,
one of the first transistor and the second transistor is used as an amplification transistor for amplifying the charge;
The other of the first transistor and the second transistor has a gate connected to the FD section and a drain connected to the source of the amplification transistor, or a source connected to the drain of the amplification transistor. An electronic device comprising a solid-state imaging device having pixels.