WO2022247193A1 - 用于数据处理的装置、方法、芯片、计算机设备及介质 - Google Patents

用于数据处理的装置、方法、芯片、计算机设备及介质 Download PDF

Info

Publication number
WO2022247193A1
WO2022247193A1 PCT/CN2021/134278 CN2021134278W WO2022247193A1 WO 2022247193 A1 WO2022247193 A1 WO 2022247193A1 CN 2021134278 W CN2021134278 W CN 2021134278W WO 2022247193 A1 WO2022247193 A1 WO 2022247193A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
sub
stage
processing
circuit
Prior art date
Application number
PCT/CN2021/134278
Other languages
English (en)
French (fr)
Inventor
张国栋
冷祥纶
周琳
Original Assignee
上海阵量智能科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海阵量智能科技有限公司 filed Critical 上海阵量智能科技有限公司
Publication of WO2022247193A1 publication Critical patent/WO2022247193A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of computers, and in particular, to devices, methods, chips, computer equipment and storage media for data processing.
  • dividers are widely used in various chips.
  • Commonly used division algorithms are mostly implemented based on addition and subtraction operations or multiplication operations, which have the problem of slow operation speed, resulting in a decrease in the efficiency of data processing.
  • Embodiments of the present disclosure at least provide a data processor, a data processing method, a chip, a computer device, and a storage medium.
  • an embodiment of the present disclosure provides a data processor, including: a multi-stage operation circuit and a register; each stage of the operation circuit in the multi-stage operation circuit is used to obtain the first Processing data and second processing data, obtaining result data obtained by performing preset processing on the first processing data and the second processing data from the register based on the first processing data and the second processing data ; the register is used to store the result data obtained by performing preset processing on the first processing data and the second processing data; wherein, the first-stage operation circuit in the multi-stage operation circuit corresponds to the The first processing data is determined based on the original data to be processed externally input, and the first processing data corresponding to other operation circuits in the multi-stage operation circuit except the first-stage operation circuit is based on the other-stage operation circuit It is determined by the result data output by the upper stage operation circuit.
  • the result data corresponding to each level is obtained through the result data search operation step by step through the multi-level operation circuit, and the time required is less than the result of the division operation obtained by combining the multiplication operation with the comparison operation, so it has higher processing efficiency.
  • the first processing data includes: a dividend; the second processing data includes: a divisor; the preset processing includes: using the divisor to perform a division operation on the dividend; The result data includes: a quotient and a remainder obtained by performing a division operation on the dividend with the divisor.
  • the first processed data corresponding to the first-stage operation circuit in the multi-stage operation circuit includes: the original data to be processed;
  • the first processed data corresponding to any other stage of operation circuit other than the stage operation circuit includes: the remainder in the result data output by the upper stage operation circuit of the other stage operation circuit.
  • the original data to be processed is used as the first processing data corresponding to the first-stage computing circuit, which can enable the first-stage computing circuit to first divide the original data to be processed, and reduce the amount of first processing data that the second-stage computing circuit needs to process.
  • each stage of the multi-stage computing circuit obtains the first processing data from the register based on the first processing data and the second processing data
  • the result data obtained by performing preset processing with the second processing data is used to: search the register for a target lookup table corresponding to the second processing data based on the second processing data; For the first processing data, look up result data corresponding to the first processing data from the target lookup table.
  • the result data can be determined relatively quickly according to the first processing data and the second processing data through the table lookup operation.
  • each stage of the multi-stage computing circuit obtains the first processing data from the register based on the first processing data and the second processing data
  • it is used to: divide the first processed data into a plurality of sub-data; for each sub-data in the plurality of sub-data, based on the sub-data and the second processing data, obtaining from the register the intermediate result data obtained by using the second processing data to perform preset processing on the sub-data; based on the intermediate result data respectively corresponding to the plurality of sub-data, the obtained The result data corresponding to the first processing data.
  • the number of bits occupied by the multiple pieces of sub-data is the same.
  • the intermediate result data corresponding to any of the sub-data includes the quotient corresponding to the sub-data and the remainder corresponding to the sub-data; each stage of the multi-stage operation circuit, When obtaining the result data corresponding to the first processing data based on the intermediate result data respectively corresponding to the plurality of sub-data, it is used to: for each sub-data in the plurality of sub-data, according to the sub-data in the first 1.
  • Process the position in the data perform a data shift operation on the quotient corresponding to the sub-data, and add the data shift operation result of the quotient corresponding to the sub-data to the data shift operation result of the quotient corresponding to other sub-data , to obtain the quotient corresponding to the first processed data; and for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, perform data shift on the remainder corresponding to the sub-data bit operation, and add the data shift operation result of the remainder corresponding to the sub-data to the data shift operation results of the remainder corresponding to other sub-data to obtain the remainder corresponding to the first processed data.
  • each level of operation circuit can process multiple sub-data in parallel, thereby improving the efficiency of data processing.
  • it also includes: an integration circuit; the integration circuit is used to add the quotients in the result data respectively corresponding to the multi-level operation circuits to obtain the target corresponding to the original data to be processed quotient in the result data, and output the quotient in the target result data.
  • the last-stage arithmetic circuit in the multi-stage arithmetic circuit is further configured to use the remainder in the result data corresponding to the last-stage arithmetic circuit as the corresponding value of the original data to be processed.
  • the remainder output in the target result data for .
  • each stage of the multi-stage arithmetic circuit for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, the Carry out a data shift operation on the quotient corresponding to the sub-data, and add the data shift operation result of the quotient corresponding to the sub-data to the data shift operation results of the quotient corresponding to other sub-data to obtain the first processed data corresponding to
  • the quotient it is used to: for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, perform a data shift operation on the quotient corresponding to the sub-data, and transfer the The data shift operation result of the quotient corresponding to the sub-data, the data shift operation result of the quotient corresponding to other sub-data, and the quotient in the result data of the previous stage operation circuit of the operation circuit of this stage are added to obtain the operation circuit of this stage
  • the last-stage arithmetic circuit in the multi-stage arithmetic circuit is further configured to use the result data corresponding to the last-stage arithmetic circuit as the target processing corresponding to the original data to be processed The result output.
  • each stage of the multi-stage computing circuit includes: a data segmentation circuit, configured to, after receiving the first processed data corresponding to the stage of computing circuit, The first processed data is divided into a plurality of sub-data; the data search circuit is configured to, after receiving the plurality of sub-data from the data segmentation circuit, based on the obtained second processed data and the plurality of sub-data performing a table lookup operation on the data to obtain the intermediate result data respectively corresponding to the multiple sub-data; The intermediate result data corresponding to the plurality of sub-data respectively is used to obtain the result data corresponding to the first processing data.
  • the embodiment of the present disclosure also provides a data processing method, which is applied to a data processor;
  • the data processor includes a multi-stage operation circuit and a register;
  • the data processing method includes: the multi-stage operation circuit Each stage of operation circuit obtains the first processing data and the second processing data corresponding to the stage of operation circuit, and obtains the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the first processing data corresponding to the first-level operation circuit of the circuit is determined based on the original data to be processed externally input, and the second-level operation circuits corresponding to the other-level operation circuits in the multi-level operation circuit except the first-level operation circuit
  • a processing data is determined based on result data output by an upper stage operation circuit of the other stage operation circuit.
  • the first processing data includes: a dividend; the second processing data includes: a divisor; the preset processing includes: using the divisor to perform a division operation on the dividend; The result data includes: a quotient and a remainder obtained by performing a division operation on the dividend with the divisor.
  • the first processed data corresponding to the first-stage operation circuit in the multi-stage operation circuit includes: the original data to be processed;
  • the first processed data corresponding to any other stage of operation circuit other than the stage operation circuit includes: the remainder in the result data output by the upper stage operation circuit of the other stage operation circuit.
  • each stage of the multi-stage computing circuit obtains a combination of the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the result data obtained by performing preset processing on the second processing data includes: each stage of the operation circuit in the multi-stage operation circuit searches the register corresponding to the second processing data based on the second processing data A target lookup table; based on the first processing data, look up result data corresponding to the first processing data from the target lookup table.
  • each stage of the multi-stage computing circuit obtains a combination of the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the result data obtained by performing preset processing on the second processed data including: dividing the first processed data into a plurality of sub-data; for each sub-data in the plurality of sub-data, based on the sub-data and the first second processing data, obtaining from the register the intermediate result data obtained by using the second processing data to perform preset processing on the sub-data; and obtaining the first processing based on the intermediate result data respectively corresponding to the plurality of sub-data
  • the result data corresponding to the data including: dividing the first processed data into a plurality of sub-data; for each sub-data in the plurality of sub-data, based on the sub-data and the first second processing data, obtaining from the register the intermediate result data obtained by using the second processing data to perform preset processing on the sub-data; and obtaining the first processing based on the intermediate result data respectively corresponding to the
  • the number of bits occupied by the multiple pieces of sub-data is the same.
  • the intermediate result data corresponding to any sub-data includes the quotient corresponding to the sub-data and the remainder corresponding to the sub-data; each stage of the multi-stage operation circuit is based on the The intermediate result data corresponding to the plurality of sub-data respectively, and obtaining the result data corresponding to the first processing data includes: each stage of the operation circuit in the multi-stage operation circuit, for each sub-data in the plurality of sub-data, according to the sub-data At the position in the first processed data, perform a data shift operation on the quotient corresponding to the sub-data, and shift the operation result of the data of the quotient corresponding to the sub-data, and shift the data of the quotient corresponding to other sub-data Adding up the operation results to obtain the quotient corresponding to the first processed data; and for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, perform the remainder corresponding to the sub-data A data shift operation, and adding the data shift operation
  • the integrated circuit adds up the quotients in the result data corresponding to the multi-level operation circuits respectively, to obtain the quotient in the target result data corresponding to the original data to be processed, and converts the The quotient output in the target result data.
  • the last stage of the multi-stage operation circuit uses the remainder in the result data corresponding to the last stage of operation circuit as the remainder corresponding to the original data to be processed Remainder output in target result data.
  • each stage of the multi-stage arithmetic circuit for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, for the sub-data Perform a data shift operation on the corresponding quotient, and add the data shift operation result of the quotient corresponding to the sub-data to the data shift operation results of the quotient corresponding to other sub-data to obtain the quotient corresponding to the first processed data , including: for each sub-data in the plurality of sub-data, each stage of the multi-stage operation circuit performs a data shift operation on the quotient corresponding to the sub-data according to the position of the sub-data in the first processed data , and add the data shift operation result of the quotient corresponding to this sub-data, the data shift operation result of the quotient corresponding to other sub-data, and the quotient in the result data of the previous stage of the operation circuit of this stage of operation circuit, to obtain The quotient in the result data corresponding to the
  • the last stage of the multi-stage operation circuit uses the result data corresponding to the last stage of operation circuit as the target processing result corresponding to the original data to be processed output.
  • each stage of the multi-stage arithmetic circuit includes: a data segmentation circuit, a data search circuit connected to the data segmentation circuit, and a data search circuit connected to the data search circuit.
  • the splicing circuit; the data processing method further includes: after the data segmentation circuit receives the first processing data corresponding to the operation circuit of the stage, the corresponding first processing data is segmented into a plurality of sub-data; After the data lookup circuit receives the plurality of sub-data from the data segmentation circuit, it performs a table lookup operation based on the obtained second processed data and the plurality of sub-data, and obtains that the plurality of sub-data respectively correspond to intermediate result data; after the splicing circuit receives the intermediate result data respectively corresponding to the plurality of sub-data sent by the data search circuit, based on the intermediate result data respectively corresponding to the plurality of sub-data, obtains the first processing The result data corresponding to the data.
  • an optional implementation manner of the present disclosure further provides a chip, including the data processor according to any one of the first aspect.
  • an optional embodiment of the present disclosure further provides a computer device, including: an instruction memory and the data processor according to any one of the first aspect; or the computer device includes the chip according to the third aspect .
  • an optional embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the above-mentioned second aspect, or any of the second aspects may be executed. Steps in one possible implementation.
  • FIG. 1 shows a schematic diagram of a data processor provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of a specific internal circuit structure of a data processor provided by an embodiment of the present disclosure
  • FIG. 3 shows a flow chart of specific steps for performing a table lookup operation from a register based on the first processing data and the second processing data provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a segmentation circuit provided by an embodiment of the present disclosure when the first processing data is segmented
  • FIG. 5(a) and FIG. 5(b) show schematic diagrams of multiple look-up tables stored in registers provided by embodiments of the present disclosure
  • FIG. 6 shows a schematic diagram of a circuit structure for determining the remainder in the corresponding result data of the first-level operation circuit provided by an embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of another integrated circuit provided by an embodiment of the present disclosure.
  • Fig. 9 shows a flowchart of a data processing method provided by an embodiment of the present disclosure.
  • a data processor such as a divider
  • it is usually converted into a multiplication operation, so as to obtain the target result data of the division operation relatively simply.
  • the product C of the predicted quotient A and the divisor N can be determined, and then use a comparator to determine whether the difference between the dividend M and the product C is less than The divisor N, so as to determine whether the predicted quotient A is the quotient in the target result data of the division operation corresponding to the dividend M and the divisor N.
  • the predicted quotient A can be set to 1 first, and then increased by 1 until the comparator determines that the difference between the dividend M and the product C is less than the divisor N, then the predicted quotient A here is used as the target The quotient in the result data, and the difference between the dividend M determined at this time and the product C is used as the remainder in the target result data.
  • This method needs to use an iterative method to determine the target result data. When the value difference between the dividend and the divisor is large, it takes a lot of time, resulting in low efficiency when processing the data.
  • the present disclosure provides a data processor, including multi-level arithmetic circuits and registers, each level of arithmetic circuits can use its corresponding first processing data and second processing data to perform result data search operations, that is The corresponding result data is determined from the result data stored in the register.
  • the time required to obtain the result data corresponding to each level by using the result data search operation level by level through the multi-level operation circuit is less than the time required to obtain the result of the division operation through the multiplication operation combined with the comparison operation, so it has more advantages. High processing efficiency.
  • the data processor can be deployed on a computer device with a certain computing capability, and the computer device includes, for example: a terminal device or a server or Other processing devices, terminal devices can be user equipment (User Equipment, UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (Personal Digital Assistant, PDA), handheld devices, computing devices, vehicle-mounted devices , wearable devices, etc.
  • UE User Equipment
  • PDA Personal Digital Assistant
  • FIG. 1 it is a schematic diagram of a data processor provided by an embodiment of the present disclosure.
  • the data processor includes a multi-stage operation circuit 10 and a register 20 .
  • Each stage of the operation circuit 10 in the multi-stage operation circuit 10 is used to obtain the first processing data and the second processing data corresponding to the operation circuit 10 of this stage, based on the first processing data and the second processing data Obtain the result data obtained by performing preset processing on the first processing data and the second processing data from the register 20; the register 20 is used to store the first processing data and the second processing data Preset processing of the processed data corresponds to the obtained result data; wherein, the first processed data corresponding to the first-stage computing circuit in the multi-stage computing circuit is determined based on the original data to be processed externally input, and the multi-stage computing circuit The first processing data corresponding to the operation circuit of other stages except the operation circuit of the first stage is determined based on the result data output by the operation circuit 10 of the upper stage of the operation circuit of other stages.
  • FIG. 2 a schematic diagram of a specific internal circuit structure of a data processor is shown.
  • the first processed data includes a dividend, denoted as M;
  • the second processed data includes a divisor, denoted as N.
  • the data used by the computer is binary data when processing the first processing data and the second processing data, when describing the data processor provided by the embodiment of the present disclosure, the subscript "(2)" is used to identify the binary data ;Decimal data is identified with the subscript "(10)".
  • a specific step of performing a table lookup operation from a register based on the first processed data and the second processed data provided by an embodiment of the present disclosure includes the following steps S301 to S303.
  • the number of bits occupied by multiple pieces of sub-data is the same.
  • each stage of arithmetic circuits 10 in the multi-stage arithmetic circuits 10 corresponds to different first processed data and second processed data.
  • the first processed data corresponding to the first-stage operation circuit 10 in the multi-stage operation circuit 10 includes: original data to be processed.
  • the original data to be processed may include, for example, a dividend M0 that needs to be divided.
  • the dividend M0 is represented by a binary number, it may occupy multiple bits. For example, when the dividend M0 is 16 (10) , the corresponding binary number is 1111 (2) , occupying 4 bits; when the dividend M0 is 256 (10) , the corresponding binary number is 11111111 (2) , occupying 8 bits.
  • the first processing data when the value of the dividend M0 expressed in decimal data is larger, the number of bits occupied by the corresponding binary number will increase. Therefore, when using the first-stage arithmetic circuit 10 to perform data processing on the first processing data, the first processing data will be segmented first, and the table look-up operation will be performed using the segmented data occupying a small number of bits. Determine result data corresponding to the first processing data.
  • the segmenting circuit in the first stage operation circuit 10 may be used to perform segmenting processing on the first processed data.
  • a segmentation circuit 11 is included in the first stage operation circuit 10 .
  • the number of bits occupied by the sub-data obtained by the segmentation circuit after the segmentation of the first processed data can be determined according to the determined number of stages of the multi-stage operation circuit 10 . For example, if it is determined that the first processed data is represented by binary data, occupying 32 bits, and the number of stages corresponding to the multi-stage operation circuit 10 is 3, it can be determined that the corresponding first processed data in the first-stage operation circuit 10 needs to be cut. Divided into multiple sub-data occupying 8 bits.
  • the number of stages of the arithmetic circuit should be determined in advance according to the highest bit number actually occupied by the data to be processed.
  • the multi-stage arithmetic circuit 10 with a fixed number of stages will be used for processing.
  • the processed data can be filled with zeros, so that the data after the zero-padding operation reaches the highest number of bits, so as to realize the use of multi-level operation circuits 10 for processing.
  • the number of stages of the multi-stage arithmetic circuit 10 it may be determined according to the predetermined number of bits respectively corresponding to the first processing data and the second processing data, for example.
  • the number of bits of the first processed data is at most 4 bits
  • the number of bits of the second processed data is at least 2 bits
  • use the second processing data to perform data processing on the segmented sub-data, and the sub-data obtained by shifting the upper two digits to the left can also carry out the next step with the second processing data data processing. That is, two stages of computing circuits 10 need to be provided in total to process the first processing data.
  • FIG. 4 it is a schematic diagram of a segmentation circuit provided by an embodiment of the present disclosure when the first processing data is segmented.
  • the segmentation The circuit 11 divides the first processed data into 4 sub-data.
  • the data of each bit in the first processed data can be transmitted to corresponding bits of the corresponding 4 sub-data by using the segmentation circuit 11, so as to realize the data processing process of dividing the first processed data into 4 sub-data.
  • the first processed data 41 includes binary data 10101011101010101010100110101000 (2) occupying 32 bits.
  • each data input channel completes the transmission of the corresponding position data, such as the first data channel, and transmits the data "0" corresponding to the first bit in the first processed data 41 to the segmentation circuit middle.
  • Utilize the cutting circuit 11 shown in Fig. 4 to cut out 4 sub-data 43 comprise 10101011 (2) , 10101010 (2) , 10101001 (2) , and 10101000 (2) , utilize decimal notation, then be respectively 171 (10) , 170 (10) , 169 (10) , and 168 (10) .
  • the structure of the segmentation circuit 11 inside a data processor is predetermined.
  • the segmentation circuit 11 in FIG. 4 above can divide the first processed data into 4 sub-data occupying 8 bits each. Therefore, for the case where the number of bits corresponding to the first processed data is less than the maximum number of bits that can be processed by the slicing circuit 11, for example, in FIG.
  • the segmentation circuit can segment the 30-bit data; but for the sub-data corresponding to the highest 8 bits of the first processed data, since there is no data in the highest 2 bits, it can be complemented, for example For example, 0 is added to the two bits, so that the number of bits occupied by the plurality of sub-data obtained by dividing by the dividing circuit 11 is the same under the condition that the value of the sub-data is guaranteed not to change.
  • each circuit in the data processor is pre-designed to ensure that the data can be processed correctly when the first processing data is the largest, that is, each circuit is designed according to the maximum data processing capacity, so when the first processing data
  • the padding operation may not be performed under the condition of ensuring safety and accuracy.
  • the details may be determined according to the actual situation, and details are not repeated here.
  • the segmentation circuit 11 determines a plurality of sub-data
  • the plurality of sub-data can be respectively transmitted to the corresponding data search circuit, so that the data search circuit in the first stage operation circuit 10 performs next data processing on the plurality of sub-data.
  • its corresponding first processing data includes: the result data output by the upper stage computing circuit 10 of the other stage computing circuits;
  • the manner in which the stage operation circuit 10 divides the corresponding first processed data into a plurality of sub-data is similar to the manner in which the first-stage operation circuit 10 divides the corresponding first processed data into a plurality of sub-data, and will not be repeated here.
  • S302 For each sub-data in the plurality of sub-data, based on the sub-data and the second processing data, acquire intermediate result data obtained by performing preset processing on the sub-data by using the second processing data from the register.
  • a table look-up operation when acquiring the intermediate result data obtained by performing preset processing on the sub-data by using the second processing data from the register, for example, a table look-up operation may be used.
  • the data lookup circuit in the first stage operation circuit 10 may be used to search multiple lookup tables in the register 20 .
  • a data search circuit 12 is also included in the first stage operation circuit 10 .
  • the data search circuit 12 in the first-stage arithmetic circuit 10 can perform a table lookup operation according to the obtained second processed data and sub-data, and obtain the sub-data by using the second processed data. Intermediate result data for preset processing.
  • the multi-stage operation circuit 10 may include one or more data search circuits 12 .
  • the data lookup circuit 12 may, for example, first determine a lookup table corresponding to the second processed data, and then perform a table lookup operation on the determined lookup table according to the sub-data.
  • data lookup circuitry 12 may access multiple lookup tables.
  • the multiple data lookup circuits 12 may respectively correspond to different lookup tables, for example.
  • the data lookup circuit 12 corresponding to the second processing data can be determined according to the second processing data, and then the data lookup circuit 12 accesses its corresponding lookup table according to the sub-data to perform a table lookup operation. That is, the data lookup circuit 12 accesses the lookup table corresponding thereto.
  • FIG. 5( a ) and FIG. 5( b ) are schematic diagrams of multiple look-up tables stored in registers provided by an embodiment of the present disclosure.
  • Lookup tables respectively corresponding to a plurality of possible second processing data are stored in the register 20 .
  • the second processing data may include, for example, 2 (10) , 3 (10) , 5 (10) , and 9 (10)
  • the corresponding lookup table 51 in the register 20 may be included in FIG. 5(a)
  • Four look-up tables T1, T2, T3, and T4 are shown.
  • the data contained therein includes the intermediate result data corresponding to the sub-data.
  • the lookup table 51 includes the quotient and remainder corresponding to the sub-data
  • the data included in the lookup table T1 is shown in FIG. 5( b ).
  • the data in the first column is the possible first processing data (which is divided into multiple sub-data)
  • the data in the second column and the data in the third column are the corresponding first processing data (specifically including from The quotient and the remainder in the intermediate result data of a plurality of sub-data segmented from the first processed data.
  • the data search circuit can store a plurality of look-up tables T1, T2, In T3 and T4, the lookup table T1 corresponding to the second processed data 2 (10) is determined as the target lookup table. Then, in the target lookup table T1, the data lookup circuit determines the intermediate result data corresponding to the subdata 10101011 (2) , that is, 1010101 (2) and 00000001 (2) that can be found in the target lookup table T1. Similarly, the data lookup circuit can also determine the intermediate result data respectively corresponding to the remaining sub-data 10101010 (2) , 10101001 (2) and 10101000 (2) in the target lookup table T1. In this way, the data search circuit can obtain the quotient and the remainder in the intermediate result data determined in the first stage operation circuit 10 .
  • the data search circuit 12 in the first stage operation circuit 10 can transmit the intermediate result data to the splicing circuit, so that the first stage operation circuit 10 The splicing circuit performs next data processing on the intermediate result data.
  • S303 Obtain result data corresponding to the first processed data based on the intermediate result data respectively corresponding to the plurality of sub-data.
  • a splicing circuit may be used to complete the splicing operation.
  • a splicing circuit 13 is also included in the first stage operation circuit 10 .
  • the splicing circuit 13 can obtain the intermediate result data respectively based on the multiple data search circuits.
  • the result data corresponding to the first processing data.
  • the first-level arithmetic circuit 10 its corresponding quotient can be directly reserved and used to calculate the target result data, while its corresponding remainder needs to be restored to the original data to be processed because the corresponding sub-data may be high-order data. Then calculate the real value in .
  • the first-level arithmetic circuit 10 obtains the result data corresponding to the first processing data based on the intermediate result data respectively corresponding to a plurality of sub-data
  • the following method can be adopted: for each sub-data in the plurality of sub-data, According to the position of the sub-data in the first processed data, perform a data shift operation on the quotient corresponding to the sub-data, and shift the data shift operation result of the quotient corresponding to the sub-data with the data of the quotient corresponding to other sub-data.
  • the intermediate result data corresponding to the first sub-data 10101011 (2) includes Represent the data 1010101 (2) of the quotient and the data 00000001 (2) representing the remainder; determine that the intermediate result data corresponding to the second sub-data 101010 (2) includes representing the data 1010101 (2) of the quotient and the data 00000000 (2) representing the remainder ; Determine that the corresponding intermediate result data of the third sub-data 10101001 (2) includes the data 1010100 (2) representing the quotient and the data 00000001 (2) representing the remainder; determine that the corresponding intermediate result data of the fourth sub-data 10101000 (2) includes the expression The data 1010100 (2) for the quotient and the data 00000000 (2) for the remainder.
  • the first sub-data 10101011 (2) corresponds to the 31st to 24th bits of the first processing data in the first-stage arithmetic circuit 10, its actual value should be the value of 10101011 (2) shifted left by 24 bits.
  • the quotient corresponding to the first sub-data is 1010101 (2) the actual value should be 1010101 (2) the value shifted to the left by 16 bits; the remainder corresponding to the first sub-data is 00000001 (2) the actual value should be It is 00000001 (2) the value shifted to the left by 24 bits.
  • the above-mentioned method for determining the intermediate result data corresponding to the first sub-data can be used to determine the intermediate result data respectively corresponding to the second sub-data to the fourth sub-data.
  • the first sub-data to the fourth sub-data can be respectively corresponding to The results of the data shift operations are added together to obtain the corresponding result data in the first-stage arithmetic circuit 10 .
  • FIG. 6 it is a schematic diagram of a circuit structure for determining the remainder in the result data corresponding to the first-level operation circuit provided by an embodiment of the present disclosure.
  • the remainders 61 to 64 corresponding to the four sub-data included in Figure 6 correspond to the 0th to 7th, 8th to 15th, 16th to 23rd, and The 24th to the 31st bits, so when using the splicing circuit to complete the splicing operation, for example, the sub-data 61-64 can be determined according to the number of bits occupied by the corresponding original data to be processed to determine the intermediate result data corresponding to the sub-data Each bit of data transfer in the data path.
  • the circuit structure shown by the dotted line box 65 the remainder in the intermediate result data corresponding to the multiple sub-data can be shifted to obtain the remainder 66 in the result data corresponding to the first-stage arithmetic circuit 10 .
  • stages of operation circuits 10 except the first stage operation circuit 10 use similar processing steps as the first stage operation circuit 10 when performing data processing on the first processing data and the second processing data.
  • the first processed data corresponding to other operation circuits 10 other than the first operation circuit 10 includes result data output by the upper operation circuit 10 of the other operation circuit 10 . In this way, a large externally input original data to be processed can be processed in a multi-level operation manner to reduce the data level when directly operating on it, thereby reducing the time spent on data processing.
  • any one of the following methods (A) and (B) can be adopted but not limited to.
  • the last-stage arithmetic circuit 10 in the multi-stage arithmetic circuit 10 outputs the remainder in the result data corresponding to the last-stage arithmetic circuit 10 as the remainder in the target result data corresponding to the original data to be processed.
  • an integrated circuit is also included, and the integrated circuit can add the quotients in the result data output by each stage, that is, in each stage of the multi-stage arithmetic circuit 10, 10, there is a data path that transmits the quotient in the resulting data to the integrated circuit.
  • the integrated circuit for example, at least one result data register may be included.
  • the multiple result data registers 20 may respectively correspond to one stage of operation circuits 10 and store the quotients in the result data output by each stage of operation circuits 10 .
  • the integrated circuit can store the quotient of the result data obtained by each stage of operation circuit 10 respectively stored in a plurality of result data registers. Add up to get the quotient in the target result data.
  • an integrated circuit 14 is also included in the data processor.
  • FIG. 7 is a schematic diagram of an integrated circuit 14 provided by an embodiment of the present disclosure.
  • the result data registers 71, 72, and 73 respectively corresponding to the three-stage arithmetic circuit 10 are included, and the splicing circuit 13 of the first-stage arithmetic circuit 10 and the splicing circuit 10 of the second-stage arithmetic circuit 10 are respectively included.
  • the circuit 13 is connected with the splicing circuit 13 of the third stage operation circuit 10 to store the quotient in the result data output by each stage operation circuit 10 .
  • the result data register only stores the quotient in the result data output in the previous stage operation circuit 10 of the current stage operation circuit 10, and then utilizes the integration circuit to store the result data in the result data register
  • the stored quotient output from the previous stage operation circuit 10 is added to the quotient in the result data output from the current stage operation circuit 10 . In this way, after the last stage operation circuit 10 completes the processing of the corresponding first processing data and the second processing data, the quotient of the target result data corresponding to the original data to be processed can be obtained in the result data register.
  • FIG. 8 it is a schematic diagram of another integrated circuit provided by an embodiment of the present disclosure.
  • a result data register 81 is included.
  • the first stage operation circuit 10 determines the quotient in its corresponding result data
  • the quotient is stored in the result data register 81
  • the next stage operation circuit 10 calculates the corresponding result data
  • this next stage operation The quotient in the result data corresponding to the circuit and the quotient stored in the result data register 81 are integrated into a new quotient and stored in the result data register 81 again.
  • the remainder in the result data corresponding to the last stage of operation circuit 10 may also be output as the remainder in the target result data corresponding to the original data to be processed.
  • each level of computing circuits can output result data corresponding to the computing circuits, that is, each level of computing circuits can output corresponding quotients.
  • the corresponding result data may include, for example, quotients corresponding to the four sub-data obtained after performing division operations on the four sub-data. Based on the bits occupied by the sub-data corresponding to the four quotients, data shift operations can be performed on the obtained four quotients to obtain the quotient in the result data output by the first-stage operation circuit 10 , which can be expressed as q1, for example.
  • the quotient q1 determined by the first-stage arithmetic circuit 10 is output to the second-stage arithmetic circuit 10 .
  • the second stage operation circuit performs division operation on the corresponding sub-data (for example, may include 2 sub-data), for example, the quotient corresponding to the 2 sub-data can be obtained.
  • data shift operations can be performed on the obtained two quotients to obtain the quotient obtained by the second-stage arithmetic circuit 10 after processing the corresponding sub-data, Denoted as q2'.
  • the second-stage arithmetic circuit 10 is obtained by further dividing the remainder obtained by the first-stage arithmetic circuit 10, in the second-stage arithmetic circuit 10, for example, the first-stage arithmetic circuit 10 can be transferred to the second-stage arithmetic circuit 10.
  • the quotient q1 input by the second-stage arithmetic circuit is added to the quotient q2' determined by the second-stage arithmetic circuit to obtain the quotient q2 in the result data corresponding to the second-stage arithmetic circuit.
  • the quotient q2 in the result data can be output.
  • the third-stage computing circuit is, for example, the last stage computing circuit in the multi-stage computing circuit, and the corresponding sub-data is, for example, Including the remainder obtained after the division operation performed by the second-stage operation circuit.
  • the third stage operation circuit 10 divides the remainder, the quotient q3' obtained after processing and the upper stage, that is, the quotient q2 output by the second stage operation circuit 10 are added, and the obtained result q3 is used as The quotient in the result data corresponding to the third stage operation circuit 10 .
  • the third-level operation circuit 10 is the last-level operation circuit, the quotient q3 in the result data corresponding to this level operation circuit can be used as the quotient in the target result data corresponding to the original data to be processed.
  • the process of determining the remainder in the target result data corresponding to the original data to be processed is similar to the above-mentioned process of determining the quotient in the target result data corresponding to the original data to be processed, and will not be repeated here.
  • the corresponding result data in the last stage of operation circuit 10 can be output as the target processing result corresponding to the original data to be processed.
  • the embodiment of the present disclosure provides a specific example of using a data processor to perform data processing on the original data m to be processed.
  • the number of levels corresponding to the data processor for example, it can be based on the maximum number of bits occupied by the original data to be processed, the number of bits occupied by the second processed data, and the number of sub-data obtained after the data is divided by the slicing circuit.
  • the number of bits is determined; or, a larger number of levels can also be set to meet the requirements of the original data to be processed occupying different bits when performing data processing.
  • the corresponding divisor is n, including 9 (10) for example.
  • the original data A to be processed includes 11011011110110111101101111011011 (2) , which corresponds to 3688618971 (10) in decimal notation.
  • the original data m to be processed is the first processed data.
  • Segment the first processed data by using the slicing circuit to obtain four sub-data, namely 11011011 (2) , 11011011 (2) , 11011011 (2) and 11011011 (2) , corresponding to the decimal representation of 219 (10) .
  • the data search circuit in the first stage operation circuit 10 can determine the corresponding second processing data in a plurality of corresponding look-up tables according to the second processing data, that is, the divisor 9 (10).
  • Look up table T4 The data search circuit can determine the intermediate result data corresponding to the plurality of sub-data in the look-up table T4, including 11000 (2) and 011 (2) , respectively representing the quotient and the remainder in the intermediate result data.
  • the splicing circuit can be used to determine that the quotient in the corresponding result data is 00011000000110000001100000011000 (2) , and determine that the remainder in the corresponding result data is 00000011000000110000001100000011 (2) ; and, the result data
  • the quotient 00011000000110000001100000011000 (2) is stored in the storage unit corresponding to the first stage operation circuit 10 in the integrated circuit.
  • the remainder 00000011000000110000001100000011 (2) in the result data determined in the first-stage computing circuit 10 is used as the first processing data corresponding to the second-stage computing circuit 10 .
  • the data corresponding to the eight bits can be concatenated to determine two sub-data, and each sub-data includes 0000001100000011 (2) .
  • the intermediate result data corresponding to the second-stage arithmetic circuit 10 can be determined, including 01010101 (2) (that is, 85 (10) ) and 110 (2) ( That is, 6 (10) ), respectively represent the quotient and remainder in the intermediate result data.
  • the quotient in the corresponding result data can be determined to be 010101010000000001010101 (2) by using the splicing circuit, and the remainder in the corresponding result data is determined to be 000000000000000110 (2) ; and, the result
  • the quotient 010101010000000001010101 in the data (2) is stored in the storage unit corresponding to the second stage operation circuit 10 in the integrated circuit.
  • the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process.
  • the specific execution order of each step should be based on its function and possible
  • the inner logic is OK.
  • the embodiment of the present disclosure also provides a data processing method corresponding to the data processor. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned data processor in the embodiment of the present disclosure, the implementation of the method Reference can be made to the implementation of the device, and repeated descriptions will not be repeated.
  • FIG. 9 it is a flowchart of a data processing method provided by an embodiment of the present disclosure.
  • the data processing method is applied to a data processor; the data processor includes a multi-stage arithmetic circuit and registers; the data processing Methods include:
  • Each stage of the multi-stage computing circuit obtains the first processing data and the second processing data corresponding to the stage computing circuit, and obtains the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the register stores the result data obtained by performing preset processing on the first processing data and the second processing data; wherein, the first processing data corresponding to the first-stage operation circuit in the multi-stage operation circuit is based on the original input from the outside The data to be processed is determined, and the first processed data corresponding to the other-level operation circuits in the multi-level operation circuit except the first-level operation circuit is based on the result data output by the upper-level operation circuit of the other-level operation circuit definite.
  • the first processing data includes: a dividend; the second processing data includes: a divisor; the preset processing includes: using the divisor to perform a division operation on the dividend; The result data includes: a quotient and a remainder obtained by performing a division operation on the dividend with the divisor.
  • the first processed data corresponding to the first-stage operation circuit in the multi-stage operation circuit includes: the original data to be processed;
  • the first processed data corresponding to any other stage of operation circuit other than the stage operation circuit includes: the remainder in the result data output by the upper stage operation circuit of the other stage operation circuit.
  • each stage of the multi-stage computing circuit obtains a combination of the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the result data obtained by performing preset processing on the second processing data includes: each stage of the operation circuit in the multi-stage operation circuit searches the register corresponding to the second processing data based on the second processing data A target lookup table; based on the first processing data, look up the result data corresponding to the first processing data from the target lookup table.
  • each stage of the multi-stage computing circuit obtains a combination of the first processing data and the second processing data from the register based on the first processing data and the second processing data.
  • the result data obtained by performing preset processing on the second processed data including: dividing the first processed data into a plurality of sub-data; for each sub-data in the plurality of sub-data, based on the sub-data and the first second processing data, obtaining from the register the intermediate result data obtained by using the second processing data to perform preset processing on the sub-data; and obtaining the first processing based on the intermediate result data respectively corresponding to the plurality of sub-data
  • the result data corresponding to the data including: dividing the first processed data into a plurality of sub-data; for each sub-data in the plurality of sub-data, based on the sub-data and the first second processing data, obtaining from the register the intermediate result data obtained by using the second processing data to perform preset processing on the sub-data; and obtaining the first processing based on the intermediate result data respectively corresponding to the
  • the number of bits occupied by the multiple pieces of sub-data is the same.
  • the intermediate result data corresponding to any sub-data includes the quotient corresponding to the sub-data and the remainder corresponding to the sub-data; each stage of the multi-stage operation circuit is based on the The intermediate result data corresponding to the plurality of sub-data respectively, and obtaining the result data corresponding to the first processing data includes: each stage of the operation circuit in the multi-stage operation circuit, for each sub-data in the plurality of sub-data, according to the sub-data At the position in the first processed data, perform a data shift operation on the quotient corresponding to the sub-data, and shift the operation result of the data of the quotient corresponding to the sub-data, and shift the data of the quotient corresponding to other sub-data Adding up the operation results to obtain the quotient corresponding to the first processed data; and for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, perform the remainder corresponding to the sub-data A data shift operation, and adding the data shift operation
  • the integrated circuit adds up the quotients in the result data corresponding to the multi-level operation circuits respectively, to obtain the quotient in the target result data corresponding to the original data to be processed, and converts the The quotient output in the target result data.
  • the last stage of the multi-stage operation circuit uses the remainder in the result data corresponding to the last stage of operation circuit as the remainder corresponding to the original data to be processed Remainder output in target result data.
  • each stage of the multi-stage arithmetic circuit for each sub-data in the plurality of sub-data, according to the position of the sub-data in the first processed data, for the sub-data Perform a data shift operation on the corresponding quotient, and add the data shift operation result of the quotient corresponding to the sub-data to the data shift operation results of the quotient corresponding to other sub-data to obtain the quotient corresponding to the first processed data , including: for each sub-data in the plurality of sub-data, each stage of the multi-stage operation circuit performs a data shift operation on the quotient corresponding to the sub-data according to the position of the sub-data in the first processed data , and add the data shift operation result of the quotient corresponding to this sub-data, the data shift operation result of the quotient corresponding to other sub-data, and the quotient in the result data of the previous stage of the operation circuit of this stage of operation circuit, to obtain The quotient in the result data corresponding to the
  • the last stage of the multi-stage operation circuit uses the result data corresponding to the last stage of operation circuit as the target processing result corresponding to the original data to be processed output.
  • each stage of the multi-stage arithmetic circuit includes: a data segmentation circuit, a data search circuit connected to the data segmentation circuit, and a data search circuit connected to the data search circuit.
  • the splicing circuit; the data processing method further includes: after the data segmentation circuit receives the first processing data corresponding to the operation circuit of the stage, the corresponding first processing data is segmented into a plurality of sub-data; After the data lookup circuit receives the plurality of sub-data from the data segmentation circuit, it performs a table lookup operation based on the obtained second processed data and the plurality of sub-data, and obtains that the plurality of sub-data respectively correspond to intermediate result data; after the splicing circuit receives the intermediate result data respectively corresponding to the plurality of sub-data sent by the data search circuit, based on the intermediate result data respectively corresponding to the plurality of sub-data, obtains the first processing The result data corresponding to the data.
  • An embodiment of the present disclosure further provides a chip, including the data processor according to any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a computer device, including: an instruction memory and the data processor according to any one of the embodiments of the present disclosure, or the chip according to the embodiments of the present disclosure.
  • the data processor provided in the embodiments of the present disclosure may include a chip, an AI chip, and the like.
  • the computer device provided in the embodiment of the present disclosure may include a smart terminal such as a mobile phone, or may also be other devices, servers, etc. that can be used for data processing, which is not limited here.
  • Embodiments of the present disclosure further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the steps of the data processing method described in the foregoing method embodiments are executed.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the data processing method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)

Abstract

本公开提供了一种用于数据处理的装置、方法、芯片、计算机设备及介质，其中，数据处理器包括：多级运算电路以及寄存器；多级运算电路中的每级运算电路，用于获取与该级运算电路对应的第一处理数据和第二处理数据，基于第一处理数据和第二处理数据从寄存器中获取对第一处理数据和第二处理数据进行预设处理得到的结果数据；寄存器，用于存储对第一处理数据和第二处理数据进行预设处理对应的结果数据；其中，多级运算电路中的第一级运算电路对应的第一处理数据基于外部输入的原始待处理数据确定，且多级运算电路中除第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。

Description

用于数据处理的装置、方法、芯片、计算机设备及介质
相关申请的交叉引用
本公开要求于2021年05月27日提交的、申请号为202110585822.0、发明名称为“数据处理器、数据处理方法、芯片、计算机设备及介质”的中国专利申请的优先权，该申请以引用的方式并入本文中。
技术领域
本公开涉及计算机技术领域，具体而言，涉及用于数据处理的装置、方法、芯片、计算机设备及存储介质。
背景技术
随着集成电路的不断发展，除法器被广泛的应用于各式芯片中。常用的除法算法大多基于加减法运算或者乘法运算实现，存在运算速度慢的问题，导致数据处理的效率降低。
发明内容
本公开实施例至少提供一种数据处理器、数据处理方法、芯片、计算机设备及存储介质。
第一方面，本公开实施例提供了一种数据处理器，包括：多级运算电路以及寄存器；所述多级运算电路中的每级运算电路，用于获取与该级运算电路对应的第一处理数据和第二处理数据，基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据；所述寄存器，用于存储对所述第一处理数据和所述第二处理数据进行预设处理所得到的结果数据；其中，所述多级运算电路中的第一级运算电路对应的所述第一处理数据基于外部输入的原始待处理数据确定，且所述多级运算电路中除所述第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。
这样，通过多级运算电路逐级通过结果数据查找操作得到每一级对应的结果数据，所需要的时间较之通过乘法运算结合比较运算得到除法运算的结果更少，因此具有更高的处理效率。
一种可选的实施方式中，所述第一处理数据包括：被除数；所述第二处理数据包括：除数；所述预设处理包括：利用所述除数对所述被除数进行除法运算处理；所述结果数据包括：利用所述除数对所述被除数进行除法运算处理得到的商和余数。
一种可选的实施方式中，所述多级运算电路中所述第一级运算电路对应的第一处理数据包括：所述原始待处理数据；所述多级运算电路中除所述第一级运算电路外的其他任一级运算电路对应的第一处理数据包括：该其他级运算电路的上一级运算电路输出的结果数据中的余数。
这样，原始待处理数据作为第一级运算电路对应的第一处理数据，可以使第一级运算电路能够先对原始待处理数据进行分割，减少第二级运算电路需要处理的第一处理数据的数据量；利用第二级运算电路后的运算电路对上一级运算电路中确定结果数据进行处理，可以保证在高位的数据经过有效处理，直至不再能够被第二处理数据除尽，也即保证了数据处理的准确性。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，在基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据时，用于：基于所述第二处理数据，在所述寄存器中查找与所述第二处理数据对应的目标查找表；基于所述第一处理数据，从所述目标查找表中查找与所述第一处理数据对应的结果数据。
这样，通过查表操作可以较为快速的根据第一处理数据以及第二处理数据确定结果数据。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，在基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据时，用于：将所述第一处理数据切分为多个子数据；针对所述多个子数据中的每个子数据，基于该子数据和所述第二处理数据，从所述寄存器中获取利用所述第二处理数据对该子数据进行预设处理得到的中间结果数据；基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
一种可选的实施方式中，所述多个子数据占用的比特位数量相同。
一种可选的实施方式中，任一所述子数据对应的中间结果数据，包括该子数据对应的商、以及该子数据对应的余数；所述多级运算电路中的每级运算电路，在基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据时，用于：针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商；以及针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的余数进行数据移位操作，并将该子数据对应的余数的数据移位操作结果，与其他子数据对应的余数的数据移位操作结果相加，得到所述第一处理数据对应的余数。
这样，通过利用切分电路将第一处理数据切分为多个子数据，可以使得每级运算电 路均可以对多个子数据并行处理，从而提高数据处理的效率。
一种可选的实施方式中，还包括：整合电路；所述整合电路，用于将所述多级运算电路分别对应的结果数据中的商相加，得到所述原始待处理数据对应的目标结果数据中的商，并将所述目标结果数据中的商输出。
一种可选的实施方式中，所述多级运算电路中的最后一级运算电路，还用于将所述最后一级运算电路对应的结果数据中的余数，作为所述原始待处理数据对应的目标结果数据中的余数输出。
这样，通过整合电路，可以较为容易的对各级运算电路输出的结果数据进行处理，并得到目标结果数据。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，在针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商时，用于：针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果、其他子数据对应的商的数据移位操作结果、以及该级运算电路的前一级运算电路的结果数据中的商相加，得到该级运算电路对应的结果数据中的商。
一种可选的实施方式中，所述多级运算电路中的最后一级运算电路，还用于将所述最后一级运算电路对应的结果数据，作为所述原始待处理数据对应的目标处理结果输出。
这样，从每一级运算电路均可以直接确定在该级运算电路以及该级运算电路之前，确定的商和余数，因此可以不必附加一个整合电路，即可以使最后一级运算电路输出目标结果数据，减小电路的体积开销，同时减少数据处理需要的耗时。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，包括：数据切分电路，用于在接收到该级运算电路对应的第一处理数据后，将所述对应的第一处理数据切分为多个子数据；数据查找电路，用于在从所述数据切分电路接收到所述多个子数据后，基于获取的所述第二处理数据、以及所述多个子数据进行查表操作，得到所述多个子数据分别对应的中间结果数据；拼接电路，用于在接收到所述数据查找电路发送的所述多个子数据分别对应的中间结果数据后，基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
第二方面，本公开实施例还提供一种数据处理方法，应用于数据处理器；所述数据处理器包括多级运算电路以及寄存器；所述数据处理方法包括：所述多级运算电路中的每级运算电路获取与该级运算电路对应的第一处理数据和第二处理数据，基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处 理数据进行预设处理得到的结果数据；所述寄存器存储对所述第一处理数据和所述第二处理数据进行预设处理所得到的结果数据；其中，所述多级运算电路的第一级运算电路对应的所述第一处理数据基于外部输入的原始待处理数据确定，且所述多级运算电路中除所述第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。
一种可选的实施方式中，所述第一处理数据包括：被除数；所述第二处理数据包括：除数；所述预设处理包括：利用所述除数对所述被除数进行除法运算处理；所述结果数据包括：利用所述除数对所述被除数进行除法运算处理得到的商和余数。
一种可选的实施方式中，所述多级运算电路中所述第一级运算电路对应的第一处理数据包括：所述原始待处理数据；所述多级运算电路中除所述第一级运算电路外的其他任一级运算电路对应的第一处理数据包括：该其他级运算电路的上一级运算电路输出的结果数据中的余数。
一种可选的实施方式中，所述多级运算电路中的每级运算电路基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据，包括：所述多级运算电路中的每级运算电路基于所述第二处理数据，在所述寄存器中查找与所述第二处理数据对应的目标查找表；基于所述第一处理数据，从所述目标查找表中查找与所述第一处理数据对应的结果数据。
一种可选的实施方式中，所述多级运算电路中的每级运算电路基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据，包括：将所述第一处理数据切分为多个子数据；针对所述多个子数据中的每个子数据，基于该子数据和所述第二处理数据，从所述寄存器中获取利用所述第二处理数据对该子数据进行预设处理得到的中间结果数据；基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
一种可选的实施方式中，所述多个子数据占用的比特位数量相同。
一种可选的实施方式中，任一子数据对应的中间结果数据，包括该子数据对应的商、以及该子数据对应的余数；所述多级运算电路中的每级运算电路基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据，包括：所述多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商；以及针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的余数进行数据移位操作，并将该子数据对应的余数的数据移位操作结果，与其他子数据对应的余数的数据移位操作结果相加，得到所述第一处理 数据对应的余数。
一种可选的实施方式中，还包括：整合电路将多级运算电路分别对应的结果数据中的商相加，得到所述原始待处理数据对应的目标结果数据中的商，并将所述目标结果数据中的商输出。
一种可选的实施方式中，还包括：所述多级运算电路中的最后一级运算电路将所述最后一级运算电路对应的结果数据中的余数，作为所述原始待处理数据对应的目标结果数据中的余数输出。
一种可选的实施方式中，所述多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商，包括：多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果、其他子数据对应的商的数据移位操作结果、以及该级运算电路的前一级运算电路的结果数据中的商相加，得到该级运算电路对应的结果数据中的商。
一种可选的实施方式中，还包括：所述多级运算电路中的最后一级运算电路将所述最后一级运算电路对应的结果数据，作为所述原始待处理数据对应的目标处理结果输出。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，包括：数据切分电路、与所述数据切分电路连接的数据查找电路、以及与所述数据查找电路连接的拼接电路；所述数据处理方法还包括：所述数据切分电路在接收到该级运算电路对应的第一处理数据后，将所述对应的第一处理数据切分为多个子数据；所述数据查找电路在从所述数据切分电路接收到所述多个子数据后，基于获取的所述第二处理数据、以及所述多个子数据进行查表操作，得到所述多个子数据分别对应的中间结果数据；所述拼接电路接收到所述数据查找电路发送的所述多个子数据分别对应的中间结果数据后，基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
第三方面，本公开可选实施方式还提供一种芯片，包括如第一方面任一项所述的数据处理器。
第四方面，本公开可选实施方式还提供一种计算机设备，包括：指令存储器和如第一方面任一项所述的数据处理器；或者所述计算机设备包括如第三方面所述的芯片。
第五方面，本公开可选实施方式还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被运行时执行上述第二方面，或第二方面中任一种可能的实施方式中的步骤。
关于上述数据处理方法、芯片、计算机设备、及计算机可读存储介质的效果描述参 见上述数据处理器的说明，这里不再赘述。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍。这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种数据处理器的示意图；
图2示出了本公开实施例所提供的一种数据处理器的具体内部电路结构的示意图；
图3示出了本公开实施例所提供的基于第一处理数据和第二处理数据从寄存器中进行查表操作的具体步骤的流程图；
图4示出了本公开实施例所提供的一种切分电路在对第一处理数据进行切分时的示意图；
图5(a)和图5(b)示出了本公开实施例所提供的在寄存器中存储的多个查找表的示意图；
图6示出了本公开实施例所提供的一种确定第一级运算电路对应结果数据中余数的电路结构的示意图；
图7示出了本公开实施例提供的一种整合电路的示意图；
图8示出了本公开实施例提供的另一种整合电路的示意图；
图9示出了本公开实施例提供的一种数据处理方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
经研究发现，在利用例如除法器等数据处理器执行除法运算时，通常会将其转换为 乘法运算，以较为简单的得到除法运算的目标结果数据。示例性的，在确定被除数M以及除数N后，通过确定一个预测的商A，可以确定该预测的商A与除数N的乘积C，然后利用比较器确定被除数M与乘积C的差值是否小于除数N，从而确定预测的商A是否为被除数M以及除数N对应的除法运算的目标结果数据中的商。在确定预测的商A时，例如可以将预测商A先设置为1，然后逐次增加1，直至比较器确定被除数M与乘积C的差值小于除数N，则将此处的预测商A作为目标结果数据中的商，并将此时确定的被除数M与乘积C的差值作为目标结果数据中的余数。这种方式需要采用迭代的方式确定目标结果数据，在被除数与除数的数值差异较大时，需要耗费较多的时间，导致在对数据进行处理时效率较低。
基于上述研究，本公开提供了一种数据处理器，包括多级运算电路以及寄存器，每一级运算电路均可以利用其对应的第一处理数据和第二处理数据进行结果数据查找操作，也即从寄存器中存储的结果数据中确定对应的结果数据。这样，通过多级运算电路逐级利用结果数据查找操作得到每一级对应的结果数据，所需要的时间较之通过乘法运算结合比较运算得到除法运算的结果所需的时间更少，因此具有更高的处理效率。
以上均是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及下文中本公开针对上述问题所提出的解决方案，都应该是发明人在本公开过程中对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种数据处理器进行详细介绍，数据处理器可部署于具有一定计算能力的计算机设备，该计算机设备例如包括：终端设备或服务器或其它处理设备，终端设备可以为用户设备(User Equipment，UE)、移动设备、用户终端、终端、蜂窝电话、无绳电话、个人数字助理(Personal Digital Assistant，PDA)、手持设备、计算设备、车载设备、可穿戴设备等。
下面对本公开实施例提供的数据处理器加以说明。
参见图1所示，为本公开实施例提供的一种数据处理器的示意图，在图1中，所述数据处理器包括多级运算电路10以及寄存器20。
所述多级运算电路10中的每级运算电路10，用于获取与该级运算电路10对应的第一处理数据和第二处理数据，基于所述第一处理数据和所述第二处理数据从所述寄存器20中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据；所述寄存器20，用于存储对所述第一处理数据和所述第二处理数据进行预设处理对应所得到的结果数据；其中，所述多级运算电路中的第一级运算电路对应的第一处理数据基于外部输入的原始待处理数据确定，所述多级运算电路中除所述第一级运算电路外的其他级 运算电路对应的第一处理数据基于该其他级运算电路的上一级运算电路10输出的结果数据确定的。
在图2中，示出了数据处理器具体内部电路结构的示意图。在将数据处理器用于除法运算时，第一处理数据包括被除数，表示为M；第二处理数据包括除数，表示为N。由于计算机在对第一处理数据以及第二处理数据进行处理时，使用的数据是二进制数据，因此在对本公开实施例提供的数据处理器进行说明时，利用下角标“(2)”标识二进制数据；利用下角标“(10)”标识十进制数据。
参见图3所示，为本公开实施例提供的一种基于第一处理数据和第二处理数据从寄存器中进行查表操作的具体步骤包括以下步骤S301至S303。
S301：将第一处理数据切分为多个子数据。
在一种可能的实施方式中，多个子数据占用的比特位数量相同。
具体地，多级运算电路10中的每级运算电路10对应不同的第一处理数据和第二处理数据。多级运算电路10中的第一级运算电路10对应的第一处理数据包括：原始待处理数据。此处，原始待处理数据例如可以包括需要进行除法运算的一个被除数M0。被除数M0以二进制数表示时，可能占据多个比特位，例如在被除数M0为16 (10)时，对应的二进制数为1111 (2)，占据4个比特位；在被除数M0为256 (10)时，对应的二进制数为11111111 (2)，占据8个比特位。也即，当被除数M0以十进制数据表示的值越大时，对应的二进制数占据的比特位数会增加。因此，在利用第一级运算电路10对第一处理数据进行数据处理时，会先将第一处理数据进行切分，并利用切分后占用比特位数量较少的数据进行查表操作，以确定第一处理数据对应的结果数据。
其中，在对第一处理数据进行切分，得到多个子数据时，例如可以利用第一级运算电路10中的切分电路对第一处理数据进行切分处理。参见图2所示，在第一级运算电路10中，包括切分电路11。
切分电路11对第一处理数据进行切分时，可以根据确定的多级运算电路10的级数确定切分电路在对第一处理数据进行切分后，得到的子数据占据的比特位数量。例如，确定第一处理数据利用二进制数据表示，占据32个比特位、并且多级运算电路10对应的级数为3级，可以确定需要将第一级运算电路10中对应的第一处理数据切分为多个占据8个比特位的子数据。
示例性的，由于多级运算电路10的结构会在确定后被固化到芯片中，因此要预先根据实际要处理的数据所占用的最高比特数，确定运算电路的级数。在对运算电路使用过程中，无论要处理的数据是否达到最高比特数，都会利用固定级数的多级运算电路10进行处理。在一种可能的情况下，若要处理的数据未达到最高比特数，可以对该处理的数据进行补零操作，使得补零操作后的数据达到最高比特数，以能够实现利用多级运算 电路10进行处理。
在确定多级运算电路10的级数时，例如可以根据预先确定的第一处理数据以及第二处理数据分别对应的比特数确定。
示例性的，在确定第一处理数据的比特位数量最多为4位，而第二处理数据的比特位数量最少为2位时，可以确定在利用2比特位对第一处理数据对应的4个比特位进行切分后，利用第二处理数据对切分出的子数据进行数据处理后，高两位得到的子数据在左移两位后对应的数值还可以与第二处理数据进行下一步的数据处理。也即，共需要设置两级运算电路10，以对第一处理数据进行处理。
参见图4所示，为本公开实施例提供的一种切分电路在对第一处理数据进行切分时的示意图，在第一级运算电路10接收到第一处理数据后，其中的切分电路11将第一处理数据切分为4个子数据。利用切分电路11可以将第一处理数据中各个比特位的数据传输到对应的4个子数据分别对应的比特位上，以实现将第一处理数据切分为4个子数据的数据处理过程。在图4中，第一处理数据41包括占据32个比特位的二进制数据10101011101010101010100110101000 (2)，在输入时例如可以先经过切分电路11的多个数据输入通路，确定为如图4中虚线框42所示的形式，也即每个数据输入通路完成对应位置数据的传输，如第一个数据通路，将第一处理数据41中第一个比特位对应的数据“0”传输至切分电路中。利用图4中所示的切分电路11可以切分出4个子数据43，包括10101011 (2)、10101010 (2)、10101001 (2)、以及10101000 (2)，利用十进制表示，则分别为171 (10)、170 (10)、169 (10)、以及168 (10)。
此处，一个数据处理器内部的切分电路11的结构是预先确定的，例如上述图4中切分电路11可以将第一处理数据切分为4个分别占据8个比特位的子数据。因此对于第一处理数据对应的比特位数小于切分电路11可以处理的最大比特位数的情况，例如在图4中切分电路11切分的第一处理数据占据的比特位为30位时，切分电路可以对该30个比特位的数据进行切分；但对于第一处理数据最高的8比特位对应的子数据，由于其最高2个比特位没有数据，因此例如可以进行补位处理，例如在该2个比特位补0，以在保证子数据的数值没有变化的情况下，使得利用切分电路11切分得到的多个子数据占据的比特位数量相同。
这样，由于数据处理器中的各个电路在预先设计时均保证了在第一处理数据最大时可以正确地处理数据，也即各个电路均按照最大的数据处理量设计，因此在对第一处理数据进行处理时，为了避免电路中的部分数据通路由于不传输数据而输出错误数值，可以选择在切分电路所得到的子数据前补位，以保证后续对该子数据进行处理的安全性和准确性。或者，也可以在保证安全性和准确性的情况下不进行补位操作。具体可以根据实际情况确定，在此不再赘述。
在切分电路11确定多个子数据后，可以将多个子数据分别传输至对应的数据查找电路中，以使第一级运算电路10中的数据查找电路对此多个子数据进行下一步数据处理。
对于多级运算电路10中除第一级运算电路10外的其他级运算电路10，其对应的第一处理数据包括：该其他级运算电路的上一级运算电路10输出的结果数据；该其他级运算电路10将对应的第一处理数据切分为多个子数据的方式，与第一级运算电路10将对应的第一处理数据切分为多个子数据的方式类似，在此不再赘述。
S302：针对多个子数据中的每个子数据，基于该子数据和第二处理数据，从寄存器中获取利用第二处理数据对该子数据进行预设处理得到的中间结果数据。
其中，在从寄存器中获取利用第二处理数据对该子数据进行预设处理得到的中间结果数据时，例如可以采用查表操作。以第一级运算电路10为例，例如可以利用第一级运算电路10中的数据查找电路对寄存器20中的多个查找表进行查找。参见图2所示，在第一级运算电路10中，还包括数据查找电路12。
具体地，第一级运算电路10中的数据查找电路12在接收到多个子数据后，可以根据获取的第二处理数据以及子数据进行查表操作，得到利用第二处理数据对该子数据进行预设处理的中间结果数据。
在一种可能的实施方式中，多级运算电路10可以包括一个或多个数据查找电路12。在仅存在一个数据查找电路12的情况下，数据查找电路12例如可以先确定与第二处理数据对应的查找表，然后再根据子数据对该确定的查找表进行查表操作。此处，数据查找电路12可以访问多个查找表。
在存在多个数据查找电路12的情况下，多个数据查找电路12例如可以分别对应于不同的查找表。在确定第二处理数据的情况下，可以根据第二处理数据确定与第二处理数据对应的数据查找电路12，然后该数据查找电路12根据子数据访问其对应的查找表以进行查表操作。也即，数据查找电路12访问与其对应的查找表。
参见图5(a)和图5(b)所示，为本公开实施例提供的在寄存器中存储的多个查找表的示意图。在寄存器20中存储有分别与多个可能的第二处理数据对应的查找表。示例性的，第二处理数据例如可以包括2 (10)、3 (10)、5 (10)、以及9 (10)，在寄存器20中对应的查找表51可以包括在图5(a)中示出的四个查找表T1、T2、T3、以及T4。在确定子数据占据的比特位为8位的情况下，对于任一查找表，例如查找表T1，其中包含的数据包括该子数据对应的中间结果数据。具体地，查找表51包括该子数据对应的商和余数，并在图5(b)中示出了查找表T1所包括的数据。在图5(b)中，第一列的数据为可能的第一处理数据(其被切分成多个子数据)，第二列数据与第三列数据分别为对应第一处理数据(具体包括从该第一处理数据切分出的多个子数据)的中间结果数据中的商以及余数。
以一个子数据10101011 (2)为例，在第二处理数据包括2 (10)时，数据查找电路可以根据第二处理数据2 (10)，在寄存器20存放的多个查找表T1、T2、T3、以及T4中，确定第二处理数据2 (10)对应的查找表T1，作为目标查找表。然后，在目标查找表T1中，数据查找电路确定与子数据10101011 (2)对应的中间结果数据，也即在目标查找表T1中可以查找到的1010101 (2)以及00000001 (2)。类似的，数据查找电路还可以在目标查找表T1中确定其余的子数据10101010 (2)、10101001 (2)、以及10101000 (2)分别对应的中间结果数据。这样，数据查找电路可以得到在第一级运算电路10中确定的中间结果数据中的商和余数。
在得到第一级运算电路10中确定的中间结果数据后，第一级运算电路10中的数据查找电路12可以将该中间结果数据传输至拼接电路中，以使第一级运算电路10中的拼接电路对此中间结果数据进行下一步数据处理。
类似的，多级运算电路10中除第一级运算电路10外的其他级运算电路10从寄存器20中进行查表操作，得到在该其他级运算电路10中确定的中间结果数据(即利用第二处理数据对该其他级运算电路10对应的子数据进行预设处理得到的中间结果数据)的过程，与第一级运算电路10得到中间结果数据的过程类似，在此不再赘述。
S303：基于多个子数据分别对应的中间结果数据，得到第一处理数据对应的结果数据。
其中，在根据多个子数据分别对应的中间结果数据确定第一处理数据对应的结果数据时，例如可以采用拼接电路完成拼接操作。参见图2所示，在第一级运算电路10中，还包括拼接电路13。
仍然以第一级运算电路10为例，拼接电路13在接收到所述多个数据查找电路分别发送的中间结果数据后，可以基于所述多个数据查找电路分别发送的中间结果数据，得到所述第一处理数据对应的结果数据。
此处，对于第一级运算电路10，其对应的商可以直接保留并用于计算目标结果数据，而其对应的余数则由于对应的子数据可能为高位数据，因此需要还原为在原始待处理数据中的真实值后再进行计算。
在具体实施中，第一级运算电路10在基于多个子数据分别对应的中间结果数据，得到第一处理数据对应的结果数据时，可以采用下述方法：针对多个子数据中的每个子数据，根据该子数据在第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果与其他子数据对应的商的数据移位操作结果相加，得到第一处理数据对应的商；以及针对多个子数据中的每个子数据，根据该子数据在第一处理数据中的位置，对该子数据对应的余数进行数据移位操作，并将该子数据对应的余数的数据移位操作结果与其他子数据对应的余数的数据移位操作结果相加， 得到第一处理数据对应的余数。
示例性的，在4个子数据包括10101011 (2)、10101010 (2)、10101001 (2)、以及10101000 (2)的情况下，可以确定第一个子数据10101011 (2)对应的中间结果数据包括表示商的数据1010101 (2)以及表示余数的数据00000001 (2)；确定第二个子数据10101010 (2)对应的中间结果数据包括表示商的数据1010101 (2)以及表示余数的数据00000000 (2)；确定第三个子数据10101001 (2)对应的中间结果数据包括表示商的数据1010100 (2)以及表示余数的数据00000001 (2)；确定第四个子数据10101000 (2)对应的中间结果数据包括表示商的数据1010100 (2)以及表示余数的数据00000000 (2)。
由于第一个子数据10101011 (2)对应第一级运算电路10中第一处理数据的第31位至第24位，因此其实际的数值应当为10101011 (2)左移24位后的数值。对应的，第一个子数据对应的商1010101 (2)实际的数值应当为1010101 (2)向左移位16位后的数值；第一个子数据对应的余数00000001 (2)实际的数值应当为00000001 (2)向左移位24位后的数值。
类似的，可以用上述确定第一个子数据对应的中间结果数据的方法，确定第二个子数据至第四个子数据分别对应的中间结果数据。
在查找表中确定第一个子数据至第四个子数据分别对应的商和余数，并将其通过移位操作确定其实际的数值后，可以将第一个子数据至第四个子数据分别对应的数据移位操作结果相加，得到在第一级运算电路10对应的结果数据。
参见图6所示，为本公开实施例提供的一种确定第一级运算电路对应的结果数据中余数的电路结构的示意图。图6中包括的四个子数据对应的余数61～64，分别对应了原始待处理数据占据比特位的第0位至第7位、第8位至第15位、第16位至第23位、第24位至第31位，因此在利用拼接电路完成拼接操作时，例如可以先将子数据61～64按照其对应原始待处理数据占据比特位的位数，确定将子数据对应的中间结果数据中的每一位数据传输的数据通路。利用虚线框65所示的电路结构，可以将多个子数据对应的中间结果数据中的余数进行移位，得到第一级运算电路10对应的结果数据中的余数66。
类似的，除第一级运算电路10外的其他级运算电路10在对第一处理数据以及第二处理数据进行数据处理时，利用与第一级运算电路10相似的处理步骤。但除第一级运算电路10外的其他级运算电路10对应的第一处理数据包括该其他级运算电路10的上一级运算电路10输出的结果数据。这样，可以将一个较大的外部输入的原始待处理数据利用多级运算处理的方式来减少直接对其进行运算时的数据量级，从而减少数据处理所耗费的时间。
在利用多级运算电路10确定原始待处理数据对应的目标处理结果时，例如可以采用 但不限于下述(A)和(B)中任一种方法。
(A)：利用整合电路，将多级运算电路10分别对应的结果数据中的商相加，得到原始待处理数据对应的目标结果数据中的商，并将该目标结果数据中的商输出；多级运算电路10中的最后一级运算电路10，将最后一级运算电路10对应的结果数据中的余数，作为原始待处理数据对应的目标结果数据中的余数输出。
下面对确定原始待处理数据对应的目标结果数据中的商进行说明。
此时，在多级运算电路10中，还包括一个整合电路，该整合电路可以将每一级输出的结果数据中的商进行相加，也即在多级运算电路10的每一级运算电路10中，均存在将结果数据中的商传输至整合电路的数据通路。该整合电路中，例如可以包括至少一个结果数据寄存器。
在整合电路包括多个结果数据寄存器的情况下，多个结果数据寄存器20可以分别对应一级运算电路10，并分别存储每一级运算电路10输出的结果数据中的商。在最后一级运算电路10对其对应的第一处理数据以及第二处理数据处理完毕后，整合电路可以将多个结果数据寄存器中分别存储的每一级运算电路10得到的结果数据中的商相加，得到目标结果数据中的商。
参见图2所示，在数据处理器中还包括整合电路14。具体地，参见图7所示，为本公开实施例提供的一种整合电路14的示意图。在图7所示的整合电路中，包括与三级运算电路10分别对应的结果数据寄存器71、72、73，分别与第一级运算电路10的拼接电路13、第二级运算电路10的拼接电路13以及第三级运算电路10的拼接电路13相连接，以存储每一级运算电路10输出的结果数据中的商。
在整合电路仅存在一个结果数据寄存器的情况下，结果数据寄存器仅存储当前级运算电路10的前一级运算电路10中输出的结果数据中的商，然后利用整合电路将在此结果数据寄存器中存储的前一级运算电路10中输出的商与当前级运算电路10输出的结果数据中的商相加。这样，在最后一级运算电路10完成对其对应的第一处理数据和第二处理数据的处理后，即可以在此结果数据寄存器中得到原始待处理数据对应的目标结果数据中的商。
参见图8所示，为本公开实施例提供的另一种整合电路的示意图。在图8所示的整合电路14中，包括一个结果数据寄存器81。这样，在第一级运算电路10确定其对应的结果数据中的商后，将商存储至结果数据寄存器81中，并在下一级运算电路10计算对应的结果数据后，将此下一级运算电路对应的结果数据中的商、以及已存储至结果数据寄存器81中的商整合为新的商，并重新存储在结果数据寄存器81中。
在确定原始待处理数据对应的目标结果数据中的商后，还可以将最后一级运算电路10对应的结果数据中的余数作为原始待处理数据对应的目标结果数据中的余数输出。
(B)：针对多个子数据中的每个子数据，根据该子数据在第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果、其他子数据对应的商的数据移位操作结果、以及前一级运算电路10的结果数据中的商相加，得到该级运算电路10对应的结果数据中的商；将最后一级运算电路10对应的结果数据，作为原始待处理数据对应的目标处理结果输出。
以存在三级运算电路为例，在每一级运算电路中，均可以输出对应于该运算电路的结果数据，也即在每一级运算电路中均可以输出对应的商。针对于第一级运算电路10，其对应的结果数据例如可以包括对4个子数据进行除法运算后得到的、与4个子数据分别对应的商。基于4个商分别对应的子数据所占据的比特位，可以对得到的4个商进行数据移位操作，得到第一级运算电路10输出的结果数据中的商，例如可以表示为q1。
然后，将第一级运算电路10确定的商q1输出至第二级运算电路10。在第二级运算电路对其对应的子数据(例如可以包括2个子数据)进行除法运算后，例如可以得到2个子数据分别对应的商。基于该2个商分别对应的子数据所占据的比特位，可以对得到的2个商进行数据移位操作，得到第二级运算电路10在对其对应的子数据进行处理后得到的商，表示为q2’。此处，由于第二级运算电路10是对第一级运算电路10得到的余数进行进一步除法运算得到的，因此在该第二级运算电路10中，例如可以将第一级运算电路10向第二级运算电路输入的商q1与第二级运算电路确定的商q2’相加，得到第二级运算电路对应的结果数据中的商q2。此时，对于第二级运算电路10而言，可以输出结果数据中的商q2。
然后，将第二级运算电路10确定的商q2输出至第三级运算电路10，此处，该第三级运算电路例如是多级运算电路中的最后一级运算电路，对应的子数据例如包括由第二级运算电路进行除法运算后得到的余数。在第三级运算电路10对该余数进行除法运算后，将处理后得到的商q3’以及上一级，也即第二级运算电路10输出的商q2相加，并将得到的结果q3作为第三级运算电路10对应的结果数据中的商。此处，由于第三级运算电路10为最后一级运算电路，因此可以将该级运算电路对应的结果数据中的商q3作为原始待处理数据对应的目标结果数据中的商。
针对余数而言，确定原始待处理数据对应的目标结果数据中的余数的过程，与上述确定原始待处理数据对应的目标结果数据中的商的过程相似，在此不再赘述。
此时，即可以将最后一级运算电路10中对应的结果数据，作为原始待处理数据对应的目标处理结果输出。
本公开实施例提供了一种利用数据处理器对原始待处理数据m进行数据处理的具体示例。在确定数据处理器对应的层级数量时，例如可以根据原始待处理数据最多可以占据的比特位数、第二处理数据占据的比特位数、以及切分电路切分数据后所得到子数 据占据的比特位数决定；或者，还可以设置一个较大的层级数量，以满足占据比特位数不同的原始待处理数据在进行数据处理时的要求。在对原始待处理数据m进行数据处理时，对应的除数为n，例如包括9 (10)。其中，原始待处理数据A包括11011011110110111101101111011011 (2)，对应十进制表示为3688618971 (10)。
在第一级运算电路10中，原始待处理数据m即为第一处理数据。利用切分电路将第一处理数据进行切分，可以得到四个子数据，分别为11011011 (2)、11011011 (2)、11011011 (2)、以及11011011 (2)，对应十进制表示为219 (10)。
在确定四个子数据后，第一级运算电路10中的数据查找电路依据第二处理数据，也即除数9 (10)，可以在对应的多个查找表中，确定与第二处理数据对应的查找表T4。数据查找电路在查找表T4中依据多个子数据，可以确定多个子数据分别对应的中间结果数据，包括11000 (2)以及011 (2)，分别表示中间结果数据中的商和余数。
此时，在第一级运算电路10中，可以利用拼接电路确定对应的结果数据中的商为00011000000110000001100000011000 (2)，并确定对应的结果数据中的余数为00000011000000110000001100000011 (2)；以及，将结果数据中的商00011000000110000001100000011000 (2)存储至整合电路中第一级运算电路10对应的存储单元中。
在第二级运算电路10中，以第一级运算电路10中确定的结果数据中的余数00000011000000110000001100000011 (2)作为第二级运算电路10对应的第一处理数据。在对第一处理数据进行划分后，可以对其进行八个比特位对应数据的拼接，确定两个子数据，每个子数据包括0000001100000011 (2)。
按照与上述确定第一级运算电路10对应的结果数据的方式，可以确定第二级运算电路10对应的中间结果数据，包括01010101 (2)(也即85 (10))以及110 (2)(也即6 (10))，分别表示中间结果数据中的商和余数。
此时，在第二级运算电路10中，可以利用拼接电路确定其对应的结果数据中的商为010101010000000001010101 (2)，并确定对应的结果数据中的余数为000000000000000000110 (2)；以及，将结果数据中的商010101010000000001010101 (2)存储至整合电路中第二级运算电路10对应的存储单元中。
依此类推，直至在最后一级运算电路10中，确定其输出的结果数据中的余数，即为原始待处理数据对应的目标结果数据中的余数；以及根据在每一级运算电路10中确定的结果数据中的商，确定原始待处理数据对应的目标结果数据中的商。其中，确定目标结果数据中的商的方式例如可以包括上述(A)以及(B)中的任一种，在此不再赘述。则对应于原始待处理数据A 11011011110110111101101111011011 (2)，其在第 二处理数据为9时，对应的商为11000011011011100001100011000 (2)，对应的余数为10 (2)。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于同一发明构思，本公开实施例中还提供了与数据处理器对应的数据处理方法，由于本公开实施例中的方法解决问题的原理与本公开实施例上述数据处理器相似，因此方法的实施可以参见装置的实施，重复之处不再赘述。
参照图9所示，为本公开实施例提供的一种数据处理方法的流程图，所述数据处理方法应用于数据处理器；所述数据处理器包括多级运算电路以及寄存器；所述数据处理方法包括：
S901：多级运算电路中的每级运算电路获取与该级运算电路对应的第一处理数据和第二处理数据，基于第一处理数据和第二处理数据从寄存器中获取对第一处理数据和第二处理数据进行预设处理得到的结果数据；
S902：寄存器存储对第一处理数据和第二处理数据进行预设处理所得到的结果数据；其中，所述多级运算电路中的第一级运算电路对应的第一处理数据基于外部输入的原始待处理数据确定，且所述多级运算电路中除所述第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。
一种可选的实施方式中，所述第一处理数据包括：被除数；所述第二处理数据包括：除数；所述预设处理包括：利用所述除数对所述被除数进行除法运算处理；所述结果数据包括：利用所述除数对所述被除数进行除法运算处理得到的商和余数。
一种可选的实施方式中，所述多级运算电路中所述第一级运算电路对应的第一处理数据包括：所述原始待处理数据；所述多级运算电路中除所述第一级运算电路外的其他任一级运算电路对应的第一处理数据包括：该其他级运算电路的上一级运算电路输出的结果数据中的余数。
一种可选的实施方式中，所述多级运算电路中的每级运算电路基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据，包括：所述多级运算电路中的每级运算电路基于所述第二处理数据，在所述寄存器中查找与所述第二处理数据对应的目标查找表；基于所述第一处理数据，从所述目标查找表中查找与所述第一处理数据对应的所述结果数据。
一种可选的实施方式中，所述多级运算电路中的每级运算电路基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数 据进行预设处理得到的结果数据，包括：将所述第一处理数据切分为多个子数据；针对所述多个子数据中的每个子数据，基于该子数据和所述第二处理数据，从所述寄存器中获取利用所述第二处理数据对该子数据进行预设处理得到的中间结果数据；基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
一种可选的实施方式中，所述多个子数据占用的比特位数量相同。
一种可选的实施方式中，任一子数据对应的中间结果数据，包括该子数据对应的商、以及该子数据对应的余数；所述多级运算电路中的每级运算电路基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据，包括：所述多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商；以及针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的余数进行数据移位操作，并将该子数据对应的余数的数据移位操作结果，与其他子数据对应的余数的数据移位操作结果相加，得到所述第一处理数据对应的余数。
一种可选的实施方式中，还包括：整合电路将多级运算电路分别对应的结果数据中的商相加，得到所述原始待处理数据对应的目标结果数据中的商，并将所述目标结果数据中的商输出。
一种可选的实施方式中，还包括：所述多级运算电路中的最后一级运算电路将所述最后一级运算电路对应的结果数据中的余数，作为所述原始待处理数据对应的目标结果数据中的余数输出。
一种可选的实施方式中，所述多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果，与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商，包括：多级运算电路中的每级运算电路针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果、其他子数据对应的商的数据移位操作结果、以及该级运算电路的前一级运算电路的结果数据中的商相加，得到该级运算电路对应的结果数据中的商。
一种可选的实施方式中，还包括：所述多级运算电路中的最后一级运算电路将所述最后一级运算电路对应的结果数据，作为所述原始待处理数据对应的目标处理结果输出。
一种可选的实施方式中，所述多级运算电路中的每级运算电路，包括：数据切分 电路、与所述数据切分电路连接的数据查找电路、以及与所述数据查找电路连接的拼接电路；所述数据处理方法还包括：所述数据切分电路在接收到该级运算电路对应的第一处理数据后，将所述对应的第一处理数据切分为多个子数据；所述数据查找电路在从所述数据切分电路接收到所述多个子数据后，基于获取的所述第二处理数据、以及所述多个子数据进行查表操作，得到所述多个子数据分别对应的中间结果数据；所述拼接电路接收到所述数据查找电路发送的所述多个子数据分别对应的中间结果数据后，基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
关于数据处理方法的处理流程可以参照上述数据处理器对应实施例中的相关说明，这里不再详述。
本公开实施例还提供了一种芯片，包括如本公开任一实施例所述的数据处理器。
本公开实施例还提供一种计算机设备，包括：指令存储器和如本公开实施例任一项所述的数据处理器，或如本公开实施例所述的芯片。
本公开实施例提供的数据处理器可以包括芯片、AI芯片等。本公开实施例提供的计算机设备可以包括手机等智能终端，或者也可以是其他可以用于进行数据处理的设备、服务器等，这里并不限制。
本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的数据处理方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的数据处理方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (16)

  1. 一种数据处理器，包括多级运算电路以及寄存器；
    所述多级运算电路中的每级运算电路，用于获取与该级运算电路对应的第一处理数据和第二处理数据，基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据；
    所述寄存器，用于存储对所述第一处理数据和所述第二处理数据进行预设处理所得到的结果数据；
    其中，所述多级运算电路中的第一级运算电路对应的所述第一处理数据基于外部输入的原始待处理数据确定，且所述多级运算电路中除所述第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。
  2. 根据权利要求1所述的数据处理器，其特征在于，
    所述第一处理数据包括：被除数；
    所述第二处理数据包括：除数；
    所述预设处理包括：利用所述除数对所述被除数进行除法运算处理；
    所述结果数据包括：利用所述除数对所述被除数进行除法运算处理得到的商和余数。
  3. 根据权利要求2所述的数据处理器，其特征在于，
    所述多级运算电路中所述第一级运算电路对应的第一处理数据包括：所述原始待处理数据；
    所述多级运算电路中除所述第一级运算电路外的其他任一级运算电路对应的第一处理数据包括：该其他级运算电路的上一级运算电路输出的结果数据中的余数。
  4. 根据权利要求1-3任一项所述的数据处理器，其特征在于，所述多级运算电路中的每级运算电路，在基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据时，用于：
    基于所述第二处理数据，在所述寄存器中查找与所述第二处理数据对应的目标查找表；
    基于所述第一处理数据，从所述目标查找表中查找与所述第一处理数据对应的结果数据。
  5. 根据权利要求1-4任一项所述的数据处理器，其特征在于，所述多级运算电路中的每级运算电路，在基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据时，用于：
    将所述第一处理数据切分为多个子数据；
    针对所述多个子数据中的每个子数据，基于该子数据和所述第二处理数据，从所述 寄存器中获取利用所述第二处理数据对该子数据进行预设处理得到的中间结果数据；
    基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
  6. 根据权利要求5所述的数据处理器，其特征在于，所述多个子数据占用的比特位数量相同。
  7. 根据权利要求5或6所述的数据处理器，其特征在于，任一所述子数据对应的中间结果数据包括该子数据对应的商以及该子数据对应的余数；所述多级运算电路中的每级运算电路，在基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据时，用于：
    针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商；以及
    针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的余数进行数据移位操作，并将该子数据对应的余数的数据移位操作结果与其他子数据对应的余数的数据移位操作结果相加，得到所述第一处理数据对应的余数。
  8. 根据权利要求7所述的数据处理器，其特征在于，还包括整合电路，用于：
    将所述多级运算电路分别对应的结果数据中的商相加，得到所述原始待处理数据对应的目标结果数据中的商，并
    将所述目标结果数据中的商输出。
  9. 根据权利要求8所述的数据处理器，其特征在于，所述多级运算电路中的最后一级运算电路，还用于将所述最后一级运算电路对应的结果数据中的余数，作为所述原始待处理数据对应的目标结果数据中的余数输出。
  10. 根据权利要求7所述的数据处理器，其特征在于，所述多级运算电路中的每级运算电路，在针对多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果与其他子数据对应的商的数据移位操作结果相加，得到所述第一处理数据对应的商时，用于：
    针对所述多个子数据中的每个子数据，根据该子数据在所述第一处理数据中的位置，对该子数据对应的商进行数据移位操作，并将该子数据对应的商的数据移位操作结果、其他子数据对应的商的数据移位操作结果、以及该级运算电路的前一级运算电路的结果数据中的商相加，得到该级运算电路对应的结果数据中的商。
  11. 根据权利要求10所述的数据处理器，其特征在于，所述多级运算电路中的最 后一级运算电路，还用于将所述最后一级运算电路对应的结果数据，作为所述原始待处理数据对应的目标处理结果输出。
  12. 根据权利要求1-11任一项所述的数据处理器，其特征在于，所述多级运算电路中的每级运算电路，包括：
    数据切分电路，用于在接收到该级运算电路对应的第一处理数据后，将所述对应的第一处理数据切分为多个子数据；
    数据查找电路，用于在从所述数据切分电路接收到所述多个子数据后，基于获取的所述第二处理数据、以及所述多个子数据进行查表操作，得到所述多个子数据分别对应的中间结果数据；
    拼接电路，用于在接收到所述数据查找电路发送的所述多个子数据分别对应的中间结果数据后，基于所述多个子数据分别对应的中间结果数据，得到所述第一处理数据对应的结果数据。
  13. 一种数据处理方法，应用于数据处理器；所述数据处理器包括多级运算电路以及寄存器；所述数据处理方法包括：
    所述多级运算电路中的每级运算电路获取与该级运算电路对应的第一处理数据和第二处理数据，基于所述第一处理数据和所述第二处理数据从所述寄存器中获取对所述第一处理数据和所述第二处理数据进行预设处理得到的结果数据；
    所述寄存器存储对所述第一处理数据和所述第二处理数据进行预设处理所得到的结果数据；
    其中，所述多级运算电路的第一级运算电路对应的所述第一处理数据基于外部输入的原始待处理数据确定，且所述多级运算电路中除所述第一级运算电路外的其他级运算电路对应的第一处理数据是基于该其他级运算电路的上一级运算电路输出的结果数据确定的。
  14. 一种芯片，包括：如权利要求1-12任一项所述的数据处理器。
  15. 一种计算机设备，包括处理器、存储器以及如权利要求1-12任一项所述的数据处理器；或者
    所述计算机设备包括如权利要求14所述的芯片。
  16. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被数据处理器运行时执行如权利要求13所述的数据处理方法的步骤。
PCT/CN2021/134278 2021-05-27 2021-11-30 用于数据处理的装置、方法、芯片、计算机设备及介质 WO2022247193A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110585822.0 2021-05-27
CN202110585822.0A CN113254072B (zh) 2021-05-27 2021-05-27 数据处理器、数据处理方法、芯片、计算机设备及介质

Publications (1)

Publication Number Publication Date
WO2022247193A1 true WO2022247193A1 (zh) 2022-12-01

Family

ID=77184828

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/134278 WO2022247193A1 (zh) 2021-05-27 2021-11-30 用于数据处理的装置、方法、芯片、计算机设备及介质

Country Status (2)

Country Link
CN (1) CN113254072B (zh)
WO (1) WO2022247193A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113254072B (zh) * 2021-05-27 2023-04-07 上海阵量智能科技有限公司 数据处理器、数据处理方法、芯片、计算机设备及介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725974A (en) * 1984-02-07 1988-02-16 Nec Corporation Electronic circuit capable of accurately carrying out a succession of divisions in a pipeline fashion
JPH01286023A (ja) * 1988-05-12 1989-11-17 Fujitsu Ltd 除算命令処理装置
JPH07210371A (ja) * 1994-01-19 1995-08-11 Nec Eng Ltd パイプライン型除算処理装置
CN104375802A (zh) * 2014-09-23 2015-02-25 上海晟矽微电子股份有限公司 一种乘除法器及运算方法
CN113222132A (zh) * 2021-05-22 2021-08-06 上海阵量智能科技有限公司 乘法器、数据处理方法、芯片、计算机设备及存储介质
CN113254072A (zh) * 2021-05-27 2021-08-13 上海阵量智能科技有限公司 数据处理器、数据处理方法、芯片、计算机设备及介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001188468A (ja) * 1999-12-27 2001-07-10 Toyo Commun Equip Co Ltd ガロア体上の元の除算演算方法および除算演算回路
US8914431B2 (en) * 2012-01-03 2014-12-16 International Business Machines Corporation Range check based lookup tables
CN103593159A (zh) * 2012-08-14 2014-02-19 重庆重邮信科通信技术有限公司 一种高效率高精度除法实现方法及装置
US20160034256A1 (en) * 2014-08-01 2016-02-04 Imagination Technologies, Limited Fast integer division
GB2540215B (en) * 2015-07-10 2020-09-09 Advanced Risc Mach Ltd An apparatus and method for performing division
CN106354473B (zh) * 2015-07-16 2019-02-12 浙江大华技术股份有限公司 一种除法器和求商和余数的方法
CN106959840B (zh) * 2016-01-08 2019-06-28 瑞昱半导体股份有限公司 除法运算装置及其运算方法
CN107766031B (zh) * 2017-11-14 2020-06-19 京东方科技集团股份有限公司 分段式除法器、分段式除法运算方法、以及电子设备
CN108595146B (zh) * 2017-12-29 2020-10-27 珠海市杰理科技股份有限公司 除法运算方法、装置及设备
CN110147217A (zh) * 2018-02-12 2019-08-20 北京忆芯科技有限公司 除法器
CN108897523B (zh) * 2018-07-02 2021-01-26 京东方科技集团股份有限公司 一种除法器及其运算方法、电子设备
CN111399803B (zh) * 2019-01-03 2022-07-15 北京小米松果电子有限公司 除法运算方法、装置、存储介质及电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725974A (en) * 1984-02-07 1988-02-16 Nec Corporation Electronic circuit capable of accurately carrying out a succession of divisions in a pipeline fashion
JPH01286023A (ja) * 1988-05-12 1989-11-17 Fujitsu Ltd 除算命令処理装置
JPH07210371A (ja) * 1994-01-19 1995-08-11 Nec Eng Ltd パイプライン型除算処理装置
CN104375802A (zh) * 2014-09-23 2015-02-25 上海晟矽微电子股份有限公司 一种乘除法器及运算方法
CN113222132A (zh) * 2021-05-22 2021-08-06 上海阵量智能科技有限公司 乘法器、数据处理方法、芯片、计算机设备及存储介质
CN113254072A (zh) * 2021-05-27 2021-08-13 上海阵量智能科技有限公司 数据处理器、数据处理方法、芯片、计算机设备及介质

Also Published As

Publication number Publication date
CN113254072B (zh) 2023-04-07
CN113254072A (zh) 2021-08-13

Similar Documents

Publication Publication Date Title
US9384145B2 (en) Systems and methods for implementing dynamically configurable perfect hash tables
KR102581403B1 (ko) 공유 하드웨어 로직 유닛 및 그것의 다이 면적을 줄이는 방법
US20200218509A1 (en) Multiplication Circuit, System on Chip, and Electronic Device
US9495131B2 (en) Multi-input and binary reproducible, high bandwidth floating point adder in a collective network
US20190146756A1 (en) Segment divider, segment division operation method, and electronic device
KR102449169B1 (ko) 나눗셈 연산을 수행하는 장치, 그것을 포함하는 시스템 온 칩 및 그것의 방법
US11283464B2 (en) Compression and decompression engines and compressed domain processors
WO2022247193A1 (zh) 用于数据处理的装置、方法、芯片、计算机设备及介质
US11294634B2 (en) Float division by constant integer
JP2006172035A (ja) 除算・開平演算器
US10230376B2 (en) Apparatus and method for performing division
WO2024007506A1 (zh) 一种通用轻量哈希处理方法、系统及可储存介质
US10387492B2 (en) Information processing system, information processing method, and program
RU2559771C2 (ru) Устройство для основного деления модулярных чисел
CN112764713A (zh) 随机数的生成方法和装置
CN111526120B (zh) 一种多级流水线电路生成tcp校验和的方法
KR100901478B1 (ko) 나눗셈기의 평균값 출력 장치 및 출력 방법
US20230403028A1 (en) Parallelized decoding of variable-length prefix codes
US20080307032A1 (en) Divider Circuit
JP2005165502A (ja) Ｌｕｔ符号化方法及びｌｕｔ符号化装置並びにｌｕｔカスケード論理回路
RU2614932C1 (ru) Устройство для логарифмирования двоичных чисел
GB2590865A (en) Float division by constant integer with output subtraction
CN111147390A (zh) 负载分担求余的方法及装置
Schlage-Puchta Representation of numbers with negative digits and multiplication of small integers
Sandhu et al. Efficient Partial Product Generation using Radix4 & Radix8 for Multi-Modulus Multiplication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21942756

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21942756

Country of ref document: EP

Kind code of ref document: A1