WO2022246790A1 - 显示面板的侦测方法及显示面板 - Google Patents

显示面板的侦测方法及显示面板 Download PDF

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Publication number
WO2022246790A1
WO2022246790A1 PCT/CN2021/096718 CN2021096718W WO2022246790A1 WO 2022246790 A1 WO2022246790 A1 WO 2022246790A1 CN 2021096718 W CN2021096718 W CN 2021096718W WO 2022246790 A1 WO2022246790 A1 WO 2022246790A1
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Prior art keywords
sensing
sub
pixel
clock
signal
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PCT/CN2021/096718
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English (en)
French (fr)
Inventor
韦晓龙
杨飞
孟松
许静波
先建波
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/096718 priority Critical patent/WO2022246790A1/zh
Priority to CN202180001326.4A priority patent/CN115699144A/zh
Priority to US17/764,992 priority patent/US12118906B2/en
Publication of WO2022246790A1 publication Critical patent/WO2022246790A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • This article relates to but not limited to the field of display technology, especially a detection method of a display panel and a display panel.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a detection method of a display panel and the display panel.
  • an embodiment of the present disclosure provides a detection method of a display panel, including: detecting the electrical voltage of the driving transistor of the pixel circuit of the sub-pixel in the Xth row during the idle period between the Nth frame and the N+1th frame.
  • Feature parameters including: detecting the electrical voltage of the driving transistor of the pixel circuit of the sub-pixel in the Xth row during the idle period between the Nth frame and the N+1th frame.
  • X is a non-repetitive random number determined by traversing a first range, and the first range includes a positive integer not greater than R, where R is the total number of rows of sub-pixels of the display panel.
  • the value range of N is the first range.
  • the relationship between N and X in at least one detection period is determined by a Randperm function.
  • the random array is obtained by the Randperm function, and X is the Nth element value in the random array.
  • detecting the electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel in the X-th row includes: using random control The signal generates a sensing clock signal; the sensing clock signal, the sensing start signal and the enabling control signal are used by the sensing drive circuit to generate and provide Sensing control signal for the pixel circuit of the sub-pixel in row X.
  • the sensing clock signal, sensing start signal and enable control signal are pulse signals.
  • the pulse width of the sensing pulse of the sensing start signal is greater than the pulse width of the clock pulse of the sensing clock signal and not greater than twice the pulse width of the clock pulse, and the pulse width of the enabling control signal is greater than the sensing pulse. Measure the pulse width of the pulse.
  • the sensing start signal includes a sensing pulse, and at least R clock pulses are included between adjacent sensing pulses, where R is the total number of rows of sub-pixels of the display panel.
  • the sensing pulse provided by the sensing start signal in the Nth frame is shifted by the sensing driving circuit during the idle period between the Nth frame and the N+1th frame Output to the pixel circuit of the X-th row of sub-pixels.
  • the sensing clock signal provided to the sensing driving circuit at the Nth frame includes a first clock pulse group, the first clock pulse group includes X clock pulses, and the X clock pulses The starting moment of the first clock pulse in the pulses is no earlier than the starting moment of the sensing pulse in the sensing start signal provided to the sensing driving circuit in the Nth frame.
  • the detecting method further includes: after detecting the electrical characteristic parameters of the driving transistors of the pixel circuits of the sub-pixels in the X-th row, using the second clock pulse group of the sensing clock signal to The sensing driving circuit is reset; the second clock pulse group includes X1 clock pulses, and X1 is greater than R-X; R is the total number of rows of sub-pixels of the display panel.
  • the detection method further includes: using the sensing pulse provided by the sensing start signal in the N+1th frame and the sensing pulse provided by the sensing clock signal in the N+1th frame by the sensing drive circuit.
  • a clock pulse group and an enable control signal in the idle period between the N+1th frame and the N+2th frame, generate a sensing control signal provided to the pixel circuit of the sub-pixel in the Yth row; the sensing
  • the first clock pulse group provided by the clock signal at frame N+1 includes Y clock pulses; wherein, Y is a random positive integer, and Y is different from X.
  • the Y clock pulses and the X1 clock pulses are discontinuous.
  • the detecting method further includes: after detecting the electrical characteristic parameters of the driving transistors of the pixel circuits of the sub-pixels in the Y-th row, using the second clock pulse group of the sensing clock signal to The sensing driving circuit is reset, the second clock pulse group includes Y1 clock pulses, Y1 is greater than R-Y, and R is the number of rows of sub-pixels of the display panel.
  • detecting the electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel in the Xth row includes: in the Nth frame In the idle period between the N+1th and N+1th frames, the electrical characteristic parameters of the driving transistors of the pixel circuits of the b color subpixels in the Xth row of subpixels are detected, where b is a positive integer, and b is less than or equal to one The number of sub-pixels included in the pixel unit.
  • an embodiment of the present disclosure provides a display panel, including: a pixel array and a gate driver.
  • the pixel array includes a plurality of sub-pixels, at least one of which includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light.
  • the gate drive circuit is configured to provide a sensing control signal to the pixel circuit of the Xth row of sub-pixels through the sensing control line in the idle period between the Nth frame and the N+1th frame, so as to detect the The electrical characteristic parameters of the driving transistors of the pixel circuit of the X row of sub-pixels. Wherein, both N and X are positive integers, and X is a random number.
  • the display panel further includes: a timing controller.
  • the timing controller is configured to generate a sensing clock signal using a random control signal and provide the sensing clock signal to the gate driver.
  • the gate driver is configured to use the sensing clock signal, the sensing start signal and the enable control signal to generate and provide to the X-th row sub-frames in the idle period between the N-th frame and the N+1-th frame. Sensing control signal for the pixel circuit of the pixel.
  • the timing controller includes: a random signal generating circuit configured to generate the random control signal.
  • the gate driver includes: a sensing driving circuit
  • the sensing driving circuit includes: a plurality of cascaded shift register units and a plurality of logical AND gates.
  • the output end of the i-th shift register unit is connected to the input end of the i+1-th shift register unit, and the input end of the first shift register unit is connected to the sensing start signal line that provides the sensing start signal .
  • Clock terminals of the plurality of shift register units are connected to a sensing clock signal line that provides a sensing clock signal.
  • the input end of the i-th logical AND gate is connected to the output end of the ith-stage shift register unit and the enable control line that provides the enable control signal, and the output end of the i-th logical AND gate is connected to the sub-pixel in the i-th row.
  • the sensing control line of the pixel circuit is connected. Among them, i is a positive integer.
  • the pixel circuit includes: an input transistor, a driving transistor, a sensing transistor, and a first storage capacitor.
  • the control electrode of the input transistor is connected to the scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the control electrode of the driving transistor.
  • the first pole of the drive transistor is connected to the first power line, and the second pole is connected to the light emitting element.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor.
  • the control pole of the sensing transistor is connected to the sensing control line, the first pole is connected to the second pole of the driving transistor, and the second pole is connected to the sensing signal line.
  • FIG. 1 is a schematic diagram of a pixel circuit
  • FIG. 2 is a schematic diagram of horizontal dark lines generated by a display panel
  • FIG. 3 is a schematic structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a random array of at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a sensing driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a working sequence of a sensing driving circuit according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the means and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense unless otherwise specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes the situation that the constituent elements are connected together through an element having some kind of electrical effect.
  • the “element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • a transistor refers to an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source electrode or the drain electrode
  • the second pole can be A drain electrode or a source electrode
  • a gate electrode of a transistor is called a gate electrode.
  • parallel means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus may include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° to 100°, and therefore, an angle of 85° to 95° may be included.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • the pixel circuits of the sub-pixels in the display panel drive the light-emitting elements in the display panel to emit light, thereby realizing the display function.
  • the pixel circuit includes a driving transistor, and the driving transistor generates a driving current, and the driving current drives the light emitting element to emit light.
  • the driving transistor due to the limitation of the manufacturing process of the display panel, there are differences in the electrical characteristic parameters of the driving transistors included in the pixel circuits in the display panel, and this difference easily affects the brightness uniformity of the display panel.
  • an external compensation technique can be used to generate a corrected compensation data signal by detecting the electrical characteristic parameters (including, for example, threshold voltage and electron mobility) of the driving transistor in each pixel circuit, and then the compensation data The signal is input to the driving transistor to realize the compensation of the electrical characteristic parameters of the driving transistor, thereby improving the inconsistency of display brightness of the display panel caused by the different electrical characteristic parameters of the driving transistor in the pixel circuit.
  • electrical characteristic parameters including, for example, threshold voltage and electron mobility
  • FIG. 1 is a schematic diagram of a pixel circuit.
  • the pixel circuit may include: an input transistor T1, a driving transistor DTFT, a sensing transistor T2, and a first storage capacitor C1.
  • the control electrode of the input transistor T1 is connected to the scanning signal line GL
  • the first electrode of the input transistor T1 is connected to the data signal line DL
  • the second electrode of the input transistor T1 is connected to the control electrode of the driving transistor DTFT.
  • the first pole of the driving transistor DTFT is connected to the first power supply line ELVDD
  • the second pole of the driving transistor DTFT is connected to the first pole of the light emitting element OLED.
  • the second pole of the light emitting element OLED is connected to the second power line ELVSS.
  • the first electrode of the first storage capacitor C1 is connected to the control electrode of the driving transistor DTFT, and the second electrode of the first storage capacitor C1 is connected to the second electrode of the driving transistor DTFT.
  • the control electrode of the sensing transistor T2 is connected to the sensing control line SL, the first electrode of the sensing transistor T2 is connected to the second electrode of the driving transistor DTFT, and the second electrode of the sensing transistor T2 is connected to the sensing signal line RL.
  • the display panel is provided with a second storage capacitor C2 connected to the pixel circuit, a digital sampler ADC and a sampling switch SW.
  • the first electrode of the second storage capacitor C2 is connected to the sensing signal line RL, and the second electrode of the second storage capacitor C2 is connected to the ground signal line.
  • the sampling switch SW is configured to control the electrical connection between the digital sampler ADC and the sensing signal line RL.
  • the driving voltage applied to the control electrode of the driving transistor DTFT is Vg
  • the source voltage of the driving transistor DTFT is detected as the sensing voltage Vs
  • the driving voltage of the driving transistor DTFT can be calculated according to the driving voltage Vg and the sensing voltage Vs. Electron mobility K.
  • the process of compensating the electrical characteristic parameters of the driving transistor DTFT in the pixel circuit of the display panel may include the following process. Input the scanning signal through the scanning signal line GL to control the conduction of the input transistor T1, the data signal line DL writes the test data signal, the test data signal is transmitted to the control electrode of the driving transistor DTFT through the input transistor T1, and the control electrode G of the driving transistor DTFT The voltage becomes Vg, and the second electrode (for example, the source S) of the driving transistor DTFT has an initialization voltage V 0 .
  • the sensing transistor T2 is controlled to be turned on by the sensing control signal input from the sensing control line SL.
  • Vs ie, the sensing voltage
  • the threshold voltage Vth, electron mobility K and driving current I oled of the driving transistor DTFT satisfy the following formula:
  • C ox is the capacitance of the gate oxide layer
  • W/L is the width-to-length ratio of the channel region of the driving transistor DTFT
  • Vgs is the gate-source voltage of the driving transistor DTFT.
  • the voltage after threshold voltage compensation is used to charge the second storage capacitor C2 at a fixed time, and the obtained voltage value stored in the second storage capacitor C2 (that is, the driving The source potential of the transistor DTFT) is directly proportional to the electron mobility K, so the electron mobility K can be inversely deduced by using the source potential.
  • the compensated compensation data signal After obtaining the threshold voltage Vth and the electron mobility K of the driving transistor DTFT, the compensated compensation data signal can be obtained, and the compensation data signal can be written into the control electrode of the driving transistor DTFT to realize the compensation of the electrical characteristic parameters of the driving transistor DTFT.
  • the real-time detection method may include: in the idle phase (Blank) between the display phase (Active) of every two frames, providing the sensing control signal to one or more sensing control lines to complete the detection of one or more rows of sub-lines
  • the electron mobility K of the driving transistor DTFT of the pixel is detected, and the compensation data signal obtained by using the detected data is used in the display stage to complete the display.
  • the idle period is a time period outside the display screen of the display panel.
  • FIG. 2 is a schematic diagram of horizontal dark lines generated by a display panel. As shown in Figure 2, in the process of detecting the electrical characteristic parameters of the driving transistor of the display panel in real time, a period of detection is completed in order from the top to the bottom of the display panel, and a horizontal dark line L will appear on the display panel. Cycle through the display from top to bottom.
  • At least one embodiment of the present disclosure provides a detection method of a display panel, including: detecting the electrical characteristics of the driving transistor of the pixel circuit of the sub-pixel in the Xth row during the idle period between the Nth frame and the N+1th frame parameter.
  • N and X are positive integers
  • X is a random number.
  • the detection method of the display panel provided by this exemplary embodiment randomly detects the electrical characteristic parameters of the driving transistors of a row of sub-pixels of the display panel during the idle period between two adjacent frames. Using the random detection method of this example, it is impossible to artificially predict the position of the horizontal dark line generated by real-time detection, which makes it impossible for human eyes to detect, thereby improving user experience.
  • X is a non-repetitive random number determined by traversing a first range
  • the first range includes a positive integer not greater than R
  • R is the total number of rows of sub-pixels of the display panel.
  • the pixel circuits of the sub-pixels are detected in a randomly determined row detection sequence within a detection period.
  • a detection period may include a detection process for R rows of sub-pixels.
  • a pixel unit may include a sub-pixels (for example, include three-color sub-pixels of red, green, and blue, or include four-color sub-pixels of red, green, blue, and white), and a is a positive integer.
  • the pixel circuit of one color sub-pixel can be detected in one detection cycle.
  • the pixel circuit of the red sub-pixel in each row can be detected in accordance with a randomly determined row detection sequence ;
  • the pixel circuit of the green sub-pixel in each row can be detected according to the randomly determined row detection sequence;
  • the randomly determined row detection sequence can be The pixel circuits of the blue sub-pixels in each row are detected.
  • Subsequent detection periods may be cycled sequentially in the manner of the first detection period, the second detection period and the third detection period.
  • this embodiment does not limit it.
  • the pixel circuits of multiple color sub-pixels can be detected in one detection period; detection.
  • the electrical characteristic parameters of the driving transistors of the pixel circuits of at least two color sub-pixels in a random row may be detected.
  • the electrical characteristic parameters of the transistors of the pixel circuits of the red and green subpixels in the Xth row of subpixels can be detected.
  • the row detection sequence in each detection period may be the same, that is, after a random row detection sequence is determined in the first detection period, the subsequent detection periods may follow the established row detection sequence. Detection is performed in the determined line detection order.
  • the row detection sequences in different detection periods may be partly the same or completely different; for example, the row detection sequences of odd detection periods are the same, and the row detection sequences of even detection periods are the same;
  • the row detection sequences in the detection cycle can be different, and are determined randomly.
  • this embodiment does not limit it.
  • the value range of N is the first range.
  • the value range of N in the first detection period, is the same as the value range of X. However, this embodiment does not limit it.
  • the value range of N in the first detection period, may be different from the value range of X. For example, X may be determined by traversing the first range, and the value range of N may be greater than the first range.
  • X can be a non-repeating random number determined by traversing 1 to 2160
  • N can be 2160 non-repeating numbers selected from 1 to 2200.
  • the electrical characteristic parameters of the driving transistors of the pixel circuits of a row of sub-pixels may be detected during the idle period between two adjacent frames, or may not be detected. In some examples, one detection period requires at least R frames to complete.
  • the relationship between N and X in at least one detection period may be determined by a Randperm function.
  • a one-dimensional array may be generated by the Randperm function
  • X may be an element value in the one-dimensional array
  • N may be an address indicating an element value in the one-dimensional value.
  • X can be the value of the Nth element in the random array.
  • N may be an element value in the one-dimensional array
  • X may be an address indicating the element value in the one-dimensional array.
  • N can be the value of the Xth element in the random array.
  • the random array can be obtained by using the Randperm function, so as to determine the random relationship between the display frame and the detection line.
  • the relationship between N and X in each detection period can be determined by the Randperm function.
  • the value range of X may be the first range
  • the value range of N may vary with the detection cycle.
  • R is 2160
  • the value range of N can be the first range (ie 1 to 2160)
  • the value range of N can be 2161 to 4320, and so on.
  • this embodiment does not limit it.
  • the value range of N can be updated according to the determined sequence of row detection to determine the random relationship between N and X.
  • the pixel circuit of the sub-pixel in the xth row is detected, then in the cth detection cycle, the k During the idle period between row +R*(c-1) and row k+R*(c-1)+1, the pixel circuit of the sub-pixel in row X is detected, and k and c are both positive integers.
  • the electrical characteristic parameters of the driving transistor of the pixel circuit of the subpixel of one color in the Xth row of subpixels are detected.
  • the electrical characteristic parameter of the driving transistor of the pixel circuit of the sub-pixel of another color in the sub-pixel in the row X is detected.
  • the driving transistor of the pixel circuit of the red sub-pixel in the X-th row of sub-pixels is detected Electrical characteristic parameters; during the idle period between the N+1 frame and the N+2 frame, detect the electrical characteristic parameters of the driving transistor of the pixel circuit of the green sub-pixel in the X-th row of sub-pixels; at the N+2 During the idle period between the frame and the N+3th frame, the electrical characteristic parameter of the driving transistor of the pixel circuit of the blue sub-pixel in the X-th row of sub-pixels is detected.
  • a detection cycle of this example (that is, to complete R row detection) requires at least R*a
  • this embodiment does not limit it.
  • detecting the electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel in the Xth row includes: using a random control signal to generate Sensing clock signal; using the sensing clock signal, sensing start signal and enabling control signal through the sensing drive circuit, in the idle period between the Nth frame and the N+1th frame, generate and provide to the Xth row The sensing control signal of the pixel circuit of the sub-pixel.
  • the sensing clock signal, the sensing start signal, and the enable control signal are pulse signals.
  • the pulse width of the sensing pulse of the sensing start signal is greater than the pulse width of the clock pulse of the sensing clock signal and not greater than twice the pulse width of the clock pulse, and the pulse width of the enabling control signal is greater than the pulse width of the sensing pulse. width.
  • the pulse width is the pulse width, that is, the duration of the high level.
  • the sensing start signal includes a sensing pulse, and at least R clock pulses are included between adjacent sensing pulses, where R is the total number of rows of sub-pixels of the display panel. This example can ensure that there is enough time to reset the sensing driving circuit after the random row is detected in the idle phase.
  • the sensing pulse provided by the sensing start signal in the Nth frame is shifted and output to the Xth frame through the sensing driving circuit during the idle period between the Nth frame and the N+1th frame A pixel circuit for a row of sub-pixels.
  • the sensing clock signal provided to the sensing driving circuit at the Nth frame includes a first clock pulse group, the first clock pulse group includes X clock pulses, the first of the X clock pulses
  • the starting moment of the clock pulse is no earlier than the starting moment of the sensing pulse in the sensing start signal provided to the sensing driving circuit in the Nth frame.
  • the start time of the first clock pulse of the first clock pulse group provided to the sensing driving circuit in the Nth frame is substantially the same as the start time of the sensing pulse.
  • X clock pulses are used to shift the sensing pulse to control the sub-pixels in row X to realize detection.
  • the detection method of this embodiment further includes: after detecting the electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel in the X-th row, using the second clock pulse group of the sensing clock signal Reset the sensing driving circuit.
  • the second clock pulse group includes X1 clock pulses, where X1 is greater than R-X; R is the total number of rows of sub-pixels of the display panel.
  • the sensing pulse is shifted by using the second clock pulse group, so as to reset the sensing driving circuit.
  • the detection method of this embodiment further includes: using the sensing pulse provided by the sensing start signal at frame N+1 through the sensing drive circuit, and the sensing clock signal at frame N+1
  • the first clock pulse group provided by the frame and the enable control signal in the idle period between the N+1 frame and the N+2 frame, generate a sensing control signal provided to the pixel circuit of the Y-th row of sub-pixels ;
  • the first clock pulse group provided by the sensing clock signal in the N+1th frame includes Y clock pulses.
  • Y is a random positive integer, and Y is different from X.
  • the Y clock pulses and the X1 clock pulses are discontinuous.
  • the detection method of this embodiment further includes: after detecting the electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel in the Y-th row, using the second clock signal of the sensing clock signal
  • the pulse group resets the sensing driving circuit
  • the second clock pulse group includes Y1 clock pulses, Y1 is greater than R-Y, and R is the number of rows of sub-pixels of the display panel.
  • FIG. 3 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display panel of this exemplary embodiment includes: a pixel array 12 and a panel driver.
  • the panel driver is configured to drive the pixel array 12 .
  • the panel driver may include: a timing controller 10, a data driver 20, a gate driver 30, and a memory 40 for storing compensation data.
  • the pixel array 12 may include: a plurality of scanning signal lines (for example, GL1 to GLm), a plurality of data signal lines (for example, DL1 to DLn), a plurality of sensing control lines (for example, SL1 to SLm), a plurality of sensing signal lines (not shown), and a plurality of sub-pixels Pxij.
  • m and n are both positive integers.
  • a plurality of scanning signal lines GL1 to GLm and a plurality of sensing control lines SL1 to SLm are formed in a first direction (for example, a horizontal direction) of the display panel, and a plurality of data signal lines DL1 to DLn and A plurality of sensing signal lines may be formed in a second direction (eg, a vertical direction) of the display panel.
  • the first direction and the second direction intersect, for example, the first direction is perpendicular to the second direction.
  • the plurality of data signal lines and the plurality of sensing signal lines are configured to intersect the plurality of scanning signal lines and the plurality of sensing control lines.
  • the timing controller 10 may provide the data driver 20 with grayscale values and control signals suitable for specifications of the data driver.
  • the data driver 20 may generate data voltages to be supplied to the data signal lines DL1 to DLn using the gray values and control signals received from the timing controller 10 .
  • the data driver 20 may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines DL1 to DLn in units of sub-pixel rows.
  • the timing controller 10 may provide a clock signal, a scan start signal, a sensing start signal, etc. suitable for specifications of the gate driver to the gate driver 30 .
  • the gate driver 30 may generate scan signals to be supplied to the scan signal lines GL1 to GLm and to the sensing control lines SL1 to SLm by receiving a clock signal, a scan start signal, a sense start signal, etc. from the timing controller 10 . sensing control signal.
  • the gate driver 30 may include: a scanning driving circuit and a sensing driving circuit. The scan driving circuit may sequentially supply scan signals having turn-on level pulses to the scan signal lines GL1 to GLm.
  • the sensing driving circuit may sequentially supply sensing control signals having turn-on level pulses to the sensing control lines SL1 to SLm.
  • the scan driving circuit can be constructed in the form of a shift register, and can be generated in such a way that a scan start signal provided in the form of a conduction level pulse is sequentially transmitted to a next-stage circuit under the control of a scan clock signal scan signal.
  • the sensing driving circuit can be constructed in the form of a shift register, and can be generated in a manner of sequentially transmitting sensing control signals provided in the form of on-level pulses to the next-stage circuit under the control of the sensing clock signal sense control signal.
  • the data driver 20 may acquire sensing data through the sensing signal line, and transmit the sensing data to the timing controller 10 .
  • the timing controller 10 can determine the compensation data of the electrical characteristic parameters of the driving transistor according to the sensing data, and store the compensation data in the memory 40 .
  • the memory 40 may store compensation data of electrical characteristic parameters of the driving transistors included in the display panel, and may also store optical compensation data of light emitting elements of the display panel. However, this embodiment does not limit it.
  • the scanning driving circuit and the sensing driving circuit included in the gate driver 30 may be located on opposite sides of the pixel array 12 (eg, left and right sides of the pixel array).
  • this embodiment does not limit it.
  • gate drivers are provided on opposite sides of the pixel array to realize bilateral driving of the sub-pixels.
  • the gate driver 30 may be formed using an integrated circuit, or may be directly formed on the substrate of the display panel during the process of manufacturing the pixel circuit of the sub-pixel. However, this embodiment does not limit it.
  • each sub-pixel PXij in the pixel array 12 may be connected to a corresponding data signal line, scan signal line, sensing control line and sensing signal line, and i and j may be natural numbers.
  • the sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.
  • FIG. 4 is a schematic plan view of a display panel according to at least one embodiment of the present disclosure.
  • the display area of the display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a sub-pixel that emits light of a second color.
  • the second sub-pixel P2 for the light and the third sub-pixel P3 for emitting the light of the third color.
  • Each of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 includes a pixel circuit and a light emitting element.
  • the pixel circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be respectively connected to the scanning signal line and the data signal line, and the pixel circuits are configured to receive the data signal line under the control of the scanning signal line.
  • the transmitted data voltage outputs a corresponding driving current to the light emitting element.
  • the light-emitting elements in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel circuits of the sub-pixels, and the light-emitting elements are configured to emit corresponding brightness in response to the driving current output by the pixel circuits of the sub-pixels. of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, blue sub-pixels
  • the pixel and the white sub-pixel are not limited in this disclosure.
  • the shape of a sub-pixel in a pixel unit may be a rectangle, a rhombus, a pentagon or a hexagon.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely. Disclosure is not limited here.
  • a sub-pixel includes a pixel circuit and a light emitting element.
  • the pixel circuit may be the pixel circuit shown in FIG. 1 .
  • the scan transistor T1 , the driving transistor DTFT and the sensing transistor T2 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active layer of the oxide thin film transistor is made of oxide (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • low temperature polysilicon thin film transistors and oxide thin film transistors can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be used , can achieve high resolution (Pixel Per Inch, PPI for short), low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the light-emitting element may be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • OLED organic light-emitting diode
  • this embodiment does not limit it.
  • the timing controller 10 may generate a clock signal provided to the gate driver 30 according to the timing control signal.
  • the timing control signal includes a random control signal, and the timing controller 10 can use the random control signal to generate a sensing clock signal provided to the sensing driving circuit of the gate driver 30 .
  • the random control signal can be determined by a random array generated by the Randperm function. However, this embodiment does not limit it.
  • random arrays can be generated using the Randperm function in the following manner.
  • ran_ge randperm(2160,2160);
  • fid fopen('random_sense_4k.coe','wt');
  • the above program can be used to generate a random array using the Randperm function, and save the random array in a configuration file for subsequent use.
  • FIG. 5 is a schematic diagram of a random array according to at least one embodiment of the present disclosure.
  • the abscissa in FIG. 5 represents the frame number, and the ordinate represents the number of sub-pixel rows to be detected.
  • the number of sub-pixel rows of the display panel is 2160.
  • the electrical characteristic parameters of the driving transistors of the pixel circuits of the 2160 rows of sub-pixels of the display panel are detected in real time.
  • the data of the random array generated in this example is random and traverses 1 to 2160 to meet the random detection of a detection cycle. In this example, a period of random detection can be completed in the 2160-frame display stage.
  • the random array shown in FIG. 5 it can be determined which row of sub-pixel driving circuit's electrical characteristic parameters are to be detected in the idle period after which frame. That is, the random detection order of the sub-pixel rows of the display panel can be determined. For example, in the idle period between the first frame and the second frame, the electrical characteristic parameter of the driving transistor of the pixel circuit of the sub-pixel in the 100th row can be detected, and in the idle period between the second frame and the third frame, it can be Detecting the electrical characteristic parameter of the driving transistor of the pixel circuit of the sub-pixel in the 50th row.
  • this embodiment does not limit it.
  • one period of random detection can be completed during the display period of more than 2160 frames.
  • 2160 frames may be selected from the display period of 2200 frames, and detection may be performed in random order during the idle period between the selected 2160 frames and adjacent frames. For example, in the idle period between the first frame and the second frame, the electrical characteristic parameter of the driving transistor of the pixel circuit of the sub-pixel in the 100th row can be detected, and in the idle period between the second frame and the third frame, it can be No detection is performed. In some examples, during detection of a row of sub-pixels, all sub-pixels of the row may be detected.
  • the idle period is relatively short, it is also possible to detect only a certain sub-pixel or a certain two sub-pixels of a row of pixels, for example, only detect the electrical characteristic parameters of the driving transistor of the pixel circuit of the red sub-pixel, or detect The electrical characteristic parameters of the driving transistors of the pixel circuits of the red sub-pixel and the green sub-pixel are measured.
  • the timing controller 10 may include a random signal generating circuit 101, through which a random control signal is generated, and then the random control signal is used to generate a sensing clock signal provided to the sensing driving circuit.
  • a random signal generating circuit 101 through which a random control signal is generated, and then the random control signal is used to generate a sensing clock signal provided to the sensing driving circuit.
  • this embodiment does not limit it.
  • the timing controller 10 may receive a random control signal generated by an external circuit.
  • FIG. 6 is a schematic structural diagram of a sensing driving circuit according to at least one embodiment of the present disclosure.
  • the sensing driving circuit of this exemplary embodiment is used to generate sensing control signals provided to the sensing control lines.
  • the sensing driving circuit includes: multiple cascaded shift register units 301 and multiple logical AND gates 302 . Multiple logical AND gates 302 are connected to multiple shift register units 301 in one-to-one correspondence.
  • the output terminal Q(i) of the i-th stage shift register unit is connected to the input terminal D(i+1) of the i+1-th stage shift register unit.
  • the clock terminals of the plurality of shift register units 301 receive the sensing clock signal provided by the timing controller 10 through the sensing clock signal line CLK, for example.
  • the input terminal of the shift register unit of the first stage receives a sensing start signal from the timing controller 10, for example, through the sensing start signal line 10.
  • the sensing driving circuit may sequentially shift the sensing start signal by using a plurality of cascaded shift register units 301 according to the sensing clock signal.
  • the timing controller 10 also provides an enable control signal to the sensing driving circuit through the enable control signal line OE.
  • the logical AND gate 302 connected to the output terminal of the i-th shift register unit can provide the sensing control signal obtained after the output signal of the i-th shift register unit and the enable control signal to the i-th row
  • the pixels are connected to the sensing control line SLi.
  • i is a positive integer.
  • the structure of the scanning driving circuit is similar to that of the sensing driving circuit, so details will not be repeated here.
  • CLK, IO and OE represent signal lines and may also represent signals provided by corresponding signal lines.
  • FIG. 7 is a working timing diagram of the sensing driving circuit according to at least one embodiment of the present disclosure.
  • the enable control signal OE is a pulse signal
  • the high level pulse of the enable control signal OE is located in the idle period between adjacent frames
  • the enable control signal OE is Both OE are at low potential.
  • the sensing start signal 10 is a pulse signal, including a sensing pulse, which can be provided to the sensing driving circuit in the frame display phase, so that the sensing pulse is shifted and output to the random rows in the idle phase by the sensing driving circuit.
  • the sensing clock signal CLK is a pulse signal.
  • the interval PI between two adjacent sensing pulses includes at least R clock pulses.
  • R represents the total number of rows of sub-pixels of the display panel. For example, R is 2160 rows.
  • the pulse width of the sensing pulse is greater than and not greater than twice the pulse width of the clock pulse.
  • the pulse width of the sensing pulse may be approximately equal to 1.5 times the pulse width of the clock pulse.
  • the pulse width of the high level pulse of the enabling control signal is greater than the pulse width of the sensing pulse. In this example, the pulse width is the pulse width, which is the duration of the high level.
  • the timing controller may generate a sensing clock signal including a first clock pulse group according to a random control signal, and the first clock pulse group may include X consecutive of clock pulses.
  • the sensing drive circuit can control the X-stage shift register unit to output a high level according to the sensing pulse provided by the sensing initial signal IO and X consecutive clock pulses, in the idle phase of the Nth frame and the N+1th frame , combined with the high-level pulse of the enable control signal OE, through a logic AND gate, a high-potential sensing control signal can be provided to the sensing control line SLx connected to the sub-pixels in the X-th row to turn on the sub-pixels in the X-th row
  • the sensing transistor in the pixel circuit detects the electrical characteristic parameter of the driving transistor in the pixel circuit.
  • the start time of the first clock pulse of the X clock pulses is no earlier than the start time of the sense pulse in the sense start signal.
  • the start moment of the first clock pulse in the X clock pulses is the same as the start moment of the sensing pulse in the sensing start signal.
  • X can be a positive integer.
  • the timing controller may generate the sensing clock signal including the second clock pulse group according to the random control signal.
  • the second clock pulse group may include X1 consecutive clock pulses.
  • the sensing driving circuit is reset with X1 consecutive clock pulses. After the detection of the electrical characteristic parameters of the driving transistor of the sub-pixel in the X-th row is completed, X1 consecutive clock pulses are used to shift the sensing pulse, so that multiple output signals of the sensing driving circuit are all at low level , that is, the driving transistors of any row of sub-pixels are not detected.
  • X1 may be greater than R-X. Wherein, X1 is a positive integer.
  • the X1 consecutive clock pulses may be within the interval PI between the sensing pulse of the Nth frame and the sensing pulse of the N+1th frame, and end at the high level pulse of the enable control signal OE available afterwards.
  • the X1 consecutive clock pulses may be provided in the N+1th frame, or after the end of the high-level pulse of the enable control signal OE in the idle period between the Nth frame and the N+1th frame
  • the sensing pulse of the N+1th frame is provided before it is provided.
  • this embodiment does not limit it.
  • the timing controller may generate a sensing clock signal including a first clock pulse group according to a random control signal, and the first clock pulse group may include Y consecutive clock pulses.
  • the X1 consecutive clock pulses and the Y consecutive clock pulses may not be consecutive. In this embodiment, there is no limitation on the interval between Y consecutive clock pulses and X1 consecutive clock pulses.
  • the sensing drive circuit can control the Y-th stage shift register unit to output a high level according to the sensing pulse of the sensing initial signal IO and Y consecutive clock pulses, and the N+1th frame and the N+2th frame In the idle phase, combined with the high level of the enable control signal OE, a high potential sensing control signal can be provided to the sensing control line SLy connected to the sub-pixels in the Y-th row through a logic AND gate, so as to turn on the sub-pixels in the Y-th row
  • the sensing transistor in the pixel circuit detects the electrical characteristic parameter of the driving transistor in the pixel circuit.
  • Y is a random positive integer
  • Y is different from X.
  • X can be the value of the Nth element in the random array
  • Y can be the value of the N+1th element in the random array.
  • the timing controller in the N+2th frame, the timing controller generates a sensing clock signal including a second clock pulse group according to the random control signal, and the second clock pulse group may include Y1 continuous clock pulses.
  • the sensing driving circuit is reset with Y1 consecutive clock pulses. After the detection of the electrical characteristic parameters of the driving transistor of the sub-pixel in the Yth row is completed, Y1 consecutive clock pulses are used to shift the sensing pulse, so that the multiple output signals of the sensing driving circuit are all at low level , that is, the driving transistors of any row of sub-pixels are not detected.
  • Y1 may be greater than R-Y. Wherein, Y1 is a positive integer.
  • the Y1 consecutive clock pulses may be within the interval between the sensing pulse of the N+1th frame and the sensing pulse of the N+2th frame, and at the high level pulse of the enable control signal OE Provided after completion.
  • Y1 consecutive clock pulses may be provided in frame N+2, or after the high-level pulse of the enable control signal OE in the idle period between frame N+1 and frame N+2 ends and provided before the sensing pulse of the N+2th frame is provided.
  • this embodiment does not limit it.
  • the sensing control signal generated by the sensing driving circuit in an idle period may be provided to the pixel circuits of a randomly determined row of sub-pixels through the sensing control line.
  • the pixel circuits of the red sub-pixels in the row are provided with test data signals through the data signal lines, so as to detect the electrical characteristic parameters of the driving transistors of the red sub-pixels in the row.
  • this embodiment does not limit it.
  • the driving transistors of the R rows of sub-pixels of the display panel can be detected sequentially, and the detection sequence is randomly determined, so as to complete a detection period.
  • the random detection sequence determined in this detection cycle can be used, or a random detection sequence can be regenerated. In this way, the viewer cannot pre-perceive the position of the dark horizontal line generated by the real-time detection, thereby improving user experience.
  • At least one embodiment of the present disclosure further provides a display panel, including: a pixel array and a gate driver.
  • the pixel array includes a plurality of sub-pixels, and at least one sub-pixel includes a light emitting element and a pixel circuit for driving the light emitting element to emit light.
  • the gate drive circuit is configured to provide a sensing control signal to the pixel circuit of the X-th row of sub-pixels through the sensing control line to detect the X-th row during the idle period between the Nth frame and the N+1th frame Electrical characteristic parameters of the driving transistor of the pixel circuit of the sub-pixel.
  • X is a random number, and both N and X are positive integers.
  • the display panel of this embodiment further includes: a timing controller.
  • the timing controller is configured to generate a sensing clock signal using the random control signal, and provide the sensing clock signal to the gate driver.
  • the gate driver is configured to use the sensing clock signal, the sensing start signal, and the enable control signal to generate a pixel circuit provided to the sub-pixels of the X-th row in an idle period between the N-th frame and the N+1-th frame sensing control signal.
  • the timing controller includes: a random signal generating circuit configured to generate a random control signal.
  • the gate driver includes: a sensing driving circuit.
  • the sensing driving circuit includes: multiple cascaded shift register units and multiple logical AND gates.
  • the output end of the i-th shift register unit is connected to the input end of the i+1-th shift register unit, and the input end of the first shift register unit is connected to the sensing start signal line that provides the sensing start signal .
  • Clock terminals of the plurality of shift register units are connected to a sensing clock signal line that provides a sensing clock signal.
  • the input end of the i-th logical AND gate is connected to the output end of the i-th stage shift register unit and the enable control line that provides the enable control signal, and the output end of the i-th logical AND gate is connected to the i-th row of sub-pixels
  • the sensing control line of the pixel circuit is connected.
  • i is a positive integer.
  • the pixel circuit includes: an input transistor, a driving transistor, a sensing transistor, and a first storage capacitor.
  • the control electrode of the input transistor is connected to the scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the control electrode of the driving transistor.
  • the first pole of the driving transistor is connected to the first power supply line, and the second pole is connected to the light emitting element.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor.
  • the control pole of the sensing transistor is connected to the sensing control line, the first pole is connected to the second pole of the driving transistor, and the second pole is connected to the sensing signal line.

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Abstract

一种显示面板的侦测方法，包括：在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数。其中，X为随机数，且N和X均为正整数。

Description

显示面板的侦测方法及显示面板 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板的侦测方法及显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diode，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板的侦测方法及显示面板。
一方面，本公开实施例提供一种显示面板的侦测方法，包括：在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数。其中，N和X均为正整数，且X为随机数。
在一些示例性实施方式中，X为通过遍历第一范围确定的不重复随机数，所述第一范围包括不大于R的正整数，R为所述显示面板的子像素的总行数。
在一些示例性实施方式中，在第一个侦测周期，N的取值范围为第一范围。
在一些示例性实施方式中，至少一个侦测周期内的N和X的关系通过Randperm函数确定。
在一些示例性实施方式中，通过Randperm函数得到随机数组，X为随 机数组中的第N个元素值。
在一些示例性实施方式中，所述在第N帧和第N+1帧之间的空闲阶段内，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数，包括：利用随机控制信号产生感测时钟信号；通过感测驱动电路利用所述感测时钟信号、感测起始信号和使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
在一些示例性实施方式中，所述感测时钟信号、感测起始信号和使能控制信号为脉冲信号。所述感测起始信号的感测脉冲的脉宽大于感测时钟信号的时钟脉冲的脉宽且不大于所述时钟脉冲的脉宽的两倍，所述使能控制信号的脉宽大于感测脉冲的脉宽。
在一些示例性实施方式中，所述感测起始信号包括感测脉冲，且相邻感测脉冲之间至少包括R个时钟脉冲，R为所述显示面板的子像素的总行数。
在一些示例性实施方式中，通过所述感测驱动电路在第N帧和第N+1帧之间的空闲阶段，将所述感测起始信号在第N帧提供的感测脉冲移位输出给第X行子像素的像素电路。
在一些示例性实施方式中，在第N帧提供给感测驱动电路的所述感测时钟信号包括第一时钟脉冲群，所述第一时钟脉冲群包括X个时钟脉冲，所述X个时钟脉冲中的第一个时钟脉冲的起始时刻不早于在第N帧提供给感测驱动电路的所述感测起始信号中的感测脉冲的起始时刻。
在一些示例性实施方式中，侦测方法还包括：在完成侦测第X行子像素的像素电路的驱动晶体管的电学特性参数之后，利用所述感测时钟信号的第二时钟脉冲群对所述感测驱动电路进行复位；所述第二时钟脉冲群包括X1个时钟脉冲，X1大于R-X；R为所述显示面板的子像素的总行数。
在一些示例性实施方式中，侦测方法还包括：通过感测驱动电路利用感测起始信号在第N+1帧提供的感测脉冲、感测时钟信号在第N+1帧提供的第一时钟脉冲群、以及使能控制信号，在第N+1帧和第N+2帧之间的空闲阶段内，产生提供给第Y行子像素的像素电路的感测控制信号；所述感测时钟信号在第N+1帧提供的第一时钟脉冲群包括Y个时钟脉冲；其中，Y为随机的正整数，且Y不同于X。
在一些示例性实施方式中，Y个时钟脉冲和X1个时钟脉冲不连续。
在一些示例性实施方式中，侦测方法还包括：在完成侦测第Y行子像素的像素电路的驱动晶体管的电学特性参数之后，利用所述感测时钟信号的第二时钟脉冲群对所述感测驱动电路进行复位，所述第二时钟脉冲群包括Y1个时钟脉冲，Y1大于R-Y，R为所述显示面板的子像素的行数。
在一些示例性实施方式中，所述在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数，包括：在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素中的b种颜色子像素的像素电路的驱动晶体管的电学特性参数，其中，b为正整数，且b小于或等于一个像素单元包括的子像素的个数。
另一方面，本公开实施例提供一种显示面板，包括：像素阵列以及栅极驱动器。所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动发光元件发光的像素电路。所述栅极驱动电路，配置为在第N帧和第N+1帧之间的空闲阶段内，通过感测控制线向第X行子像素的像素电路提供感测控制信号，以侦测第X行子像素的像素电路的驱动晶体管的电学特性参数。其中，N和X均为正整数，且X为随机数。
在一些示例性实施方式中，显示面板还包括：时序控制器。所述时序控制器配置为利用随机控制信号产生感测时钟信号，并将感测时钟信号提供给所述栅极驱动器。所述栅极驱动器配置为利用所述感测时钟信号、感测起始信号和使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
在一些示例性实施方式中，所述时序控制器包括：随机信号生成电路，配置为生成所述随机控制信号。
在一些示例性实施方式中，所述栅极驱动器包括：感测驱动电路，所述感测驱动电路包括：多个级联的移位寄存器单元以及多个逻辑与门。第i级移位寄存器单元的输出端与第i+1级移位寄存器单元的输入端连接，第一极移位寄存器单元的输入端与提供感测起始信号的感测起始信号线连接。多个移位寄存器单元的时钟端与提供感测时钟信号的感测时钟信号线连接。第i个逻辑与门的输入端与第i级移位寄存器单元的输出端和提供使能控制信号 的使能控制线连接，第i个逻辑与门的输出端与连接第i行子像素的像素电路的感测控制线连接。其中，i为正整数。
在一些示例性实施方式中，所述像素电路包括：输入晶体管、驱动晶体管、感测晶体管、以及第一存储电容。所述输入晶体管的控制极与扫描信号线连接，第一极与数据信号线连接，第二极与驱动晶体管的控制极连接。所述驱动晶体管的第一极与第一电源线连接，第二极与发光元件连接。所述第一存储电容的第一电极与驱动晶体管的控制极连接，第二电极与驱动晶体管的第二极连接。所述感测晶体管的控制极与感测控制线连接，第一极与驱动晶体管的第二极连接，第二极与感测信号线连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种像素电路的示意图；
图2为显示面板产生水平暗线的示意图；
图3为本公开至少一实施例的显示面板的结构示意图；
图4为本公开至少一实施例的显示面板的平面结构示意图；
图5为本公开至少一实施例的随机数组的示意图；
图6为本公开至少一实施例的感测驱动电路的结构示意图；
图7为本公开至少一实施例的感测驱动电路的工作时序示意图。
具体实施方式
下文将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实， 就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，晶体管是指至少包括栅电极(栅极)、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电 极(源电极端子、源区域或源极)之间具有沟道区，并且电流能够流过漏电极、沟道区以及源电极。在本公开中，沟道区是指电流主要流过的区域。
在本公开中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源电极或者漏电极，第二极可以为漏电极或源电极，另外，将晶体管的栅电极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
以OLED显示面板为例，OLED显示面板工作时，由显示面板中的子像素的像素电路驱动显示面板中的发光元件发光，从而实现显示功能。一般而言，像素电路包括驱动晶体管，由驱动晶体管产生驱动电流，驱动电流驱动发光元件发光。然而，由于显示面板在制作过程中受到制备工艺的限制，使得显示面板中的像素电路包括的驱动晶体管的电学特性参数存在差异，而这种差异容易影响显示面板的亮度均一性。
在一些示例中，可以采用外部补偿技术，通过侦测每个像素电路中的驱动晶体管的电学特性参数(例如包括：阈值电压和电子迁移率)，产生校正后的补偿数据信号，然后将补偿数据信号输入至驱动晶体管，实现对驱动晶体管的电学特性参数进行补偿，从而改善由于像素电路中的驱动晶体管的电学特性参数不同导致的显示面板显示亮度不一致情况。
图1为一种像素电路的示意图。如图1所示，像素电路可以包括：输入晶体管T1、驱动晶体管DTFT、感测晶体管T2、以及第一存储电容C1。输 入晶体管T1的控制极与扫描信号线GL连接，输入晶体管T1的第一极与数据信号线DL连接，输入晶体管T1的第二极与驱动晶体管DTFT的控制极连接。驱动晶体管DTFT的第一极与第一电源线ELVDD连接，驱动晶体管DTFT的第二极与发光元件OLED的第一极连接。发光元件OLED的第二极与第二电源线ELVSS连接。第一存储电容C1的第一电极与驱动晶体管DTFT的控制极连接，第一存储电容C1的第二电极与驱动晶体管DTFT的第二极连接。感测晶体管T2的控制极与感测控制线SL连接，感测晶体管T2的第一极与驱动晶体管DTFT的第二极连接，感测晶体管T2的第二极与感测信号线RL连接。如图1所示，显示面板设置有与像素电路连接的第二存储电容C2、数字采样器ADC和采样开关SW。其中，第二存储电容C2的第一电极与感测信号线RL连接，第二存储电容C2的第二电极与接地信号线连接。采样开关SW配置为控制数字采样器ADC和感测信号线RL之间的电连接。
在一些示例中，当加载在驱动晶体管DTFT的控制极的驱动电压为Vg，侦测驱动晶体管DTFT的源极电压作为感测电压Vs，根据驱动电压Vg与感测电压Vs可以计算驱动晶体管DTFT的电子迁移率K。
在一些示例中，基于图1所示的像素电路，对显示面板的像素电路中的驱动晶体管DTFT进行电学特性参数的补偿过程可以包括以下过程。通过扫描信号线GL输入扫描信号控制输入晶体管T1导通，数据信号线DL写入测试数据信号，测试数据信号经输入晶体管T1传输至驱动晶体管DTFT的控制极，将驱动晶体管DTFT的控制极G的电压变为Vg，驱动晶体管DTFT的第二极(例如源极S)具有初始化电压V 0。通过由感测控制线SL输入的感测控制信号控制感测晶体管T2导通，当驱动晶体管DTFT的控制极和源极的电压差Vgs大于驱动晶体管DTFT的阈值电压时，驱动晶体管DTFT导通，产生驱动电流I oled，驱动电流I oled通过感测晶体管T2为第二存储电容C2充电，且随着充电时长的增加，驱动晶体管DTFT的源极电位不断升高，直至驱动晶体管DTFT处于截止状态，驱动晶体管DTFT的源极电位不再升高，停止对第二存储电容C2充电。此时，通过感测信号线RL感测驱动晶体管DTFT的源极电压Vs(即感测电压)，可得到驱动晶体管DTFT的阈值电压Vth＝Vg-Vs。
驱动晶体管DTFT的阈值电压Vth、电子迁移率K和驱动电流I oled满足以下式子：
Figure PCTCN2021096718-appb-000001
其中，C ox为栅氧化层电容，W/L为驱动晶体管DTFT的沟道区的宽长比，Vgs为驱动晶体管DTFT的栅源电压。
由上式可见，驱动晶体管DTFT的电子迁移率K和阈值电压Vth对驱动电流I oled具有一定影响。
基于上述式子，在对驱动晶体管DTFT进行阈值电压补偿后，使用阈值电压补偿后的电压在固定时间对第二存储电容C2进行充电，得到的第二存储电容C2中存储的电压值(即驱动晶体管DTFT的源极电位)与电子迁移率K成正比关系，从而利用该源极电位可以反推出电子迁移率K。
在得到驱动晶体管DTFT的阈值电压Vth和电子迁移率K后，可以得到补偿后的补偿数据信号，将补偿数据信号写入驱动晶体管DTFT的控制极，可以实现补偿驱动晶体管DTFT的电学特性参数。
在一些示例中，由于在显示过程中驱动晶体管DTFT的电子迁移率容易受到温度等因素的影响，因此通过实时侦测方式来实现更好的显示效果。其中，实时侦测方式可以包括：在每两帧显示阶段(Active)之间的空闲阶段(Blank)，将感测控制信号提供给一条或多条感测控制线，完成对一行或多行子像素的驱动晶体管DTFT的电子迁移率K的侦测，在显示阶段使用侦测到的数据得到的补偿数据信号完成显示。其中，空闲阶段为显示面板显示画面之外的时段。由于空闲阶段的实时侦测过程中，被侦测行的发光元件不再点亮发光，所以被侦测行的点亮发光时间少于非侦测行(即使对被侦测行的显示亮度进行补偿，也无法完全消除亮度差异)，其在显示现象上是一条水平暗线。图2为显示面板产生水平暗线的示意图。如图2所示，在实时侦测显示面板的驱动晶体管的电学特性参数的过程中，按照从显示面板的顶部到底部的顺序完成一个周期的侦测，在显示面板上会出现一条水平暗线L从顶部至底部循环显示。
本公开至少一实施例提供一种显示面板的侦测方法，包括：在第N帧和 第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数。其中，N和X均为正整数，且X为随机数。
本示例性实施例提供的显示面板的侦测方法，在相邻两帧之间的空闲阶段随机侦测显示面板的一行子像素的驱动晶体管的电学特性参数。采用本示例的随机侦测方式无法人为预判实时侦测产生的水平暗线出现的位置，使得人眼无法察觉，从而提高用户体验。
在一些示例性实施方式中，X为通过遍历第一范围确定的不重复随机数，第一范围包括不大于R的正整数，R为显示面板的子像素的总行数。在本示例中，在一个侦测周期内按照随机确定的行侦测顺序对子像素的像素电路进行侦测。在本示例中，一个侦测周期可以包括对R行子像素的侦测过程。
在一些示例性实施方式中，在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素中的b种颜色子像素的像素电路的驱动晶体管的电学特性参数。其中，b为正整数，且b小于或等于一个像素单元包括的子像素的个数。在一些示例中，一个像素单元可以包括a个子像素(例如，包括红绿蓝三色子像素，或者包括红绿蓝白四色子像素)，a为正整数。在一个侦测周期可以对一种颜色子像素的像素电路进行侦测。例如，以一个像素单元包括红绿蓝三种颜色的子像素为例，在第一个侦测周期，可以按照随机确定的行侦测顺序对每一行中的红色子像素的像素电路进行侦测；在第二个侦测周期，可以按照随机确定的行侦测顺序对每一行中的绿色子像素的像素电路进行侦测；在第三个侦测周期，可以按照随机确定的行侦测顺序对每一行中的蓝色子像素的像素电路进行侦测。在之后的侦测周期可以按照第一侦测周期、第二侦测周期和第三侦测周期的方式依次循环。然而，本实施例对此并不限定。在一些示例中，在一个侦测周期中可以侦测多种颜色子像素的像素电路；例如，在一个侦测周期内可以按照行侦测顺序依次对红绿蓝三色子像素的像素电路进行侦测。比如，在一个侦测周期内，针对第X行，侦测第X行中红色子像素的像素电路，针对第X+1行，侦测第X+1行中绿色子像素的像素电路，针对第X+2行，侦测第X+2行中蓝色子像素的像素电路。在另一些示例中，在一个侦测周期内，在相邻两帧的空闲阶段，可以侦测随机行中至少两种颜色子像素的像素电路的驱动晶体管的电学特性参数。例如，在第N帧和第 N+1帧之间的空闲阶段，可以侦测第X行子像素中红色和绿色子像素的像素电路的晶体管的电学特性参数。
在一些示例性实施方式中，在每个侦测周期中的行侦测顺序可以相同，即在第一个侦测周期确定随机的行侦测顺序之后，在后续的侦测周期均可以按照已确定的行侦测顺序进行侦测。或者，在不同侦测周期中的行侦测顺序可以部分相同或完全不同；例如，奇数侦测周期的行侦测顺序相同，偶数侦测周期的行侦测顺序相同；又如，多个侦测周期中的行侦测顺序可以均不同，且都是随机确定的。然而，本实施例对此并不限定。
在一些示例性实施方式中，在第一个侦测周期，N的取值范围为第一范围。例如，R＝2160，在第一帧至第2160帧中的每一帧之后的空闲阶段，对随机确定的一行子像素的像素电路的驱动晶体管的电学特性参数进行侦测。在本示例中，在第一个侦测周期，N的取值范围和X的取值范围相同。然而，本实施例对此并不限定。在一些示例中，在第一个侦测周期，N的取值范围可以不同于X的取值范围。例如，X可以通过遍历第一范围确定，N的取值范围可以大于第一范围。以R＝2160为例，X可以为通过遍历1至2160确定的不重复随机数，N可以为从1至2200中选出的2160个不重复数。在本示例中，在连续的多帧中，相邻两帧之间的空闲阶段可能会侦测一行子像素的像素电路的驱动晶体管的电学特性参数，或者，不进行侦测。在一些示例中，一个侦测周期至少需要R帧完成。
在一些示例性实施方式中，至少一个侦测周期内的N和X的关系可以通过Randperm函数确定。在一些示例中，通过Randperm函数可以产生一个一维数组，X可以为该一维数组中的元素值，N可以为指示该一维数值中元素值的地址。例如，X可以为随机数组中第N个元素值。或者，N可以为该一维数组中的元素值，X可以为指示该一维数组中元素值的地址。例如，N可以为随机数组中第X个元素值。在本示例中，利用Randperm函数可以得到随机数组，从而确定显示帧和侦测行之间的随机关系。
在一些示例中，每个侦测周期内的N和X的关系均可以通过Randperm函数确定。其中，在每个侦测周期，X的取值范围可以均为第一范围，N的取值范围可以随着侦测周期变化。例如，R为2160，在第一个侦测周期，N 的取值范围可以为第一范围(即1至2160)，在第二个侦测周期，N的取值范围可以为2161至4320，并依此类推。然而，本实施例对此并不限定。在一些示例中，在第一个侦测周期内的N和X的关系通过Randperm函数确定之后，在后续的侦测周期内，可以按照已确定的行侦测顺序，并更新N的取值范围来确定N和X之间的随机关系。例如，在第一个侦测周期，在第k行和第k+1行之间的空闲阶段，侦测第X行子像素的像素电路，则在第c个侦测周期，可以在第k+R*(c-1)行和第k+R*(c-1)+1行之间的空闲阶段，侦测第X行子像素的像素电路，k和c均为正整数。
在一些示例性实施方式中，在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素中一种颜色子像素的像素电路的驱动晶体管的电学特性参数，在第N+1帧和第N+2帧之间的空闲阶段，侦测第X行子像素中另一种颜色子像素的像素电路的驱动晶体管的电学特性参数。以一个像素单元包括红绿蓝三色子像素为例，在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素中的红色子像素的像素电路的驱动晶体管的电学特性参数；在第N+1帧和第N+2帧之间的空闲阶段，侦测第X行子像素中的绿色子像素的像素电路的驱动晶体管的电学特性参数；在第N+2帧和第N+3帧之间的空闲阶段，侦测第X行子像素中的蓝色子像素的像素电路的驱动晶体管的电学特性参数。在本示例中，在一个空闲阶段，对一行子像素中的一种颜色子像素的像素电路进行侦测，而且，本示例的一个侦测周期(即完成R行侦测)至少需要R*a帧完成，其中，a为像素单元包括的子像素的个数，例如，a＝3。然而，本实施例对此并不限定。
在一些示例性实施方式中，在第N帧和第N+1帧之间的空闲阶段内，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数，包括：利用随机控制信号产生感测时钟信号；通过感测驱动电路利用感测时钟信号、感测起始信号和使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
在一些示例性实施方式中，感测时钟信号、感测起始信号和使能控制信号为脉冲信号。感测起始信号的感测脉冲的脉宽大于感测时钟信号的时钟脉冲的脉宽且不大于所述时钟脉冲的脉宽的两倍，使能控制信号的脉宽大于感 测脉冲的脉宽。在本示例中，脉宽为脉冲宽度，即高电平持续时长。
在一些示例性实施方式中，感测起始信号包括感测脉冲，且相邻感测脉冲之间至少包括R个时钟脉冲，R为显示面板的子像素的总行数。本示例可以保证在空闲阶段对随机行进行侦测之后，有足够时间可以对感测驱动电路进行复位。
在一些示例性实施方式中，通过感测驱动电路在第N帧和第N+1帧之间的空闲阶段，将感测起始信号在第N帧提供的感测脉冲移位输出给第X行子像素的像素电路。
在一些示例性实施方式中，在第N帧提供给感测驱动电路的感测时钟信号包括第一时钟脉冲群，第一时钟脉冲群包括X个时钟脉冲，X个时钟脉冲中的第一个时钟脉冲的起始时刻不早于在第N帧提供给感测驱动电路的感测起始信号中的感测脉冲的起始时刻。例如，在第N帧提供给感测驱动电路的第一时钟脉冲群的第一个时钟脉冲的起始时刻与感测脉冲的起始时刻大致相同。在本示例中，利用X个时钟脉冲对感测脉冲进行移位，来控制第X行子像素实现侦测。
在一些示例性实施方式中，本实施例的侦测方法还包括：在完成侦测第X行子像素的像素电路的驱动晶体管的电学特性参数之后，利用感测时钟信号的第二时钟脉冲群对感测驱动电路进行复位。第二时钟脉冲群包括X1个时钟脉冲，X1大于R-X；R为显示面板的子像素的总行数。在本示例中，利用第二时钟脉冲群对感测脉冲进行移位，实现对感测驱动电路进行复位。
在一些示例性实施方式中，本实施例的侦测方法还包括：通过感测驱动电路利用感测起始信号在第N+1帧提供的感测脉冲、感测时钟信号在第N+1帧提供的第一时钟脉冲群、以及使能控制信号，在第N+1帧和第N+2帧之间的空闲阶段内，产生提供给第Y行子像素的像素电路的感测控制信号；所述感测时钟信号在第N+1帧提供的第一时钟脉冲群包括Y个时钟脉冲。其中，Y为随机的正整数，且Y不同于X。
在一些示例性实施方式中，Y个时钟脉冲和X1个时钟脉冲不连续。
在一些示例性实施方式中，本实施例的侦测方法还包括：在完成侦测第Y行子像素的像素电路的驱动晶体管的电学特性参数之后，利用所述感测时 钟信号的第二时钟脉冲群对所述感测驱动电路进行复位，所述第二时钟脉冲群包括Y1个时钟脉冲，Y1大于R-Y，R为所述显示面板的子像素的行数。
下面通过一些示例对本实施例的方案进行举例说明。
图3为本公开至少一实施例的显示面板的示意图。如图3所示，本示例性实施例的显示面板包括：像素阵列12和面板驱动器。面板驱动器配置为驱动像素阵列12。面板驱动器可以包括：时序控制器10、数据驱动器20、栅极驱动器30以及用于存储补偿数据的存储器40。
在一些示例性实施方式中，像素阵列12可以包括：多条扫描信号线(例如，GL1至GLm)、多条数据信号线(例如，DL1至DLn)、多条感测控制线(例如，SL1至SLm)、多条感测信号线(图未示)以及多个子像素Pxij。其中，m和n均为正整数。
在一些示例性实施方式中，多条扫描信号线GL1至GLm和多条感测控制线SL1至SLm在显示面板的第一方向(例如水平方向)上形成，多条数据信号线DL1至DLn和多条感测信号线可以在显示面板的第二方向(例如，垂直方向)上形成。其中，第一方向和第二方向交叉，例如，第一方向垂直于第二方向。多条数据信号线和多条感测信号线配置为与多条扫描信号线和多条感测控制线相交。
在一些示例性实施方式中，时序控制器10可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器20。数据驱动器20可以利用从时序控制器10接收的灰度值和控制信号来产生将提供到数据信号线DL1至DLn的数据电压。例如，数据驱动器20可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线DL1至DLn。
在一些示例性实施方式中，时序控制器10可以将适于栅极驱动器的规格的时钟信号、扫描起始信号、感测起始信号等提供到栅极驱动器30。栅极驱动器30可以通过从时序控制器10接收时钟信号、扫描起始信号、感测起始信号等来产生将提供到扫描信号线GL1至GLm的扫描信号以及提供到感测控制线SL1至SLm的感测控制信号。例如，栅极驱动器30可以包括：扫描驱动电路和感测驱动电路。扫描驱动电路可以将具有导通电平脉冲的扫描信 号顺序地提供到扫描信号线GL1至GLm。感测驱动电路可以将具有导通电平脉冲的感测控制信号顺序地提供到感测控制线SL1至SLm。例如，扫描驱动电路可以被构造为移位寄存器的形式，并且可以以在扫描时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。感测驱动电路可以被构造为移位寄存器的形式，并且可以以在感测时钟信号的控制下顺序地将以导通电平脉冲形式提供的感测控制信号传输到下一级电路的方式产生感测控制信号。
在一些示例性实施方式中，数据驱动器20可以通过感测信号线获取感测数据，并将感测数据传输给时序控制器10。时序控制器10可以根据感测数据确定驱动晶体管的电学特性参数的补偿数据，并将补偿数据存储在存储器40中。在一些示例中，存储器40可以存储显示面板包括的驱动晶体管的电学特性参数的补偿数据，还可以存储显示面板的发光元件的光学补偿数据。然而，本实施例对此并不限定。
在一些示例性实施方式中，栅极驱动器30包括的扫描驱动电路和感测驱动电路可以位于像素阵列12的相对两侧(例如，像素阵列的左侧和右侧)。然而，本实施例对此并不限定。例如，在像素阵列的相对两侧均设置栅极驱动器，实现对子像素的双边驱动。
在一些示例性实施方式中，栅极驱动器30可以采用集成电路形成，或者，可以在制备子像素的像素电路的工艺期间直接形成在显示面板的基底上。然而，本实施例对此并不限定。
在一些示例性实施方式中，像素阵列12内的每个子像素PXij可以连接到对应的数据信号线、扫描信号线、感测控制线和感测信号线，i和j可以是自然数。子像素PXij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图4为本公开至少一实施例的显示面板的平面结构示意图。如图4所示，显示面板的显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。第一子像素P1、第二子像素P2和第三子像素P3均包括像素电路和发光元件。第一子像素P1、 第二子像素P2和第三子像素P3中的像素电路可以分别与扫描信号线和数据信号线连接，像素电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向发光元件输出相应的驱动电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光元件分别与所在子像素的像素电路连接，发光元件被配置为响应所在子像素的像素电路输出的驱动电流发出相应亮度的光。
在一些示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在一些示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列，本公开在此不做限定。
在一些示例性实施方式中，子像素包括像素电路和发光元件。像素电路可以为如图1所示的像素电路。在一些示例性实施方式中，扫描晶体管T1、驱动晶体管DTFT和感测晶体管T2可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在一些示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。然而，本实施例对此并不限定。
在一些示例性实施方式中，发光元件可以是有机发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。然而，本实施例对此并不限定。
在一些示例性实施方式中，时序控制器10可以根据时序控制信号来产生 提供给栅极驱动器30的时钟信号。在一些示例中，时序控制信号包括随机控制信号，时序控制器10可以利用随机控制信号产生提供给栅极驱动器30的感测驱动电路的感测时钟信号。在一些示例中，随机控制信号可以通过Randperm函数产生的随机数组确定。然而，本实施例对此并不限定。
在一些示例中，可以利用Randperm函数通过以下方式生成随机数组。
ran_ge＝randperm(2160,2160)；
M＝2160；
data＝[]；
t＝[]；
for i＝1:M；
     A＝ran_ge(i)-1；
     t(i)＝A；
             if(i＝＝M)
                 B＝strcat(num2str(A),’；’)；
             else
                 B＝strcat(num2str(A),’,’)；
             end
             data＝[data B]；
end
fid＝fopen(’random_sense_4k.coe’,’wt’)；
fwrite(fid,’memory_initialization_radix＝10；’)；
fprintf(fid,’\n’)；
fwrite(fid,’memory_initializaton_vector＝’)；
fprintf(fid,’\n’)；
fwrite(fid,data)；
fclose(fid)；
在一些示例中，通过以上程序可以利用Randperm函数生成随机数组，并将随机数组保存在配置文件中，以供后续使用。
图5为本公开至少一实施例的随机数组的示意图。图5中的横坐标表示帧编号，纵坐标表示待侦测的子像素行数。在本示例中，以尺寸为3840*2160的显示面板为例，显示面板的子像素行数为2160。在一个侦测周期内，实时侦测显示面板的2160行子像素的像素电路的驱动晶体管的电学特性参数。本 示例产生的随机数组的数据是随机的、且遍历1至2160，以满足一个侦测周期的随机侦测。本示例中，可以在2160帧显示阶段，完成一个周期的随机侦测。根据图5所示的随机数组，可以确定在哪一帧之后的空闲阶段侦测哪一行子像素的驱动电路的电学特性参数。即，可以确定显示面板的子像素行的随机侦测顺序。例如，在第一帧和第二帧之间的空闲阶段，可以侦测第100行子像素的像素电路的驱动晶体管的电学特性参数，在第二帧和第三帧之间的空闲阶段，可以侦测第50行子像素的像素电路的驱动晶体管的电学特性参数。然而，本实施例对此并不限定。在一些示例中，可以在大于2160帧显示阶段，完成一个周期的随机侦测。例如，可以从2200帧显示阶段，选择出2160帧，并在选择出的2160帧和相邻帧之间的空闲阶段中按照随机顺序进行侦测。例如，在第一帧和第二帧之间的空闲阶段，可以侦测第100行子像素的像素电路的驱动晶体管的电学特性参数，在第二帧和第三帧之间的空闲阶段，可以不进行侦测。在一些示例中，在一行子像素的侦测过程中，可以对该行的全部子像素进行侦测。在一些示例中，如果空闲阶段时间较短，也可以只侦测一行像素的某一个子像素或某两个子像素，例如只侦测红色子像素的像素电路的驱动晶体管的电学特性参数，或者侦测红色子像素和绿色子像素的像素电路的驱动晶体管的电学特性参数。
在一些示例性实施方式中，时序控制器10可以包括随机信号生成电路101，通过随机信号生成电路来生成随机控制信号，再利用随机控制信号来产生提供给感测驱动电路的感测时钟信号。然而，本实施例对此并不限定。例如，时序控制器10可以接收外部电路产生的随机控制信号。
图6为本公开至少一实施例的感测驱动电路的结构示意图。在一些示例性实施方式中，如图6所示，本示例性实施例的感测驱动电路用于产生提供给感测控制线的感测控制信号。感测驱动电路包括：多个级联的移位寄存器单元301、以及多个逻辑与门302。多个逻辑与门302与多个移位寄存器单元301一一对应连接。第i级移位寄存器单元的输出端Q(i)与第i+1级移位寄存器单元的输入端D(i+1)连接。多个移位寄存器单元301的时钟端例如通过感测时钟信号线CLK接收时序控制器10提供的感测时钟信号。第一级移位寄存器单元的输入端例如通过感测起始信号线IO从时序控制器10接收 感测起始信号。感测驱动电路可以根据感测时钟信号，通过使用多个级联的移位寄存器单元301顺序移位感测起始信号。时序控制器10还通过使能控制信号线OE向感测驱动电路提供使能控制信号。与第i级移位寄存器单元的输出端连接的逻辑与门302，可以将第i级移位寄存器单元的输出信号和使能控制信号相与后得到的感测控制信号提供给第i行子像素连接的感测控制线SLi。其中，i为正整数。
在一些示例性实施方式中，扫描驱动电路的结构与感测驱动电路的结构类似，故于此不再赘述。
在本实施例中，CLK、IO和OE表示信号线也可以表示对应信号线提供的信号。
图7为本公开至少一实施例的感测驱动电路的工作时序图。在本示例性实施方式中，如图7所示，使能控制信号OE为脉冲信号，使能控制信号OE的高电平脉冲位于相邻帧之间的空闲阶段，在其余阶段使能控制信号OE均处于低电位。感测起始信号IO为脉冲信号，包括感测脉冲，感测脉冲可以在帧显示阶段提供给感测驱动电路，以便通过感测驱动电路在空闲阶段将感测脉冲移位输出给随机行的感测控制线。感测时钟信号CLK为脉冲信号。在一些示例中，相邻两个感测脉冲之间的间隔PI至少包括R个时钟脉冲。R表示显示面板的子像素的总行数。例如，R为2160行。感测脉冲的脉宽大于时钟脉冲的脉宽且不大于时钟脉冲的脉宽的两倍。例如，感测脉冲的脉宽可以约等于时钟脉冲的脉宽的1.5倍。使能控制信号的高电平脉冲的脉宽大于感测脉冲的脉宽。在本示例中，脉宽即脉冲宽度，为高电平持续时长。
在一些示例性实施方式中，如图7所示，在第N帧，时序控制器可以根据随机控制信号产生包括第一时钟脉冲群的感测时钟信号，第一时钟脉冲群可以包括X个连续的时钟脉冲。感测驱动电路根据感测初始信号IO提供的感测脉冲和X个连续的时钟脉冲，可以控制第X级移位寄存器单元输出高电平，在第N帧和第N+1帧的空闲阶段，结合使能控制信号OE的高电平脉冲，通过逻辑与门，可以向第X行子像素连接的感测控制线SLx提供高电位的感测控制信号，以导通第X行子像素的像素电路中的感测晶体管，对像素电路中的驱动晶体管的电学特性参数进行侦测。在一些示例中，X个时钟脉冲中 的第一个时钟脉冲的起始时刻不早于感测起始信号中的感测脉冲的起始时刻。例如，X个时钟脉冲中的第一个时钟脉冲的起始时刻与感测起始信号中的感测脉冲的起始时刻相同。其中，X可以为正整数。
在一些示例性实施方式中，如图7所示，在第N+1帧，时序控制器可以根据随机控制信号产生包括第二时钟脉冲群的感测时钟信号。第二时钟脉冲群可以包括X1个连续的时钟脉冲。感测驱动电路利用X1个连续的时钟脉冲进行复位。在完成第X行子像素的驱动晶体管的电学特性参数的侦测之后，利用X1个连续的时钟脉冲对感测脉冲进行移位，以使感测驱动电路的多个输出信号均为低电平，即不对任一行子像素的驱动晶体管进行侦测。在一些示例中，X1可以大于R-X。其中，X1为正整数。在一些示例中，X1个连续的时钟脉冲可以在第N帧的感测脉冲和第N+1帧的感测脉冲之间的间隔PI内、且在使能控制信号OE的高电平脉冲结束之后提供。例如，X1个连续的时钟脉冲可以在第N+1帧提供，或者，可以在第N帧和第N+1帧之间的空闲阶段的使能控制信号OE的高电平脉冲结束之后并在第N+1帧的感测脉冲提供之前提供。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7所示，在第N+1帧，时序控制器可以根据随机控制信号产生包括第一时钟脉冲群的感测时钟信号，第一时钟脉冲群可以包括Y个连续的时钟脉冲。在一些示例中，X1个连续的时钟脉冲和Y个连续的时钟脉冲可以不连续。本实施例对于Y个连续的时钟脉冲和X1个连续的时钟脉冲之间的间隔时长并不限定。感测驱动电路可以根据感测初始信号IO的感测脉冲和Y个连续的时钟脉冲，控制第Y级移位寄存器单元输出高电平，并且在第N+1帧和第N+2帧的空闲阶段，结合使能控制信号OE的高电平，通过逻辑与门，可以向第Y行子像素连接的感测控制线SLy提供高电位的感测控制信号，以导通第Y行子像素的像素电路中的感测晶体管，对像素电路中的驱动晶体管的电学特性参数进行侦测。其中，Y为随机的正整数，且Y不同于X。X可以为随机数组中的第N个元素值，Y可以为随机数组中的第N+1个元素值。
在一些示例性实施方式中，如图7所示，在第N+2帧，时序控制器根据随机控制信号产生包括第二时钟脉冲群的感测时钟信号，第二时钟脉冲群可 以包括Y1个连续的时钟脉冲。感测驱动电路利用Y1个连续的时钟脉冲进行复位。在完成第Y行子像素的驱动晶体管的电学特性参数的侦测之后，利用Y1个连续的时钟脉冲对感测脉冲进行移位，以使感测驱动电路的多个输出信号均为低电平，即不对任一行子像素的驱动晶体管进行侦测。在一些示例中，Y1可以大于R-Y。其中，Y1为正整数。在一些示例中，Y1个连续的时钟脉冲可以在第N+1帧的感测脉冲和第N+2帧的感测脉冲之间的间隔内、且在使能控制信号OE的高电平脉冲结束之后提供。例如，Y1个连续的时钟脉冲可以在第N+2帧提供，或者，可以在第N+1帧和第N+2帧之间的空闲阶段的使能控制信号OE的高电平脉冲结束之后并在第N+2帧的感测脉冲提供之前提供。然而，本实施例对此并不限定。
在本示例性实施方式中，感测驱动电路在一个空闲阶段产生的感测控制信号可以通过感测控制线提供给随机确定的一行子像素的像素电路。例如，在侦测过程中，通过数据信号线给该行中的红色子像素的像素电路提供测试数据信号，实现侦测该行中的红色子像素的驱动晶体管的电学特性参数。然而，本实施例对此并不限定。
在本示例性实施方式中，按照图7所示的时序控制，可以依次对显示面板的R行子像素的驱动晶体管进行侦测，且侦测顺序是随机确定的，从而完成一个侦测周期。在后续的侦测周期中，可以利用本侦测周期已确定的随机侦测顺序，或者重新产生随机的侦测顺序。如此一来，观看者无法认为预先感知由实时侦测产生的水平暗线的位置，从而提高用户体验。
本公开至少一实施例还提供一种显示面板，包括：像素阵列以及栅极驱动器。像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动发光元件发光的像素电路。栅极驱动电路，配置为在第N帧和第N+1帧之间的空闲阶段内，通过感测控制线向第X行子像素的像素电路提供感测控制信号，以侦测第X行子像素的像素电路的驱动晶体管的电学特性参数。其中，X为随机数，且N和X均为正整数。
在一些示例性实施方式中，本实施例的显示面板还包括：时序控制器。时序控制器配置为利用随机控制信号产生感测时钟信号，并将感测时钟信号提供给栅极驱动器。栅极驱动器配置为利用感测时钟信号、感测起始信号和 使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
在一些示例性实施方式中，时序控制器包括：随机信号生成电路，配置为生成随机控制信号。
在一些示例性实施方式中，栅极驱动器包括：感测驱动电路。感测驱动电路包括：多个级联的移位寄存器单元以及多个逻辑与门。第i级移位寄存器单元的输出端与第i+1级移位寄存器单元的输入端连接，第一极移位寄存器单元的输入端与提供感测起始信号的感测起始信号线连接。多个移位寄存器单元的时钟端与提供感测时钟信号的感测时钟信号线连接。第i个逻辑与门的输入端与第i级移位寄存器单元的输出端和提供使能控制信号的使能控制线连接，第i个逻辑与门的输出端与连接第i行子像素的像素电路的感测控制线连接。其中，i为正整数。
在一些示例性实施方式中，像素电路包括：输入晶体管、驱动晶体管、感测晶体管、以及第一存储电容。输入晶体管的控制极与扫描信号线连接，第一极与数据信号线连接，第二极与驱动晶体管的控制极连接。驱动晶体管的第一极与第一电源线连接，第二极与发光元件连接。第一存储电容的第一电极与驱动晶体管的控制极连接，第二电极与驱动晶体管的第二极连接。感测晶体管的控制极与感测控制线连接，第一极与驱动晶体管的第二极连接，第二极与感测信号线连接。
关于本实施例的显示面板的结构的相关说明如前所述，故于此不再赘述。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示面板的侦测方法，包括：
    在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数；
    其中，N和X均为正整数，且X为随机数。
  2. 根据权利要求1所述的方法，其中，X为通过遍历第一范围确定的不重复随机数，所述第一范围包括不大于R的正整数，R为所述显示面板的子像素的总行数。
  3. 根据权利要求2所述的方法，其中，在第一个侦测周期，N的取值范围为第一范围。
  4. 根据权利要求1至3任一所述的方法，其中，至少一个侦测周期内的N和X的关系通过Randperm函数确定。
  5. 根据权利要求4所述的方法，其中，通过Randperm函数得到随机数组，X为所述随机数组中的第N个元素值。
  6. 根据权利要求1至5任一所述的方法，其中，所述在第N帧和第N+1帧之间的空闲阶段内，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数，包括：
    利用随机控制信号产生感测时钟信号；
    通过感测驱动电路利用所述感测时钟信号、感测起始信号和使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
  7. 根据权利要求6所述的方法，其中，所述感测时钟信号、感测起始信号和使能控制信号为脉冲信号；所述感测起始信号的感测脉冲的脉宽大于感测时钟信号的时钟脉冲的脉宽且不大于所述时钟脉冲的脉宽的两倍，所述使能控制信号的脉宽大于感测脉冲的脉宽。
  8. 根据权利要求6所述的方法，其中，所述感测起始信号包括感测脉冲，且相邻感测脉冲之间至少包括R个时钟脉冲，R为所述显示面板的子像素的 总行数。
  9. 根据权利要求6所述的方法，其中，通过所述感测驱动电路在第N帧和第N+1帧之间的空闲阶段，将所述感测起始信号在第N帧提供的感测脉冲移位输出给第X行子像素的像素电路。
  10. 根据权利要求9所述的方法，其中，在第N帧提供给感测驱动电路的所述感测时钟信号包括第一时钟脉冲群，所述第一时钟脉冲群包括X个时钟脉冲，所述X个时钟脉冲中的第一个时钟脉冲的起始时刻不早于在第N帧提供给感测驱动电路的所述感测起始信号中的感测脉冲的起始时刻。
  11. 根据权利要求6至10任一所述的方法，还包括：在完成侦测第X行子像素的像素电路的驱动晶体管的电学特性参数之后，利用所述感测时钟信号的第二时钟脉冲群对所述感测驱动电路进行复位；所述第二时钟脉冲群包括X1个时钟脉冲；X1大于R-X，R为所述显示面板的子像素的总行数。
  12. 根据权利要求11所述的方法，还包括：通过感测驱动电路利用感测起始信号在第N+1帧提供的感测脉冲、感测时钟信号在第N+1帧提供的第一时钟脉冲群、以及使能控制信号，在第N+1帧和第N+2帧之间的空闲阶段内，产生提供给第Y行子像素的像素电路的感测控制信号；所述感测时钟信号在第N+1帧提供的第一时钟脉冲群包括Y个时钟脉冲；
    其中，Y为随机的正整数，且Y不同于X。
  13. 根据权利要求12所述的方法，其中，Y个时钟脉冲和X1个时钟脉冲不连续。
  14. 根据权利要求12或13所述的方法，还包括：在完成侦测第Y行子像素的像素电路的驱动晶体管的电学特性参数之后，利用所述感测时钟信号的第二时钟脉冲群对所述感测驱动电路进行复位，所述第二时钟脉冲群包括Y1个时钟脉冲，Y1大于R-Y，R为所述显示面板的子像素的行数。
  15. 根据权利要求1至14任一所述的方法，其中，所述在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素的像素电路的驱动晶体管的电学特性参数，包括：
    在第N帧和第N+1帧之间的空闲阶段，侦测第X行子像素中的b种颜 色子像素的像素电路的驱动晶体管的电学特性参数，其中，b为正整数，且b小于或等于一个像素单元包括的子像素的个数。
  16. 一种显示面板，包括：像素阵列以及栅极驱动器；
    所述像素阵列包括多个子像素，至少一个子像素包括发光元件和驱动发光元件发光的像素电路；
    所述栅极驱动电路，配置为在第N帧和第N+1帧之间的空闲阶段内，通过感测控制线向第X行子像素的像素电路提供感测控制信号，以侦测第X行子像素的像素电路的驱动晶体管的电学特性参数；
    其中，N和X均为正整数，且X为随机数。
  17. 根据权利要求16所述的显示面板，还包括：时序控制器；
    所述时序控制器配置为利用随机控制信号产生感测时钟信号，并将感测时钟信号提供给所述栅极驱动器；
    所述栅极驱动器配置为利用所述感测时钟信号、感测起始信号和使能控制信号，在第N帧和第N+1帧之间的空闲阶段内，产生提供给第X行子像素的像素电路的感测控制信号。
  18. 根据权利要求17所述的显示面板，其中，所述时序控制器包括：随机信号生成电路，配置为生成所述随机控制信号。
  19. 根据权利要求16至18任一所述的显示面板，其中，所述栅极驱动器包括：感测驱动电路，所述感测驱动电路包括：多个级联的移位寄存器单元以及多个逻辑与门；
    第i级移位寄存器单元的输出端与第i+1级移位寄存器单元的输入端连接，第一极移位寄存器单元的输入端与提供感测起始信号的感测起始信号线连接；
    多个移位寄存器单元的时钟端与提供感测时钟信号的感测时钟信号线连接；
    第i个逻辑与门的输入端与第i级移位寄存器单元的输出端和提供使能控制信号的使能控制线连接，第i个逻辑与门的输出端与连接第i行子像素的像素电路的感测控制线连接；
    其中，i为正整数。
  20. 根据权利要求16至19任一所述的显示面板，其中，所述像素电路包括：输入晶体管、驱动晶体管、感测晶体管、以及第一存储电容；
    所述输入晶体管的控制极与扫描信号线连接，第一极与数据信号线连接，第二极与驱动晶体管的控制极连接；
    所述驱动晶体管的第一极与第一电源线连接，第二极与发光元件连接；
    所述第一存储电容的第一电极与驱动晶体管的控制极连接，第二电极与驱动晶体管的第二极连接；
    所述感测晶体管的控制极与感测控制线连接，第一极与驱动晶体管的第二极连接，第二极与感测信号线连接。
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