WO2022245323A1 - Filter combining system and method - Google Patents

Abstract

The present invention is a system and method that enables the use of less number of DSP blocks by means of finding common filter coefficients, comprising of the following; multiplier block (1) for multiplying two digital signals on the FPGA, adder block (2) for summing two digital signals on the FPGA, delay block (3) for allowing a digital signal on the FPGA to be transferred to the next block with a one-unit delay, delay block connection (5) providing the connection between said delay blocks (3), coefficient groups (10) in which the digital signal values multiplied by the grouped filter coefficients (8) grouped according to the values of the filter coefficients in the same indices are added, and each group result is added to a different filter result directly or reciprocally (multiplied by -1).

Description

FILTER COMBINING SYSTEM AND METHOD

Field of the Invention

The present invention relates to a system and method that enables more efficient use of system resources by combining filters when using Field Programmable Gate Array (FPGA) circuits in hardware signal filtering processes.

In particular, the present invention relates to a system and method that enables the circuit created on the FPGA to be less resource consuming, during the detection and separation of a plurality of correlation signals in a single signal in communication systems.

State of the Art

The use of correlator (filter) banks in communication systems has a special importance. A common use of the used correlator banks to reveal the task is shown in the block diagram in Figure-4.

The RF signal from the antenna is received by the RF front end and reduced to the baseband level. The signal digitized by the A/D converter at the baseband level is directly entered into the baseband processor and decoding is performed. The use of FPGAs as baseband processors is quite common in the state of the art. The design of receivers defined as digital receivers has become possible with the processing of the baseband signal directly in the FPGA. One of the most important problems in signal processing systems such as digital receivers is the establishment of the structure that will decide when the decoder should start working. Decoders must be activated on the correct bit sequence with the correct timing so as to operate properly. Meaningful bit sequences can only be obtained in this manner. For this reason, the bit sequences sent to the receivers are framed so as to operate the decoders of the digital receivers on the correct bit sequence. An example frame structure that can be used is shown in Figure 5. Here, the coefficients of an A or B filter can be used as the frame starting word. Thus, a communication bit structure using two different frames can be created by using two different frame starting words with the filter coefficients A and B. Two correlators that can detect both A and B filter coefficients must be implemented in the FPGA so as to find out which frame came in the digital receiver and to insert the encoded bit sequence into the decoder with the correct timing. In case more than two frame structures are required based on the design requirement in communication, the number of filters in the correlator bank also increases.

One Digital Signal Processing (DSP) circuit block is used for each multiplication operation on FPGAs. It is important to use the existing blocks efficiently since these blocks are limited in number. An example image of the use of two parallel filters (A and B filters) with a total of 32 multipliers and 30 adders with 16 coefficients with the classical design used in the state of the art is given in Figure 1 . A digital signal can be passed through a plurality of filters simultaneously in parallel filters. The filtering process begins with receiving a S signal (6) (input signal) into digital blocks. Each time the delay block (3) delays the signal by one unit of time and forwards it to the next block with the delay block connections (5). The imported signal with delays is multiplied by multiplier blocks (1) with certain filter coefficients, and the result is summed up with adder blocks (2). The result of the filtered signal is obtained as the filtering result A (7) (A(S)) as a result of all the addition operations. Figure 1 shows the simultaneous use of two filters to filter the signal. A multiplication must be made as much as the filter length for a filter. It may not be possible to perform intensive filtering operations with these circuits since FPGA circuits have a limited number of DSP blocks. An example of these parallel filters is the Global Positioning System (GPS). Each satellite transmits data by sending a series of chips consisting of 1s and 0s. The correlation of the airborne signal with each satellite array is checked so as to understand the presence of signals from all satellites. Correlation means that the signal is filtered by each satellite array. In case it is desired to use these filters simultaneously, all filters are designed separately and multiplication is required as the number of filters multiplied by the length of the array (1023 for GPS) in conventional methods. This means using a large amount of DSP on the FPGA.

As a result due to the abovementioned disadvantages and the insufficiency of the current solutions regarding the subject matter, a development is required to be made in the relevant technical field.

Aim of the Invention The invention aims to solve the abovementioned disadvantages by being inspired from the current conditions.

The main aim of the present invention is to reveal a system and method that enables more efficient use of system resources by combining filters when using Field Programmable Gate Array (FPGA) circuits in hardware signal filtering processes.

Another aim of the present invention is to reveal a system and method that enables the circuit created on the FPGA to be less resource consuming, during the detection and separation of a plurality of correlation signals in a single signal in communication systems.

Another aim of the invention is to create a system and method that enables the use of less number of DSP blocks by means of finding common filter coefficients.

Filters are examined during the hardware design process, and 'the use of less number of DSP blocks by means of finding common filter coefficients' is ensured with the present invention. For example, if the filter lengths are 1023 in a system using two binary filters, the results of the two filters on the flowing signal can be obtained using a total of 2046 multipliers and 2044 adders. It can be represented by 0:-1 to 1 :1 (BPSK) in current systems. The inventive system is divided into 4 groups according to the commonality of the coefficients of the two filters (-1 ,-1 ; -1 ,1 ; 1 ,-1 ; 1 ,1). Values of -1 in both filters are approximately 1/4 of the filter length on average. Likewise, other groups also contain a coefficient of about 1/4. If we consider the group of coefficients that have a value of 1 in both filters, a total of 256 multiplier and 255 adder requirements are obtained by multiplying and adding the signal elements corresponding to these coefficients by 1 (approximately 1023 1 4 256 coefficients). When this requirement is used, the resulting value is added to both filter results. Similarly, 256 multipliers and 256 adders are used for the signal elements corresponding to the coefficients of 1 in the first filter and -1 in the second. While the value found in the first filter is added directly, this value is added to the second filter by multiplying it by -1. The results for 4 cases are obtained with approximately 1023 multipliers and 1022 adders by performing similar operations for the other two cases (-1 ,1 and -1 ,-1) 3 adders and 2 more multipliers are used to add these cases (these values are insignificant in large filters) while creating the first and second filter results. As a result, the total number of multipliers and adders used is approximately halved for two filters with the present invention. Additionally, when filters are partitioned, each partition will need to be rewired. This process is not a high resource consuming work on FGPA.

In order to fulfill the above-described aims, the present invention is a system that enables more efficient use of system resources by combining filters when using Field Programmable Gate Array (FPGA) circuits in hardware signal filtering processes. Accordingly, the system comprises the following;

• Multiplier block for multiplying two digital signals on the FPGA,

• Adder block for summing two digital signals on the FPGA,

• Delay block for allowing a digital signal on the FPGA to be transferred to the next block with a one-unit delay,

• Delay block connection providing the connection between said delay blocks,

• Coefficient groups in which the digital signal values multiplied by the grouped filter coefficients grouped according to the values of the filter coefficients in the same indices are added, and each group result is added to a different filter result directly or reciprocally (multiplied by -1).

In order to fulfill the above-described aims, the present invention is a method that enables more efficient use of system resources by combining filters during the use of FPGA circuits in hardware signal filtering processes. Accordingly, the method comprises the following process steps;

• creating coefficient groups by grouping delay blocks according to filter coefficients,

• S signal, which is an input signal, entering the system through delay blocks connected to each other with delay block connections and ranking in front of the grouped coefficients,

• multiplying the elements in each coefficient group using only one multiplier block (1) for the two filters,

• adding each coefficient group directly with the adder block since each of it has the same coefficient in itself,

• reversing the results collected according to the group coefficients, depending on the coefficient equivalent of the filter in the relevant coefficient group,

• summation of coefficient group results with an adder block for conversion to filter results. The structural and characteristic features of the present invention will be understood clearly by the following drawings and the detailed description made with reference to these drawings and therefore the evaluation shall be made by taking these figures and the detailed description into consideration.

Figures Clarifying the Invention

Figure-1 gives an example view of the use of two parallel filters (A and B filters) with a total of 32 multipliers and 30 adders with 16 coefficients with the classical design used in the state of the art.

Figure-2 gives an example view of the use of two parallel filters (A and B filters) with a total of 17 multipliers and 16 adders with 16 coefficients in the inventive system.

Figure-3 gives an example view of the use of two parallel filters (A and B filters) with a total of 3 multipliers and 16 adders with 16 binary coefficients in the inventive system.

Figure-4 gives an example digital receiver block diagram.

Figure-5 gives an example frame structure that can be used in communication.

Description of the Part References

1. Multiplier block

2. Adder block

3. Delay block

4. Filter coefficient

5. Delay block connection

6. S signal

7. Filtering result A

8. Grouped filter coefficients 9. Filtering result B

10. Coefficient groups A(S): Filtering result with filter A B(S): Filtering result with filter B G1 : Group-1 A15: A15 coefficient

G2: Group-2 A16: A16 coefficient G3: Group-3 25 B1 : B1 coefficient G4: Group-4 B2: B2 coefficient A1 : A1 coefficient B3: B3 coefficient A2: A2 coefficient B4: B4 coefficient

A3: A3 coefficient B5: B5 coefficient A4: A4 coefficient 30 B6: B6 coefficient A5: A5 coefficient B7: B7 coefficient A6: A6 coefficient B8: B8 coefficient A7: A7 coefficient B9: B9 coefficient

A8: A8 coefficient B10: B10 coefficient A9: A9 coefficient 35 B11 : B11 coefficient A10: A10 coefficient B12: B12 coefficient A11 : A11 coefficient B13: B13 coefficient A12 : A12 coefficient B14: B14 coefficient

A13: A13 coefficient B15: B15 coefficient

A14: A14 coefficient 40 B16: B16 coefficient X1 : X1 coefficient S1 : S1 index X2: X2 coefficient S2: S2 index X3: X3 coefficient S3: S3 index X4: X4 coefficient 20 S4: S4 index X5: X5 coefficient S5: S5 index

X6: X6 coefficient S6: S6 index X7: X7 coefficient S7: S7 index X8: X8 coefficient S8: S8 index X9: X9 coefficient 25 S9: S9 index X10: X10 coefficient S10: S10 index

X11 : X11 coefficient S11 : S11 index X12: X12 coefficient S12: S12 index X13: X13 coefficient S13: S13 index X14: X14 coefficient 30 S14: S14 index X15: X15 coefficient S15: S15 index

X16: X16 coefficient S16: S16 index Detailed Description of the Invention

In this detailed description, the preferred embodiments of the inventive system and method are described by means of examples only for clarifying the subject matter. The invention is a system that enables the use of less number of DSP blocks by finding common filter coefficients. Accordingly, the system comprises the following; multiplier block (1) for multiplying two digital signals on the FPGA, adder block (2) for summing two digital signals on the FPGA, delay block (3) for allowing a digital signal on the FPGA to be transferred to the next block with a one-unit delay, delay block connection (5) providing the connection between said delay blocks (3), coefficient groups (10) in which the digital signal values multiplied by the grouped filter coefficients (8) grouped according to the values of the filter coefficients in the same indices are added, and each group result is added to a different filter result directly or reciprocally (multiplied by -1) ·

The operating principle of the invention is as follows:

The following multiplication and addition operations occur during the application of two filters on the flowing signal in the conventional methods applied in the state of the art. The following process shows the use of two parallel filters. These filters are for example selected as follows;

A = [-1 , -1 , 1 , 1 , -1 , 1 , 1 , 1 , 1 , -1 , -1 , -1 , -1 , -1 , 1 , -1]

B = [-1 , 1 , 1 , 1 , 1 , -1 , 1 , 1 , -1 , -1 , 1 , -1 , -1 , -1 , -1 , 1]

The classical FPGA circuit design in which two parallel filters are used in the state of the art is as in Figure-1 . The operation mode of the invention is explained for the two filters with 16 coefficients on Figure-2. The filter coefficients are divided into 4 coefficient groups (10). These groups are as follows, from left to right:

- Group-1 (G1): Indexes with filter coefficients A and B of -1 (S1 , S10, S12, S13, S14)

- Group-2 (G2): Indexes with filter coefficients A and B of 1 (S3, S4, S7, S8)

- Group-3 (G3): Indexes with filter coefficient B of 1 while A filter coefficient is -1 (S2, S5, S 11 , S 16)

- Group 4 (G4): Indexes with filter coefficient B of -1 while A filter coefficient is 1 (S6, S9, S15).

The input signal S (6) is transferred to each delay block (3) by delay block connections (5), in such a way that the order of the coefficients does not change. Here, the grouped filter coefficients (8) are formed by combining the two filter coefficients. In this sequence, the multiplication operations (1) performed by the multiplier blocks (1) are combined. Because all the signal parts in a group will be multiplied by the same numbers with the determination of the coefficient groups (10). In this way, the addition operations performed with the adder block (2) are also combined (D). In groups where the coefficients of the two filters are different (G3 and G4 groups), after the signal is multiplied by a single number and added, while the obtained value is added directly to one filter result, it is added to the other filter result by multiplying by -1. The filtering results are obtained by filtering result A (7) and filtering result B (9). In this way, the result in Figure-1 , which shows the invention in Figure-2 and the design in the state of the art, is obtained by using less resource.

The inventive grouping method can be used for a larger number of parallel filters. In this case, the number of groups increases as pow (2, N). Flere N is the total number of filters. If the filters are binary, the number of multipliers can be further reduced. In Figure 2, complex filters depending on time can be used. If the filters are not complex, the structure in Figure-3 will further reduce the number of multipliers.

Although different numbers of multiplier and adder circuit elements are used in Figure-1 and Figure-2, the obtained correlation results (filter results) are the same. Likewise, if the filters are binary and real, the filter result obtained as a result of Figure-3 will be equal to the other two filters. In this context, the invention has provided the result of performing the same filtering processes by using less circuit elements.

Claims

1. A system that enables more efficient use of system resources by combining filters during the use of FPGA circuits in hardware signal filtering processes, characterized by comprising, the following;

• A multiplier block (1) for multiplying two digital signals on the FPGA,

• An adder block (2) for summing two digital signals on the FPGA,

• A delay block (3) for allowing a digital signal on the FPGA to be transferred to the next block with a one-unit delay,

• A delay block connection (5) providing the connection between said delay blocks (3),

• Coefficient groups (10) in which the digital signal values multiplied by the grouped filter coefficients (8) grouped according to the values of the filter coefficients in the same indices are added, and each group result is added to a different filter result directly or reciprocally (multiplied by -1).

2. A method that enables more efficient use of system resources by combining filters during the use of FPGA circuits in hardware signal filtering processes, characterized by comprising, the following steps;

• creating coefficient groups (10) by grouping delay blocks (3) according to filter coefficients,

• S signal (6), which is an input signal, entering the system through delay blocks (3) connected to each other with delay block connections (5) and ranking in front of the grouped coefficients,

• multiplying the elements in each coefficient group (10) using only one multiplier block (1) for the two filters,

• adding each coefficient group (10) directly with the adder block (2) since each of it has the same coefficient in itself,

• reversing the results collected according to the group coefficients, depending on the coefficient equivalent of the filter in the relevant coefficient group (10),

• summation of coefficient group (10) results with an adder block (2) for conversion to filter results.