WO2022241125A9 - Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers - Google Patents
Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers Download PDFInfo
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- WO2022241125A9 WO2022241125A9 PCT/US2022/029008 US2022029008W WO2022241125A9 WO 2022241125 A9 WO2022241125 A9 WO 2022241125A9 US 2022029008 W US2022029008 W US 2022029008W WO 2022241125 A9 WO2022241125 A9 WO 2022241125A9
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8416—Electrodes adapted for supplying ionic species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- the implementations of the disclosure relate generally to resistive random-access memory (RRAM) devices and, more specifically, to RRAM devices with multi-component electrodes and discontinuous interface films.
- RRAM resistive random-access memory
- a resistive random-access memory (RRAM) device is a two-terminal passive device with tunable and non-volatile resistance.
- the resistance of the RRAM device may be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying suitable programming signals to the RRAM device.
- RRAM devices may be used to form crossbar arrays that may be used to implement in-memory computing applications, nonvolatile solid-state memory, image processing applications, neural networks, etc.
- a resistive randomaccess memory (RRAM) device may include a first electrode, a first interface layer fabricated on the first electrode, a switching oxide layer fabricated on the first interface layer, and a second electrode fabricated on the switching oxide layer.
- the first interface layer may include a first discontinuous film of a first material.
- the switching oxide layer may include at least one transition metal oxide. In some embodiments, the first material is more chemically stable than the at least one transition metal oxide.
- the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x ⁇ 2.0, and wherein y ⁇ 2.5.
- the first material includes at least one of AI2O3, MgO, Y2O3, or La2C>3.
- the first discontinuous film of the first material may include one or more first pores, where the switching oxide layer contacts at least a portion of the first electrode through at least one of the first pores.
- a thickness of the first interface layer is between 0.2nm and Inm.
- the second electrode may include an alloy of tantalum.
- the alloy of tantalum may further include at least one of hafnium, molybdenum, tungsten, niobium, or zirconium.
- the alloy of tantalum may include at least one of a binary alloy may include tantalum, a ternary alloy may include tantalum, a quaternary alloy may include tantalum, a quinary alloy may include tantalum, a senary alloy may include tantalum, or a high order alloy may include tantalum.
- the RRAM device further includes a second interface layer including a second discontinuous film of a second material.
- the second material is more chemically stable than the at least one transition metal oxide.
- the second electrode contacts at least a portion of the switching oxide layer.
- the second material may include at least one of AI2O3, MgO, Y2O3, or La2O3.
- a thickness of the second interface layer is between 0.2nm and Inm.
- the second electrode may include: a first layer may include a first metallic material and a second layer including a second metallic material.
- the first layer is fabricated on the switching oxide layer.
- the second layer is fabricated on the first layer.
- the first material is more chemically stable than an oxide of the first metallic material.
- the oxide of the first metallic material is more chemically stable than the at least one transition metal oxide.
- the first metallic material in the second electrode comprises at least one of Ti, Hf, or Zr.
- the second metallic material in the second electrode may include tantalum.
- a thickness of the first layer including the first metallic material is between 0.2nm and 5nm.
- One or more aspects of the present disclosure provides a method for fabricating a resistive random-access memory (RRAM) device.
- the method includes fabricating, on a first electrode of the RRAM device, a first interface layer including a first discontinuous film of a first material.
- the method also includes fabricating, on the first interface layer, a switching oxide layer including at least one transition metal oxide.
- the first material is more chemically stable than the at least one transition metal oxide.
- the method also includes fabricating, on the switching oxide layer, a second interface layer including a second discontinuous film of a second material, where the second material is more chemically stable than the at least one transition metal oxide.
- the method also includes fabricating, on the second interface layer, a second electrode.
- the first discontinuous film of the first material may include one or more pores. Fabricating, on the first interface layer, the switching oxide layer may include depositing the at least one transition metal oxide on the first electrode through one or more of the pores. Fabricating on the first electrode of the RRAM device, the first interface layer may include depositing the first material on the first electrode to form the first discontinuous film.
- an RRAM device may include the first electrode, the first interface layer fabricated on the first electrode, the switching oxide layer fabricated on the first interface layer, the second interface layer fabricated on the switching oxide layer, and the second electrode fabricated on the switching oxide layer.
- an RRAM device may include a first electrode, a switching oxide layer fabricated on the first electrode, an interface layer fabricated on the switching oxide layer, and a second electrode fabricated on the interface layer.
- the switching oxide layer may include at least one transition metal oxide.
- the interface layer may include a discontinuous film of a material that is more chemically stable than the at least one transition metal oxide.
- FIG. 1 is a schematic diagram illustrating an example of a crossbar circuit in accordance with some implementations of the disclosure.
- FIG. 2 is a schematic diagram illustrating an example of a cross-point device in accordance with some implementations of the disclosure.
- FIGS. 3A-3C, 4A-4F, 5A-5D, and 6A-6D illustrate cross-sectional views of example RRAM devices in accordance with some embodiments of the present disclosure.
- FIG. 7 is a schematic diagram illustrating cross-sectional views of a top electrode of an RRAM device in accordance with some embodiments of the present disclosure.
- FIG. 8 is an example Ellingham diagram showing chemical stability of metal oxides in accordance with some embodiments of the present disclosure.
- FIG. 9 depicts a tantalum-titanium (Ta-Ti) binary phase diagram in accordance with some embodiments of the present disclosure.
- FIG. 10 is a flow diagram illustrating a method for fabricating an RRAM device in accordance with some embodiments of the present disclosure.
- FIG. 11 is a flow diagram illustrating a method for fabricating an RRAM device in accordance with some embodiments of the present disclosure.
- FIG. 12 is a flow diagram illustrating a method for fabricating an RRAM device in accordance with some embodiments of the present disclosure.
- FIG. 13 is a flow diagram illustrating a method for fabricating a top electrode of an RRAM device in accordance with some embodiments of the present disclosure.
- FIG. 14A depicts a tantalum-hafnium (Ta-Hf) binary phase diagram in accordance with some embodiments of the present disclosure.
- FIG. 14B depicts a tantalum-tungsten (Ta-W) binary phase diagram in accordance with some embodiments of the present disclosure.
- FIG. 14C depicts a tantalum-molybdenum (Ta-Mo) binary phase diagram in accordance with some embodiments of the present disclosure.
- FIG. 14D depicts a tantalum-niobium (Ta-Nb) binary phase diagram in accordance with some embodiments of the present disclosure.
- FIG. 14E depicts a tantalum-zirconium (Ta-Zr) binary phase diagram in accordance with some embodiments of the present disclosure.
- RRAM resistive random-access memory
- An RRAM device is a two-terminal passive device with tunable resistance.
- the RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode.
- the first electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.
- the second electrode may include a reactive metal, such as tantalum (Ta).
- the electrode including the non-reactive metal is also referred to herein as the “non-reactive electrode.”
- the electrode including the reactive metal is also referred to herein as the “reactive electrode.”
- the switching oxide layer may include a transition metal oxide, such as hafnium oxide (HfOx) or tantalum oxide (TaO x ).
- the RRAM device may be in an initial state or virgin state and may have an initial high resistance before it is subject to a suitable electrical stimulation (e.g., a voltage or current signal applied to the RRAM device).
- the RRAM device may be tuned to a lower resistance state from the virgin state via a forming process or from a high-resistance state (HRS) to a lower resistance state (LRS) via a setting process.
- the forming process may refer to programming a device starting from the virgin state.
- the setting process may refer to programming a device starting from the high resistance state (HRS).
- HRS high resistance state
- the reactive metal electrode After the reactive metal electrode is deposited on the switching oxide, the reactive metal can absorb oxygen from the switching oxide layer and create oxygen vacancies in the switching oxide layer, and oxygen ions can migrate in the switching oxide through a vacancy mechanism.
- a suitable programming signal e.g., a voltage or current signal
- a conductive channel or filament may form through the switching oxide layer (e.g., from the reactive electrode to the non-reactive electrode).
- the RRAM device may then be reset to a high-resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device.
- a reset signal e.g., a voltage signal, a current signal
- the application of the reset signal to the RRAM device may cause oxygen to migrate back to the switching oxide layer and may thus interrupt the conductive filament.
- the RRAM device may be electrically switched between a high-resistance state and a low-resistance state by applying suitable programming signals (e.g., voltage signals, current signals, etc.) to the RRAM device.
- suitable programming signals e.g., voltage signals, current signals, etc.
- the programming signals may be provided to the designated RRAM device via a selector, such as a transistor.
- RRAM devices it might be desirable to scale down RRAM devices to a suitable size (e.g., a critical dimension of lOOnm, lOnm, or a smaller dimension) to implement certain in-memory computing (IMC) applications (e.g., an IMC application that requires high density RRAM devices and/or low-power consumption).
- IMC in-memory computing
- the critical dimension of a conventional RRAM device scales down, the filament formed in the conventional RRAM device may not scale down accordingly.
- the size of the filament formed in the scaled- down RRAM device may not be scaled-down proportionally. As such, forming, setting, and/or resetting such a conventional scaled-down RRAM device may still require a relatively high current or voltage.
- the scaled-down RRAM device may have a relatively smaller area of top electrode.
- the top electrode may not be able to absorb as much oxygen as that of a larger RRAM device. This may cause device failures and/or operation failures of the RRAM device.
- a device failure can be caused by delamination between the reactive electrode and the switching oxide by the presence of oxygen molecules.
- the oxygen ions may drift from the switching oxide into the top electrode under an external voltage and may migrate back to the switching oxide once the external voltage is removed, resulting in the operation to be volatile which is an operation failure for non-volatile memory.
- an RRAM device may include a bottom electrode, a first interface layer fabricated on the bottom electrode, a switching oxide layer fabricated on the first interface layer, and a top electrode fabricated on the switching oxide layer.
- the bottom electrode may include Pt or any other suitable nonactive metal.
- the switching oxide layer may include a transition metal oxide, such as HfOx, TaOx, TiOx, NbOx, ZrOx, etc.
- the first interface layer may include a discontinuous film of a first material that is more chemically stable than the transition metal oxide.
- the first material may include, for example, AI2O3, MgO, Y2O3, La2O3, etc.
- the incorporation of the first interface layer may reduce the contact area between the switching oxide layer and the first electrode, resulting in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce voltage and/or current requirements in subsequent operation processes.
- the first electrode and the switching oxide may be in full direct contact without the presence of the first interface layer.
- the first electrode does not directly contact the switching oxide with the presence of a continuous first interface layer between the first electrode and the switching oxide.
- the first electrode and the switching oxide are in reduced or controlled direct contact with the presence of a non-continuous first interface layer between the first electrode and the switching oxide.
- the RRAM device may further include a second interface layer fabricated on the switching oxide layer.
- the top electrode may be fabricated on the second interface layer.
- the second interface layer may include a discontinuous film of a second material that is more chemically stable than the transition metal oxide. The incorporation of the second interface layer may reduce the contact area between the switching oxide layer and the top electrode.
- the top electrode may include one or more multicomponent electrode structures.
- the top electrode may include one or more alloys of Ta in one implementation.
- the alloys of Ta may be and/or include a binary alloy containing Ta, a ternary alloy containing Ta, a quaternary alloy containing Ta, a quinary alloy containing Ta, a senary alloy containing Ta, and/or a high order alloy (e.g., an alloy containing more than six metallic elements) containing Ta.
- Each of the alloys may include Ta and one or more other metallic elements that have required thermodynamic and/or kinetic properties than Ta, such as tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc.
- fabricating the top electrode using an alloy of Ta instead of pure Ta metal may reduce the migration of Ta into the switching oxide layer during the forming process and may thus reduce the size of the filament formed in the switching oxide layer (e.g., by reducing the lateral dimension or diameter of the filament).
- the RRAM device incorporating the multi-component electrode structure may present dynamic memristive behavior in multiple dimensions suitable for implementing dynamic learning, edge processing, inference engine accelerators, and other IMC applications.
- the top electrode may include multiple layers of different metallic materials.
- the top electrode may include a layer of titanium (Ti) and a layer of tantalum (Ta).
- the layer of Ti may be much thinner than the layer of Ta.
- a thickness of the layer of Ti may be between about 0.2nm and 5nm.
- a thickness of the layer of Ta may be about 50nm.
- the thickness of the layer of Ti may be between 0.3nm and 2nm. Both Ti and Ta may trap and release oxygen during device operations.
- the incorporation of the thin Ti layer into the RRAM device may change the virgin resistance of the RRAM device, result in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce voltage and/or current requirements in subsequent operation processes.
- the present disclosure provides techniques for fabricating RRAM devices with high filament resistance and reduced operation voltages and currents.
- the RRAM devices also present desirable linearity, analog, retention, and endurance etc. behaviors for IMC applications.
- the incorporation of the first interface layer and/or the second interface layer may reduce the contact between the switching oxide layer and the bottom electrode and/or the contact between the switching oxide layer and the top electrode.
- the techniques may enable efficient scaling down of RRAM devices and low-power consumption IMC applications utilizing RRAM devices.
- FIG. 1 is a schematic diagram illustrating an example 100 of a crossbar circuit in accordance some embodiments of the present disclosure.
- crossbar circuit 100 may include a plurality of interconnecting electrically conductive wires, such as one or more row wires Illa, 111b, . . ., Illi, . . ., 11 In, and column wires 113a, 113b, . . ., 113j, . . ., 113m for an n-row by m-column crossbar array.
- the crossbar circuit 100 may further include cross-point devices 120a, 120b, . . ., 120z, etc.
- Each of the cross-point devices may connect a row wire and a column wire.
- the cross-point device 120ij may connect the row wire Illi and the column wire 113j .
- crossbar circuit 100 may further include digital to analog converters (DAC, not shown), analog to digital converters (ADC, not shown), switches (not shown), and/or any other suitable circuit components for implementing a crossbar-based apparatus.
- DAC digital to analog converters
- ADC analog to digital converters
- switches not shown
- any other suitable circuit components for implementing a crossbar-based apparatus.
- the number of the column wires 113a-m and the number of the row wires 11 la-n may or may not be the same.
- Row wires 111 may include a first row wire 11 la, a second row wire 111b, . . ., 11 li, . . ., and a n-th row wire 11 In.
- Each of row wires 11 la, . . ., 11 In may be and/or include any suitable electrically conductive material.
- each row wire 11 la-n may be a metal wire.
- Column wires 113 may include a first column wire 113a, a second column wire 113b, . . ., and an m-th column wire 113m.
- Each of column wires 113a-m may be and/or include any suitable electrically conductive material.
- each column wire 113a-m may be a metal wire.
- Each cross-point device 120 may be and/or include any suitable device with tunable resistance, such as a memristor, pulse-code modulation (PCM) devices, floating gates, spintronic devices, RRAM, static random-access memory (SRAM), etc.
- PCM pulse-code modulation
- RRAM static random-access memory
- one or more of cross-point devices 120 may include an RRAM device as described in connection with FIGS. 3A-5B.
- Crossbar circuit 100 may perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal may be applied to one or more rows of crossbar circuit 100 (e.g., one or more selected rows). The input signal may flow through the cross-point devices of the rows of the crossbar circuit 100. The conductance of the cross-point device may be tuned to a specific value (also referred to as a “weight”). By Ohm’s law, the input voltage multiplies the cross-point conductance generates a current form the cross-point device. By Kirchhoff’ s law, the summation of the current passing the devices on each column generates the current as the output signal, which may be read from the columns (e.g., outputs of the ADCs).
- the input signal is weighted at each of the cross-point devices by its conductance according to Ohm’ s law.
- the weighted current is outputted via each column wire and may be accumulated according to Kirchhoff’s current law. This may enable inmemory computing (IMC) via parallel multiplications and summations performed in the crossbar arrays.
- IMC inmemory computing
- FIG. 2 is a schematic diagram illustrating an example 200 of a cross-point device in accordance some embodiments of the present disclosure.
- cross-point device 200 may connect a bitline (BE) 211, a select line (SEL) 213, and a wordline (WE) 215.
- BE bitline
- SEL select line
- WE wordline
- the bitline 211 and the wordline 215 may be a column wire and a row wire as described in connection with FIG. 1 , respectively.
- Cross-point device 200 may include an RRAM device 201 and a transistor 203.
- a transistor is a three-terminal device, which may be marked as gate (G), source (S), and drain (D), respectively.
- the transistor 203 may be serially connected to RRAM device 201. As shown in FIG. 2, the first electrode of the RRAM device 201 may be connected to the drain of transistor 203. The second electrode of the RRAM device 201 may be connected to the bitline 211. The source of the transistor 203 may be connected to the wordline 215. The gate of the transistor 203 may be connected to the select line 213.
- RRAM device 201 may include one or more RRAM devices as described in connection with FIGS. 3A-7 below.
- Cross-point device 200 may also be referred to as in a 1-transitor-l -resistor (1T1R) configuration.
- the transistor 203 may perform as a selector as well as a current controller, which may set the current compliance, to the RRAM device 201 during programing.
- the gate voltage on transistor 203 can set current compliances to cross-point device 200 during programming and can thus control the conductance and analog behavior of cross-point device 200.
- a set signal e.g., a voltage signal, a current signal
- BL bitline
- Another voltage also referred as a select voltage or gate voltage, may be applied via the select line (SEL) 213 to the transistor gate to open the gate and set the current compliance, while the wordline (WL) 215 may be set to ground.
- SEL select voltage
- WL wordline
- a gate voltage may be applied to the gate of the transistor 203 via the select line 213 to open the transistor gate.
- a reset signal may be sent to the RRAM device 201 via the wordline 215, while the bitline 211 may be set to ground.
- FIGS. 3A, 3B, and 3C illustrate cross-sectional views of example RRAM devices in accordance with some embodiments of the present disclosure.
- RRAM devices 300a, 300b, and 300c may correspond to an RRAM device in an initial state, a low-resistance state, and a high-resistance state, respectively.
- RRAM device 300a may include a substrate 310, a first electrode 320, a switching oxide layer 330, and a second electrode 340. RRAM device 300a may further include one or more other components for implementing in-memory computing applications.
- Substrate 310 may include one or more layers of any suitable material that may serve as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (SisN4), aluminum oxide (AI2O3), aluminum nitride (AIN), etc.
- substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc.
- the substrate may include a driving circuit including one or more electrical circuits (e.g., an array of electrical circuits) that may be individually controllable.
- the driving circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.
- CMOS complementary metal-oxide-semiconductor
- First electrode 320 may be and/or include any suitable material that is electronically conductive and non-reactive to the switching oxide.
- first electrode 320 may include platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc.
- Switching oxide layer 330 may include one or more transition metal oxides, such as TaOx, HfO x , TiO x , NbOx, ZrOx, etc., in binary oxides, ternary oxides, and high order oxides.
- the chemical stability of the non-reactive material in first electrode 320 may be higher than that of the transition metal oxide(s) in switching oxide layer 330.
- Second electrode 340 may include any suitable metallic material that are electronically conductive and reactive to the switching oxide.
- the metallic material in second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc.
- Second electrode 340 may be reactive to the switching oxide and may have suitable oxygen solubility to adsorb some oxygen from the switching oxide layer 330 and create oxygen vacancies in the switching oxide layer 330.
- the reactive metallic material(s) in second electrode 340 may have suitable oxygen solubility and/or oxygen mobility.
- second electrode 340 not only may be able to create oxygen vacancies in switching oxide layer 330 (e.g., by scavenging oxygen), but also may function as oxygen reservoir or source to the switching oxide layer 330 during cell programming.
- RRAM device 300a may have an initial resistance (also referred to herein as the “virgin resistance”) after it is fabricated.
- the initial resistance of RRAM device 300a may be changed and RRAM device 300a may be switched to a state of a lower resistance via a forming process.
- a suitable voltage or current may be applied to RRAM device 300a.
- the application of the voltage to RRAM device 300a may induce the metallic material(s) in the second electrode to absorb oxygen from the switching oxide layer 330 and create oxygen vacancies in the switching oxide layer 330.
- a conductive channel e.g., a filament which is oxygen vacancy rich may form in the switching oxide layer 330.
- a conductive channel e.g., a filament
- a conductive channel 335a may be formed in the switching oxide layer 330. As shown, conductive channel 335a may be formed from the second electrode 340 to the first electrode 320 across the switching oxide layer 330.
- RRAM device 300b may be reset to a high-resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) may be applied to RRAM device 300b during a reset process.
- the set signal and the reset signal may have opposite polarity, i.e., a positive signal and a negative signal, respectively. The application of the reset signal may cause oxygen to drift back to the switching oxide layer 330 and recombine with one or more of the oxygen vacancies.
- an interrupted conductive channel 335b as shown in FIG. 3C may be formed in the switching oxide layer 330 during the reset process.
- the conductive channel may be interrupted with an oxide gap between the interrupted conductive channel 335b and the first electrode 320.
- the lateral dimension of conductive channel 335b may be smaller than that of the conductive channel 335a.
- conductive channel 335b does not continuously connect the first electrode 320 and the second electrode 340.
- RRAM device 300a-c may be electrically switched between the high-resistance state and the low-resistance state by applying suitable programming signals (e.g., voltage signals, current signals, etc.) to the RRAM device.
- FIGS. 4A-4F are schematic diagrams illustrating cross-sectional views of example structures 400a, 400b, 400c, 400d, 400e, and 400f of RRAM devices in accordance with some embodiments of the present disclosure.
- a first electrode 420 may be fabricated on a substrate 410.
- the first electrode 420 and the substrate 410 may correspond to the first electrode 320 and the substrate 310 as described in conjunction with FIGS. 3A, 3B, and 3C, respectively.
- an interface layer 422 may be fabricated on the first electrode 420.
- the interface layer 422 (also referred to herein as the “first interface layer”) may be and/or include a discontinuous film 422a.
- the discontinuous film 422a may include one or more pores 424.
- the pore(s) 424 (also referred to herein as the “first pores”) may have any suitable size and/or dimension and may be dispersed randomly on the interface layer 422. While certain number of pores are illustrated in FIG. 4B, this is merely illustrative.
- the discontinuous film 422a may include any suitable number of pores.
- a thickness of the interface layer 422 and/or the discontinuous film 422a may be between about 0.2nm and about 0.5nm.
- the discontinuous film 422a may be an AI2O3 film having a thickness equal to or less than 0.5nm.
- the discontinuous film 422a may be and/or include an AI2O3 film having a thickness less than Inm.
- a switching oxide layer 430 may be fabricated on the interface layer 422.
- the switching oxide layer 430 may include one or more transition metal oxides, such as TaO x , HfO x , TiO x , NbOx, ZrOx, etc., in binary oxides, ternary oxides, and high order oxides, wherein x may be used to indicate the oxide being oxygen deficient compared to its full (or terminal) oxide and the value of x may be varied from the oxygen to metal atomic ratio in the stoichiometry of its full oxide, such as x ⁇ 2.0 for HfOx (where HfCh being the full oxide), and x ⁇ 2.5 for TaOx (where Ta2Os being the full oxide).
- the switching oxide layer 430 may include Ta2Os. As the other example, the switching oxide layer 430 may include Hl'Cb. [0061] In some embodiments, during the fabrication of the switching oxide layer 430, one or more portions of the transition metal oxides may be disposed on the first electrode 420 through one or more pores 424. As such, the switching oxide layer 430 may contact one or more portions of the first electrode 420.
- the interface layer 422 may contain a first material that is more chemically stable than the transition metal oxide(s) in the switching oxide layer 430.
- the first material may not react with the transition metal oxide(s) of the switching oxide layer 430.
- the first material may include a metallic element that is univalent.
- the switching oxide of the switching oxide layer may be and/or include one or more transition metal oxides, such as at least one of HfO x or TaO y , wherein x ⁇ 2.0, and wherein y ⁇ 2.5, and the first material may include AI2O3, MgO, Y2O3, La2O3, etc.
- an Ellingham diagram 800 plots the Gibbs free energy change for an oxidation reaction as a function of temperature.
- the chemical stability of the materials may be determined based on the Gibbs formation energy values of the materials.
- the Gibbs free energy shown on the vertical axis in FIG. 8 represents the free energy of formation of an oxide (containing 1 mole of oxygen) and the horizontal- axis represents the temperature in Kelvin.
- the relative stability of these oxides increases from Ta2Os, TiO2, HfO2to AI2O3.
- AI2O3 is more stable than HfO2 at room temperature.
- the curve of the material of the interface layer 422 may be below the curve corresponding to the transition metal oxide(s) of the switching oxide layer 430.
- AI2O3 may be used as the first material in some embodiments in which the transition metal oxide in the switching oxide layer 430 contains HfO2 or Ta2Os. The first material containing AI2O3 does not react with the transition metal oxide containing HfO2 or Ta2Os during the setting process and resetting process.
- a second electrode 440 may be fabricated on the switching oxide layer 430.
- the second electrode 440 may include one or more top electrodes 700 as described in connection with FIG. 7.
- the second electrode 440 fabricated on the switching oxide layer 430 may include one or more alloys. Each of the alloys may contain two or more metallic elements.
- Each of the alloys may include a binary alloy (e.g., an alloy containing two metallic elements), a ternary alloy (e.g., an alloy containing three metallic elements), a quaternary alloy (e.g., an alloy containing four metallic elements), a quinary alloy (e.g., an alloy containing five metallic elements), a senary alloy (e.g., an alloy containing six metallic elements), and/or a high order alloy (e.g., an alloy containing more than six metallic elements).
- the second electrode 440 may include one or more alloys containing a first metallic element and one or more second metallic elements. Each of the second metallic elements may be less or more reactive to the transition metal oxide in the switching oxide layer than the first metallic element.
- the first metallic element may be Ta.
- the second metallic elements may include one or more of W, Hf, Mo, Nb, Zr, etc.
- the ratio of the first metallic element to the second metallic element(s) in an alloy in the second electrode 340 may be about 50 atomic percent.
- the suitable ratio of the first metallic element to the second metallic element in the alloy may be optimized from the entire composition range.
- the second metallic element(s) may create fewer oxygen vacancies in the switching oxide layer than the first metallic element.
- the lateral size of the filament formed in an RRAM device comprising a second electrode containing the alloy may be smaller than that of the filament formed in an RRAM device comprising a second electrode made of only the first metal.
- the implementation of alloy containing Ta in the second electrode 440 in the RRAM device may result in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce voltage and/or current requirements in subsequent operation processes.
- the second electrode 440 may include one or more alloys containing Ta (also referred to as “Ta alloys”). Each of the Ta alloys may include Ta and one or more other metallic elements (e.g., Hf, W, Mo, Nb, Zr, etc.). As an example, the second electrode 440 may include one or more binary alloys containing Ta. Examples of the binary alloys containing Ta include a Ta-Hf alloy, a Ta-W alloy, a Ta-Mo alloy, a Ta-Nb alloy, a Ta-Zr alloy, etc. As another example, the second electrode 440 may include one or more ternary alloys containing Ta.
- the ternary alloys containing Ta include a Ta-Hf-Mo alloy, a Ta-Hf- Nb alloy, a Ta-Hf-W alloy, a Ta-Hf-Zr alloy, a Ta-Mo-Nb alloy, a Ta-Mo-W alloy, a Ta-Mo-Zr alloy, a Ta-Nb-W alloy, a Ta-Nb-Zr alloy, a Ta-W-Zr alloy, etc.
- the second electrode 440 may include one or more quaternary alloys containing Ta.
- the quaternary alloys containing Ta include a Ta-Hf-Mo-Nb alloy, a Ta-Hf-Mo-W alloy, a Ta-Hf- Mo-Zr alloy, a Ta-Hf-Nb-W alloy, a Ta-Hf-Nb-Zr alloy, a Ta-Mo-Nb-W alloy, a Ta-Mo-Nb-Zr alloy, a Ta-Nb-W-Zr alloy, etc.
- the second electrode 440 may include one or more quinary alloys containing Ta.
- the quinary alloys containing Ta include a Ta-Hf-Mo-Nb-W alloy, a Ta-Mo-Nb-W-Zr alloy, a Ta-Hf-Nb-W-Zr alloy, a Ta-Hf-Mo-W-Zr alloy, a Ta-Hf-Mo-Nb-Zr alloy, etc.
- the second electrode 440 may include a senary alloy containing Ta, such as a Ta-Hf-Mo-Nb-W-Zr alloy.
- the second electrode 440 may include a high order alloy containing Ta. In some embodiments, the high order alloy may further contain vanadium (V).
- the second electrode 440 may include a plurality of alloys.
- Each of the alloys may be a Ta alloy containing Ta and one or more other metallic elements (e.g., Hf, W, Mo, Nb, Zr, etc.).
- the Ta alloy may be and/or include a binary alloy, a ternary alloy, a quaternary alloy, a quinary alloy, a senary alloy, a high-order alloy, etc.
- the second electrode 440 may include two or more of a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a sixth alloy containing Ta.
- the first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta, and the sixth alloy containing Ta may be a binary alloy, a ternary alloy, a quaternary alloy, a quinary alloy, a senary alloy, and a high-order alloy, respectively.
- the first alloy containing Ta and the second alloy containing Ta may include a first binary alloy containing Ta (e.g., a Ta-W alloy) and a second binary alloy containing Ta (e.g., a Ta-Mo alloy), respectively.
- the first alloy containing Ta and the second alloy containing Ta may include a first ternary alloy containing Ta (e.g., a Ta-Hf-Mo alloy) and a second ternary alloy containing Ta (e.g., a Ta-Hf-Nb alloy), respectively.
- the second electrode 440 may include a plurality of alloy systems.
- Each of the alloy systems may contain the alloys containing the mixtures of certain metallic elements with varying compositions.
- a binary system may include one or more binary alloys of two metallic elements (e.g., Ta and Hf) with varying compositions. Each of the binary alloys may be a combination of the two metallic elements with a certain composition.
- a ternary system may include one or more ternary alloys of three metallic elements (e.g., Ta, Hf, and W) with varying compositions. Each of the ternary alloys may be a combination of the three metallic elements with a certain composition.
- the second electrode 440 may include a Ta alloy system containing one or more alloy systems.
- the Ta alloy system may include two or more alloy systems.
- the Ta alloy system may contain a senary system containing one or more alloys of Ta, Hf, W, Mo, Nb, and Zr.
- the Ta alloy system may further include one or more binary systems, ternary systems, quaternary systems, and/or quinary systems containing Ta alloys.
- the binary systems may include one or more of a Ta-Hf alloy system, a Ta-W alloy system, a Ta-Mo alloy system, a Ta-Nb alloy system, and/or a Ta-Zr alloy system.
- the ternary systems may include one or more of a Ta-Hf- Mo alloy system, a Ta-Hf- Nb alloy system, a Ta-Hf-W alloy system, a Ta-Hf-Zr alloy system, a Ta-Mo-Nb alloy system, a Ta- Mo-W alloy system, a Ta-Mo-Zr alloy system, a Ta-Nb-W alloy system, a Ta-Nb-Zr alloy system, and/or a Ta-W-Zr alloy system.
- the quaternary systems may include one or more of a Ta-Hf-Mo-Nb alloy system, a Ta-Hf-Mo-W alloy system, a Ta-Hf-Mo-Zr alloy system, a Ta-Hf- Nb-W alloy system, a Ta-Hf-Nb-Zr alloy system, a Ta-Mo-Nb-W alloy system, a Ta-Mo-Nb-Zr alloy system, a Ta-Nb-W-Zr alloy system.
- the quinary systems may include one or more of a Ta-Hf-Mo-Nb-W alloy system, a Ta-Mo-Nb-W-Zr alloy system, a Ta-Hf-Nb-W-Zr alloy system, a Ta-Hf-Mo-W-Zr alloy system, and/or a Ta-Hf-Mo-Nb-Zr alloy system.
- Each of the alloy systems contained in the second electrode 440 may have unique thermodynamic and kinetic characteristics and may be regarded as an electrode component.
- the second electrode 440 may include multiple electrode components for providing multiple state variables that may lead to rich dynamics with various time constants for computing and learning. For example, each electrode component may have different reactivity to the switching oxide or the affinity for oxygen.
- Each electrode element may have different diffusivity (e.g., self-diffusion, interdiffusion, diffusion time constants, etc.).
- the second electrode 440 with multiple components may provide the multiple dynamic behavior for IMC applications.
- the RRAM device incorporating the multi-component second electrode may present dynamic memristive behavior in multiple dimensions.
- FIGS. 4E and 4F illustrate semiconductor devices 400e and 400f that may correspond to a low-resistance state and a high-resistance state of the RRAM device 400d, respectively.
- the incorporation of the discontinuous film 422 may reduce the contact area between the switching oxide layer 430 and the first electrode 420.
- a conductive channel 435a e.g., a filament
- an interrupted conductive channel 435b may be formed in the switching oxide layer 430 during the reset process.
- the lateral size of the conductive channel 435a and the interrupted conductive channel 435b may be smaller than that of 335a and 335b respectively.
- the lateral size of the filament formed in an RRAM device with discontinuous film 422 may be smaller than that of the filament formed in an RRAM device without a porous and/or discontinuous film formed between the first electrode and the switching oxide layer.
- the incorporation of the discontinuous film 422 into the RRAM device may result in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce voltage and/or current requirements in subsequent operation processes.
- an RRAM device may include multiple interface layers fabricated between the first electrode and the second electrode. Each of the interface layers may include a discontinuous film as described in connection with FIG. 4B.
- a semiconductor device 500a may be fabricated, by fabricating an interface layer 532 (also referred to as the “second interface layer”) on the semiconductor structure 400c as described in connection with FIG. 4C.
- the second interface layer 532 may include a discontinuous film 532a of a second material.
- the second material may be more chemically stable than the at least one transition metal oxide in the switching oxide layer 430.
- the second material may include AI2O3, MgO, Y2O3, La2O3, etc.
- the second material may or may be the same as the first material.
- the discontinuous film 532a may include one or more pores 534 (also referred to as the “one or more second pores”).
- the pore(s) 534 may have any suitable size and/or dimension. Multiple pores 534 may or may not have the same size and/or dimension.
- the second interface layer 532 and/or the second discontinuous film 532a may include multiple pores 534 dispersed randomly on the second discontinuous film 532.
- the discontinuous film 532a may include any suitable number of pores.
- a thickness of the second interface layer 532 and/or the second discontinuous film may be between about 0.2 nm and about 0.5 nm.
- the second interface layer 532 may include a discontinuous AI2O3 film having a thickness equal to or less than 0.5 nm.
- the second interface layer 532 may include a discontinuous AI2O3 film having a thickness less than Inm.
- the second thickness of the second interface layer 532 may or may not be the same as the first thickness of the first interface layer 422.
- a second electrode 540 may be fabricated on the second interface layer 532 to fabricate a semiconductor device 500b.
- the second interface layer 532 may thus be positioned between the switching oxide layer 430 and the second electrode 540.
- the second electrode 540 may be and/or include the second electrode 440 as described in conjunction with FIGS. 4D-4F.
- one or more portions of the second electrode 540 may be disposed on the switching oxide layer 430 through one or more pores 534. As such, the second electrode 540 may contact one or more portions of the switching oxide layer 430 through the one or more pores 534.
- FIGS. 5C and 5D illustrate semiconductor devices 500c and 500d that may correspond to a low-resistance state and a high-resistance state of the RRAM device 500b, respectively.
- the incorporation of both the first interface layer 422 and the second interface layer 532 may further reduce the contact area between the switching oxide layer 430 and the first electrode 420 and the contact area between the switching oxide layer 430 and the second electrode 540.
- a conductive channel 535a e.g., a filament
- FIG. 5C e.g., a filament
- an interrupted conductive channel 535b may be formed in the switching oxide layer 530 during the reset process.
- the lateral size of the conductive channel 535a and the interrupted conductive channel 535b may be further smaller than that of 335a and 335b, respectively.
- the lateral size of the filament formed in an RRAM device with both the interface layer 422 and the second interface layer 532 may be further reduced, resulting in a less abrupt forming process, reducing the forming voltage, reducing the reset current, and reducing voltage and/or current requirements in subsequent operation processes.
- an interface layer may be fabricated on a switching oxide layer of an RRAM device in accordance with some embodiments of the present disclosure.
- a switching oxide layer 630 may be fabricated on the semiconductor device 400a as described in FIG. 4A.
- An interface layer 632 may be fabricated on the switching oxide layer 630 to fabricate a semiconductor device 600a.
- the switching oxide layer 630 may be and/or include the switching oxide layer 430 as described in conjunction with FIGS. 4C-4F.
- the interface layer 632 may include a discontinuous film of a third material.
- the third material may be more chemically stable than the at least one transition metal oxide in the switching oxide layer 630.
- the third material may include AI2O3, MgO, Y2O3, La2O3, etc.
- the discontinuous film 632a may include one or more pores 634 (also referred to herein as the “one or more third pores”).
- the pore(s) 634 may have any suitable size and/or dimension and may be dispersed randomly on the interface layer 632.
- a thickness of the interface layer 632 (also referred to as the “third thickness”) may be between about 0.2 nm and about 0.5 nm.
- the interface layer 632 may have a thickness equal to or less than 0.5 nm thickness.
- the interface layer 632 may have a thickness less than 1 nm.
- a second electrode 640 may be fabricated on the interface layer 632 to fabricate a semiconductor device 600b.
- the interface layer 632 may thus be positioned between the switching oxide layer 630 and the second electrode 640.
- the second electrode 640 may be and/or include the second electrode 440 as described in conjunction with FIGS. 4D-4F.
- one or more portions of the second electrode 640 may be disposed on the switching oxide layer 630 through one or more pores 634. As such, the second electrode 640 may contact one or more portions of the switching oxide layer 630.
- FIGS. 6C and 6D illustrate semiconductor devices 600c and 600d that may correspond to a low-resistance state and a high-resistance state of the RRAM device 600b, respectively.
- the incorporation of the discontinuous film 632 may reduce the contact area between the switching oxide layer 630 and the second electrode 640.
- a conductive channel 635a e.g., a filament
- an interrupted conductive channel 635b may be formed in the switching oxide layer 630 during the reset process.
- the lateral size of the conductive channel 635a and the interrupted conductive channel 635b may be smaller than that of 335a and 335b respectively.
- the lateral size of the filament formed in an RRAM device with a discontinuous film 632 may be smaller than that of the filament formed in an RRAM device without the discontinuous film 632.
- the incorporation of a discontinuous film 632 into the RRAM device may result in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce voltage and/or current requirements in subsequent operation processes.
- FIG. 7 is a schematic diagram illustrating cross-sectional views of an example 700 of a top electrode in accordance with some embodiments of the present disclosure.
- the top electrode 700 may include a first layer 710 and a second layer 720.
- the first layer 710 may include a first metallic material that may scavenge oxygen from the transition metal oxide(s) of the switching oxide layer.
- the second layer 720 may include a second metallic material that may scavenge oxygen from the transition metal oxide(s) of the switching oxide layer.
- the oxide of the first metallic material may have greater chemical stability than the transition metal oxide(s) of the switching oxide layer. As a result, the first metallic material may react with and scavenge oxygen from the transition metal oxide(s) of the switching oxide layer.
- the oxide of the first metallic material may have less chemical stability than the first material of the first discontinuous film and the second material of the second discontinuous film. As a result, the first metallic material may not chemically reduce the first discontinuous film and the second discontinuous film.
- the Ellingham diagrams may be employed to determine the comparative chemical stability of two or more elements.
- the first metallic material and the second metallic material may include different chemical elements and may have different affinities for oxygen and/or different thermodynamic and kinetic properties.
- the first metallic material and the second metallic material may be immiscible.
- the first metallic material may include Ti.
- the second metallic material may include Ta.
- the first layer 710 may be and/or include a layer of Ti metal (e.g., a Ti film).
- the second layer 720 may be and/or include a layer of Ta metal (e.g., a Ta film). As shown in the Ta-Ti binary phase diagram of FIG.
- Ta and Ti phases are immiscible and have minimum mutual solubilities at 300K (27°C) which is around the operating temperatures of RRAM devices (e.g., temperatures around, below, or above room temperature).
- the addition of Ti into the RRAM device may not affect the operation mechanism of the Ta filament in the switching oxide and the switching mechanism of RRAM devices as described herein.
- the RRAM devices as described in FIG. 7 may thus be used for IMC applications that require RRAM devices with excellent performance in analog behaviors, linearity, retention, reliability, etc.
- the immiscibility and minimum mutual solubilities between Ta and Ti phases may also enable a thermodynamic equilibrium between the second layer 720 and the first layer 710. As a result, a thin Ti film can function as designed without reacting with the Ta film or being dissolved by the Ta film.
- Ti may readily scavenge oxygen from the switching oxide because it has higher affinity for oxygen than Ta.
- the incorporation of the first layer 710 into the RRAM device may further improve the performance of the RRAM device by reducing the forming voltage required in the RRAM forming process and the current and voltage requirements in subsequent operations.
- the second electrode 440 in FIGS. 4D-4F, the second electrode 540 in FIGS.5B-5D, and/or the second electrode 640 in FIGS. 6B-6D as described above may be and/or include the second electrode 700.
- both the first metallic material and the second metallic material may generate oxygen vacancies in the switching oxide layer 330, 430, and/or 630. Compared with FIGS.
- the lateral size of the conductive channel and the interrupted conductive channel may be smaller than that of 335a and 335b, respectively.
- the virgin resistance of an RRAM device including the top electrode 700 may be lower than that of an RRAM device that does not include the top electrode 700, resulting in the lower forming voltage, the lower reset voltage, the low reset current, etc.
- Ti may also readily store oxygen during a set process (when oxygen is migrating from switching oxide to the second electrode). This may enable the second electrode to store oxygen during the reset process and may thus prevent device failures (which can be caused by the presence of oxygen molecules between switching oxide and the second electrode) and/or operation failures (which can be caused by the oxygen migrating back to the switching oxide once the reset voltage being remove, or the switch being volatile).
- the first layer 710 may be grown to a suitable thickness so that the first metallic material (e.g., Ti) of the first layer 710 may function as described above without affecting the formation of the filament comprising the second metallic material (e.g., a Ta filament) in the switching oxide layer 330.
- a thickness of the first layer 710 may be between about 0.2nm and about 5nm.
- a thickness of the first layer 710 may be between about 0.5nm and about 2nm.
- a thickness of the first layer 710 may be about Inm.
- a thickness of the first layer 710 may be less than Inm.
- the second layer 720 may be thicker than the first layer 710.
- a thickness of the second layer 720 may be between 5nm and 300nm.
- the thickness of the second layer 720 may be between about lOnm and about lOOnm.
- the thickness of the second layer 720 may be between about lOnm and about 200nm.
- the thickness of the second layer 720 may be about 50nm.
- a thickness of the first electrode may be between about 5nm and lOOnm.
- the thickness of the first electrode may be about 30nm.
- a dimension (e.g., a critical dimension) of RRAM device 400d, 500b, and/or 600b may be between 1pm and single digit nanometers.
- the critical dimension of RRAM device 400d, 500b, and/or 600b may be about or less than 0.28 pm, and/or between 1pm and 1 nanometer. In some embodiments, the critical dimension of RRAM device 400d, 500b, and/or 600b may be between 1pm and 2nm. In some embodiments, the critical dimension of RRAM device 400d, 500b, and/or 600b may be between 1pm and 5nm. In some embodiments, the critical dimension of RRAM device 400d, 500b, and/or 600b may be at the single-digit nanoscale (e.g., between about Inm and about 9nm).
- the second layer 720 may be fabricated directly on the first layer 710. For example, as shown in FIG. 7, a surface of the second layer 720 may directly contact one or more portions of a surface of the first layer 710. In another implementation, one or more other layers of suitable materials may be deposited between the first layer 710 and the second layer 720.
- the incorporation of the first layer 710 in RRAM device may reduce the virgin resistance of the RRAM device, reduce the forming voltage, and reduce the reset current, resulting in a less abrupt forming process, a filament with lower conductance, and lower voltage and current in the subsequent operation process.
- RRAM devices 400d-f, 500b-d, and 600b-d may include one or more other layers of suitable materials for implementing IMC applications.
- RRAM devices 400d-f, 500b-d, and 600b-d may include one or more other layers of suitable materials for implementing IMC applications.
- one or more interfacial layers may be fabricated between the switching oxide layer and one or more of the second electrode and the first electrode to improve the interface stability and device performance.
- FIG. 10 is a flow diagram illustrating an example 1000 of a method for fabricating an RRAM device according to some embodiments of the disclosure.
- a first electrode may be fabricated on a substrate. Fabricating the first electrode may involve depositing one or more layers of one or more nonactive metals, such as Pt, Pd, Ir, etc. utilizing a physical vapor deposition (PVD) technique, a chemical vapor deposition (CVD) technique, a sputtering deposition technique, an atomic layer deposition (ALD) technique, and/or any other suitable deposition technique. In some embodiments, fabricating the first electrode may involve depositing one or more layers of Pt. The first electrode may be and/or include first electrode 320, 420 as described in connection with FIGS. 3A-6D above.
- an interface layer may be fabricated on the first electrode. Fabricating the interface layer may involve depositing a first material on the first electrode to form a first discontinuous film of the first material.
- the first discontinuous film may contain one or more first pores.
- the first material may be more chemically stable than the transition metal oxide(s) in the switching oxide layer as described below.
- the first material may include AI2O3, MgO, Y2O3, La2O3, etc.
- the interface layer may be and/or include the first interface layer 422 as described in connection with FIGS. 4B-5D above in some embodiments.
- fabricating the interface layer may involve depositing a layer of the first material having a suitable thickness to form the first discontinuous film. For example, fabricating the first interface layer may involve depositing the first material to a thickness between about 0.2nm and about Inm.
- the first discontinuous film may be deposited utilizing PVD, CVD, ALD, and/or any other suitable deposition technique.
- a switching oxide layer may be fabricated on the interface layer.
- the switching oxide layer may include one or more transition metal oxides.
- the transition metal oxides may include, for example, TaO x , HfO x , TiO x , NbO x , ZrO x , etc.
- one or more portions of the transition metal oxides may be disposed on the first electrode through one or more of the first pores.
- the switching oxide layer may be deposited utilizing PVD, CVD, ALD, and/or any other suitable deposition technique.
- the switching oxide layer may be and/or include switching oxide layer 430 as described in connection with FIGS. 4C-5D above.
- a second electrode may be fabricated on the switching oxide layer.
- the second electrode may include one or more alloys.
- Each of the alloys may contain a first metallic element and one or more second metallic elements.
- Each of the second metallic elements and the first metallic element may have different reactivity to the transition metal oxide in the switching oxide layer.
- the first metallic element may be Ta.
- the second metallic elements may be one or more of W, Hf, Mo, Nb, Zr, etc. Based on the binary phase diagrams involving Ta and the second metallic elements W, Hf, Mo, Nb, or Zr as shown in FIGS. 14A-14E, Ta-W (FIG. 14B), Ta-Mo (FIG. 14C), and Ta-Nb (FIG.
- fabricating the second electrode may involve sputtering from an alloy target (e.g., a Ta-W alloy, Ta-Hf alloy, Ta-Mo alloy, Ta-Nb alloy, Ta-Zr alloy, etc.) for a required composition between the first metallic element (e.g., a pure Ta metal) and the second metallic element(s) (e.g., a pure Hf metal).
- an alloy target e.g., a Ta-W alloy, Ta-Hf alloy, Ta-Mo alloy, Ta-Nb alloy, Ta-Zr alloy, etc.
- fabricating the second electrode may involve fabricating multiple electrode components including Ta, Hf, Nb, Mo, W, and/or Zr.
- Each of the electrode components may be and/or include a binary alloy, a ternary alloy, a quaternary alloy, a quinary alloy, a senary alloy, and/or a high order alloy of Ta.
- fabricating the second electrode may involve fabricating the second electrode 340b with one or more alloys and/or alloy systems as described in connection with FIG. 4D. More particularly, for example, fabricating the second electrode may involve fabricating two or more of a first alloy containing Ta, a second alloy containing Ta, a third alloy containing Ta, a fourth alloy containing Ta, a fifth alloy containing Ta, and a sixth alloy containing Ta.
- the first alloy containing Ta, the second alloy containing Ta, the third alloy containing Ta, the fourth alloy containing Ta, the fifth alloy containing Ta, and the sixth alloy containing Ta may be a binary alloy, a ternary alloy, a quaternary alloy, a quinary alloy, a senary alloy, and a high-order alloy, respectively.
- fabricating the second electrode may involve fabricating multiple layers of multiple metallic materials, such as layers 710 and 720 as described in conjunction with FIG.7.
- the second electrode may be fabricated by performing one or more operations as described in connection with FIG. 13.
- the second electrode may be deposited utilizing PVD, CVD, AED, and/or any other suitable deposition technique.
- the second electrode may be and/or include second electrode 440 as described in connection with FIGS. 4D-4F above.
- FIG. 11 is a flow diagram illustrating an example 1100 of a method for fabricating an RRAM device according to some embodiments of the disclosure.
- a first electrode may be fabricated on a substrate.
- the first electrode may be fabricated on the substrate by performing one or more operations described in connection with block 1010 of FIG. 10.
- the first electrode may be and/or include first electrode 320 and/or 420 as described in connection with FIGS. 3A-6D above.
- a first interface layer may be fabricated on the first electrode. Fabricating the first interface layer may involve fabricating a first discontinuous film of a first material. The first interface layer may be fabricated on the first electrode by performing one or more operation described in connection with block 1020 of FIG. 10. The first interface layer may be and/or include the first interface layer 422 as described in connection with FIGS. 4B-5D above.
- a switching oxide layer may be fabricated on the first interface layer.
- the switching oxide layer may be fabricated on the first interface layer by performing one or more operation described in connection with block 1030 of FIG. 10.
- the switching oxide layer may be and/or include switching oxide layer 430 as described in connection with FIGS. 4C-5D above.
- a second interface layer may be fabricated on the switching oxide layer. Fabricating the second interface layer may involve fabricating a second discontinuous film of a second material that is more chemically stable than the transition metal oxide(s) of the switching oxide layer.
- the second material may include AI2O3, MgO, Y2O3, La2O3, etc.
- fabricating the second interface layer may involve depositing the second material to a suitable thickness (e.g., a thickness between 0.2nm and Inm) to form the second discontinuous film.
- the discontinuous film may be deposited utilizing PVD, CVD, ALD, and/or any other suitable deposition technique.
- the second interface layer may be and/or include second interface layer 532 as described in connection with FIGS. 5A-5D.
- a second electrode may be fabricated on the second interface layer.
- the second electrode may be fabricated on the second interface layer by performing one or more operation described in connection with block 1040 of FIG. 10.
- one or more portions of the second electrode may be deposited on the switching oxide layer through the one or more second pores.
- the second electrode may be and/or include second electrode 540 as described in connection with FIGS. 5B- 5D above.
- FIG. 12 is a flow diagram illustrating an example 1200 of a method for fabricating an RRAM device according to some embodiments of the disclosure.
- a first electrode may be fabricated on a substrate.
- the first electrode may be fabricated on the substrate by performing one or more operations described in connection with block 1010 of FIG. 10.
- the first electrode may be and/or include first electrode 320 as described in connection with FIGS. 3A-6D above.
- a switching oxide layer may be fabricated on the first electrode.
- the switching oxide layer may include one or more transition metal oxides.
- the transition metal oxides may include, for example, TaO x , HfO x , TiO x , NbO x , ZrO x , etc.
- the switching oxide layer may be deposited utilizing PVD, CVD, ALD, and/or any other suitable deposition technique.
- the switching oxide layer may be and/or include switching oxide layer 630 as described in connection with FIGS. 6A-6D above.
- an interface layer may be fabricated on the switching oxide layer.
- the interface layer may include a discontinuous film of a material that is more chemically stable than the transition metal oxide(s) in the switching oxide layer.
- the interface layer may be fabricated on the switching oxide layer by performing one or more operations described in connection with block 1140 of FIG. 11.
- the interface layer may be and/or include the second interface layer 632 as described in connection with FIGS. 6A-6D above.
- a second electrode may be fabricated on the interface layer.
- the second electrode may be fabricated on the interface layer by performing one or more operations described in connection with block 1150 of FIG. 11.
- the second electrode may be and/or include the second electrode 640 as described in connection with FIGS. 6B-6D above.
- FIG. 13 is a flow diagram illustrating an example 1300 of a method for fabricating a top electrode of an RRAM device according to some embodiments of the disclosure.
- a first layer including a first metallic material may be fabricated.
- the first metallic material may include a first metallic element, such as Ti, Hf, and Zr.
- the first layer of the first metallic material may be fabricated by depositing a first metal (e.g., Ti metal) utilizing PVD, CVD, sputtering, ALD, and/or any other suitable deposition technique. Fabricating the first layer of the first metal may involve depositing a layer of the first metal with a suitable thickness, such as a thickness between about 0.2nm and about 5nm, a thickness between about 0.5nm and about 2nm, etc.
- a second layer including a second metallic material may be fabricated.
- the second metallic material may include a second metallic element that is different from the first metallic element.
- the second metallic element may be Ta.
- fabricating the second layer including the second metallic material may involve depositing a second metal (e.g., Ta metal) utilizing PVD, CVD, sputtering, ALD, and/or any other suitable deposition technique.
- Fabricating the second layer of the second metal may involve depositing a layer of the second metal with a suitable thickness, such as a layer of the second metal that is thicker than that of the first layer of the first metal.
- a layer of the second metal having a thickness between lOnm and lOOnm may be deposited.
- the second layer of the second metal may be deposited directly on the first layer of the first metal.
- a surface of the first layer of the first metal may directly contact one or more portions of a surface of the second layer of the second metal.
- fabricating the second layer including the second metallic material may involve fabricating a layer including one or more alloys.
- each of the alloys may contain a first metallic element and one or more second metallic elements.
- Each of the second metallic elements may have different reactivity to the transition metal oxide in the switching oxide layer than the first metallic element.
- the first metallic element may be Ta.
- the second metallic elements may be one or more of W, Hf, Mo, Nb, Zr, etc.
- Fabricating the second layer of the Ta alloy may involve depositing the Ta alloy utilizing PVD, CVD, sputtering, ALD, and/or any other suitable deposition technique.
- fabricating the second layer of the Ta alloy may involve depositing a layer of the Ta alloy with a suitable thickness, such as a layer of the Ta alloy that is thicker than that of the first layer of the first metal.
- a layer of one or more Ta alloys having a thickness between about 5nm and about lOOnm may be deposited.
- the terms “approximately,” “about,” and “substantially” as used herein may mean within a range of normal tolerance in the art, such as within 2 standard deviations of the mean, within ⁇ 20% of a target dimension in some embodiments, within ⁇ 10% of a target dimension in some embodiments, within ⁇ 5% of a target dimension in some embodiments, within ⁇ 2% of a target dimension in some embodiments, within ⁇ 1% of a target dimension in some embodiments, and yet within ⁇ 0.1% of a target dimension in some embodiments.
- the terms “approximately” and “about” may include the target dimension. Unless specifically stated or obvious from context, all numerical values described herein are modified by the term “about.”
- a range includes all the values within the range.
- a range of 1 to 10 may include any number, combination of numbers, sub-range from the numbers of 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 and fractions thereof.
- example or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion.
- the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations.
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CN202280034491.4A CN117480878A (en) | 2021-05-12 | 2022-05-12 | Resistive random access memory device having multicomponent electrode and discontinuous interface layer |
EP22808352.3A EP4338206A1 (en) | 2021-05-12 | 2022-05-12 | Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers |
KR1020237042863A KR20240006677A (en) | 2021-05-12 | 2022-05-12 | Resistive random access memory device with multi-component electrodes and discontinuous interface layers |
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US17/319,057 US20220367802A1 (en) | 2021-05-12 | 2021-05-12 | Resistive random-access memory devices with multi-component electrodes |
US17/319,068 US20220367803A1 (en) | 2021-05-12 | 2021-05-12 | Resistive random-access memory devices with multi-component electrodes |
US17/319,068 | 2021-05-12 | ||
US17/454,914 | 2021-11-15 | ||
US17/454,914 US20220077389A1 (en) | 2020-07-06 | 2021-11-15 | Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers |
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