WO2022237098A1 - 一种异构程序执行方法、装置、计算设备及可读存储介质 - Google Patents

一种异构程序执行方法、装置、计算设备及可读存储介质 Download PDF

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WO2022237098A1
WO2022237098A1 PCT/CN2021/129673 CN2021129673W WO2022237098A1 WO 2022237098 A1 WO2022237098 A1 WO 2022237098A1 CN 2021129673 W CN2021129673 W CN 2021129673W WO 2022237098 A1 WO2022237098 A1 WO 2022237098A1
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program
simulator
heterogeneous program
target heterogeneous
target
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PCT/CN2021/129673
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English (en)
French (fr)
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吕果
黄林
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统信软件技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present invention relates to the field of computer technology, in particular to a heterogeneous program execution method, device, computing equipment and readable storage medium.
  • Application software has become an important tool for people to use computers to achieve various life and work needs.
  • the software resources are very rich.
  • most of the software resources are implemented based on the X86 architecture.
  • the software manufacturer does not provide versions for other platforms, and the software resources are not perfect.
  • the application software realizes the compatibility between different operating system platforms through wine, for example, common software such as WeChat and QQ only provide the Windows version under X86, with the help of the Windows compatibility layer provided by wine, it can be sure on the X86 Linux system.
  • common software such as WeChat and QQ only provide the Windows version under X86, with the help of the Windows compatibility layer provided by wine, it can be sure on the X86 Linux system.
  • Qemu's user mode can provide simulation execution of heterogeneous machine code, but Qemu does not provide an external secondary development interface and cannot be used directly.
  • Unicorn has implemented a lightweight CPU emulator framework that supports multiple platforms and architectures, supports JIT, and can simulate and execute heterogeneous machine code locally through Unicorn. Because the Unicorn translation engine itself is based on the Qemu2.0 version, and the developer has not updated it for a long time, the design idea has been outdated, the overall execution performance is not high, there are many bugs, and the actual effect is not good in the process of use.
  • Unicorn's memory management mechanism uses a set of simulated physical CPU memory memory access mechanisms to manage the address space of GVA. Every time an instruction or data is fetched, it is necessary to convert GVA into HVA through SoftMMU and obtain instruction data from HVA. , this mechanism is complex and inefficient.
  • the present invention provides a heterogeneous program execution method, device, computing device and readable storage medium in an attempt to solve or at least alleviate the above existing problems.
  • a heterogeneous program execution method is provided, which is suitable for execution in a simulator, the simulator is suitable for residing in a computing device, and a target heterogeneous program is installed on the simulator, the method includes: when simulating When the simulator starts, obtain the target heterogeneous program on the simulator; load the target heterogeneous program into the memory address space of the simulator process; create a virtual CPU according to the start request of the target heterogeneous program; execute the target heterogeneous program through the virtual CPU.
  • loading the target heterogeneous program into the memory address space of the simulator process includes: loading the code segment, data segment and dependent library files of the target heterogeneous program into The memory address space of the emulator process; record the entry address of the target heterogeneous program.
  • creating a virtual CPU according to a start request of a target heterogeneous program includes: when receiving a start request from a user to start a target heterogeneous program, creating a virtual CPU, the virtual CPU Feature information includes general-purpose registers, PC registers, floating-point registers, status registers, and segment registers.
  • the computing device is a first processor architecture
  • the target heterogeneous program is suitable for execution in the second processor architecture
  • executing the target heterogeneous program through a virtual CPU includes: Translate the original machine code of the target heterogeneous program into intermediate bytecode according to the disassembly rules of the CPU in the second processor architecture; translate the intermediate bytecode into local machine code, and the local machine code is suitable for the first processor architecture Execute in; Execute the local machine code according to the entry memory address of the target heterogeneous program.
  • the heterogeneous program execution method further includes: when the virtual CPU finishes executing the target heterogeneous program, returning to the memory address space corresponding to the emulator process.
  • the emulator is realized based on Qemu.
  • a heterogeneous program execution device which is suitable for residing in a simulator, and the simulator is suitable for residing in a computing device.
  • the heterogeneous program execution device includes a loader module, an execution module, The CPU module, wherein the loader module is adapted to obtain the target heterogeneous program on the simulator when the simulator starts; the target heterogeneous program is loaded into the memory address space of the simulator process; the CPU module is adapted to obtain the target heterogeneous program according to the target heterogeneous program.
  • the start request of the structured program creates a virtual CPU; the execution module is suitable for executing the target heterogeneous program through the virtual CPU.
  • loading the target heterogeneous program into the memory address space of the simulator process includes: loading the code segment, data segment and dependent library files of the target heterogeneous program into The memory address space of the emulator process; record the entry address of the target heterogeneous program.
  • a computing device comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be executed by the at least one processor, the program instructions comprising An instruction for executing any one of the above heterogeneous program execution methods.
  • a readable storage medium storing program instructions, and when the program instructions are read and executed by a computing device, the computing device executes any one of the heterogeneous program execution methods above.
  • the target heterogeneous program on the simulator is obtained, and the target heterogeneous program is directly loaded into the memory address space of the simulator process, when the target heterogeneous program is received
  • the target heterogeneous program is received
  • the memory address mapping process reduces the complexity of heterogeneous process management. Without the address mapping process, the operating efficiency and performance of heterogeneous programs are improved, and there will be no lack of address memory.
  • FIG. 1 shows a block diagram of a computing device 100 according to one embodiment of the invention
  • FIG. 2 shows a flowchart of a heterogeneous program execution method 200 according to an embodiment of the present invention
  • FIG. 3 shows a schematic diagram of a heterogeneous program execution apparatus 300 according to an embodiment of the present invention
  • Fig. 4 shows the schematic diagram that the target heterogeneous program is loaded into the emulator process address space according to one embodiment of the present invention
  • Fig. 5 shows a schematic diagram of a machine code translation process of a target heterogeneous program according to an embodiment of the present invention.
  • Qemu an analog processor widely used in Linux system platforms, which implements CPU operations through software.
  • Qemu There are two modes, user mode and system mode. Among them, user mode can provide simulation execution of heterogeneous programs. However, Qemu does not provide external secondary development interface, and its use has limitations and cannot be used directly.
  • Unicorn through the in-depth transformation and packaging of Qemu, a lightweight, multi-platform, multi-architecture CPU emulator framework has been realized. It supports JIT and can simulate and execute heterogeneous machine code locally. It is easy to use and quick to use. , good encapsulation, cross-target platform, and realized instruction translation and simulated execution of heterogeneous machine codes.
  • the emulator In terms of memory address space management, the emulator itself has a virtual address space (Guest Virtual Address, GVA). Address, HVA) and physical memory space (Host Physical Address, HPA), therefore, the problem of memory virtualization becomes the mapping problem of GVA to HPA, GVA to GPA is realized through the page table mapping of the simulator, and HVA to HPA is realized through the host
  • the host s page table mapping implementation can solve the problem of memory virtualization as long as the mapping relationship between GPA and HVA is established. Unicorn uses the software SoftMMU to realize this address mapping in the memory management mechanism, but this mechanism is complicated and inefficient.
  • the present invention proposes a heterogeneous program execution method, so that each data of the heterogeneous program can be preloaded into the virtual address space of the host machine when starting, so that the GVA and HVA are both in the address space of the host machine process , does not need to distinguish and maintain the relationship among GVA, GPA and HVA, and realizes the transparent access of heterogeneous program address space.
  • FIG. 1 shows a schematic diagram of a computing device 100 according to one embodiment of the invention.
  • the computing device 100 shown in FIG. 1 is only an example.
  • the computing device used to implement the heterogeneous program execution method of the present invention may be any type of device, and its hardware configuration may be the same as that shown in FIG.
  • the computing device 100 shown in FIG. 1 is the same, or may be different from the computing device 100 shown in FIG. 1 .
  • the computing device used to implement the heterogeneous program execution method of the present invention may add or delete hardware components of the computing device 100 shown in FIG. 1 , and the present invention does not limit the specific hardware configuration of the computing device.
  • computing device 100 typically includes system memory 106 and one or more processors 104 .
  • a memory bus 108 may be used for communication between the processor 104 and the system memory 106 .
  • processor 104 may be any type of processing including, but not limited to, a microprocessor ( ⁇ P), microcontroller ( ⁇ C), digital information processor (DSP), or any combination thereof.
  • Processor 104 may include one or more levels of cache such as L1 cache 110 and L2 cache 112 , processor core 114 and registers 116 .
  • Exemplary processor core 114 may include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof.
  • ALU arithmetic logic unit
  • FPU floating point unit
  • DSP core digital signal processing core
  • An example memory controller 118 may be used with the processor 104 or, in some implementations, the memory controller 118 may be an internal part of the processor 104 .
  • system memory 106 may be any type of memory including, but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof.
  • volatile memory such as RAM
  • non-volatile memory such as ROM, flash memory, etc.
  • the physical memory in the computing device usually refers to the volatile memory RAM, and the data in the disk needs to be loaded into the physical memory before being read by the processor 104 .
  • System memory 106 may include an operating system 120 , one or more applications 122 , and program data 124 .
  • applications 122 may be arranged to execute instructions on an operating system with program data 124 by one or more processors 104 .
  • the operating system 120 may be, for example, Linux, Windows, etc., which includes program instructions for handling basic system services and performing hardware-dependent tasks.
  • the application 122 includes program instructions for realizing various user-desired functions.
  • the application 122 may be, for example, a browser, instant messaging software, software development tools (such as an integrated development environment IDE, a compiler, etc.), but is not limited thereto.
  • a driver module may be added to the operating system 120 .
  • the processor 104 When the computing device 100 starts to run, the processor 104 reads program instructions of the operating system 120 from the memory 106 and executes them.
  • the application 122 runs on the operating system 120, and utilizes the interface provided by the operating system 120 and the underlying hardware to realize various user-desired functions.
  • the application 122 is loaded into the memory 106 , and the processor 104 reads and executes the program instructions of the application 122 from the memory 106 .
  • Computing device 100 also includes storage device 132 , which includes removable storage 136 and non-removable storage 138 , both of which are connected to storage interface bus 134 .
  • Computing device 100 may also include interface bus 140 to facilitate communication from various interface devices (eg, output devices 142 , peripheral interfaces 144 , and communication devices 146 ) to base configuration 102 via bus/interface controller 130 .
  • Example output devices 142 include a graphics processing unit 148 and an audio processing unit 150 . They may be configured to facilitate communication with various external devices such as a display or speakers via one or more A/V ports 152 .
  • Example peripherals interfaces 144 may include serial interface controller 154 and parallel interface controller 156, which may be configured to facilitate communication via one or more I/O ports 158 and input devices such as (e.g., keyboard, mouse, pen) , voice input device, touch input device) or other peripherals (such as printers, scanners, etc.) to communicate with external devices such as.
  • the example communication device 146 may include a network controller 160 , which may be arranged to facilitate communication with one or more other computing devices 162 over a network communication link via one or more communication ports 164 .
  • a network communication link may be one example of a communication medium.
  • Communication media typically embodies computer readable instructions, data structures, program modules in a modulated data signal such as a carrier wave or other transport mechanism and may include any information delivery media.
  • a "modulated data signal" may be a signal that has one or more of its data sets or changes thereof in such a manner as to encode information in the signal.
  • communication media may include wired media such as a wired or dedicated-line network, and various wireless media such as acoustic, radio frequency (RF), microwave, infrared (IR) or other wireless media.
  • RF radio frequency
  • IR infrared
  • the term computer readable media as used herein may include both storage media and communication media.
  • the application 122 includes instructions for executing the heterogeneous program execution method 200 of the present invention, and the instructions can instruct the processor 104 to execute the heterogeneous program execution method 200 of the present invention.
  • FIG. 2 shows a flowchart of a heterogeneous program execution method 200 according to an embodiment of the present invention.
  • the method 200 is suitable for execution in a simulator, and the simulator is suitable for residing in a computing device (such as the computing device shown in Figure 1), and the target heterogeneous program is installed in the simulator, and the essence of the simulator is to make A
  • the working mode of the host architecture is similar to that of the B host architecture, which can execute the executable program compiled by the B host architecture and simulate the behavior and status of the B host architecture CPU running the program.
  • the method 200 starts at step S210, and starts the emulator program, wherein, the processor architecture of the computing device where the emulator resides is the first processor architecture (for example: ARM architecture), and the emulator is installed with The target heterogeneous program is adapted to run in a computing device with a second processor architecture (for example: X86).
  • the processor architecture of the computing device where the emulator resides is the first processor architecture (for example: ARM architecture)
  • the emulator is installed with
  • the target heterogeneous program is adapted to run in a computing device with a second processor architecture (for example: X86).
  • step S220 load the target heterogeneous program into the emulator process address space, and record the entry address of the target heterogeneous program.
  • the program header, dependent library files, code segments, data segments, etc. of the target heterogeneous program are loaded into the HVA of the simulator, therefore, when the simulator executes the target application program, the By eliminating the mapping process from GPA-HVA, the host process can directly read target heterogeneous programs from HVA without addressing through softMMU, without virtual memory management unit, and without updating memory topology, which improves the overall translation execution efficiency , there will be no page fault in the GVA memory during the address mapping process. During this process, it is necessary to record the entry point of the target heterogeneous program, which is the first instruction that the simulator needs to simulate when executing the target heterogeneous program.
  • FIG. 4 shows a schematic diagram of loading a target heterogeneous program into the address space of the simulator process according to an embodiment of the present invention, that is, the memory topology of the target heterogeneous program and the host process (simulator process) all belong to the address space of the host process,
  • the simulator implements transparent access to the address space of the target heterogeneous program.
  • step S230 a start request from the user to start the target heterogeneous program is received.
  • step S240 When receiving the start request of the target heterogeneous program, enter step S240, create a virtual CPU and initialize it, and the virtual CPU includes general registers, PC registers, floating point registers, status registers, segment registers, etc.
  • the role of the virtual CPU is to determine the disassembly rules of the machine code of the target architecture, and to simulate the behavior and state of the target CPU when executing the machine code of the architecture.
  • step S250 and translate the original machine code of the target heterogeneous program into local machine code.
  • the target heterogeneous program A is suitable for running under the X86 architecture, and the architecture of the current computing device is an ARM architecture, then it is necessary to convert the original machine code of the A program into a code suitable for execution under the ARM architecture.
  • FIG. 5 shows a schematic diagram of the machine code translation process of the target heterogeneous program according to an embodiment of the present invention, through semantic equivalent translation, the application program can be run on the current ARM computing device.
  • the translation process needs to combine the target CPU architecture type, CPU characteristics, instruction-by-instruction translation, and simulate the behavior of the target CPU when executing the instruction.
  • the simulator needs to modify the target CPU registers, target CPU internal variables, and target CPU according to the results of the instruction simulation execution. operating status, etc.
  • step S260 the virtual CPU executes the translated local machine code from the program entry address. Because the semantics of the generated local machine code and the original machine code are equivalent, it looks like the local machine code is being executed.
  • step S270 After executing the local machine code of the target heterogeneous program, enter step S270, and return to the emulator process memory address space to execute other codes.
  • FIG. 3 shows a schematic diagram of a heterogeneous program execution apparatus 300 according to an embodiment of the present invention, which is suitable for residing in a simulator, and the simulator is suitable for residing in a computing device (such as the computing device shown in FIG. 1 ).
  • the processor architecture of the computing device is the first processor architecture (for example: ARM), and the apparatus 300 includes a loader module 310, a CPU module 320, a translation module 330 and an execution module 340.
  • the loader module 310 is adapted to obtain the target heterogeneous program on the simulator when the simulator starts, and load the target heterogeneous program into the memory address space of the simulator process, wherein the target heterogeneous program is suitable for processing in the second Execute in devices with processor architecture (for example: X86).
  • the CPU module is adapted to create a virtual CPU when the emulator receives a startup instruction to start a target heterogeneous program, wherein the feature information of the virtual CPU includes general registers, PC registers, floating point registers, status registers, and segment registers.
  • the translation module 330 is adapted to convert the original machine code of the target heterogeneous program into local machine code suitable for execution in the first processor architecture.
  • the execution module 340 is adapted to execute the local machine code of the target heterogeneous program from the program entry address.
  • the target heterogeneous program on the simulator is obtained, and the target heterogeneous program is directly loaded into the memory address space of the simulator process, when the target heterogeneous program is received
  • the target heterogeneous program is received
  • the memory address mapping process reduces the complexity of heterogeneous process management. Without the address mapping process, the operating efficiency and performance of heterogeneous programs are improved, and there will be no lack of address memory.
  • the various techniques described herein can be implemented in conjunction with hardware or software, or a combination thereof.
  • the method and device of the present invention, or certain aspects or parts of the method and device of the present invention may be embedded in a tangible medium, such as a removable hard disk, USB flash drive, floppy disk, CD-ROM or any other machine-readable storage medium
  • program code ie, instructions
  • a machine such as a computer
  • the program when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes an apparatus for practicing the invention.
  • the computing device In the case of program code execution on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
  • the memory is configured to store program codes; the processor is configured to execute the heterogeneous program execution method of the present invention according to instructions in the program codes stored in the memory.
  • Readable media include, by way of example and not limitation, readable storage media and communication media.
  • Readable storage media store information such as computer readable instructions, data structures, program modules or other data.
  • Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of readable media.
  • the algorithms and displays are not inherently related to any particular computer, virtual system, or other device.
  • Various general-purpose systems can also be used with examples of the invention. The structure required to construct such a system is apparent from the above description.
  • the present invention is not specific to any particular programming language. It should be understood that various programming languages can be used to implement the content of the present invention described herein, and the above description of specific languages is for disclosing the best mode of the present invention.
  • modules or units or components of the devices in the examples disclosed herein may be arranged in the device as described in this embodiment, or alternatively may be located in a different location than the device in this example. in one or more devices.
  • the modules in the preceding examples may be combined into one module or furthermore may be divided into a plurality of sub-modules.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies.
  • All features disclosed in this specification including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

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Abstract

本发明公开了一种异构程序执行方法，适于在模拟器中执行，模拟器适于驻留在计算设备中，模拟器上安装有目标异构程序，方法包括：当模拟器启动时，获取模拟器上的目标异构程序；将目标异构程序加载到模拟器进程的内存地址空间；根据目标异构程序的启动请求创建虚拟CPU；通过虚拟CPU执行目标异构程序。本发明一并公开了相应的装置、计算设备及可读存储介质。

Description

一种异构程序执行方法、装置、计算设备及可读存储介质 技术领域
本发明涉及计算机技术领域，尤其涉及一种异构程序执行方法、装置、计算设备及可读存储介质。
背景技术
应用程序软件成为人们应用计算机实现各种生活、工作需求的重要工具，软件资源非常丰富，但是，目前大部分软件资源都是基于X86架构实现的，而对于其他架构平台(例如：ARM、PowerPC)，软件厂商并未提供其他平台的版本，软件资源并不完善。虽然应用软件通过wine实现了不同操作系统平台之间的兼容，例如，微信、QQ等常用软件都只提供了X86下的Windows版本，借助wine提供的Windows兼容层，可以在X86的linux系统上一定程度地使用这些程序，但wine并未提供CPU级别的仿真，因此通过wine也无法在非X86的平台上执行X86的程序。
在现有的技术中，Qemu的user mode能够提供异构机器码的仿真执行，但是Qemu并未提供对外的二次开发接口，无法直接使用。Unicorn通过对Qemu的改造和封装，实现了一个轻量级并支持多平台、多体系结构的CPU仿真器框架，支持JIT，通过Unicorn能够在本地模拟执行异构机器码。Unicorn翻译引擎因为本身基于Qemu2.0的版本，且开发者长期未更新，设计思想已经落后，执行性能整体不高，BUG较多，实际使用过程中效果不好。同时，Unicorn的内存管理机制使用的一整套模拟物理CPU内存内存访问机制对GVA进行地址空间管理，在每次取指令或者取数据时，都需要通过SoftMMU将GVA转换成HVA，从HVA获取指令数据，这套机制复杂而且低效。
发明内容
为此，本发明提供了一种异构程序执行方法、装置、计算设备及可读存 储介质，以力图解决或者至少缓解上面存在的问题。
根据本发明的一个方面，提供一种异构程序执行方法，适于在模拟器中执行，模拟器适于驻留在计算设备中，模拟器上安装有目标异构程序，方法包括：当模拟器启动时，获取模拟器上的目标异构程序；将目标异构程序加载到模拟器进程的内存地址空间；根据目标异构程序的启动请求创建虚拟CPU；通过虚拟CPU执行目标异构程序。
可选的，在根据本发明的异构程序执行方法中，将目标异构程序加载到模拟器进程的内存地址空间包括：将目标异构程序的代码段、数据段以及依赖的库文件加载到模拟器进程的内存地址空间；记录目标异构程序的入口地址。
可选的，在根据本发明的异构程序执行方法中，根据目标异构程序的启动请求创建虚拟CPU包括：当接收到用户启动目标异构程序的启动请求时，创建虚拟CPU，虚拟CPU的特征信息包括通用寄存器、PC寄存器、浮点寄存器、状态寄存器、段寄存器。
可选的，在根据本发明的异构程序执行方法中，计算设备为第一处理器架构，目标异构程序适于在第二处理器架构中执行，通过虚拟CPU执行目标异构程序包括：根据第二处理器架构中CPU的反汇编规则将目标异构程序的原机器码翻译成中间字节码；将中间字节码翻译成本地机器码，本地机器码适于在第一处理器架构中执行；根据目标异构程序的入口内存地址执行本地机器码。
可选的，在根据本发明的异构程序执行方法中，还包括：当虚拟CPU执行完目标异构程序时，返回模拟器进程对应的内存地址空间。
可选的，在根据本发明的异构程序执行方法中，模拟器是基于Qemu实现的。
根据本发明的又一个方面，提供一种异构程序执行装置，适于驻留在模拟器中，模拟器适于驻留在计算设备中，异构程序执行装置包括加载器模块、执行模块、CPU模块，其中，加载器模块，适于当模拟器启动时，获取模拟器上的目标异构程序；将目标异构程序加载到模拟器进程的内存地址空间；CPU模块，适于根据目标异构程序的启动请求创建虚拟CPU；执行模块，适 于通过虚拟CPU执行目标异构程序。
可选的，在根据本发明的异构程序执行装置中，将目标异构程序加载到模拟器进程的内存地址空间包括：将目标异构程序的代码段、数据段以及依赖的库文件加载到模拟器进程的内存地址空间；记录目标异构程序的入口地址。
根据本发明的又一个方面，提供一种计算设备，包括：至少一个处理器；以及存储器，存储有程序指令，其中，程序指令被配置为适于由至少一个处理器执行，程序指令包括用于执行如上的任一项异构程序执行方法的指令。
根据本发明的又一方面，提供一种存储有程序指令的可读存储介质，当程序指令被计算设备读取并执行时，使得计算设备执行如上的任一项异构程序执行方法。
根据本发明的异构程序执行方法，当模拟器启动时，获取模拟器上的目标异构程序，将目标异构程序直接加载到模拟器进程的内存地址空间中，当接收到目标异构程序的启动指令时，通过创建虚拟CPU直接从模拟器进程的内存地址空间中读取应用程序指令，实现了透明内存访问，可以在宿主进程的内存地址空间直接访问应用程序指令，避免了Un icorn中内存地址映射过程，降低了异构进程管理的复杂性，没有了地址映射过程，提升了异构程序运行效率和性能，也不会出现地址内存缺失的情况。
附图说明
为了实现上述以及相关目的，本文结合下面的描述和附图来描述某些说明性方面，这些方面指示了可以实践本文所公开的原理的各种方式，并且所有方面及其等效方面旨在落入所要求保护的主题的范围内。通过结合附图阅读下面的详细描述，本公开的上述以及其它目的、特征和优势将变得更加明显。遍及本公开，相同的附图标记通常指代相同的部件或元素。
图1示出了根据本发明一个实施例的计算设备100的框图；
图2示出了根据本发明一个实施例的异构程序执行方法200的流程图；
图3示出了根据本发明一个实施例的异构程序执行装置300的示意图；
图4示出了根据本发明一个实施例的目标异构程序加载至模拟器进程地 址空间的示意图；
图5示出了根据本发明一个实施例的目标异构程序机器码翻译过程示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
基于目前X86架构中丰富的应用程序，为了便于将这些应用程序软件移植到其他架构上运行，于是，一款广泛应用于Linux系统平台的模拟处理器Qemu出现了，其通过软件实现CPU操作，Qemu有两种模式，用户模式和系统模式，其中，用户模式能够提供异构程序的仿真执行，但是，Qemu并未提供对外的二次开发接口，使用具有局限性，无法直接使用。直到Unicorn，通过对Qemu的深度改造和封装，实现了一种轻量级、多平台、多体系结构的CPU仿真器框架，支持JIT，能够在本地模拟执行异构机器码，使用简单、上手快、封装性较好、跨目标平台，并实现了异构机器码的指令翻译和模拟执行。
在内存地址空间管理上，模拟器本身有虚拟地址空间(Guest Virtual Address，GVA)，模拟器认为自己独占整个物理内存空间(Guest Physical Address，GPA)，宿主机本身有模拟器地址空间(Host Virtual Address，HVA)和物理内存空间(Host Physical Address，HPA)，因此，内存虚拟化的问题变成了GVA到HPA的映射问题，GVA到GPA通过模拟器的页表映射实现，HVA到HPA通过宿主机的页表映射实现，只要建立GPA到HVA的映射关系，即可解决内存虚拟化的问题，Unicorn在内存管理机制中，使用软件SoftMMU实现这一地址映射，然而这套机制复杂而且效率低下。
针对这一问题，本发明提出一种异构程序执行方法，使得异构程序的各个数据能够在启动时被预先加载到宿主机虚拟地址空间中，使GVA和HVA同处于宿主机进程的地址空间，不需要区分和维护GVA、GPA和HVA之间的关系，实现了异构程序地址空间的透明访问。
图1示出了根据本发明一个实施例的计算设备100的示意图。需要说明的是，图1所示的计算设备100仅为一个示例，在实践中，用于实施本发明的异构程序执行方法的计算设备可以是任意型号的设备，其硬件配置情况可以与图1所示的计算设备100相同，也可以与图1所示的计算设备100不同。实践中用于实施本发明的异构程序执行方法的计算设备可以对图1所示的计算设备100的硬件组件进行增加或删减，本发明对计算设备的具体硬件配置情况不做限制。
如图1所示，在基本的配置102中，计算设备100典型地包括系统存储器106和一个或者多个处理器104。存储器总线108可以用于在处理器104和系统存储器106之间的通信。
取决于期望的配置，处理器104可以是任何类型的处理，包括但不限于：微处理器(μP)、微控制器(μC)、数字信息处理器(DSP)或者它们的任何组合。处理器104可以包括诸如一级高速缓存110和二级高速缓存112之类的一个或者多个级别的高速缓存、处理器核心114和寄存器116。示例的处理器核心114可以包括运算逻辑单元(ALU)、浮点数单元(FPU)、数字信号处理核心(DSP核心)或者它们的任何组合。示例的存储器控制器118可以与处理器104一起使用，或者在一些实现中，存储器控制器118可以是处理器104的一个内部部分。
取决于期望的配置，系统存储器106可以是任意类型的存储器，包括但不限于：易失性存储器(诸如RAM)、非易失性存储器(诸如ROM、闪存等)或者它们的任何组合。计算设备中的物理内存通常指的是易失性存储器RAM，磁盘中的数据需要加载至物理内存中才能够被处理器104读取。系统存储器106可以包括操作系统120、一个或者多个应用122以及程序数据124。在一些实施方式中，应用122可以布置为在操作系统上由一个或多个处理器104利用程序数据124执行指令。操作系统120例如可以是Linux、Windows等，其包括用于处理基本系统服务以及执行依赖于硬件的任务的程序指令。应用122包括用于实现各种用户期望的功能的程序指令，应用122例如可以是浏览器、即时通讯软件、软件开发工具(例如集成开发环境IDE、编译器等)等，但不限于此。当应用122被安装到计算设备100中时，可以向操作系统120添加驱动模块。
在计算设备100启动运行时，处理器104会从存储器106中读取操作系统120的程序指令并执行。应用122运行在操作系统120之上，利用操作系统120以及底层硬件提供的接口来实现各种用户期望的功能。当用户启动应用122时，应用122会加载至存储器106中，处理器104从存储器106中读取并执行应用122的程序指令。
计算设备100还包括储存设备132，储存设备132包括可移除储存器136和不可移除储存器138，可移除储存器136和不可移除储存器138均与储存接口总线134连接。
计算设备100还可以包括有助于从各种接口设备(例如，输出设备142、外设接口144和通信设备146)到基本配置102经由总线/接口控制器130的通信的接口总线140。示例的输出设备142包括图形处理单元148和音频处理单元150。它们可以被配置为有助于经由一个或者多个A/V端口152与诸如显示器或者扬声器之类的各种外部设备进行通信。示例外设接口144可以包括串行接口控制器154和并行接口控制器156，它们可以被配置为有助于经由一个或者多个I/O端口158和诸如输入设备(例如，键盘、鼠标、笔、语音输入设备、触摸输入设备)或者其他外设(例如打印机、扫描仪等)之类的外部设备进行通信。示例的通信设备146可以包括网络控制器160，其可以被布置为便于经由一个或者多个通信端口164与一个或者多个其他计算设备162通过网络通信链路的通信。
网络通信链路可以是通信介质的一个示例。通信介质通常可以体现为在诸如载波或者其他传输机制之类的调制数据信号中的计算机可读指令、数据结构、程序模块，并且可以包括任何信息递送介质。“调制数据信号”可以这样的信号，它的数据集中的一个或者多个或者它的改变可以在信号中编码信息的方式进行。作为非限制性的示例，通信介质可以包括诸如有线网络或者专线网络之类的有线介质，以及诸如声音、射频(RF)、微波、红外(IR)或者其它无线介质在内的各种无线介质。这里使用的术语计算机可读介质可以包括存储介质和通信介质二者。
在根据本发明的计算设备100中，应用122包括用于执行本发明的异构程序执行方法200的指令，该指令可以指示处理器104执行本发明的异构程序执行方法200。
图2示出了根据本发明一个实施例的异构程序执行方法200的流程图。方法200适于在模拟器中执行，模拟器适于驻留在计算设备(如图1所示的计算设备)中，模拟器中安装有目标异构程序，模拟器的本质是通过软件使A主机架构的工作方式类似于B主机架构，能够执行B主机架构编译的可执行程序，并模拟B主机架构CPU运行该程序的行为和状态。
如图2所示，方法200始于步骤S210，启动模拟器程序，其中，模拟器所驻留的计算设备的处理器架构为第一处理器架构(例如：ARM架构)，模拟器中安装有目标异构程序，而目标异构程序适于运行在第二处理器架构(例如：X86)的计算设备中。
随后进入步骤S220，将目标异构程序加载到模拟器进程地址空间，并记录目标异构程序的入口地址。根据本发明的一个实施例，将目标异构程序的程序头部、依赖的库文件、代码段、数据段等加载到模拟器的HVA中，因此，在模拟器执行目标应用程序时，省去了从GPA-HVA的映射过程，宿主机进程可以直接从HVA中读取目标异构程序，无需通过softMMU进行寻址，没有虚拟内存管理单元，无需进行内存拓扑更新，提升了整体的翻译执行效率，不会出现地址映射过程中GVA内存缺页的现象。在此过程中，需要记录目标异构程序的入口地址entrypoint，该地址是模拟器在执行目标异构程序时需要模拟运行的第一条指令。
图4示出了根据本发明一个实施例的目标异构程序加载至模拟器进程地址空间的示意图，即目标异构程序和宿主进程(模拟器进程)的内存拓扑都属于宿主进程的地址空间，模拟器实现了目标异构程序地址空间的透明访问。
随后在步骤S230中，接收用户启动目标异构程序的启动请求。
在接收到目标异构程序的启动请求时，进入步骤S240，创建虚拟CPU并进行初始化，虚拟CPU包括通用寄存器、PC寄存器、浮点寄存器、状态寄存器、段寄存器等各种物理CPU应该具有的特性，除此之外，还需要保存一些内部缓存和描述状态的变量。虚拟CPU的作用是确定目标架构机器码的反汇编规则，以及模拟目标CPU在执行该架构机器码时的行为和状态。
随后进入步骤S250，将目标异构程序的原机器码翻译成本地机器码。根据本发明的一个实施例，目标异构程序A适于在X86架构下运行，而当前计算设备的架构为ARM架构，则需要将A程序的原机器码转换为适于在ARM 架构下执行的本地机器码，图5示出了根据本发明一个实施例的目标异构程序机器码翻译过程示意图，通过语义对等翻译，使应用程序能够在当前ARM计算设备上运行。翻译过程需要结合目标CPU架构类型，CPU特性，逐条指令翻译，模拟目标CPU执行该指令时的行为，模拟器需要根据指令模拟执行的结果，修改目标CPU寄存器，目标CPU内部变量，以及目标CPU的运行状态等。
随后进入步骤S260，执行翻译后的本地机器码。根据记录的程序入口地址，虚拟CPU从程序入口地址执行翻译后的本地机器码。因为生成的本地机器码和原机器码的语义对等，看起来就像在执行本地机器码一样。
在执行完目标异构程序的本地机器码后，进入步骤S270，返回模拟器进程内存地址空间执行其他代码。
图3示出了根据本发明一个实施例的异构程序执行装置300的示意图，适于驻留在模拟器中，模拟器适于驻留在计算设备(如图1所示的计算设备)中，计算设备的处理器架构够第一处理器架构(例如：ARM)，装置300包括加载器模块310、CPU模块320、翻译模块330和执行模块340,。
加载器模块310，适于当模拟器启动时，获取模拟器上的目标异构程序，并将目标异构程序加载到模拟器进程的内存地址空间，其中目标异构程序适于在第二处理器架构(例如：X86)的设备中执行。
CPU模块，适于在模拟器接收到启动目标异构程序的启动指令时创建虚拟CPU，其中，虚拟CPU的特征信息包括通用寄存器、PC寄存器、浮点寄存器、状态寄存器、段寄存器。
翻译模块330，适于当执行目标异构程序的原机器码转换为适于在第一处理器架构中执行的本地机器码。
执行模块340，适于从程序入口地址执行目标异构程序的本地机器码。
根据本发明的异构程序执行方法，当模拟器启动时，获取模拟器上的目标异构程序，将目标异构程序直接加载到模拟器进程的内存地址空间中，当接收到目标异构程序的启动指令时，通过创建虚拟CPU直接从模拟器进程的内存地址空间中读取应用程序指令，实现了透明内存访问，可以在宿主进程的内存地址空间直接访问应用程序指令，避免了Un icorn中内存地址映射过程，降低了异构进程管理的复杂性，没有了地址映射过程，提升了异构程序 运行效率和性能，也不会出现地址内存缺失的情况。
这里描述的各种技术可结合硬件或软件，或者它们的组合一起实现。从而，本发明的方法和设备，或者本发明的方法和设备的某些方面或部分可采取嵌入有形媒介，例如可移动硬盘、U盘、软盘、CD-ROM或者其它任意机器可读的存储介质中的程序代码(即指令)的形式，其中当程序被载入诸如计算机之类的机器，并被所述机器执行时，所述机器变成实践本发明的设备。
在程序代码在可编程计算机上执行的情况下，计算设备一般包括处理器、处理器可读的存储介质(包括易失性和非易失性存储器和/或存储元件)，至少一个输入装置，和至少一个输出装置。其中，存储器被配置用于存储程序代码；处理器被配置用于根据该存储器中存储的所述程序代码中的指令，执行本发明的异构程序执行方法。
以示例而非限制的方式，可读介质包括可读存储介质和通信介质。可读存储介质存储诸如计算机可读指令、数据结构、程序模块或其它数据等信息。通信介质一般以诸如载波或其它传输机制等已调制数据信号来体现计算机可读指令、数据结构、程序模块或其它数据，并且包括任何信息传递介质。以上的任一种的组合也包括在可读介质的范围之内。
在此处所提供的说明书中，算法和显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与本发明的示例一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本发明也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本发明的内容，并且上面对特定语言所做的描述是为了披露本发明的最佳实施方式。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确 记载的特征更多特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。
本领域那些技术人员应当理解在本文所公开的示例中的设备的模块或单元或组件可以布置在如该实施例中所描述的设备中，或者可替换地可以定位在与该示例中的设备不同的一个或多个设备中。前述示例中的模块可以组合为一个模块或者此外可以分成多个子模块。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
此外，所述实施例中的一些在此被描述成可以由计算机系统的处理器或者由执行所述功能的其它装置实施的方法或方法元素的组合。因此，具有用于实施所述方法或方法元素的必要指令的处理器形成用于实施该方法或方法元素的装置。此外，装置实施例的在此所述的元素是如下装置的例子：该装置用于实施由为了实施该发明的目的的元素所执行的功能。
如在此所使用的那样，除非另行规定，使用序数词“第一”、“第二”、“第三”等等来描述普通对象仅仅表示涉及类似对象的不同实例，并且并不 意图暗示这样被描述的对象必须具有时间上、空间上、排序方面或者以任意其它方式的给定顺序。
尽管根据有限数量的实施例描述了本发明，但是受益于上面的描述，本技术领域内的技术人员明白，在由此描述的本发明的范围内，可以设想其它实施例。此外，应当注意，本说明书中使用的语言主要是为了可读性和教导的目的而选择的，而不是为了解释或者限定本发明的主题而选择的。因此，在不偏离所附权利要求书的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。对于本发明的范围，对本发明所做的公开是说明性的，而非限制性的，本发明的范围由所附权利要求书限定。

Claims (10)

  1. 一种异构程序执行方法，适于在模拟器中执行，所述模拟器适于驻留在计算设备中，所述模拟器上安装有目标异构程序，所述方法包括：
    当所述模拟器启动时，获取所述模拟器上的目标异构程序；
    将所述目标异构程序加载到所述模拟器进程的内存地址空间；
    根据所述目标异构程序的启动请求创建虚拟CPU；
    通过所述虚拟CPU执行所述目标异构程序。
  2. 如权利要求1所述的方法，其中，所述将所述目标异构程序加载到所述模拟器进程的内存地址空间包括：
    将所述目标异构程序的代码段、数据段以及依赖的库文件加载到所述模拟器进程的内存地址空间；
    记录所述目标异构程序的入口地址。
  3. 如权利要求1或2所述的方法，其中，所述根据所述目标异构程序的启动请求创建虚拟CPU包括：
    当接收到用户启动所述目标异构程序的启动请求时，创建虚拟CPU，所述虚拟CPU的特征信息包括通用寄存器、PC寄存器、浮点寄存器、状态寄存器、段寄存器。
  4. 如权利要求1所述，所述计算设备为第一处理器架构，所述目标异构程序适于在第二处理器架构中执行，所述通过所述虚拟CPU执行所述目标异构程序包括：
    根据所述第二处理器架构中CPU的反汇编规则将所述目标异构程序的原机器码翻译成中间字节码；
    将所述中间字节码翻译成本地机器码，所述本地机器码适于在所述第一处理器架构中执行；
    根据所述目标异构程序的入口内存地址执行所述本地机器码。
  5. 如权利要求1-4中任意一项所述的方法，还包括：
    当所述虚拟CPU执行完所述目标异构程序时，返回所述模拟器进程对应 的内存地址空间。
  6. 如权利要求1-5中任意一项所述的方法，所述模拟器是基于Qemu实现的。
  7. 一种异构程序执行装置，适于驻留在模拟器中，所述模拟器适于驻留在计算设备中，所述异构程序执行装置包括加载器模块、执行模块、CPU模块，其中，
    加载器模块，适于当所述模拟器启动时，获取所述模拟器上的目标异构程序；将所述目标异构程序加载到所述模拟器进程的内存地址空间；
    CPU模块，适于根据所述目标异构程序的启动请求创建虚拟CPU；
    执行模块，适于通过所述虚拟CPU执行所述目标异构程序。
  8. 如权利要求7所述的装置，其中，所述将所述目标异构程序加载到所述模拟器进程的内存地址空间包括：
    将所述目标异构程序的代码段、数据段以及依赖的库文件加载到所述模拟器进程的内存地址空间；
    记录所述目标异构程序的入口地址。
  9. 一种计算设备，包括：
    至少一个处理器；以及
    存储器，存储有程序指令，其中，所述程序指令被配置为适于由所述至少一个处理器执行，所述程序指令包括用于执行如权利要求1-6中任一项所述方法的指令。
  10. 一种存储有程序指令的可读存储介质，当所述程序指令被计算设备读取并执行时，使得所述计算设备执行如权利要求1-6中任一项所述方法。
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