WO2022236799A1 - 一种电压调节模块及集成芯片 - Google Patents

一种电压调节模块及集成芯片 Download PDF

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Publication number
WO2022236799A1
WO2022236799A1 PCT/CN2021/093772 CN2021093772W WO2022236799A1 WO 2022236799 A1 WO2022236799 A1 WO 2022236799A1 CN 2021093772 W CN2021093772 W CN 2021093772W WO 2022236799 A1 WO2022236799 A1 WO 2022236799A1
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Prior art keywords
transistor
coupled
switch tube
regulation module
voltage
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PCT/CN2021/093772
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English (en)
French (fr)
Inventor
卢玉亮
曾思坷
郑远辉
张传义
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华为技术有限公司
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Priority to PCT/CN2021/093772 priority Critical patent/WO2022236799A1/zh
Priority to CN202180074467.9A priority patent/CN116391307A/zh
Publication of WO2022236799A1 publication Critical patent/WO2022236799A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Definitions

  • the present application relates to the field of chip technology, in particular to a voltage regulation module and an integrated chip.
  • the voltage regulator module is a module that provides a suitable power supply voltage for the processor. Since the VRM can provide an adjustable voltage, it can supply power to processors with different supply voltages on the single board.
  • a VRM adopts a multi-phase step-down (BUCK) circuit topology, as shown in Figure 1 for a three-phase VRM circuit.
  • the circuit includes three parallel BUCK circuits, the first BUCK circuit includes switch tube Q1A, switch tube Q1B and inductor L1, the second BUCK circuit includes switch tube Q2A, switch tube Q2B and inductor L2, and the third BUCK circuit includes switch tube Q3A, switch tube Q3B and inductor L3.
  • the BUCK circuit is used for step-down conversion of the input voltage Vin to obtain the power supply voltage Vo required by the processor chip.
  • the first BUCK circuit as an example to illustrate how the BUCK circuit steps down the input voltage Vin: when the upper transistor Q1A is turned on and the lower transistor Q1B is turned off, Vin transfers energy to the output side through Q1A and inductor L1; When the transistor Q1B is turned on and the upper transistor Q1A is turned off, the inductor L1 freewheels through the lower transistor Q1B to transfer energy to the output side.
  • the output voltage Vo can be adjusted by controlling the conduction time of the upper transistor Q1A and the lower transistor Q1B.
  • the reason why multiple BUCK circuits are connected in parallel is: in the case of a large load current Io, multiple BUCK circuits can be connected in parallel to realize the shunting of the load current, and avoid a single BUCK circuit from flowing through a relatively large load current. High current, resulting in the risk of damage to the switch tube.
  • the rapid rise and fall of the output voltage is usually suppressed by adjusting the conduction time of the upper transistor: when the chip is loaded rapidly, the output voltage Vo falls and the amplitude exceeds the threshold V LT and triggers nonlinear regulation, and the controller increases the BUCK
  • the conduction time of the tubes (Q1A, Q2A, Q3A) on the circuit allows more energy to be transferred to the output side per unit time, suppressing voltage drops; when the chip is quickly unloaded, the output voltage Vo rises rapidly and exceeds the threshold V HT
  • the controller turns off the upper transistors (Q1A, Q2A, Q3A) of the BUCK circuit, disconnects the energy transfer from the input side to the output side, and suppresses the rise of the output voltage.
  • the power control scheme provided by the prior art has an unsatisfactory suppression effect on the rapid rise of the output voltage Vo when the chip is rapidly unloaded, which affects the performance of the chip and even causes damage to the chip.
  • the embodiment of the present application provides a voltage regulation module and an integrated chip, which are used to supply power to the processor chip, and suppress the rapid rise of the output voltage of the voltage regulation module when the processor chip is quickly unloaded, so as to provide stable power supply for the chip.
  • the embodiment of the present application provides a voltage regulation module, the voltage regulation module includes a first conversion circuit and a first discharge circuit; wherein, the first conversion circuit includes: a first switch tube, a first primary coil and the second switch tube.
  • the first switch tube is coupled to the positive pole of the input source; one end of the first primary coil is coupled to the first switch tube, and the other end of the first primary coil is coupled to the processor chip; one end of the second switch tube is coupled to the first switch tube It is coupled to the connection point of the first primary coil, and the other end is coupled to the negative pole of the input source; the first switching tube and the second switching tube are turned on alternately.
  • the two ends of the first unloading circuit are respectively coupled with the positive pole and the negative pole of the input source, and the first unloading circuit includes a first secondary coil, a first transistor and a second transistor connected in series; the first secondary coil and the first primary The coils form a first transformer by electromagnetic coupling.
  • the processor chip may be a central processing unit CPU or a graphics processing unit GPU.
  • the first switch tube and the second switch tube may be metal-oxide semiconductor field effect transistors MOSFETs, gallium nitride transistors, triodes, and the like.
  • the first conversion circuit is used to realize the step-down function, and may be, for example, a BUCK conversion circuit or a BUCK-BOOST conversion circuit.
  • the first transistor and the second transistor in the first unloading circuit can be controlled to switch from the off state to the on state, so that the first secondary coil
  • the generated first induced current can be discharged through the first discharge circuit, so as to reduce the energy of the output side of the voltage regulation module and suppress the rapid rise of the output voltage of the voltage regulation module.
  • the energy of the first primary coil can be released not only through the output capacitor, but also through the first discharge circuit, so that the energy of the first primary coil can be released quickly, shortening the adjustment time of the output voltage , to improve the suppression effect on the rapid rise of the output voltage.
  • the winding directions of the first primary coil and the first secondary coil are opposite.
  • the first transistor and the second transistor are only turned on when the output voltage of the voltage regulation module is too high, the voltage at the end of the positive coupling between the first primary coil and the input source is lower than that between the first primary coil and the processor.
  • the voltage at one end of the chip coupling only when the voltage at the end of the first secondary coil coupled with the positive pole of the input source is greater than the voltage at the end coupled with the negative pole of the first secondary coil with the input source, the first unloading circuit can release the first induced current discharge to prevent the first sense current from pouring back into the input source. Therefore, the winding directions of the first primary coil and the first secondary coil need to be opposite, so that the polarities of the first primary coil and the first secondary coil are opposite to prevent the phenomenon that the first induced current flows back into the input source.
  • the first transistor and the second transistor are switched from the off state to the on state, and the first induced current in the first secondary coil passes through The first unloading circuit unloads.
  • the first transistor and the second transistor when the conduction duration of the first transistor and the second transistor reaches a preset duration or the current flowing through the first secondary coil is less than the second threshold, the first transistor and the second transistor are turned on by state switches to off state.
  • the turn-off time of the first transistor and the second transistor can be reasonably controlled, so as to avoid the phenomenon that the above-mentioned input source reversely charges the first primary coil through the first secondary coil.
  • the voltage regulation module provided in the first aspect may further include a current sampling circuit and a comparator.
  • the current sampling circuit is used to detect the current of the first secondary coil after the first transistor and the second transistor are switched from the off state to the on state;
  • the comparator is coupled with the current sampling circuit, and is used to convert the current of the first secondary coil to value is compared with the third threshold value, when the current value of the first secondary coil is less than the third threshold value, the output signal of the comparator is turned from high level to low level; the output terminal of the comparator and the gate of the first transistor /base coupling.
  • the output terminal of the comparator may also be coupled to the gate/base of the second transistor.
  • the current sampling circuit and the comparator can be used to control the voltage of the first transistor and the second transistor. off.
  • the voltage regulation module provided in the first aspect may further include a timer and a comparator.
  • the timer is used to start counting when the first transistor and the second transistor are switched from the off state to the on state;
  • the comparator is coupled to the timer, and is used to compare the timing duration of the timer with a preset duration, and when the timing duration reaches During a preset time period, the output signal of the comparator is inverted from high level to low level; the output terminal of the comparator is coupled to the gate/base of the first transistor.
  • the output terminal of the comparator may also be coupled to the gate/base of the second transistor.
  • the current sampling circuit and the timer can be used to control the current of the first transistor and the second transistor. off.
  • the conduction time of the first switch within a unit time length changes from the first time length to the second time length, and the second time length is longer than the first time length .
  • the configurations of the first transistor and the second transistor are described below through several specific examples.
  • Example 1 the first transistor is a third switch transistor, and the second transistor is a fourth switch transistor. That is to say, both the first transistor and the second transistor are switch transistors.
  • a connection mode of the third switch tube and the fourth switch tube may be: the source/collector of the third switch tube and the The first secondary coil is coupled, the drain/emitter of the third switching tube is coupled with the drain/emitter of the fourth switching tube, and the source/collector of the fourth switching tube is coupled with the negative electrode of the input source.
  • both the third switch transistor and the fourth switch transistor may also be NMOS.
  • the third switch transistor is NMOS
  • the fourth switch transistor is PMOS
  • the third switch transistor is PMOS
  • the fourth switch transistor is NMOS.
  • the third switch tube and the fourth switch tube are turned off. At this time, it is not expected that there will be current flowing in the first unloading circuit, otherwise the input voltage will pass through the coupling inductor (that is, the first The primary coil and the first secondary coil) are superimposed on the output side, causing the output voltage to fluctuate.
  • the drain of the third switching tube is connected to the drain of the fourth switching tube, and the diodes in the third switching tube and the fourth switching tube cannot form a conduction loop, which can avoid the above phenomenon.
  • the first transistor is a diode
  • the second transistor is a third switch. That is to say, among the first transistor and the second transistor, one transistor is a switch transistor, and the other transistor is a diode.
  • the third switch tube is a MOSFET
  • the third switch tube may be NMOS or PMOS.
  • the cathode of the diode is coupled to the first secondary coil
  • the anode of the diode is coupled to the drain/collector of the third switch
  • the source/emitter of the third switch is coupled to the cathode of the input source coupling.
  • the source/collector of the third switching tube is coupled to the first secondary coil
  • the drain/emitter of the third switching tube is coupled to the cathode of the diode
  • the anode of the diode is coupled to the input source Negative coupling.
  • the diode and the third switching tube are connected in this way. Due to the reverse cut-off characteristic of the diode, when the third switching tube is turned off, the first discharge circuit cannot form a conduction loop, thereby preventing the input side from coupling The coil reverse charges the output side.
  • the cathode of the diode is coupled to the anode of the input source
  • the anode of the diode is coupled to the first secondary coil
  • the drain/collector of the third switching tube is coupled to the first secondary coil
  • the third The source/emitter of the switch tube is coupled to the negative pole of the input source.
  • the diode and the third switching tube are connected in this way. Due to the reverse cut-off characteristic of the diode, when the third switching tube is turned off, the first discharge circuit cannot form a conduction loop, thereby preventing the input side from coupling The coil reverse charges the output side.
  • the voltage regulation module provided in the first aspect can also adopt a method of connecting multiple conversion circuits in parallel, so as to realize the shunting of the input current, and avoid large current from flowing through the switch tube in the conversion circuit and damaging the switch tube.
  • the voltage regulation module provided in the first aspect may further include a second conversion circuit and a second unloading circuit.
  • the second conversion circuit includes: a fifth switching tube, the fifth switching tube is coupled to the positive pole of the input source; a second primary coil, one end of the second primary coil is coupled to the fifth switching tube, and the second primary coil The other end is coupled to the processor chip; the sixth switch tube, one end of the sixth switch tube is coupled to the connection point between the fifth switch tube and the second primary coil, and the other end is coupled to the negative pole of the input source; the fifth switch tube is connected to the second primary coil
  • the six switch tubes are turned on alternately.
  • the voltage regulation module adopts multiple conversion circuits connected in parallel
  • the structures of the multiple parallel conversion circuits are similar, but there are many ways to implement the second unloading circuit, some of which are listed below.
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a third transistor and a fourth transistor connected in series; the second The secondary coil and the second primary coil form a second transformer through electromagnetic coupling.
  • the second conversion circuit is connected in parallel with the first conversion circuit, and the second unloading circuit is connected in parallel with the first unloading circuit.
  • the structure of the voltage regulation module is simple, and there is no coupling between the phases, which is convenient for control. More generally, the voltage regulation module may include multiple parallel conversion circuits and multiple parallel discharge circuits.
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a first transistor, and a second transistor connected in series;
  • the second transformer is formed by electromagnetic coupling between the two secondary coils and the second primary coil.
  • the second unloading circuit and the first unloading circuit share the first transistor and the second transistor, so the number of transistors configured in the voltage regulation module is small, which is convenient for control.
  • the voltage regulation module may include multiple parallel conversion circuits and multiple parallel unloading circuits, each unloading circuit is configured with a separate secondary coil, and multiple unloading circuits share the first transistor and the second transistor. Two transistors.
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a first transistor, and a third transistor connected in series;
  • the second transformer is formed by electromagnetic coupling between the two secondary coils and the second primary coil.
  • a diode is separately configured in each unloading circuit. Due to the reverse cut-off characteristic of the diode, no circulating current can be generated between the secondary coils, which can reduce the loss of the voltage regulation module. In addition, since each discharge circuit includes a diode, the reverse blocking characteristic of the diode can also prevent the input side from reversely charging the output side through the coupling coil.
  • the first conversion circuit may further include an input capacitor and an output capacitor, the two ends of the input capacitor are respectively coupled to the positive pole and the negative pole of the input source, and the two ends of the output capacitor are respectively coupled to the processor chip and the negative pole of the input source.
  • the embodiment of the present application also provides an integrated chip, the integrated chip includes a processor chip and the voltage regulation module provided in the above-mentioned first aspect and any possible design thereof, the voltage regulation module is used for the processor chip powered by.
  • FIG. 1 is a schematic structural diagram of a voltage regulation module provided in the prior art
  • FIG. 2 is a schematic structural diagram of the first voltage regulation module provided by the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a second voltage regulation module provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a third voltage regulation module provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a fourth voltage regulation module provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a fifth voltage regulation module provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a sixth voltage regulation module provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a seventh voltage regulation module provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an eighth voltage regulation module provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a ninth voltage regulation module provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a tenth voltage regulation module provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an eleventh voltage regulation module provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a twelfth voltage regulation module provided by an embodiment of the present application.
  • FIG. 14 is a timing diagram of the state of a switch tube and the magnitude of the output current provided by the embodiment of the present application;
  • FIG. 15 is a timing diagram of the state of the switching tube, the output current, and the output voltage provided by the embodiment of the present application;
  • FIG. 16 is a schematic structural diagram of a thirteenth voltage regulation module provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a fourteenth voltage regulation module provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a fifteenth voltage regulation module provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of an integrated chip provided by an embodiment of the present application.
  • An embodiment of the present application provides a voltage regulation module, which is used to supply power to a processor chip.
  • the processor chip may be a central processing unit (central processing unit, CPU), a graphics processing unit (graphics processing unit, GPU) and the like.
  • CPU central processing unit
  • GPU graphics processing unit
  • the processor chip may also be other chips for processing services, and the embodiment of the present application does not limit the specific type of the processor chip.
  • the voltage regulation module 200 includes a first conversion circuit 201 and a first discharge circuit 202 .
  • the first conversion circuit 201 includes a first switch tube, a first primary coil and a second switch tube.
  • the first switch tube is coupled to the positive pole of the input source; one end of the first primary coil is coupled to the first switch tube, and the other end of the first primary coil is coupled to the processor chip; one end of the second switch tube is coupled to the first switch tube It is coupled to the connection point of the first primary coil, and the other end is coupled to the negative pole of the input source; the first switching tube and the second switching tube are turned on alternately.
  • the two ends of the first unloading circuit 202 are respectively coupled with the positive pole and the negative pole of the input source, and the first unloading circuit 202 includes a first secondary coil, a first transistor and a second transistor connected in series; the first secondary coil and the first The primary coil forms a first coupled inductor through electromagnetic coupling.
  • the switch tube which can also be called a power tube or a power switch tube, is commonly used as a metal-oxide-semiconductor field-effect transistor (MOSFET), a triode, or a gallium nitride transistor. (gallium nitride, GaN) transistors, etc.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • Transistors can be diodes or MOSFETs.
  • the first conversion circuit 201 is used to realize the step-down function, for example, it may be a BUCK conversion circuit or a BUCK-BOOST conversion circuit.
  • the implementation of the first conversion circuit 201 shown in FIG. 2 is only an example. In the embodiment of the present application, the specific form of the first conversion circuit 201 is not limited, as long as the first conversion circuit 201 can realize the step-down function.
  • the working principle of the first conversion circuit 201 is: when the first switch tube is turned on and the second switch tube is turned off, the input source transmits energy to the output side through the first switch tube and the first primary coil; When the second switch tube is turned on and the first switch tube is turned off, the first primary side coil continues to flow through the second switch tube to transfer energy to the output side.
  • the adjustment of the output voltage can be realized, thereby providing an adjustable voltage for the processor chip.
  • the series sequence of the first secondary coil, the first transistor and the second transistor in the first unloading circuit 202 there is no specific limitation on the series sequence of the first secondary coil, the first transistor and the second transistor in the first unloading circuit 202.
  • the series sequence of the first secondary coil ⁇ the first transistor ⁇ the second transistor can also be used.
  • the series sequence of the first secondary coil ⁇ the second transistor ⁇ the first transistor is adopted.
  • the first conversion circuit may further include an input capacitor and an output capacitor. As shown in FIG. Negative coupling between the processor chip and the input source.
  • the first transistor and the second transistor in the first unloading circuit 202 are in the off state by default, then, after the voltage regulating module 200 is powered on, the voltage regulating module 200 works normally, and the first unloading circuit 202 When not conducting, only the first conversion circuit 201 works, and the working principle of the voltage regulation module 200 is the same as that of the VRM in the prior art.
  • the voltage drop can be suppressed by the following method: increasing the conduction time of the first switch tube in a unit time, so that more energy is transferred to the output in a unit time side, thereby suppressing the output voltage drop. That is to say, when the output voltage of the voltage regulation module 200 is less than the third threshold, the turn-on time of the first switch within a unit time period can be changed from the first time period to the second time period, and the second time period is longer than the first time period.
  • the specific values of the third threshold, the first duration and the second duration can be configured.
  • the voltage regulation module 200 suppresses the voltage drop in the same way as shown in FIG. 1 in the prior art.
  • the voltage rise can be suppressed in the following manner: when the output voltage of the voltage regulation module is greater than the first threshold, the first switch tube and the second switch tube are turned off , the energy of the first primary coil is released through the output capacitor; at the same time, the first transistor and the second transistor are switched from the off state to the on state, and the first induced current in the first secondary coil passes through the first discharge circuit 202 Rapid discharge, wherein, the direction of the first induced current can refer to the label in FIG. 2 .
  • the specific value of the first threshold can be configured.
  • the first secondary coil forms a closed loop to generate a first induced current.
  • the first induced current can be discharged through the first unloading circuit 202, and part of the energy on the first coupling inductor is fed back to the input side through the first unloading circuit 202, so that the current on the first primary side coil decreases rapidly, thereby reducing
  • the energy at the output side of the voltage regulation module 200 is reduced to suppress the rapid rise of the output voltage of the voltage regulation module 200 .
  • the winding direction of the first primary coil and the first secondary coil are opposite. That is to say, in FIG. 2 , the terminal a1 of the first primary coil and the terminal a4 of the first secondary coil have the same name.
  • the first transistor and the second transistor are only turned on when the output voltage of the voltage regulation module 200 is too high, and at this time the voltage of the terminal connected to the positive pole of the first primary coil and the input source (that is, terminal a1 in FIG. 2 ) The voltage is lower than the voltage at the end of the first primary coil connected to the processor chip (namely, the a2 end in FIG. 2 ).
  • the first unloading circuit 202 can feed back the first induced current to the input side, so as to achieve the purpose of rapidly reducing the current on the first primary coil.
  • the first transistor and the second transistor in the first unloading circuit 202 can be controlled to switch from the off state to the on state, so that the first secondary side
  • the first induced current generated in the coil can be discharged through the first discharge circuit 202, so as to reduce the energy of the output side of the voltage regulation module 200 and suppress the rapid rise of the output voltage of the voltage regulation module 200.
  • the energy of the first primary coil can be released not only through the output capacitor, but also through the first discharge circuit 202, so that the energy of the first primary coil can be released quickly, shortening the adjustment of the output voltage Time, improve the suppression effect on the rapid rise of the output voltage.
  • the output voltage of the voltage regulation module 200 drops back, at this time, the first transistor and the second transistor can be switched from the on state to the off state. If the first transistor and the second transistor are always on, the induced current of the first secondary coil will continuously decrease to zero.
  • the first secondary coil has a current zero-crossing phenomenon (that is, the voltage at the a3 terminal is reduced to be equal to the voltage at the a4 terminal)
  • the input voltage of the input source reversely charges the first primary coil through the first secondary coil, and instead As a result, the output voltage of the voltage regulation module 200 increases. Therefore, in the voltage regulation module 200, it is necessary to reasonably control the off time of the first transistor and the second transistor.
  • the first transistor and the second transistor can be turned on by state switches to off state.
  • the preset duration and the second threshold can be configured according to different application scenarios.
  • the turn-off timing of the first transistor and the second transistor can be controlled from the two dimensions of the turn-on duration and current magnitude of the first discharge circuit 202 .
  • the voltage regulation module 200 may further include a current sampling circuit and a comparator, as shown in FIG. 4 .
  • the current sampling circuit is used to detect the current of the first secondary coil after the first transistor and the second transistor are switched from the off state to the on state;
  • the comparator is coupled with the current sampling circuit, and is used to convert the current of the first secondary coil to value is compared with the second threshold value, when the current value of the first secondary coil is less than the second threshold value, the output signal of the comparator is turned from high level to low level; the output terminal of the comparator is connected with the first transistor and the second The gate coupling of the transistor.
  • the transistor may be a diode or a switch.
  • the implementation shown in FIG. 4 can be adapted to the case where both the first transistor and the second transistor are switching transistors.
  • the output terminals of the comparator are respectively coupled to the gates of the first transistor and the second transistor, and are used to control the first and second transistors to be turned on and off.
  • the second transistor can also be a diode. Since the turn-on and turn-off of the diode is determined by its own polarity and the polarity of the applied voltage, it cannot be controlled through a control terminal (eg gate). Therefore, the comparator is only used to control the turn-on and turn-off of the first transistor.
  • the voltage regulation module 200 may further include a timer and a comparator, as shown in FIG. 5 .
  • the timer is used to start counting when the first transistor and the second transistor are switched from the off state to the on state; the comparator is coupled to the timer, and is used to compare the timing duration of the timer with a preset duration, and when the timing duration reaches During a preset time period, the output signal of the comparator is inverted from high level to low level; the output terminal of the comparator is coupled to the gates of the first transistor and the second transistor.
  • the implementation manner shown in FIG. 5 can be adapted to the case where both the first transistor and the second transistor are switch transistors.
  • the output terminals of the comparator are respectively coupled to the gates of the first transistor and the second transistor, and are used to control the first and second transistors to be turned on and off.
  • the second transistor can also be a diode. Since the turn-on and turn-off of the diode is determined by its own polarity and the polarity of the applied voltage, it cannot be controlled through a control terminal (eg gate). Therefore, the comparator is only used to control the turn-on and turn-off of the first transistor.
  • the transistor may be a diode or a switch.
  • Different configurations of the first transistor and the second transistor are described below with several specific examples.
  • the first transistor may be a third switch transistor
  • the second transistor may be a fourth switch transistor. That is to say, both the first transistor and the second transistor are switch transistors.
  • FIG. 6 A possible implementation manner of the voltage regulation module can be shown in FIG. 6 .
  • Q1 represents the first switching tube
  • Q2 represents the second switching tube
  • Q3 represents the third switching tube
  • Q4 represents the fourth switching tube
  • Vin represents the input source
  • Cin represents the input capacitance
  • Co represents the output capacitance
  • Lp represents the first primary coil
  • Ls represents the first secondary coil.
  • the switching tubes are illustrated by taking NMOS as an example. In practical applications, the switching transistors may all be PMOS, or a combination of NMOS and PMOS.
  • the drain of Q3 is coupled to the drain of Q4 such that the two anti-parallel diodes in Q3 and Q4 are opposite in polarity, i.e. the cathode of the diode in Q3 is connected to the diode in Q4 the cathode coupling.
  • a connection is based on the following considerations: when the voltage regulation module 200 is working normally or the output voltage drops, Q3 and Q4 are turned off. Coupled inductance (that is, Lp and Ls) is superimposed on the output side, causing output voltage fluctuations. Connect the drain of Q3 to the drain of Q4, and the diodes in the two MOSFETs cannot form a conduction loop, which can avoid the above phenomenon.
  • both the first transistor and the second transistor are switch transistors, and other coupling methods may also be used for the first transistor and the second transistor.
  • the two electrodes except the gate in Q3 are respectively coupled to the anode of Vin and Ls, and the two electrodes other than the gate in Q4 are respectively coupled to the cathode of Ls and Vin.
  • Q3 can be NMOS or PMOS, and Q4 can also be NMOS or PMOS.
  • the first transistor is a diode
  • the second transistor is a third switch. That is to say, among the first transistor and the second transistor, one transistor is a switch transistor, and the other transistor is a diode.
  • the cathode of the diode is coupled to the first secondary coil
  • the anode of the diode is coupled to the drain of the third switching transistor
  • the source of the third switching transistor is coupled to the negative electrode of the input source, as shown in FIG. 7 .
  • Q1 represents the first switching tube
  • Q2 represents the second switching tube
  • Q3 represents the third switching tube
  • D1 represents the diode
  • Vin represents the input source
  • Cin represents the input capacitance
  • Co represents the output capacitance
  • Lp represents the first A primary side coil
  • Ls represents the first secondary side coil.
  • the switching tubes are illustrated by taking MOSFET as an example, and Q3 is PMOS. In practical application, Q3 can also be NMOS.
  • the cathode of D1 is coupled to Ls
  • the anode of D1 is coupled to the drain of Q3
  • the source of Q3 is coupled to the negative pole of Vin.
  • D1 and Q3 are connected in this way. Due to the reverse cut-off characteristic of D1, when Q3 is turned off, the first discharge circuit 202 cannot form a conduction loop, so as to avoid the output voltage fluctuation caused by the aforementioned input voltage being superimposed on the output side.
  • the source of the third switch is coupled to the first secondary coil
  • the drain of the third switch is coupled to the cathode of the diode
  • the anode of the diode is coupled to the cathode of the input source, as shown in FIG. 8 Show.
  • Q1 represents the first switching tube
  • Q2 represents the second switching tube
  • Q3 represents the third switching tube
  • D1 represents the diode
  • Vin represents the input source
  • Cin represents the input capacitance
  • Co represents the output capacitance
  • Lp represents the first A primary side coil
  • Ls represents the first secondary side coil.
  • the switching tubes are illustrated by taking MOSFET as an example, and Q3 is NMOS. In practical application, Q3 can also be PMOS.
  • D1 and Q3 are connected in this way. Due to the reverse cut-off characteristic of D1, when Q3 is turned off, the first discharge circuit 202 cannot form a conduction loop, avoiding The phenomenon that the aforementioned input voltage is superimposed on the output side appears to avoid output voltage fluctuations.
  • the cathode of the diode is coupled to the anode of the input source
  • the anode of the diode is coupled to the first secondary coil
  • the drain of the third switching tube is coupled to the first secondary coil
  • the source of the third switching tube The pole is coupled to the negative pole of the input source, as shown in Figure 9.
  • Q1 represents the first switching tube
  • Q2 represents the second switching tube
  • Q3 represents the third switching tube
  • D1 represents the diode
  • Vin represents the input source
  • Cin represents the input capacitance
  • Co represents the output capacitance
  • Lp represents the first A primary side coil
  • Ls represents the first secondary side coil.
  • the switching tubes are illustrated by taking MOSFET as an example, and Q3 is PMOS. In practical application, Q3 can also be NMOS.
  • the cathode of D1 is coupled to the positive pole of Vin
  • the anode of D1 is coupled to Ls
  • the drain of Q3 is coupled to Ls
  • the source of Q3 is coupled to the negative pole of Vin.
  • D1 and Q3 are connected in this way. Due to the reverse cut-off characteristic of D1, when Q3 is turned off, the first discharge circuit 202 cannot form a conduction loop, so as to avoid the aforementioned phenomenon that the input voltage is superimposed on the output side and avoid the output voltage fluctuation.
  • the purpose of setting the first transistor and the second transistor is twofold: 1.
  • the voltage regulation module 200 is working or discharging normally, by controlling the first transistor and the second transistor The second transistor is turned off, so that no current flows through the first unloading circuit 202, and the first unloading circuit 202 does not work; 2.
  • the output voltage of the voltage regulation module 200 is too high, by controlling the first transistor and the second The transistor is turned on, so that a current flows in the first discharge circuit 202, so as to discharge the energy on the output side and suppress the rapid rise of the output voltage.
  • the arrangement of the first transistor and the second transistor can play the above functions, it should be regarded as belonging to the protection scope of the embodiment of the present application.
  • multiple conversion circuits can be connected in parallel in the voltage regulation module, so as to realize the shunting of the load current and prevent the single conversion circuit from flowing a large current and damaging the switch tube.
  • multiple parallel conversion circuits may also be included, so as to adapt to the application scenario of a large current load.
  • the voltage regulation module 200 may further include a second conversion circuit and a second discharge circuit; the second conversion circuit includes a fifth switch tube, a second primary coil and a sixth switch tube.
  • the fifth switching tube is coupled to the anode of the input source; one end of the second primary coil is coupled to the fifth switching tube, and the other end of the second primary coil is coupled to the processor chip; one end of the sixth switching tube is coupled to the fifth switching tube It is coupled to the connection point of the second primary coil, and the other end is coupled to the negative pole of the input source; the fifth switching tube and the sixth switching tube are turned on alternately.
  • the voltage regulation module 200 adopts a plurality of conversion circuits connected in parallel, the structures of the parallel conversion circuits are similar, but there are many ways to implement the second unloading circuit, some of which are listed below.
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a third transistor, and a fourth transistor connected in series; the second secondary The coil and the second primary coil form a second coupled inductance through electromagnetic coupling.
  • the second conversion circuit is connected in parallel with the first conversion circuit 201 alone, and the second unloading circuit is connected in parallel with the first unloading circuit 202 alone.
  • the voltage regulation module 200 may include multiple parallel conversion circuits, and each conversion circuit is configured with a discharge circuit, and there is no coupling between the discharge circuits.
  • FIG. 10 Exemplarily, a possible implementation manner of the voltage regulation module 200 including multiple parallel conversion circuits and multiple parallel discharge circuits may be shown in FIG. 10 .
  • the structure of the voltage regulation module 200 is simple, and there is no coupling between phases, which is convenient for control.
  • the unloading circuit adopts the same topology as the first unloading circuit shown in FIG. 6 .
  • the unloading circuit may also adopt the other topologies mentioned above, which will not be repeated here.
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a first transistor, and a second transistor connected in series; the second secondary The coil and the second primary coil form a second coupled inductance through electromagnetic coupling.
  • the second unloading circuit and the first unloading circuit 202 share the first transistor and the second transistor.
  • the voltage regulation module 200 may include multiple parallel conversion circuits and multiple parallel unloading circuits, each unloading circuit is configured with a separate secondary coil, and multiple unloading circuits share the first transistor and The second transistor, as shown in Figure 11.
  • Q3 and Q4 denote a first transistor and a second transistor, respectively.
  • the number of transistors arranged is small, which is convenient for control.
  • a loop may be formed between the secondary coils to generate a circulating current, which increases the loss of the voltage regulation module 200 .
  • the two ends of the second unloading circuit are respectively coupled to the positive pole and the negative pole of the input source, and the second unloading circuit includes a second secondary coil, a first transistor, and a third transistor connected in series; the second secondary The coil and the second primary coil form a second coupled inductance through electromagnetic coupling.
  • the second unloading circuit shares the first transistor with the first unloading circuit, and a third transistor is separately configured.
  • the second transistor in the first unloading circuit and the third transistor in the second unloading circuit may be diodes, and the first transistor shared by multiple unloading circuits may be a switch transistor.
  • the voltage regulation module 200 may include multiple parallel conversion circuits and multiple parallel unloading circuits, the multiple unloading circuits share the first transistor, and each unloading circuit is independently configured with a secondary coil and a diode, as shown in Figure 12.
  • Q3 represents a first transistor.
  • each discharge circuit is equipped with a separate diode, due to the reverse cut-off characteristics of the diode, no circulating current can be generated between the secondary coils, and the voltage can be reduced The loss of the adjustment module 200 is adjusted.
  • the reverse blocking characteristic of the diode can also prevent the input side from reversely charging the output side through the coupling coil.
  • the conduction time of the first switch tube in the unit time length can be increased, so that within the unit time length There is more energy delivered to the output side, thereby suppressing the drop of the output voltage.
  • the processor chip is quickly unloaded and the output voltage of the voltage regulation module 200 exceeds the first threshold, the first switch tube and the second switch tube are turned off, and the first transistor and the second transistor are switched from the off state to the on state.
  • the first induced current in the first secondary coil is discharged through the first unloading circuit 202, and part of the energy on the first coupled inductance is fed back to the input side through the first unloading circuit 202, thereby reducing the voltage of the voltage regulation module 200.
  • the energy on the output side suppresses the rapid rise of the output voltage of the voltage regulation module 200 .
  • the energy of the first primary coil can be released not only through the output capacitor, but also through the first discharge circuit 202, so that the energy of the first primary coil can be released quickly, shortening the adjustment of the output voltage Time, improve the suppression effect on the output voltage rise.
  • the output inductance of the BUCK circuit is a coupling inductance
  • the primary side Lp of the coupling inductance is the output inductance of the BUCK circuit
  • the secondary side Ls is connected to the input Vin to provide a discharge path.
  • the circuit is the same as the common buck circuit, and has two working states: when the upper transistor Q1 is turned on and the lower transistor Q2 is turned off, the input side Vin transfers energy to the output side through the upper transistor Q1 and the inductor Lp, and ILp gradually increase; when the lower transistor Q2 is turned on and the upper transistor Q1 is turned off, the inductance Lp continues to flow through the lower transistor Q2, and ILp gradually decreases.
  • the states of Q1 and Q2 and the changes of ILp can be shown in FIG. 14 .
  • the auxiliary transistors Q3 and Q4 are turned off, and the upper transistor Q1 and the lower transistor Q2 resume normal operation.
  • the timing diagram of the output current and the output voltage can be shown in FIG. 15 .
  • the auxiliary transistors Q3 and Q4 are not expected to be turned on, so as to prevent the input voltage from being superimposed on the output side through the coupled inductor, causing output voltage fluctuations. Therefore, during normal operation, the auxiliary tubes Q3 and Q4 are always off. Similarly, when the processor chip is loaded and the output voltage Vo drops, the auxiliary transistors Q3 and Q4 are not turned on to avoid output oscillation. Only when the output voltage Vo is too high, the auxiliary transistors Q3 and Q4 are turned on.
  • the conduction of the auxiliary transistors Q3 and Q4 can effectively suppress the rapid rise of the output voltage Vo.
  • the conduction time of Q3 and Q4 is too long, there will be a phenomenon that the secondary current of the coupled inductor crosses zero first before exiting the nonlinearity.
  • the input voltage Vin is reversely charged to the primary side through the secondary side Ls, resulting in an increase in the output voltage Vo (the loop path of the secondary side: Vin->Ls->Q3->Q4->Vin, the loop path of the primary side: Lp- >Co->Q2->Lp), as shown in Figure 16. Therefore, it is necessary to reasonably control the turn-on and turn-off moments of the auxiliary transistors Q3 and Q4.
  • the auxiliary pipes Q3 and Q4 can be controlled by the following three methods.
  • Method 1 current detection method. As shown in Figure 17, a current sampling circuit is added to the secondary side of the coupled inductor, and the detection is started when the auxiliary transistors Q3 and Q4 are turned on, and not detected when they are turned off. When it is detected that the secondary current is lower than the set threshold Is_th (threshold can be configured), the comparator U1 flips to a low level, and the auxiliary transistors Q3 and Q4 are turned off in advance.
  • Is_th threshold can be configured
  • Method 2 Constant on-time method. As shown in Figure 18, the control circuit adds a timing function, which starts timing when the auxiliary tubes Q3 and Q4 are turned on, and stops timing when they are turned off. When the timing reaches the set threshold (the threshold can be configured), the timer U2 outputs a low level, thereby turning off the auxiliary transistors Q3 and Q4.
  • the timing threshold can be set to different values according to different application scenarios.
  • Method 3 Diode unidirectional conduction method. As shown in the examples of FIG. 7 , FIG. 8 and FIG. 9 , the auxiliary transistors Q3 and Q4 are replaced with MOS transistors Q3 and diode D1 . Due to the unidirectional conduction characteristic of the diode, when the auxiliary transistor Q3 is turned on for too long, the input voltage cannot form a charging circuit on the secondary side of the coupling inductor, so the primary side will not be reversely charged. This method does not require precise control of the shutdown of the auxiliary tube Q3, as long as it is ensured that Q3 is turned on when the output voltage is high and enters nonlinearity, and Q3 is turned off when the recovery process exits nonlinearity.
  • the embodiment of the present application also provides an integrated chip.
  • the integrated chip 1900 includes a processor chip 1901 and the aforementioned voltage regulation module 200 , and the voltage regulation module 200 is used to supply power to the processor chip 1901 .

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Abstract

一种电压调节模块及集成芯片，用以为处理器芯片供电，并在处理器芯片快速卸载时抑制电压调节模块的输出电压快速上升，为芯片提供稳定供电。电压调节模块包括第一变换电路和第一卸放电路；第一变换电路包括第一开关管、第一原边线圈和第二开关管。第一开关管与输入源的正极耦合；第一原边线圈的一端与第一开关管耦合，另一端与处理器芯片耦合；第二开关管的一端与第一开关管和第一原边线圈的连接点耦合，另一端与输入源的负极耦合；第一开关管与第二开关管交替导通。第一卸放电路的两端分别与输入源的正极和负极耦合，第一卸放电路包括串联的第一副边线圈、第一晶体管和第二晶体管；第一副边线圈与第一原边线圈通过电磁耦合形成第一变压器。

Description

一种电压调节模块及集成芯片 技术领域
本申请涉及芯片技术领域，尤其涉及一种电压调节模块及集成芯片。
背景技术
电压调节模块(voltage regulator module，VRM)是为处理器提供合适的供电电压的模块。由于VRM可以提供可调节的电压，因而可以为单板上采用不同供电电压的处理器供电。
通常，VRM采用多相降压(BUCK)电路拓扑，如图1所示为三相VRM电路。该电路包括三个并联的BUCK电路，第一个BUCK电路包括开关管Q1A、开关管Q1B和电感L1，第二个BUCK电路包括开关管Q2A、开关管Q2B和电感L2，第三个BUCK电路包括开关管Q3A、开关管Q3B和电感L3。BUCK电路用于对输入电压Vin进行降压变换，以得到处理器芯片所需的供电电压Vo。下面，以第一个BUCK电路为例，说明BUCK电路如何对输入电压Vin进行降压：当上管Q1A导通、下管Q1B关断时，Vin通过Q1A和电感L1向输出侧传递能量；当下管Q1B导通、上管Q1A关断时，电感L1通过下管Q1B续流，向输出侧传递能量。通过控制上管Q1A和下管Q1B的导通时长，可以实现输出电压Vo的调节。在图1所示的VRM中，采用多个BUCK电路并联的原因是：在负载电流Io较大的情况下，多个BUCK电路并联可以实现对负载电流的分流，避免单路BUCK电路流过较大电流，造成损坏开关管的风险。
处理器芯片在处理业务时，存在快速加载和卸载的过程：当芯片处理的业务量瞬间增大(加载)时，芯片的负载电流Io突变为较大值；而流过电感(L1、L2和L3)的电流无法突变，导致电流I L无法突变，I L的值小于Io的值；因此，输出电容Co会通过向负载放电来填补电流缺口，导致Vo快速下降(跌落)。当芯片处理的业务量瞬间减小或无业务处理(卸载)时，芯片的负载电流Io突变为较小值；而流过电感(L1、L2和L3)的电流无法突变，导致电流I L无法突变，I L的值大于Io的值；因此，I L会对输出电容Co充电，导致Vo快速上升。
如果在芯片快速加载和卸载的过程中，芯片的供电电源无法满足芯片在该工况下的动态性能需求，就会造成输出电压Vo的上升和跌落超出芯片的规格要求，导致芯片的性能下降甚至损坏。因此，亟需一种在芯片快速加载和卸载的过程中为芯片提供稳定供电的控制方案。
现有技术中，通常通过调节上管的导通时间来抑制输出电压的快速上升和跌落：芯片快速加载时，输出电压Vo跌落幅值超过阈值V LT后触发非线性调节，控制器增大BUCK电路上管(Q1A、Q2A、Q3A)的导通时间，使得单位时间内有更多的能量传递到输出侧，抑制电压跌落；当芯片快速卸载时，输出电压Vo快速上升幅值超过阈值V HT后触发非线性调节，控制器关闭BUCK电路上管(Q1A、Q2A、Q3A)，断开输入侧到输出侧的能量传递，抑制输出电压的上升。
采用上述方案时，在输出电压Vo跌落进入非线性调节状态时，增大上管导通时间，单位时间内有更多的能量传递到输出侧，可以有效减小电压跌落。但是，在输出电压Vo 快速上升进入非线性调节状态时，电感能量只能通过输出电容Co释放。电感能量无法快速释放，会造成输出电压Vo调节时间长，对于输出电压Vo快速上升的抑制效果不理想。
因此，现有技术提供的电源控制方案，在芯片快速卸载时对输出电压Vo快速上升的抑制效果不理想，影响芯片性能，甚至会造成芯片损坏。
发明内容
本申请实施例提供了一种电压调节模块及集成芯片，用以为处理器芯片供电，并在处理器芯片快速卸载时抑制电压调节模块的输出电压快速上升，为芯片提供稳定供电。
第一方面，本申请实施例提供一种电压调节模块，该电压调节模块包括第一变换电路和第一卸放电路；其中，第一变换电路包括：第一开关管、第一原边线圈和第二开关管。第一开关管与输入源的正极耦合；第一原边线圈的一端与第一开关管耦合，第一原边线圈的另一端与处理器芯片耦合；第二开关管的一端与第一开关管和第一原边线圈的连接点耦合，另一端与输入源的负极耦合；第一开关管与第二开关管交替导通。第一卸放电路的两端分别与输入源的正极和负极耦合，第一卸放电路包括串联的第一副边线圈、第一晶体管和第二晶体管；第一副边线圈与第一原边线圈通过电磁耦合形成第一变压器。
其中，处理器芯片可以为中央处理器CPU或图形处理器GPU。第一开关管和第二开关管可以为金属-氧化物半导体场效应晶体管MOSFET、氮化镓晶体管或三极管等。第一变换电路用于实现降压功能，例如可以是BUCK变换电路或者BUCK-BOOST变换电路。
采用第一方面提供的电压调节模块，当输出电压过高时，可以控制第一卸放电路中的第一晶体管和第二晶体管由关断状态切换为导通状态，使得第一副边线圈中产生的第一感应电流可以通过第一卸放电路卸放，从而减小电压调节模块输出侧的能量，抑制电压调节模块的输出电压的快速上升。与现有技术方案相比，第一原边线圈的能量不仅能够通过输出电容释放，还可以通过第一卸放电路卸放，使得第一原边线圈的能量快速释放，缩短输出电压的调节时间，提升对输出电压快速上升的抑制效果。
在一种可能的设计中，第一原边线圈与第一副边线圈的绕向相反。
采用上述方案，由于第一晶体管和第二晶体管仅在电压调节模块的输出电压过高时导通，此时第一原边线圈与输入源正极耦合一端的电压小于第一原边线圈与处理器芯片耦合一端的电压。因此，相应地，只有在第一副边线圈与输入源正极耦合一端的电压大于第一副边线圈与输入源负极耦合一端的电压的情况下，第一卸放电路才可将第一感应电流卸放，防止第一感应电流倒灌至输入源。因此，第一原边线圈与第一副边线圈的绕向需相反，从而使得第一原边线圈与第一副边线圈的极性相反，防止出现第一感应电流倒灌至输入源的现象。
在一种可能的设计中，当电压调节模块的输出电压大于第一阈值时，第一晶体管和第二晶体管由关断状态切换为导通状态，第一副边线圈中的第一感应电流通过第一卸放电路卸放。
采用上述方案，第一晶体管和第二晶体管导通后，第一感应电流存在流通通路，第一感应电流可以通过第一卸放电路卸放，从而减小电压调节模块输出侧的能量，抑制电压调节模块的输出电压快速上升。
在一种可能的设计中，当第一晶体管和第二晶体管的导通时长达到预设时长或者流经第一副边线圈的电流小于第二阈值时，第一晶体管和第二晶体管由导通状态切换为关断状 态。
若第一晶体管和第二晶体管一直处于导通状态，第一副边线圈感应电流会持续减小至零。当第一副边线圈出现电流过零现象时，输入源的输入电压通过第一副边线圈向第一原边线圈反向充电，反而会导致电压调节模块的输出电压增大。因此，采用上述方案，可以合理控制第一晶体管和第二晶体管的关断时间，从而避免出现上述输入源通过第一副边线圈向第一原边线圈反向充电的现象。
在一种可能的设计中，第一方面提供的电压调节模块还可以包括电流采样电路和比较器。电流采样电路用于在第一晶体管和第二晶体管由关断状态切换为导通状态之后检测第一副边线圈的电流；比较器与电流采样电路耦合，用于将第一副边线圈的电流值与第三阈值进行比较，当第一副边线圈的电流值小于第三阈值时，比较器的输出信号由高电平翻转为低电平；比较器的输出端与第一晶体管的栅极/基极耦合。
其中，比较器的输出端还可以与第二晶体管的栅极/基极耦合。
比较器的输出信号由高电平翻转为低电平的时刻，第一晶体管和第二晶体管关断，因此，采用上述方案，可以通过电流采样电路和比较器控制第一晶体管和第二晶体管的关断。
在一种可能的设计中，第一方面提供的电压调节模块还可以包括计时器和比较器。计时器用于在第一晶体管和第二晶体管由关断状态切换为导通状态时开始计时；比较器与计时器耦合，用于将计时器的计时时长与预设时长进行比较，当计时时长达到预设时长时，比较器的输出信号由高电平翻转为低电平；比较器的输出端与第一晶体管的栅极/基极耦合。
其中，比较器的输出端还可以与第二晶体管的栅极/基极耦合。
比较器的输出信号由高电平翻转为低电平的时刻，第一晶体管和第二晶体管关断，因此，采用上述方案，可以通过电流采样电路和计时器控制第一晶体管和第二晶体管的关断。
在一种可能的设计中，当电压调节模块的输出电压小于第三阈值时，第一开关管在单位时长内的导通时间由第一时长变为第二时长，第二时长大于第一时长。
采样上述方案，可以在处理器芯片快速加载、电压调节模块的输出电压跌落时，抑制电压跌落。
下面通过几个具体示例说明第一晶体管和第二晶体管的配置。
示例一
在示例一中，第一晶体管为第三开关管，第二晶体管为第四开关管。也就是说，第一晶体管和第二晶体管均为开关管。
在一种可能的设计中，若第三开关管和第四开关管均为NMOS，第三开关管和第四开关管的一种连接方式可以是：第三开关管的源极/集电极与第一副边线圈耦合，第三开关管的漏极/发射极与第四开关管的漏极/发射极耦合，第四开关管的源极/集电极与输入源的负极耦合。
在其他示例中，第三开关管和第四开关管也可以均为NMOS。或者，第三开关管为NMOS、第四开关管为PMOS，或者，第三开关管为PMOS、第四开关管为NMOS。
当电压调节模块正常工作或输出电压跌落时，第三开关管和第四开关管关断，这时不希望第一卸放电路中有电流流过，否则输入电压会通过耦合电感(即第一原边线圈和第一副边线圈)叠加在输出侧，造成输出电压波动。将第三开关管的漏极与第四开关管的漏极连接，第三开关管和第四开关管中的二极管无法形成导通回路，可以避免上述现象。
示例二
在示例二中，第一晶体管为二极管，第二晶体管为第三开关管。也就是说，在第一晶体管和第二晶体管中，一个晶体管为开关管，另一个晶体管为二极管。其中，若第三开关管为MOSFET，则第三开关管可以为NMOS，也可以为PMOS。
在一种可能的设计中，二极管的阴极与第一副边线圈耦合，二极管的阳极与第三开关管的漏极/集电极耦合，第三开关管的源极/发射极与输入源的负极耦合。
在另一种可能的设计中，第三开关管的源极/集电极与第一副边线圈耦合，第三开关管的漏极/发射极与二极管的阴极耦合，二极管的阳极与输入源的负极耦合。
采样上述方案，二极管与第三开关管采用这种连接方式，由于二极管的反向截止特性，使得第三开关管关断时，第一卸放电路无法形成导通回路，进而阻止输入侧通过耦合线圈对输出侧反向充电。
在又一种可能的设计中，二极管的阴极与输入源的正极耦合，二极管的阳极与第一副边线圈耦合，第三开关管的漏极/集电极与第一副边线圈耦合，第三开关管的源极/发射极与输入源的负极耦合。
采样上述方案，二极管与第三开关管采用这种连接方式，由于二极管的反向截止特性，使得第三开关管关断时，第一卸放电路无法形成导通回路，进而阻止输入侧通过耦合线圈对输出侧反向充电。
此外，第一方面提供的电压调节模块还可以采用多个变换电路并联的方式，从而实现输入电流的分流，避免较大电流流过变换电路中的开关管，损坏开关管。
在一种可能的设计中，第一方面提供的电压调节模块还可以包括第二变换电路和第二卸放电路。其中，第二变换电路包括：第五开关管，第五开关管与输入源的正极耦合；第二原边线圈，第二原边线圈的一端与第五开关管耦合，第二原边线圈的另一端与处理器芯片耦合；第六开关管，第六开关管的一端与第五开关管和第二原边线圈的连接点耦合，另一端与输入源的负极耦合；第五开关管与第六开关管交替导通。
电压调节模块采用多个变换电路并联时，多个并列的变换电路的结构类似，但是第二卸放电路的实现方式可以有多种，下面列举其中几种实现方式。
实现方式一
在一种可能的设计中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第三晶体管和第四晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二变压器。
采用上述方案，第二变换电路与第一变换电路单独并联，第二卸放电路与第一卸放电路单独并联。电压调节模块的结构简单，且各相之间不存在耦合，便于控制。更为一般地，电压调节模块中可以包括多个并联的变换电路，以及多个并联的卸放电路。
实现方式二
在另一种可能的设计中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第一晶体管和第二晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二变压器。
采用上述方案，第二卸放电路和第一卸放电路共用第一晶体管和第二晶体管，因而电压调节模块中配置的晶体管的数量少，便于控制。更为一般地，电压调节模块中可以包括多个并联的变换电路，以及多个并联的卸放电路，每个卸放电路配置单独的副边线圈，多个卸放电路共用第一晶体管和第二晶体管。
实现方式三
在又一种可能的设计中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第一晶体管和第三晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二变压器。
采用上述方案，每个卸放电路中单独配置了一个二极管，由于二极管的反向截止特性，副边线圈之间无法产生环流，可以降低电压调节模块的损耗。此外，由于每个卸放电路中包括二极管，二极管的反向截止特性还可以阻止输入侧通过耦合线圈对输出侧反向充电。
此外，第一变换电路还可以包括输入电容和输出电容，输入电容的两端分别与输入源的正极和负极耦合，输出电容的两端分别与处理器芯片和输入源的负极耦合。
第二方面，本申请实施例还提供一种集成芯片，该集成芯片包括处理器芯片以及上述第一方面及其任一可能的设计中提供的电压调节模块，电压调节模块用于为处理器芯片供电。
另外，应理解，第二方面及其任一种可能设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为现有技术提供的一种电压调节模块的结构示意图；
图2为本申请实施例提供的第一种电压调节模块的结构示意图；
图3为本申请实施例提供的第二种电压调节模块的结构示意图；
图4为本申请实施例提供的第三种电压调节模块的结构示意图；
图5为本申请实施例提供的第四种电压调节模块的结构示意图；
图6为本申请实施例提供的第五种电压调节模块的结构示意图；
图7为本申请实施例提供的第六种电压调节模块的结构示意图；
图8为本申请实施例提供的第七种电压调节模块的结构示意图；
图9为本申请实施例提供的第八种电压调节模块的结构示意图；
图10为本申请实施例提供的第九种电压调节模块的结构示意图；
图11为本申请实施例提供的第十种电压调节模块的结构示意图；
图12为本申请实施例提供的第十一种电压调节模块的结构示意图；
图13为本申请实施例提供的第十二种电压调节模块的结构示意图；
图14为本申请实施例提供的一种开关管状态及输出电流大小的时序图；
图15为本申请实施例提供的一种开关管状态及输出电流、输出电压大小的时序图；
图16为本申请实施例提供的第十三种电压调节模块的结构示意图；
图17为本申请实施例提供的第十四种电压调节模块的结构示意图；
图18为本申请实施例提供的第十五种电压调节模块的结构示意图；
图19为本申请实施例提供的一种集成芯片的结构示意图。
具体实施方式
下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请实施例中，多个是指两个或两个以上。另外，在本申请的描述 中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。本申请实施例中所提到的“耦合”，是指电学连接，具体可以包括直接连接或者间接连接两种方式。
本申请实施例提供一种电压调节模块，用于为处理器芯片供电。处理器芯片可以是中央处理器(central processing unit，CPU)、图形处理器(graphics processing unit，GPU)等等。当然，处理器芯片也可以是其他用于处理业务的芯片，本申请实施例对处理器芯片的具体类型不做限定。
具体地，如图2所示，该电压调节模块200包括第一变换电路201和第一卸放电路202。
第一变换电路201包括第一开关管、第一原边线圈和第二开关管。第一开关管与输入源的正极耦合；第一原边线圈的一端与第一开关管耦合，第一原边线圈的另一端与处理器芯片耦合；第二开关管的一端与第一开关管和第一原边线圈的连接点耦合，另一端与输入源的负极耦合；第一开关管与第二开关管交替导通。
第一卸放电路202的两端分别与输入源的正极和负极耦合，第一卸放电路202包括串联的第一副边线圈、第一晶体管和第二晶体管；第一副边线圈与第一原边线圈通过电磁耦合形成第一耦合电感。
本申请实施例中，开关管，也可以称为功率管或功率开关管，一般常用为金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)、三极管或者氮化镓(gallium nitride，GaN)晶体管等。晶体管可以为二极管，也可以为MOSFET。
在电压调节模块200中，第一变换电路201用于实现降压功能，例如可以是BUCK变换电路或者BUCK-BOOST变换电路，图2中示出的第一变换电路201的实现方式仅为示例，本申请实施例中对第一变换电路201的具体形态不做限定，只要第一变换电路201可以实现降压功能即可。
具体地，第一变换电路201的工作原理是：当第一开关管导通、第二开关管关断时，输入源通过第一开关管和第一原边线圈向输出侧传递能量；当第二开关管导通、第一开关管关断时，第一原边线圈通过第二开关管续流，向输出侧传递能量。通过控制第一开关管和第二开关管的导通时长，可以实现输出电压的调节，从而为处理器芯片提供可调节的电压。
需要说明的是，本申请实施例中对第一卸放电路202中第一副边线圈、第一晶体管和第二晶体管的串联顺序不做具体限定，在图2的示例中，从输入源的正极到负极，以第一副边线圈→第一晶体管→第二晶体管的串联顺序为例进行示意，实际应用中，也可以采用第一晶体管→第一副边线圈→第二晶体管的串联顺序，或者采用第一副边线圈→第二晶体管→第一晶体管的串联顺序。
此外，在电压调节模块200中，第一变换电路还可以包括输入电容和输出电容，如图3所示，输入电容的两端分别与输入源的正极和负极耦合，输出电容的两端分别与处理器芯片和输入源的负极耦合。
在实际应用中，第一卸放电路202中的第一晶体管和第二晶体管默认处于关断状态，那么，在电压调节模块200上电以后，电压调节模块200正常工作，第一卸放电路202不导通，仅有第一变换电路201工作，电压调节模块200与现有技术中的VRM的工作原理相同。
当处理器芯片快速加载、电压调节模块200的输出电压跌落时，可以通过如下方式抑 制电压跌落：增加第一开关管在单位时长的导通时间，使得单位时长内有更多的能量传递到输出侧，从而抑制输出电压的跌落。也就是说，当电压调节模块200的输出电压小于第三阈值时，第一开关管在单位时长内的导通时间可以由第一时长变为第二时长，第二时长大于第一时长。其中，第三阈值、第一时长和第二时长的具体数值可以配置。电压调节模块200抑制电压跌落的方式与图1所示的现有技术中抑制电压跌落的方式一致。
当处理器芯片快速卸载、电压调节模块200的输出电压过高时，可以通过如下方式抑制电压上升：当电压调节模块的输出电压大于第一阈值时，关断第一开关管和第二开关管，第一原边线圈的能量通过输出电容释放；同时，第一晶体管和第二晶体管由关断状态切换为导通状态，第一副边线圈中的第一感应电流通过第一卸放电路202快速卸放，其中，第一感应电流的方向可参见图2中的标注。其中，第一阈值的具体数值可以配置。
第一原边线圈中有电流流过，通过第一耦合电感的电磁感应，第一副边线圈中会产生第一感应电动势。第一晶体管和第二晶体管导通后，第一副边线圈形成闭环回路，产生第一感应电流。第一感应电流可以通过第一卸放电路202卸放，第一耦合电感上的部分能量通过第一卸放电路202回馈至输入侧，使得第一原边线圈上的电流快速减小，从而减小电压调节模块200输出侧的能量，抑制电压调节模块200的输出电压的快速上升。
在电压调节模块200中，第一原边线圈与第一副边线圈的绕向相反。也就是说，图2中，第一原边线圈的a1端与第一副边线圈的a4端互为同名端。
这是因为，第一晶体管和第二晶体管仅在电压调节模块200的输出电压过高时导通，此时第一原边线圈与输入源正极连接一端(即图2中的a1端)的电压小于第一原边线圈与处理器芯片连接一端(即图2中的a2端)的电压。相应地，只有在第一副边线圈与输入源正极连接一端(即图2中的a3端)的电压大于第一副边线圈与输入源负极连接一端(即图2中的a4端)的电压的情况下，第一卸放电路202才可将第一感应电流回馈至输入侧，实现第一原边线圈上电流快速减小的目的。
采用电压调节模块200，当输出电压过高、超过第一阈值时，可以控制第一卸放电路202中的第一晶体管和第二晶体管由关断状态切换为导通状态，使得第一副边线圈中产生的第一感应电流可以通过第一卸放电路202卸放，从而减小电压调节模块200输出侧的能量，抑制电压调节模块200的输出电压快速上升。与现有技术方案相比，第一原边线圈的能量不仅能够通过输出电容释放，还可以通过第一卸放电路202卸放，使得第一原边线圈的能量快速释放，缩短输出电压的调节时间，提升对输出电压快速上升的抑制效果。
在第一晶体管和第二晶体管导通一段时间以后，电压调节模块200的输出电压回落，此时可以将第一晶体管和第二晶体管由导通状态切换为关断状态。若第一晶体管和第二晶体管一直处于导通状态，第一副边线圈感应电流会持续减小至零。当第一副边线圈出现电流过零现象(即a3端的电压减小至与a4端的电压相等)时，输入源的输入电压通过第一副边线圈向第一原边线圈反向充电，反而会导致电压调节模块200的输出电压增大。因此，在电压调节模块200中，需要合理控制第一晶体管和第二晶体管的关断时间。
本申请实施例中，可以在第一晶体管和第二晶体管的导通时长达到预设时长或者流经第一副边线圈的电流小于第二阈值时，将第一晶体管和第二晶体管由导通状态切换为关断状态。其中，预设时长和第二阈值可以根据不同的应用场景进行配置。
也就是说，可以从第一卸放电路202的导通时长和电流大小两个维度来控制第一晶体管和第二晶体管的关断时机。
实际应用中，为了控制第一晶体管和第二晶体管的关断，电压调节模块200中还可以包括电流采样电路和比较器，如图4所示。电流采样电路用于在第一晶体管和第二晶体管由关断状态切换为导通状态之后检测第一副边线圈的电流；比较器与电流采样电路耦合，用于将第一副边线圈的电流值与第二阈值进行比较，当第一副边线圈的电流值小于第二阈值时，比较器的输出信号由高电平翻转为低电平；比较器的输出端与第一晶体管和第二晶体管的栅极耦合。
如前所述，本申请实施例中，晶体管可以为二极管也可以为开关管。图4所示的实现方式可以适配第一晶体管和第二晶体管均为开关管的情况。比较器的输出端分别与第一晶体管和第二晶体管的栅极耦合，用于控制第一和二晶体管的导通和关断。
第二晶体管也可以为二极管，由于二极管的导通和关断是由自身极性和施加电压的极性决定的，无法通过一个控制端(例如栅极)去控制。因此，比较器仅用于控制第一晶体管的导通和关断。
实际应用中，为了控制第一晶体管和第二晶体管的关断，电压调节模块200中还可以包括计时器和比较器，如图5所示。计时器用于在第一晶体管和第二晶体管由关断状态切换为导通状态时开始计时；比较器与计时器耦合，用于将计时器的计时时长与预设时长进行比较，当计时时长达到预设时长时，比较器的输出信号由高电平翻转为低电平；比较器的输出端与第一晶体管和第二晶体管的栅极耦合。
同样地，图5所示的实现方式可以适配第一晶体管和第二晶体管均为开关管的情况。比较器的输出端分别与第一晶体管和第二晶体管的栅极耦合，用于控制第一和二晶体管的导通和关断。
第二晶体管也可以为二极管，由于二极管的导通和关断是由自身极性和施加电压的极性决定的，无法通过一个控制端(例如栅极)去控制。因此，比较器仅用于控制第一晶体管的导通和关断。
如前所述，本申请实施例中，晶体管可以为二极管，也可以为开关管。下面以几个具体示例说明第一晶体管和第二晶体管的不同配置。
示例一
在示例一中，第一晶体管可以为第三开关管，第二晶体管可以为第四开关管。也就是说，第一晶体管和第二晶体管均为开关管。
电压调节模块的一种可能的实现方式可以如图6所示。在图6的示例中，Q1表示第一开关管，Q2表示第二开关管，Q3表示第三开关管，Q4表示第四开关管，Vin表示输入源，Cin表示输入电容，Co表示输出电容，Lp表示第一原边线圈，Ls表示第一副边线圈。其中，开关管均以NMOS为例进行示意。实际应用中，开关管也可以均为PMOS，或者NMOS和PMOS组合。
在图6所示的电压调节模块中，Q3的漏极与Q4的漏极耦合，这样的话，Q3和Q4中的两个反并联二极管的极性相反，即Q3中二极管的阴极与Q4中二极管的阴极耦合。这样的连接方式是出于以下考虑：当电压调节模块200正常工作或输出电压跌落时，Q3和Q4关断，这时不希望第一卸放电路202中有电流流过，否则输入电压会通过耦合电感(即Lp和Ls)叠加在输出侧，造成输出电压波动。将Q3的漏极与Q4的漏极连接，两个MOSFET中的二极管无法形成导通回路，可以避免上述现象。
当然，在示例一中，第一晶体管和第二晶体管均为开关管，第一晶体管和第二晶体管 也可以采用其他耦合方式。比如，Q3中除栅极之外的两个电极分别与Vin正极和Ls耦合，Q4中除栅极之外的两个电极分别与Ls和Vin负极耦合。同样地，Q3可以为NMOS或PMOS，Q4也可以为NMOS或PMOS。
示例二
在示例二中，第一晶体管为二极管，第二晶体管为第三开关管。也就是说，在第一晶体管和第二晶体管中，一个晶体管为开关管，另一个晶体管为二极管。
在一种实现方式中，二极管的阴极与第一副边线圈耦合，二极管的阳极与第三开关管的漏极耦合，第三开关管的源极与输入源的负极耦合，如图7所示。在图7的示例中，Q1表示第一开关管，Q2表示第二开关管，Q3表示第三开关管，D1表示二极管，Vin表示输入源，Cin表示输入电容，Co表示输出电容，Lp表示第一原边线圈，Ls表示第一副边线圈。其中，开关管均以MOSFET为例进行示意，Q3为PMOS。实际应用中，Q3也可以为NMOS。
在图7所示的电压调节模块中，D1的阴极与Ls耦合，D1的阳极与Q3的漏极耦合，Q3的源极与Vin的负极耦合。D1与Q3采用这种连接方式，由于D1的反向截止特性，使得Q3关断时，第一卸放电路202无法形成导通回路，避免出现前述输入电压叠加在输出侧造成输出电压波动。
在另一种实现方式中，第三开关管的源极与第一副边线圈耦合，第三开关管的漏极与二极管的阴极耦合，二极管的阳极与输入源的负极耦合，如图8所示。在图8的示例中，Q1表示第一开关管，Q2表示第二开关管，Q3表示第三开关管，D1表示二极管，Vin表示输入源，Cin表示输入电容，Co表示输出电容，Lp表示第一原边线圈，Ls表示第一副边线圈。其中，开关管均以MOSFET为例进行示意，Q3为NMOS。实际应用中，Q3也可以为PMOS。
同样地，在图8所示的电压调节模块中，D1与Q3采用这种连接方式，由于D1的反向截止特性，使得Q3关断时，第一卸放电路202无法形成导通回路，避免出现前述输入电压叠加在输出侧的现象，避免输出电压波动。
在又一种实现方式中，二极管的阴极与输入源的正极耦合，二极管的阳极与第一副边线圈耦合，第三开关管的漏极与第一副边线圈耦合，第三开关管的源极与输入源的负极耦合，如图9所示。在图9的示例中，Q1表示第一开关管，Q2表示第二开关管，Q3表示第三开关管，D1表示二极管，Vin表示输入源，Cin表示输入电容，Co表示输出电容，Lp表示第一原边线圈，Ls表示第一副边线圈。其中，开关管均以MOSFET为例进行示意，Q3为PMOS。实际应用中，Q3也可以为NMOS。
在图9所示的电压调节模块中，D1的阴极与Vin的正极耦合，D1的阳极与Ls耦合，Q3的漏极与Ls耦合，Q3的源极与Vin的负极耦合。D1与Q3采用这种连接方式，由于D1的反向截止特性，使得Q3关断时，第一卸放电路202无法形成导通回路，避免出现前述输入电压叠加在输出侧的现象，避免输出电压波动。
采用示例二所述的方式，由于二极管的反向截止特性可以阻止输入侧通过耦合线圈对输出侧反向充电，因而与示例一所述的方式相比，对开关管Q3的关断时间的控制更为灵活。
从上面两个示例可以看出，本申请实施例中，设置第一晶体管和第二晶体管的目的有两个：1、在电压调节模块200正常工作或卸放时，通过控制第一晶体管和第二晶体管关 断，使得第一卸放电路202中无电流流过，第一卸放电路202不起作用；2、在电压调节模块200的输出电压过高时，通过控制第一晶体管和第二晶体管导通，使得第一卸放电路202中有电流流过，从而卸放输出侧的能量，抑制输出电压快速上升。只要第一晶体管和第二晶体管的设置起到上述作用，均应视为属于本申请实施例的保护范围。
此外，从现有技术中可以了解到，电压调节模块中可以采用多个变换电路并联的方式，从而实现对负载电流的分流，避免单路变换电路流过较大电流，损坏开关管。在本申请实施例提供的电压调节模块200中，也可以包括多个并联的变换电路，以适配大电流负载的应用场景。
也就是说，电压调节模块200还可以包括第二变换电路和第二卸放电路；第二变换电路包括第五开关管、第二原边线圈和第六开关管。第五开关管与输入源的正极耦合；第二原边线圈的一端与第五开关管耦合，第二原边线圈的另一端与处理器芯片耦合；第六开关管的一端与第五开关管和第二原边线圈的连接点耦合，另一端与输入源的负极耦合；第五开关管与第六开关管交替导通。
电压调节模块200采用多个变换电路并联时，多个并列的变换电路的结构类似，但是第二卸放电路的实现方式可以有多种，下面列举其中几种实现方式。
实现方式一
在实现方式一中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第三晶体管和第四晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二耦合电感。
在实现方式一中，第二变换电路与第一变换电路201单独并联，第二卸放电路与第一卸放电路202单独并联。更为一般地，电压调节模块200中可以包括多个并联的变换电路，且每个变换电路都配置一个卸放电路，各个卸放电路之间无耦合。
示例性地，包含多个并联的变换电路以及多个并联的卸放电路的电压调节模块200的一种可能的实现方式可以如图10所示。采用这种实现方式，电压调节模块200的结构简单，且各相之间不存在耦合，便于控制。
在图10的示例中，卸放电路采用与图6所示的第一卸放电路相同的拓扑。当然，卸放电路也可以采用前述其他拓扑，此处不再赘述。
实现方式二
在实现方式二中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第一晶体管和第二晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二耦合电感。
与实现方式一不同的是，在实现方式二中，第二卸放电路和第一卸放电路202共用第一晶体管和第二晶体管。更为一般地，电压调节模块200中可以包括多个并联的变换电路，以及多个并联的卸放电路，每个卸放电路配置单独的副边线圈，多个卸放电路共用第一晶体管和第二晶体管，如图11所示。在图11的示例中，Q3和Q4分别表示第一晶体管和第二晶体管。
采用图11所示的方案，与图10所示的方案相比，配置的晶体管的数量少，便于控制。但是，在电压调节模块200正常工作时，若每个变换电路的输出电压不完全一致，副边线圈之间可能形成回路，产生环流，使得电压调节模块200的损耗增大。比如，当第一副边线圈Ls_1a的电势高于Ls_1b、第二副边线圈Ls_na的电势低于Ls_nb，会形成Ls_1a→Ls_na →Ls_nb→Ls_1b→Ls_1a这一路径的环流，增加电压调节模块200的损耗。
实现方式三
在实现方式三中，第二卸放电路的两端分别与输入源的正极和负极耦合，第二卸放电路包括串联的第二副边线圈、第一晶体管和第三晶体管；第二副边线圈与第二原边线圈通过电磁耦合形成第二耦合电感。
与实现方式一和实现方式二不同的是，在实现方式三中，第二卸放电路与第一卸放电路共用第一晶体管，且单独配置一个第三晶体管。其中，第一卸放电路中的第二晶体管和第二卸放电路中的第三晶体管可以为二极管，多个卸放电路共用的第一晶体管可以为开关管。更为一般地，电压调节模块200中可以包括多个并联的变换电路，以及多个并联的卸放电路，多个卸放电路共用第一晶体管，且每个卸放电路单独配置一个副边线圈和一个二极管，如图12所示。在图12的示例中，Q3表示第一晶体管。
采用图12所示的方案，与图11所示的方案相比，每个卸放电路中单独配置了一个二极管，由于二极管的反向截止特性，副边线圈之间无法产生环流，可以降低电压调节模块200的损耗。此外，由于每个卸放电路中包括二极管，二极管的反向截止特性还可以阻止输入侧通过耦合线圈对输出侧反向充电。
需要说明的是，上述三个实现方式仅为具体示例。在多相并联的电压调节模块中，卸放电路的具体结构也可以参照前面的描述，并不限定为上述三种实现方式中的举例。
综上，采用本申请实施例提供的电压调节模块200，当处理器芯片快速加载、电压调节模块200的输出电压跌落时，可以增加第一开关管在单位时长的导通时间，使得单位时长内有更多的能量传递到输出侧，从而抑制输出电压的跌落。当处理器芯片快速卸载、电压调节模块200的输出电压超过第一阈值时，关断第一开关管和第二开关管，第一晶体管和第二晶体管由关断状态切换为导通状态。那么，第一副边线圈中的第一感应电流通过第一卸放电路202卸放，第一耦合电感上的部分能量通过第一卸放电路202回馈至输入侧，从而减小电压调节模块200输出侧的能量，抑制电压调节模块200的输出电压快速上升。与现有技术方案相比，第一原边线圈的能量不仅能够通过输出电容释放，还可以通过第一卸放电路202卸放，使得第一原边线圈的能量快速释放，缩短输出电压的调节时间，提升对输出电压上升的抑制效果。
下面以图6所示的电压调节模块为例，对本申请实施例提供的电压调节模块的具体工作原理进行详细介绍。
在该电压调节模块中，BUCK电路的输出电感采用耦合电感，耦合电感的原边Lp为BUCK电路的输出电感，副边Ls与输入Vin连接，用于提供卸放路径。负载卸载、输出电压过高时，开通功率管(也可以称为辅助管)Q3和Q4，将电感存储的能量通过副边回馈至输入侧，达到抑制电压快速上升、提升效率的目的。
1、正常工作时，辅助管Q3和Q4关闭不工作，耦合电感副边无通流回路，如图13所示。在正常工作时，该电路与普通BUCK电路无异，有两个工作状态：上管Q1开通、下管Q2关断时，输入侧Vin通过上管Q1和电感Lp向输出侧传递能量，ILp逐渐增大；下管Q2开通、上管Q1关断时，电感Lp通过下管Q2进行续流，ILp逐渐减小。Q1、Q2的状态以及ILp的变化可以如图14所示。
2、当处理器芯片卸载造成输出电压Vo幅值超过阈值Vth1时(进入非线性)，(在非 线性状态中)关闭上管Q1和下管Q2，同时开通辅助管Q3和Q4，耦合电感的能量通过副边Ls回馈至输入电容Cin。此时耦合电感原边Lp传输到输出电容的能量少，输出电压Vo也随之变小。输出电压升高至到峰值后会逐渐降低直至恢复至正常电压，当输出电压Vo达到阈值Vth2时，关闭辅助管Q3和Q4，上管Q1和下管Q2恢复正常工作。抑制输出电压快速上升的过程中，各开关管的状态以及输出电流、输出电压的时序图可以如图15所示。
3、当芯片加载造成输出电压Vo落幅值超过阈值时(进入非线性)，(在非线性状态中)增大上管Q1的导通时间，单位时间内有更多的能量传递到输出侧，从而抑制电压跌落。
在图6所示的电压调节模块中，正常工作时，不希望辅助管Q3和Q4导通，避免输入电压通过耦合电感叠加在输出侧，造成输出电压波动。因此，正常工作时，辅助管Q3和Q4一直处于关断状态。同理，处理器芯片加载造成输出电压Vo跌落时，辅助管Q3和Q4也不导通，避免输出振荡。只有在输出电压Vo过高时，才使辅助管Q3和Q4导通。
辅助管Q3和Q4导通能有效抑制输出电压Vo快速上升。但如果Q3和Q4导通时间过长，会存在未退出非线性时，耦合电感副边电流先过零现象。此时输入电压Vin通过副边Ls向原边反向充电，导致输出电压Vo增大(副边的回路路径：Vin->Ls->Q3->Q4->Vin，原边的回路路径：Lp->Co->Q2->Lp)，如图16所示。因此，需要合理控制辅助管Q3和Q4的导通和关断时刻。可以通过如下三种方法控制辅助管Q3和Q4。
方法1：电流检测法。如图17所示，耦合电感副边增加电流采样电路，在辅助管Q3和Q4导通时启动检测，关闭时不检测。当检测到副边电流低于设置阈值Is_th时(阈值可配)，比较器U1翻转为低电平，提前关闭辅助管Q3和Q4。
方法2：恒定导通时间法。如图18所示，控制电路增加计时功能，在辅助管Q3和Q4导通时启动计时，关闭时不计时。当计时到设置阈值(阈值可配)时，计时器U2输出低电平，从而关闭辅助管Q3和Q4。计时阈值可以根据不同应用场景设置不同的值。
方法3：二极管单向导通法。如图7、图8和图9的示例所示，将辅助管Q3和Q4换成MOS管Q3和二极管D1。由于二极管的单向导通特性，在辅助管Q3开通时间过长时，输入电压在耦合电感的副边无法构成充电回路，因此不会对原边进行反向充电。该方法不需要对辅助管Q3的关闭进行精准控制，只要保证在输出电压较高且进入非线性时开通Q3，恢复过程退出非线性时关闭Q3即可。
本申请实施例还提供一种集成芯片，如图19所示，该集成芯片1900包括处理器芯片1901以及前述电压调节模块200，电压调节模块200用于为处理器芯片1901供电。
需要说明的是，集成芯片1900中未详尽描述的实现方式及其技术效果可以参见电压调节模块200中的相关描述，此处不再赘述。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (23)

  1. 一种电压调节模块，其特征在于，包括第一变换电路和第一卸放电路；
    所述第一变换电路包括：
    第一开关管，所述第一开关管与输入源的正极耦合；
    第一原边线圈，所述第一原边线圈的一端与所述第一开关管耦合，所述第一原边线圈的另一端与处理器芯片耦合；
    第二开关管，所述第二开关管的一端与所述第一开关管和所述第一原边线圈的连接点耦合，另一端与所述输入源的负极耦合；所述第一开关管与所述第二开关管交替导通；
    所述第一卸放电路的两端分别与所述输入源的正极和负极耦合，所述第一卸放电路包括串联的第一副边线圈、第一晶体管和第二晶体管；所述第一副边线圈与所述第一原边线圈通过电磁耦合形成第一耦合电感。
  2. 如权利要求1所述的电压调节模块，其特征在于，所述第一原边线圈与所述第一副边线圈的绕向相反。
  3. 如权利要求1或2所述的电压调节模块，其特征在于，当所述电压调节模块的输出电压大于第一阈值时，所述第一晶体管和所述第二晶体管由关断状态切换为导通状态，所述第一副边线圈中的第一感应电流通过所述第一卸放电路卸放。
  4. 如权利要求3所述的电压调节模块，其特征在于，当所述第一晶体管和所述第二晶体管的导通时长达到预设时长或者流经所述第一副边线圈的电流小于第二阈值时，所述第一晶体管和所述第二晶体管由导通状态切换为关断状态。
  5. 如权利要求3或4所述的电压调节模块，其特征在于，还包括：
    电流采样电路，用于在所述第一晶体管和所述第二晶体管由关断状态切换为导通状态之后检测所述第一副边线圈的电流；
    比较器，与所述电流采样电路耦合，用于将所述第一副边线圈的电流值与第三阈值进行比较，当所述第一副边线圈的电流值小于所述第三阈值时，所述比较器的输出信号由高电平翻转为低电平；所述比较器的输出端与所述第一晶体管的栅极耦合。
  6. 如权利要求5所述的电压调节模块，其特征在于，所述比较器的输出端与所述第二晶体管的栅极耦合。
  7. 如权利要求3或4所述的电压调节模块，其特征在于，还包括：
    计时器，用于在所述第一晶体管和所述第二晶体管由关断状态切换为导通状态时开始计时；
    比较器，与所述计时器耦合，用于将所述计时器的计时时长与所述预设时长进行比较，当所述计时时长达到所述预设时长时，所述比较器的输出信号由高电平翻转为低电平；所述比较器的输出端与所述第一晶体管的栅极耦合。
  8. 如权利要求7所述的电压调节模块，其特征在于，所述比较器的输出端与所述第二晶体管的栅极耦合。
  9. 如权利要求1～8任一项所述的电压调节模块，其特征在于，当所述电压调节模块的输出电压小于第三阈值时，所述第一开关管在单位时长内的导通时间由第一时长变为第二时长，所述第二时长大于所述第一时长。
  10. 如权利要求1～9任一项所述的电压调节模块，其特征在于，所述第一晶体管为第三开关管，所述第二晶体管为第四开关管。
  11. 如权利要求10所述的电压调节模块，其特征在于，所述第三开关管的源极与所述第一副边线圈耦合，所述第三开关管的漏极与所述第四开关管的漏极耦合，所述第四开关管的源极与所述输入源的负极耦合。
  12. 如权利要求1～9任一项所述的电压调节模块，其特征在于，所述第一晶体管为二极管，所述第二晶体管为第三开关管。
  13. 如权利要求12所述的电压调节模块，其特征在于，所述二极管的阴极与所述第一副边线圈耦合，所述二极管的阳极与所述第三开关管的漏极耦合，所述第三开关管的源极与所述输入源的负极耦合。
  14. 如权利要求12所述的电压调节模块，其特征在于，所述第三开关管的源极与所述第一副边线圈耦合，所述第三开关管的漏极与所述二极管的阴极耦合，所述二极管的阳极与所述输入源的负极耦合。
  15. 如权利要求12所述的电压调节模块，其特征在于，所述二极管的阴极与所述输入源的正极耦合，所述二极管的阳极与所述第一副边线圈耦合，所述第三开关管的漏极与所述第一副边线圈耦合，所述第三开关管的源极与所述输入源的负极耦合。
  16. 如权利要求1～15任一项所述的电压调节模块，其特征在于，还包括：第二变换电路和第二卸放电路；
    所述第二变换电路包括：
    第五开关管，所述第五开关管与所述输入源的正极耦合；
    第二原边线圈，所述第二原边线圈的一端与所述第五开关管耦合，所述第二原边线圈的另一端与所述处理器芯片耦合；
    第六开关管，所述第六开关管的一端与所述第五开关管和所述第二原边线圈的连接点耦合，另一端与所述输入源的负极耦合；所述第五开关管与所述第六开关管交替导通。
  17. 如权利要求16所述的电压调节模块，其特征在于，所述第二卸放电路两端分别与 所述输入源的正极和负极耦合，所述第二卸放电路包括串联的第二副边线圈、第三晶体管和第四晶体管；所述第二副边线圈与所述第二原边线圈通过电磁耦合形成第二耦合电感。
  18. 如权利要求16所述的电压调节模块，其特征在于，所述第二卸放电路两端分别与所述输入源的正极和负极耦合，所述第二卸放电路包括串联的第二副边线圈、所述第一晶体管和所述第二晶体管；所述第二副边线圈与所述第二原边线圈通过电磁耦合形成第二耦合电感。
  19. 如权利要求16所述的电压调节模块，其特征在于，所述第二卸放电路两端分别与所述输入源的正极和负极耦合，所述第二卸放电路包括串联的第二副边线圈、所述第一晶体管和第三晶体管；所述第二副边线圈与所述第二原边线圈通过电磁耦合形成第二耦合电感。
  20. 如权利要求1～19任一项所述的电压调节模块，其特征在于，所述第一变换电路还包括输入电容和输出电容，所述输入电容的两端分别与所述输入源的正极和负极耦合，所述输出电容的两端分别与所述处理器芯片和所述输入源的负极耦合。
  21. 如权利要求1～20任一项所述的电压调节模块，其特征在于，所述处理器芯片为中央处理器CPU或图形处理器GPU。
  22. 如权利要求1～21任一项所述的电压调节模块，其特征在于，所述第一开关管和所述第二开关管为金属-氧化物半导体场效应晶体管MOSFET或三极管。
  23. 一种集成芯片，其特征在于，包括处理器芯片以及如权利要求1～22任一项所述的电压调节模块，所述电压调节模块用于为所述处理器芯片供电。
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