WO2022229972A1

WO2022229972A1 - Injection locked clock multiplier with embedded phase interpolator

Info

Publication number: WO2022229972A1
Application number: PCT/IN2022/050351
Authority: WO
Inventors: Saurabh Saxena; Gautam R; Jaya Deepthi Bandarupalli
Original assignee: Indian Institute of Technology Madras
Current assignee: Indian Institute of Technology Madras
Priority date: 2021-04-30
Filing date: 2022-04-12
Publication date: 2022-11-03
Anticipated expiration: 2023-10-30

Abstract

Injection locked clock multiplier with an embedded phase interpolator and 2X frequency range. A wide range (2X) injection locked clock multiplier (ILCM) with an embedded phase interpolator multiplies a low-frequency clock to generate a high-frequency output wherein the phase is shifted as desired during the clock generation itself. The ILCM retains the low output clock jitter across (340-550fs_rms) and a good PI resolution (1.5°-2°) across the phase interpolation range by eliminating the multiphase high-frequency clock distribution during phase interpolation.

Description

DESCRIPTION

INJECTION LOCKED CLOCK MULTIPLIER WITH EMBEDDED

PHASE INTERPOLATOR TECHNICAL FIELD

[0001] Embodiments are generally related to analog and digital communication systems and methods. Embodiments are further related to phase interpolators. Embodiments are also related to injection locked clock multipliers with embedded phase interpolators. Embodiments are particularly related to an injection locked clock multiplier with 2X frequency range and resolution (1.5°-2°) for embedded phase interpolator.

BACKGROUND OF THE INVENTION [0002] In general, phase interpolators are used to shift the output phase of a clock in a wide range of communication systems including, but not limited to wireline and wireless communication systems. Such phase interpolators require a multiphase clock, such as for example, a four phase (0º/90º/180º/270°) high frequency clock with low jitter and accurate phase-shifting capability. In such conventional systems, phase interpolation can add to the clock jitter and degrade the output clock. The multiphase high-frequency clock distribution requires to have precise matching which adds to the power consumption of the system. Furthermore, it can be beneficial to minimize the power consumption of the clock generator and phase interpolator combined, while eliminating the need for a separate high frequency clock distribution. [0003] The prior art solutions are unable to provide an effective solution to achieve low jitter and good PI resolution across the wide frequency range. Furthermore, the prior art systems require multiphase high-frequency clock distribution, clock skewing circuit, and fine current/voltage DAC, traditionally required for phase interpolation.

[0004] Based on the foregoing a need therefore exists for a low-jitter (340- 550fS_rms) clock multiplier, and a good PI resolution (1.5°-2°) across the frequency range without the need of multiphase high-frequency clock distribution, clock skewing circuit, and fine current/voltage DAC for phase interpolation. Also, a need exists for a clock multiplier with wide frequency range (2X frequency) and resolution (1.5°-2°) for embedded phase interpolator, as discussed in greater detail herein.

SUMMARY OF THE INVENTION

[0005] The following summary is provided to facilitate a clear understanding of the new features in the disclosed embodiment, and it is not intended to be a full, detailed description. A detailed description of all the aspects of the disclosed invention can be understood by reviewing the full specification, the drawing and the claims and the abstract, as a whole.

[0006] One objective of the present invention is to provide an injection locked clock multiplier with an embedded phase interpolator to achieve a low jitter (340- 550fS_rmS) and a good PI resolution (1.5°-2°) across the frequency range without the need of multiphase high-frequency clock distribution, clock skewing circuit, and fine current/voltage DAC for phase interpolation.

[0007] Further objective of the present invention is to provide an injection locked clock multiplier with 2X frequency range and 1.5°-2° phase resolution for the embedded phase interpolator across the 2X frequency range.

[0008] The aforementioned aspects along with the objectives and the advantages can be achieved as described herein. An injection locked clock multiplier with 2X frequency range and 1.5°-2° phase resolution for the embedded phase interpolator, is disclosed herein. A wide range (2X) injection locked clock multiplier (ILCM) with an embedded phase interpolator (PI) multiplies a low- frequency clock to generate a high-frequency output wherein the phase is shifted as desired during the clock generation itself. The ILCM retains the low output clock jitter across 2X frequency range (340-550fs_rms) and a good PI resolution (1.5°-2°) across the phase interpolation range while eliminating the multiphase high-frequency clock distribution during phase interpolation.

[0009] The ILCM-cum-PI disclosed herein realizes an intermediate output clock phase by digitally controlling delays for signals already present in a multiphase ring oscillator. The clock signals are manipulated in time -domain rather than voltage or current domain during phase interpolation. The proposed ILCM-cum-PI's output phase does not depend on the shape of the analog multiphase clock signals such as, sinusoidal, triangular, square wave, etc., otherwise used during summing with a different voltage or current weights. Furthermore, the proposed ILCM-cum-PI does not need multiphase high- frequency clock distribution for phase interpolation, thereby saving power in high-frequency clock distribution and matching between multiple clock phases. The proposed ILCM-cum-PFs output phase is not restricted by the number of delay cells used to realize the ring oscillator wherein the ILCM-cum-PI has a linear change in the output phase with respect to the input digital control as delays or phases are directly manipulated. Unlike conventional phase interpolators, the random jitter is independent of the input code or number of stages.

[0010] In one embodiment of the proposed invention, the embedded phase interpolator interpolates clock phases within a ring oscillator (e.g., of a four-stage pseudo-differential ring oscillator (RO)) to generate intermediate clock phases. The four-stage pseudo-differential ring oscillator (RO) can he locked to the N^th harmonic of the reference frequency wherein the

total delay and phase across the four stages are

and 180° respectively for sustained oscillations. At the output of Stage-2, the output phase

is

[0011] Where and

are phases added by the four stages,

respectively. The change in the output phase

can be:

[0012] A variation in the output phase is realized by varying delays of the four stages in a complimentary manner satisfying the below relation:

[0013] The tunable capacitor banks implement a variable delay in each stage, thereby producing a phase shift. At phase shift with 5-bit (PI_LSB)

resolution is implemented by varying the phase contributions of the four delay stages. The tapped output nodes are varied from one stage to the other, and a ±22.5° phase shift can be realized at each tapped output. Shifting between different output stages is implemented so that the final output phase spans 0-360° with respect to a fixed output clock. The proposed phase interpolator implements a 45° phase shift at its output by locking the ring oscillator with a 45° phase- shifted reference clock, injecting the ring oscillator and tapping the ring oscillator at 45° phase- shifted nodes.

BRIEF DESCRIPTION OF DRAWINGS [0014] The drawings shown here are for illustration purpose and the actual system will not be limited by the size, shape, and arrangement of components or number of components represented in the drawings.

[0015] FIG. 1 illustrates a block diagram (100) of a pseudo-differential ring oscillator (RO) implemented with an embedded phase interpolator for interpolating clock phases within the ring oscillator (RO) to generate intermediate clock phases, in accordance with the disclosed embodiments; [0016] FIG. 2 illustrates a block diagram (200) of the ILCM with embedded phase interpolator (PI) with frequency range (2X frequency) and resolution (1.5°-2°), in accordance with the disclosed embodiments;

[0017] FIG. 3 illustrates a timing diagram (300) of a single wave form for coarse phase step at its output, in accordance with the disclosed embodiments;

[0018] FIG. 4 illustrates a timing diagram (400) of a single waveform for a fine phase step at its output, in accordance with the disclosed embodiments.

[0019] FIG. 5 illustrates an operational block diagram (500) of the ILCM-cum- PI with tunable oscillator stages to embed the phase interpolation with a resolution (1.5°-2°) across 2X frequency range, in accordance with the disclosed embodiments.

DETAILED DESCRIPTION

[0020] The principles of operation, design configurations and evaluation values in these non-limiting examples can be varied and are merely cited to illustrate at least one embodiment of the invention, without limiting the scope thereof.

[0021] The embodiments will be described in detail with corresponding marked references to the drawings, in which the illustrative components of the invention are outlined. The embodiments disclosed herein can be expressed in different forms and should not be considered as limited to the listed embodiments in the disclosed invention. The various embodiments outlined in the subsequent sections are construed such that it provides a complete and a thorough understanding of the disclosed invention, by clearly describing the scope of the invention, for those skilled in the art.

[0022] An injection locked clock multiplier with 2X frequency range and 1.5°-2° resolution for the embedded phase interpolator, is disclosed herein. A wide range (2X) injection locked clock multiplier (ILCM) with an embedded phase interpolator multiplies a low-frequency clock to generate a high-frequency output wherein the phase is shifted as desired during the clock generation itself. The ILCM retains the low output clock jitter across (340-550fs_rms) and a good PI resolution (1.5°-2°) across the phase interpolation range by eliminating the multiphase high-frequency clock distribution during phase interpolation.

[0023] The ILCM-cum-PI disclosed herein realizes an intermediate output clock phase by digitally controlling delays for signals already present in a multiphase ring oscillator. The clock signals are manipulated in time -domain rather than voltage or current domain during phase interpolation. The proposed ILCM-cum-PFs output phase does not depend on the shape of the analog multiphase clock signals such as, sinusoidal, triangular, square wave, etc., otherwise used during summing with a different voltage or current weights. Furthermore, the proposed ILCM-cum-PI does not need multiphase high- frequency clock distribution for phase interpolation, thereby saving power in high-frequency clock distribution and matching between multiple clock phases. The proposed ILCM-cum-PFs output phase is not restricted by the number of delay cells used to realize the ring oscillator wherein the ILCM-cum-PI has a linear change in the output phase with respect to the input digital control as delays or phases are directly manipulated. Unlike conventional phase interpolators, the random-jitter is independent of the input code or number of stages.

[0024] In one embodiment of the proposed invention, the embedded phase interpolator interpolates clock phases within a ring oscillator (e.g., of a four-stage pseudo-differential ring oscillator (RO)) to generate intermediate clock phases. FIG. 1 illustrates a block diagram (100) of a pseudo-differential ring oscillator (RO) (exemplary embodiment) implemented with an embedded phase interpolator for interpolating clock phases within the ring oscillator (RO) to generate intermediate clock phases, in accordance with the disclosed embodiments. The four-stage pseudo-differential ring oscillator (RO) can be locked to the N^th harmonic of the reference frequency

wherein the total delay and phase across the four stages are

and 180° respectively for sustained oscillations. At the output of Stage-2, the output phase 0_OUT can be:

[0025] Where

and

are phases added by the four stages, respectively. The change in the output phase

can be:

[0026] A variation in the output phase is realized by varying delays of the four stages in a complimentary manner satisfying the below relation:

[0027] The tunable capacitor banks implement a variable delay in each stage, thereby producing a phase shift. At phase shift with 5-bit (PI_LSB)

[0028] FIG. 2 illustrates a block diagram (200) of the ILCM with embedded phase interpolator (PI) with 2X frequency range and 1.5°-2° resolution, in accordance with the disclosed embodiments. FIG. 2 illustrates a block diagram (200) of the proposed 2.5-5.0GHz ILCM with an embedded phase interpolator consisting of a pseudo-differential current-controlled ring oscillator (RCCO), a NAND-based programmable injection pulse generation circuit, a digital-to-time converter (DTC), a 1:4 DMUX, an 8:1 differential MUX, and digitally controlled current-DACs (IDACs).

[0029] An ID AC with Coarse control is used to bring the ring oscillator within ±400ppm of the center frequency (2.5-5.0GHz). The reference clock REF is delayed by the DTC and combined by the pulse generating logic to produce a short pulse for injecting in the ring oscillator. The output phase, Fout, is controlled in two steps by phase interpolation codes, PIMSB and PILSB·

[0030] A 3-bit PIMSB controls DTC’s delay in steps of T _Cco/8, changes node of injection in the oscillator through 1:4 DMUX, and taps the desired clock output phase with 8:1 MUX. It results in a coarse change in phase by 45° at the output. A 5-bit PILSB regulates the delay of different delay cells used to realize the oscillator, thereby changing the output phase in 1.5° steps. During the output phase change by varying the delay of RCCO’s delay cells, the oscillator is maintained to oscillate at the desired frequency. Any frequency perturbations at the output due to change in PILSB is compensated by current I_fine1.

[0031 ] FIG. 3 illustrates a timing diagram (300) of a single wave form for coarse phase step at its output, in accordance with the disclosed embodiments. FIG. 3 illustrates the change in control codes and output phase shifts where a coarse 45° phase step with phase selection in the ring oscillator is realized.

[0032] FIG. 4 illustrates a timing diagram (400) of a single waveform for fine phase step at its output, in accordance with the disclosed embodiments. FIG. 4 illustrates the change in control codes and output phase shifts where a fine 1.5°- 2° phase step is realised with 5-bit capacitor bank in each stage of the ring oscillator.

[0033] The proposed phase interpolator realizes the output phase at different frequencies by tuning the ring oscillator for the desired output frequencies. The DTC gives the required delay in the reference clock path for injection. Hence, an output phase with less than 2° resolution is realized across a wide range of frequencies.

[0034] FIG. 5 illustrates an operational block diagram (500) of the ILCM-cum- PI with tunable oscillator stages to embed the phase interpolation in accordance with the disclosed embodiments. The delay setting in the digital-to-time converter (DTC) controls the delay of the injected pulse according to the node of injection. The capacitor banks in the oscillator stages are adjusted to embed the phase interpolation in the oscillator. For each node of injection, a ±22.5° phase shift or ±Tcco/16 delay is implemented at output node with 1.5°-2° phase step resolution. [0035] The different output phases at frequency f, are realized digitally in two steps: The digital control bits PIMSB are used to change the injection node in the ring oscillator and select the desired output phase using an 8:1 MUX. Hence, a coarse phase-step with 45° phase resolution is realized. Depending on the desired output phase (n x 45°), the delay of the pulse used for injection in the oscillator is varied by using a DTC. The latter provides p/Hfi, delay where p c { 0, 1, 2, 3}. A fine phase step with a 5 -bit resolution around each coarse phase step is generated by digitally controlling each stage's delay within the four-stage ring oscillator. A 5-bit capacitor bank controls the delay of each stage at its output. The delays for different RO’s stages have to be complimentary to retain the clock period.

[0036] It will be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Also, that various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.

Claims

CLAIMS: I/We claim:

1. An injection locked clock multiplier with embedded phase interpolator, comprising: a wide range (2X) injection locked clock multiplier (ILCM) with an embedded phase interpolator (PI) multiplies a low-frequency clock to generate a high-frequency output wherein the phase is shifted as desired during the clock generation itself with 2X frequency range and 1.5°-2° resolution.

2. The clock multiplier as claimed in claim 1 wherein the injection locked clock multiplier with embedded phase interpolator retains the low output clock jitter across (340-550fSrms) and a good PI resolution (1.5°- 2°) across the phase interpolation range by eliminating the multiphase high-frequency clock distribution during phase interpolation.

3. The clock multiplier as claimed in claim 1 wherein the ILCM-cum-PI realizes an intermediate output clock phase by digitally controlling delays for signals already present in a multiphase ring oscillator.

4. The clock multiplier as claimed in claim 1 wherein the clock signals are manipulated in time-domain.

5. The clock multiplier as claimed in claim 1 wherein the ILCM-cum-PFs output phase does not depend on the shape of the analog multiphase clock signals otherwise used during summing with a different voltage or current weights.

6. The clock multiplier as claimed in claim 1 wherein the output phase of the ILCM-cum-PI has a linear change in the output phase with respect to the input digital control as delays or phases are directly manipulated and is not restricted by the number of delay cells used to realize the ring oscillator wherein the ILCM-cum-PI.