WO2022224949A1 - Copper/ceramic bonded body and insulated circuit board - Google Patents

Copper/ceramic bonded body and insulated circuit board Download PDF

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Publication number
WO2022224949A1
WO2022224949A1 PCT/JP2022/018135 JP2022018135W WO2022224949A1 WO 2022224949 A1 WO2022224949 A1 WO 2022224949A1 JP 2022018135 W JP2022018135 W JP 2022018135W WO 2022224949 A1 WO2022224949 A1 WO 2022224949A1
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Prior art keywords
copper
ceramic
ceramic substrate
thickness
less
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PCT/JP2022/018135
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French (fr)
Japanese (ja)
Inventor
伸幸 寺▲崎▼
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三菱マテリアル株式会社
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Publication of WO2022224949A1 publication Critical patent/WO2022224949A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/19—Soldering, e.g. brazing, or unsoldering taking account of the properties of the materials to be soldered
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
    • C04B37/02—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal

Definitions

  • the present invention provides a copper/ceramic bonded body in which a copper member made of copper or a copper alloy and a ceramic member are joined together, and an insulating circuit in which a copper plate made of copper or a copper alloy is joined to the surface of a ceramic substrate. It relates to substrates.
  • a power module, an LED module, and a thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are joined to an insulating circuit board in which a circuit layer made of a conductive material is formed on one side of an insulating layer.
  • power semiconductor elements for high power control used to control wind power generation, electric vehicles, hybrid vehicles, etc. generate a large amount of heat during operation.
  • Patent Document 1 proposes an insulated circuit board in which a circuit layer and a metal layer are formed by bonding copper plates to one side and the other side of a ceramic substrate.
  • copper plates are arranged on one surface and the other surface of a ceramic substrate with an Ag—Cu—Ti brazing material interposed therebetween, and the copper plates are joined by heat treatment (so-called active metal brazing method).
  • Patent Document 2 proposes a power module substrate in which a copper plate made of copper or a copper alloy and a ceramic substrate made of AlN or Al 2 O 3 are bonded using a bonding material containing Ag and Ti. ing. Furthermore, Patent Document 3 proposes a power module substrate in which a copper plate made of copper or a copper alloy and a ceramic substrate made of silicon nitride are bonded using a bonding material containing Ag and Ti. As described above, when a copper plate and a ceramic substrate are bonded using a bonding material containing Ti, Ti, which is an active metal, reacts with the ceramic substrate, thereby improving the wettability of the bonding material and the copper plate. The bonding strength with the ceramic substrate is improved.
  • Japanese Patent No. 3211856 (B) Japanese Patent No. 5757359 (B) Japanese Patent Application Laid-Open No. 2018-008869 (A)
  • the heat generation temperature of the semiconductor elements mounted on the insulated circuit board tends to be higher, and the insulated circuit board is required to have higher cooling/heating cycle reliability to withstand severe cooling/heating cycles.
  • Ti which is an active metal
  • an intermetallic compound containing Cu and Ti precipitates.
  • the vicinity of the joint interface becomes hard, cracks may occur in the ceramic member during thermal cycle loading, and there is a risk of deterioration in thermal cycle reliability.
  • the present invention has been made in view of the above-mentioned circumstances. It is an object of the present invention to provide an insulated circuit board made of this copper/ceramic bonded body.
  • the inventors of the present invention conducted intensive studies and found that the shape of the copper member to be bonded to one surface and the other surface of the ceramic member, the application state of the bonding material, and the liquid phase during bonding It was found that the structure of the bonding interface between the copper plate bonded to one surface of the ceramic member and the bonding interface between the copper plate bonded to the other surface of the ceramic member differs depending on the occurrence conditions. If the hardness of the bonding interface between the copper member bonded to one surface and the other surface of the ceramic member is different, the balance of the thermal stress applied to the ceramic member during the thermal cycle load will be lost, and the ceramic member will be damaged. It was found that cracks are likely to occur.
  • the copper/ceramic joined body of the present invention is a copper/ceramic joined body in which a copper member made of copper or a copper alloy and a ceramic member are joined.
  • the copper member is bonded to one surface and the other surface of the ceramic member, respectively, and an active metal compound layer is formed on the ceramic member side at the bonding interface between the ceramic member and the copper member.
  • the maximum value of indentation hardness in a region from 20 ⁇ m to 50 ⁇ m from the interface with the copper member of the active metal compound layer to the copper member side is in the range of 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less.
  • the maximum value H1 of the indentation hardness in the copper member joined on the one surface side, and the maximum value H2 of the indentation hardness in the copper member joined on the other surface side. is 50 mgf/ ⁇ m 2 or less.
  • the indentation hardness H in the present invention refers to a test load of 5000 mgf using a triangular pyramidal diamond indenter called a Berkovich indenter having an inter-ridge angle of 114.8° or more and 115.1° or less. It is calculated from the following formula by measuring the load-displacement correlation.
  • Contact area A 24.56 x hc 2
  • Indentation hardness H P/A
  • an active metal compound layer is formed on the ceramic member side at the joint interface with the copper member joined to the one surface and the other surface of the ceramic member. and the maximum value of indentation hardness in a region from 20 ⁇ m to 50 ⁇ m from the interface with the copper member of the active metal compound layer toward the copper member is in the range of 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less. Therefore, the ceramic member and the copper member are firmly joined by the active metal, and the joining interface is prevented from being hardened more than necessary.
  • the maximum value H1 of the indentation hardness of the copper member joined on the one side and the maximum value H2 of the indentation hardness of the copper member joined to the other side Since the difference is 50 mgf/ ⁇ m 2 or less, there is no large difference in the hardness of the bonding interface between the one surface of the ceramic member and the copper member bonded to the other surface of the ceramic member. It is possible to suppress the occurrence of cracks in the ceramic member at the time, and has excellent thermal cycle reliability.
  • the maximum value H1 of the indentation hardness of the copper member joined to the one surface side and the maximum value H2 of the indentation hardness of the copper member joined to the other surface side are , are within the range of 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less.
  • the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic member and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic member is within the range of 0.05 ⁇ m or more and 1.2 ⁇ m or less, so that the ceramic member and the copper member are reliably and strongly bonded by the active metal, and the hardening of the bonding interface is further suppressed.
  • the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper members respectively bonded to the one surface and the other surface of the ceramic member is increased. It is possible to further suppress the occurrence of cracks in the ceramic member under thermal cycle loads.
  • an Ag—Cu alloy layer is formed on the copper member side at the bonding interface between the ceramic member and the copper member, and the one side of the ceramic member.
  • the ratio tb1/tb2 between the thickness tb1 of the Ag—Cu alloy layer formed on the surface side and the thickness tb2 of the Ag—Cu alloy layer formed on the other surface side of the ceramic member is 0. .7 or more and 1.4 or less.
  • the thickness tb1 of the Ag—Cu alloy layer formed on the one surface side of the ceramic member and the thickness of the Ag—Cu alloy layer formed on the other surface side of the ceramic member Since the ratio tb1/tb2 to tb2 is within the range of 0.7 or more and 1.4 or less, the bonding interface between the copper member bonded to the one surface and the other surface of the ceramic member, respectively A large difference in hardness does not occur, and it is possible to further suppress the occurrence of cracks in the ceramic member during thermal cycle loads.
  • the copper member bonded to the one surface and the other surface of the ceramic member respectively has a thickness of 10 ⁇ m or more and 30 ⁇ m or less from the surface opposite to the ceramic member. It is preferable that the average value of the indentation hardness in the region is within the range of 70 mgf/ ⁇ m 2 or more and 90 mgf/ ⁇ m 2 or less. In this case, since the average value of the indentation hardness in the region of 10 ⁇ m or more and 30 ⁇ m or less from the surface of the copper member opposite to the ceramic member is in the range of 70 mgf/ ⁇ m 2 or more and 90 mgf/ ⁇ m 2 or less. , the entire copper member is not hardened, and when other members are joined to the surface of this copper member, the reliability of joining with these other members can be improved.
  • the insulated circuit board of the present invention is an insulated circuit board in which a copper plate made of copper or a copper alloy is bonded to the surface of a ceramic substrate, and the copper plate is attached to the one surface and the other surface of the ceramic substrate, respectively. is bonded, and an active metal compound layer is formed on the ceramic substrate side at the bonding interface between the ceramic substrate and the copper plate, and from the interface of the active metal compound layer with the copper plate to the copper plate side
  • the maximum value of the indentation hardness in the region from 20 ⁇ m to 50 ⁇ m is within the range of 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less, and the maximum indentation hardness of the copper plate bonded to the one surface side
  • the difference between the value H1 and the maximum value H2 of the indentation hardness of the copper plate joined to the other surface is 50 mgf/ ⁇ m 2 or less.
  • an active metal compound layer is formed on the ceramic substrate side at the bonding interface between the one surface and the other surface of the ceramic substrate and the copper plate bonded to the other surface, Since the maximum value of the indentation hardness in the region from 20 ⁇ m to 50 ⁇ m from the interface with the copper plate of the active metal compound layer to the copper plate side is in the range of 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less, The active metal firmly bonds the ceramic substrate and the copper plate, and suppresses hardening of the bonding interface.
  • the difference between the maximum value H1 of the indentation hardness of the copper plate bonded to the one surface side and the maximum value H2 of the indentation hardness of the copper plate bonded to the other surface side is Since it is set to 50 mgf/ ⁇ m 2 or less, there is no large difference in the hardness of the bonding interface between the one surface of the ceramic substrate and the copper plate bonded to the other surface of the ceramic substrate, and the ceramic substrate is subjected to a thermal cycle load. It can suppress the occurrence of cracks and has excellent thermal cycle reliability.
  • the thickness ta2 of the active metal compound layer formed on the other surface side of the substrate is in the range of 0.05 ⁇ m or more and 1.2 ⁇ m or less, and the thickness ratio ta1/ta2 is 0.7 or more and 1.4 or less.
  • the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic substrate and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic substrate is preferably within the range of In this case, the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic substrate and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic substrate.
  • the ceramic substrate and the copper plate are reliably and strongly bonded by the active metal, and hardening of the bonding interface is further suppressed.
  • the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper plates bonded to the one surface and the other surface of the ceramic substrate , and cracking of the ceramic substrate under thermal cycle load can be further suppressed.
  • an Ag—Cu alloy layer is formed on the copper plate side at the bonding interface between the ceramic substrate and the copper plate, and is formed on the one surface side of the ceramic member.
  • a ratio tb1/tb2 between the thickness tb1 of the Ag—Cu alloy layer formed on the surface of the ceramic member and the thickness tb2 of the Ag—Cu alloy layer formed on the other surface of the ceramic member is 0.7 or more and 1 .4 or less is preferable.
  • the thickness tb1 of the Ag—Cu alloy layer formed on the one surface side of the ceramic substrate and the thickness of the Ag—Cu alloy layer formed on the other surface side of the ceramic substrate Since the ratio tb1/tb2 to tb2 is within the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper plates bonded to the one surface and the other surface of the ceramic substrate, respectively. It is possible to further suppress the occurrence of cracks in the ceramic substrate under thermal cycle loads.
  • the copper plate bonded to the one surface and the other surface of the ceramic substrate, respectively has an indentation in an area of 10 ⁇ m or more and 30 ⁇ m or less from the surface opposite to the ceramic substrate. It is preferable that the average value of the hardness is within the range of 70 mgf/ ⁇ m 2 or more and 90 mgf/ ⁇ m 2 or less.
  • the average value of the indentation hardness in the region of 10 ⁇ m or more and 30 ⁇ m or less from the surface of the copper plate opposite to the ceramic substrate is in the range of 70 mgf/ ⁇ m 2 or more and 90 mgf/ ⁇ m 2 or less.
  • the entire copper plate is not hardened, and when other members are joined to the surface of this copper plate, the reliability of joining with these other members can be improved.
  • the present invention even when a severe thermal cycle is applied, the occurrence of cracks in the ceramic member can be suppressed, and the copper / ceramics joined body has excellent thermal cycle reliability, and the copper / ceramics joined body It is possible to provide an insulated circuit board that is
  • FIG. 1 is a schematic explanatory diagram of a power module using an insulated circuit board according to an embodiment of the present invention
  • FIG. FIG. 2 is an enlarged explanatory view of a bonding interface between the circuit layer of the insulated circuit board and the ceramic substrate according to the embodiment of the present invention
  • FIG. 2 is an enlarged explanatory view of a bonding interface between a metal layer of an insulated circuit board and a ceramic substrate according to an embodiment of the present invention
  • 1 is a flowchart of a method for manufacturing an insulated circuit board according to an embodiment of the present invention
  • FIG. It is a schematic explanatory drawing of the manufacturing method of the insulation circuit board which concerns on embodiment of this invention.
  • the copper/ceramic bonded body according to the present embodiment includes a ceramic substrate 11 as a ceramic member made of ceramics, and a copper plate 42 (circuit layer 12) and a copper plate 43 (metal layer 13) as copper members made of copper or a copper alloy. is an insulating circuit board 10 formed by bonding the .
  • FIG. 1 shows a power module 1 having an insulated circuit board 10 according to this embodiment.
  • This power module 1 includes an insulating circuit board 10 on which a circuit layer 12 and a metal layer 13 are arranged, and a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 via a bonding layer 2. and a heat sink 5 arranged on the other side (lower side in FIG. 1) of the metal layer 13 .
  • the semiconductor element 3 is made of a semiconductor material such as Si.
  • the semiconductor element 3 and the circuit layer 12 are bonded via the bonding layer 2 .
  • the bonding layer 2 is made of, for example, a Sn--Ag-based, Sn--In-based, or Sn--Ag--Cu-based solder material.
  • the heat sink 5 is for dissipating heat from the insulating circuit board 10 described above.
  • the heat sink 5 is made of copper or a copper alloy, and is made of phosphorus-deoxidized copper in this embodiment.
  • the heat sink 5 is provided with a channel through which cooling fluid flows.
  • the heat sink 5 and the metal layer 13 are joined by a solder layer 7 made of a solder material.
  • the solder layer 7 is made of, for example, a Sn--Ag-based, Sn--In-based, or Sn--Ag--Cu-based solder material.
  • the insulating circuit board 10 of the present embodiment includes a ceramic substrate 11, a circuit layer 12 provided on one surface (upper surface in FIG. 1) of the ceramic substrate 11, and a ceramic substrate. and a metal layer 13 disposed on the other surface (lower surface in FIG. 1) of the substrate 11 .
  • the ceramics substrate 11 is made of ceramics such as silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), alumina (Al 2 O 3 ), etc., which are excellent in insulation and heat dissipation.
  • the ceramic substrate 11 is made of aluminum nitride (AlN), which has excellent heat dissipation properties.
  • the thickness of the ceramic substrate 11 is set within a range of, for example, 0.2 mm or more and 1.5 mm or less, and is set to 0.635 mm in this embodiment.
  • the circuit layer 12 is formed by bonding a copper plate 42 made of copper or a copper alloy to one surface (upper surface in FIG. 4) of the ceramic substrate 11. As shown in FIG. In the present embodiment, the circuit layer 12 is formed by punching out a rolled plate of oxygen-free copper, arranging it in a circuit pattern and bonding it to the ceramic substrate 11 .
  • the thickness of the copper plate 42 that forms the circuit layer 12 is set within a range of 0.1 mm or more and 2.0 mm or less, and is set to 0.6 mm in this embodiment.
  • the metal layer 13 is formed by bonding a copper plate 43 made of copper or a copper alloy to the other surface of the ceramic substrate 11 (the lower surface in FIG. 4).
  • the metal layer 13 is formed by bonding a rolled plate of oxygen-free copper to the ceramic substrate 11 .
  • the thickness of the copper plate 43 that forms the metal layer 13 is set within a range of 0.1 mm or more and 2.0 mm or less, and is set to 0.6 mm in this embodiment.
  • an active metal compound layer 21 and an Ag--Cu alloy layer 22 are formed in order from the ceramic substrate 11 side.
  • the maximum value H1 of the indentation hardness in the region E1 from 20 ⁇ m to 50 ⁇ m from the interface of the active metal compound layer 21 with the circuit layer 12 toward the circuit layer 12 is 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m. It is within the range of ⁇ m 2 or less.
  • an active metal compound layer 31 and an Ag—Cu alloy layer 32 are formed in order from the ceramic substrate 11 side.
  • the maximum value H2 of the indentation hardness in the region E2 from 20 ⁇ m to 50 ⁇ m from the interface with the metal layer 13 of the active metal compound layer 31 to the metal layer 13 side is 120 mgf/ ⁇ m 2 or more and 200 mgf/ ⁇ m. It is within the range of ⁇ m 2 or less.
  • the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness of the metal layer 13 formed on the other surface of the ceramic substrate 11 The difference from the maximum value H2 of the indentation hardness is 50 mgf/ ⁇ m 2 or less.
  • the lower limit of the difference between the maximum value H1 and the maximum value H2 is not limited, it is set to 0 mgf/ ⁇ m2, for example.
  • the thickness ta1 of the active metal compound layer 21 formed on one side of the ceramic substrate 11 and the thickness ta1 of the active metal compound layer 31 formed on the other side of the ceramic substrate 11 are It is preferable that the thickness ta2 is in the range of 0.05 ⁇ m or more and 1.2 ⁇ m or less, and the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less.
  • the bonding material 45 contains Ti as an active metal and the ceramic substrate 11 is made of aluminum nitride
  • the active metal compound layers 21 and 31 are made of titanium nitride (TiN). .
  • the thickness tb1 of the Ag--Cu alloy layer 22 formed on one side of the ceramic substrate 11 and the thickness tb1 of the Ag--Cu alloy layer 32 formed on the other side of the ceramic substrate 11 It is preferable that the ratio tb1/tb2 to the thickness tb2 of the substrate be within the range of 0.7 or more and 1.4 or less. Further, the thickness of the Ag--Cu alloy layer 22 (Ag--Cu alloy layer 32) is preferably 1 ⁇ m or more and 30 ⁇ m or less.
  • the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11 are separated by 10 ⁇ m or more from the surface opposite to the ceramic substrate 11 . It is preferable that the average value of the indentation hardness in the regions E3 and E4 of 30 ⁇ m or less is within the range of 70 mgf/ ⁇ m 2 or more and 90 mgf/ ⁇ m 2 or less.
  • FIG. 1 A method for manufacturing the insulated circuit board 10 according to the present embodiment will be described below with reference to FIGS. 3 and 4.
  • FIG. 1 A method for manufacturing the insulated circuit board 10 according to the present embodiment will be described below with reference to FIGS. 3 and 4.
  • a copper plate 42 to be the circuit layer 12 and a copper plate 43 to be the metal layer 13 are prepared.
  • the copper plate 42 to be the circuit layer 12 is a pressed piece arranged in a circuit pattern.
  • a bonding material 45 is applied to the bonding surfaces of the copper plate 42 to be the circuit layer 12 and the copper plate 43 to be the metal layer 13 and dried.
  • the coating thickness of the paste-like bonding material 45 is preferably within the range of 10 ⁇ m or more and 50 ⁇ m or less after drying.
  • the paste bonding material 45 is applied by screen printing.
  • the bonding material 45 contains Ag and active metals (Ti, Zr, Nb, Hf).
  • an Ag--Ti based brazing material (Ag--Cu--Ti based brazing material) is used as the bonding material 45.
  • the Ag--Ti-based brazing material (Ag--Cu--Ti-based brazing material) contains, for example, Cu in the range of 0 mass% or more and 32 mass% or less, and Ti, which is an active metal, in the range of 0.5 mass% or more and 20 mass% or less. It is preferable to use a composition having a composition that is included within the range and that the balance is Ag and unavoidable impurities.
  • the active metal compound layers 21 and 31 are exposed to the circuit layer 12 and the metal layer 13 from the interface with the circuit layer 12 and the metal layer 13.
  • the maximum values H1 and H2 of the indentation hardness in the regions E1 and E2 from 20 ⁇ m to 50 ⁇ m toward the metal layer 13 are controlled. That is, when the specific surface area of the Ag powder is small, the sinterability of the paste-like bonding material 45 is increased, and a liquid phase is likely to occur in the heating step S03 described later, promoting diffusion of the active metal, and increasing the The maximum value of indentation hardness increases.
  • the lower limit of the specific surface area of Ag powder is preferably 0.15 m 2 /g or more, more preferably 0.25 m 2 /g or more, and more preferably 0.40 m 2 /g or more.
  • the upper limit of the specific surface area of the Ag powder is preferably 1.40 m 2 /g or less, more preferably 1.00 m 2 /g or less, and more preferably 0.75 m 2 /g or less. preferable.
  • the particle size of the Ag powder contained in the paste-like bonding material 45 is preferably in the range of D10 from 0.7 ⁇ m to 3.5 ⁇ m and D100 from 4.5 ⁇ m to 23 ⁇ m.
  • a copper plate 42 to be the circuit layer 12 is laminated on one surface (upper surface in FIG. 4) of the ceramic substrate 11 with a bonding material 45 interposed therebetween, and on the other surface (lower surface in FIG. 4) of the ceramic substrate 11 , a copper plate 43 to be the metal layer 13 is laminated with a bonding material 45 interposed therebetween.
  • Heating step S03 Next, the copper plate 42, the ceramic substrate 11, and the copper plate 43 are heated in a heating furnace in a vacuum atmosphere to melt the bonding material 45 while being pressurized.
  • the pressurized state here means, for example, a state in which the copper plates 42 and 43 are pressed toward the ceramic substrate 11 side.
  • the heating temperature in the heating step S03 is preferably within the range of 800° C. or higher and 850° C. or lower.
  • the total temperature integral value in the heating process from 780° C. to the heating temperature and the holding process at the heating temperature is preferably within the range of 7° C. ⁇ h or more and 120° C. ⁇ h or less.
  • the pressure load in the heating step S03 is preferably in the range of 0.029 MPa or more and 2.94 MPa or less. Furthermore, the degree of vacuum in the heating step S03 is preferably in the range of 1 ⁇ 10 ⁇ 6 Pa or more and 5 ⁇ 10 ⁇ 2 Pa or less.
  • cooling step S04 After the heating step S03, cooling is performed to solidify the molten bonding material 45, thereby bonding the copper plate 42 that will be the circuit layer 12 and the ceramic substrate 11, and the ceramic substrate 11 and the copper plate 43 that will be the metal layer 13. do.
  • the cooling rate in this cooling step S04 is preferably within the range of 2° C./min or more and 20° C./min or less.
  • the cooling rate here is the cooling rate from the heating temperature to 780° C., which is the Ag—Cu eutectic temperature.
  • the cooling step S04 by flowing an inert gas to either the circuit layer 12 (copper plate 42) side or the metal layer 13 (copper plate 43) side, the circuit layer 12 (copper plate 42) side and the metal layer 13 side are cooled. It becomes possible to adjust the cooling rate on the (copper plate 43) side.
  • the heating step S03 and the cooling step S04 when the SPS (discharge plasma sintering) method is applied, the electrode on the circuit layer 12 (copper plate 42) side and the electrode on the metal layer 13 (copper plate 43) side By adjusting the flow rate of the cooling water, it is possible to adjust the cooling rate on the circuit layer 12 (copper plate 42) side and the metal layer 13 (copper plate 43) side.
  • the insulated circuit board 10 of the present embodiment is manufactured through the bonding material disposing step S01, the laminating step S02, the heating step S03, and the cooling step S04.
  • Heat-sink bonding step S05 Next, the heat sink 5 is bonded to the other side of the metal layer 13 of the insulated circuit board 10 .
  • the insulating circuit board 10 and the heat sink 5 are laminated with a solder material interposed therebetween and placed in a heating furnace.
  • semiconductor element bonding step S06 Next, the semiconductor element 3 is soldered to one surface of the circuit layer 12 of the insulating circuit board 10 .
  • the power module 1 shown in FIG. 1 is produced by the above-described steps.
  • the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer formed on the other surface Active metal compound layers 21 and 31 are formed on the ceramic substrate 11 side at the bonding interface with the layer 13, and from the interface between the active metal compound layers 21 and 31 and the circuit layer 12 and the metal layer 13, the circuit layer 12 and the metal layer 13 are formed. Since the maximum values H1 and H2 of the indentation hardness in the regions E1 and E2 from 20 ⁇ m to 50 ⁇ m toward the metal layer 13 side are 120 mgf/ ⁇ m 2 or more, the active metal of the bonding material 45 reacts sufficiently.
  • maximum values H1 and H2 of indentation hardness in regions E1 and E2 from 20 ⁇ m to 50 ⁇ m from the interfaces of the active metal compound layers 21 and 31 with the circuit layer 12 and the metal layer 13 toward the circuit layer 12 and the metal layer 13. is set to 200 mgf/ ⁇ m 2 or less, it is possible to suppress the bonding interface from becoming harder than necessary, and to improve the thermal cycle reliability.
  • the maximum values H1 and H2 of the indentation hardness of the bonding interface are preferably 125 mgf/ ⁇ m 2 or more. More preferably, it is 130 mgf/ ⁇ m 2 or more. Further, in order to further suppress the bonding interface from becoming unnecessarily hard, the maximum values H1 and H2 of the indentation hardness of the bonding interface are preferably 180 mgf/ ⁇ m 2 or less, and 150 mgf/ ⁇ m 2 or less. is more preferable.
  • the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness of the metal layer 13 formed on the other surface of the ceramic substrate 11 Since the difference from the maximum value H2 of the indentation hardness is 50 mgf/ ⁇ m 2 or less, the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal formed on the other surface of the ceramic substrate 11 There is no large difference in the hardness of the bonding interface with the layer 13, cracking of the ceramic substrate 11 can be suppressed under a thermal cycle load, and the thermal cycle reliability is excellent.
  • the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness formed on the other surface of the ceramic substrate 11 The difference from the maximum value H2 of the indentation hardness of the metal layer 13 is preferably 40 mgf/ ⁇ m 2 or less, more preferably 30 mgf/ ⁇ m 2 or less.
  • the thickness ta1 of the active metal compound layer 21 formed on one side of the ceramic substrate 11 on the side of the circuit layer 12, and the thickness ta1 of the metal layer 21 formed on the other side of the ceramic substrate 11 When the thickness ta2 of the active metal compound layer 31 formed on the layer 13 side is 0.05 ⁇ m or more, the active metal of the bonding material 45 sufficiently reacts with the ceramic substrate 11, and the ceramic substrate 11, the circuit layer 12 and the metal layer 13 are joined more firmly.
  • the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 are set to 1.2 ⁇ m or less, it is possible to suppress the bonding interface from becoming unnecessarily hard, thereby improving the reliability of the thermal cycle. It is possible to further improve the performance.
  • the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 are set to 0.08 ⁇ m or more. is preferred, and 0.15 ⁇ m or more is more preferred. Further, in order to further suppress the bonding interface from becoming unnecessarily hard, it is preferable to set the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 to 1.0 ⁇ m or less. 0.6 ⁇ m or less is more preferable.
  • the thickness ratio ta1/ta2 of the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 is in the range of 0.7 or more and 1.4 or less. Therefore, there is no large difference in the hardness of the bonding interface between the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11. It is possible to further suppress the occurrence of cracks in the ceramic substrate 11 in . In order to further suppress the occurrence of cracks in the ceramic substrate 11 under thermal cycle load, the thickness ratio ta1/ta2 of the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 should be set to 0. 0.8 or more and 1.2 or less, and more preferably 0.9 or more and 1.1 or less.
  • the thickness tb1 of the Ag—Cu alloy layer 22 formed on one side of the ceramic substrate 11 and the thickness tb1 of the Ag—Cu alloy layer 32 formed on the other side of the ceramic substrate 11 are When the ratio tb1/tb2 to the thickness tb2 is in the range of 0.7 or more and 1.4 or less, the circuit layer 12 formed on one surface of the ceramics substrate 11 and the other surface of the ceramics substrate 11 There is no large difference in the hardness of the joint interface with the metal layer 13 formed on the surface of the ceramic substrate 11, and the occurrence of cracks in the ceramic substrate 11 under thermal cycle load can be further suppressed.
  • the thickness ratio tb1/ tb2 is more preferably in the range of 0.8 or more and 1.2 or less, and more preferably in the range of 0.9 or more and 1.1 or less.
  • the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11 are separated from the surface opposite to the ceramic substrate 11 by 10 ⁇ m or more and 30 ⁇ m from the surface opposite to the ceramic substrate 11 .
  • the average value of the indentation hardness in the following regions E3 and E4 is within the range of 70 mgf / ⁇ m2 or more and 90 mgf/ ⁇ m2 or less, the circuit layer 12 as a whole and the metal layer 13 as a whole are hardened.
  • the reliability of bonding between the semiconductor element 3 bonded to the surface of the circuit layer 12 and the heat sink 5 bonded to the surface of the metal layer 13 can be improved.
  • a power module is configured by mounting a semiconductor element on an insulated circuit board, but the present invention is not limited to this.
  • an LED module may be configured by mounting an LED element on the circuit layer of the insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on the circuit layer of the insulating circuit board.
  • the ceramic substrate is made of aluminum nitride ( AlN).
  • other ceramic substrates such as silicon nitride (Si 3 N 4 ) may be used.
  • Ti was used as an example of the active metal contained in the bonding material. It suffices if it contains the above active metals. These active metals may be contained as hydrides.
  • a ceramic substrate (40 mm ⁇ 40 mm) shown in Table 1 was prepared.
  • the thickness of AlN and Al 2 O 3 was 0.635 mm, and the thickness of Si 3 N 4 was 0.32 mm.
  • two copper pieces of 37 mm ⁇ 18 mm having a thickness shown in Table 1 and made of oxygen-free copper were prepared as a copper plate serving as a circuit layer.
  • a copper plate made of oxygen-free copper and having a thickness of 37 mm ⁇ 37 mm as shown in Table 1 was prepared as a copper plate serving as a metal layer.
  • a bonding material containing Ag powder having a BET value shown in Table 1 was applied to a copper plate serving as a circuit layer so that the target thickness after drying was 30 ⁇ m.
  • a bonding material containing Ag powder having a BET value shown in Table 1 was applied to a copper plate serving as a metal layer so as to have a target thickness of 30 ⁇ m after drying.
  • a paste material was used as the bonding material, and the amounts of Ag, Cu, and active metal were as shown in Table 1.
  • the BET value (specific surface area) of the Ag powder was measured by using AUTOSORB-1 manufactured by QUANTACHRROME, vacuum deaeration by heating at 150 ° C. for 30 minutes as pretreatment, N 2 adsorption, liquid nitrogen 77 K, BET multipoint method. It was measured.
  • a copper plate serving as a circuit layer was laminated on one surface of the ceramic substrate. At this time, two copper pieces were arranged with an interval of 1 mm. A copper plate serving as a metal layer was laminated on the other surface of the ceramic substrate.
  • This laminate was heated while being pressed in the lamination direction to melt the bonding material.
  • the pressure load was set to 0.196 MPa, and the temperature integral value was set as shown in Table 2.
  • the bonding was performed by the SPS (discharge plasma sintering) method, and the cooling rate shown in Table 2 was obtained by adjusting the flow rate of the cooling water between the electrode on the circuit layer side and the electrode on the metal layer side. was adjusted to be
  • the indentation hardness, active metal compound layer, Ag-Cu alloy layer, and thermal cycle reliability of the resulting insulated circuit board (copper/ceramic bonded body) were evaluated as follows.
  • the resulting insulated circuit board (copper/ceramic bonded body) was cut in the lamination direction, and the active metal compound layer was bonded to the circuit layer and metal layer at the bonding interface between the ceramic board and the circuit layer and metal layer by the method described above.
  • the indentation hardness in the regions from 20 ⁇ m to 50 ⁇ m from the interface to the circuit layer side and the metal layer side was measured and calculated at five points, and the maximum value was obtained. Further, the indentation hardness in the regions of 10 ⁇ m or more and 30 ⁇ m or less from the surface of the circuit layer and the metal layer on the side opposite to the ceramic substrate was measured and calculated at five points, and the average value was calculated.
  • the insulating circuit substrate described above was subjected to the following cooling and heating cycles, and the presence or absence of cracks in the ceramics was determined by SAT inspection.
  • Table 2 shows the evaluation results. The number of occurrences of ceramic cracks in Table 2 means the number of thermal cycles required until ceramic cracks occur.
  • AlN and Al 2 O 3 One cycle is a load of ⁇ 40° C. ⁇ 5 min and 150° C. ⁇ 5 min, and SAT inspection is performed every 50 cycles up to 500 cycles.
  • Si 3 N 4 One cycle is a load of ⁇ 40° C. ⁇ 5 min and 150° C. ⁇ 5 min, and SAT inspection is performed every 200 cycles up to 2000 cycles.
  • Comparative Example 1 in which the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side was 61 mgf/ ⁇ m 2 , and the maximum value of the indentation hardness H2 on the metal layer side was It is confirmed that the cooling/heating cycle reliability is superior to that of Comparative Example 2 with 217 mgf/ ⁇ m 2 .
  • the maximum values of the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side were 120 mgf. / ⁇ m 2 or more and 200 mgf/ ⁇ m 2 or less, and the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side is 50 mgf/ ⁇ m 2 or less.
  • the present invention even when a severe thermal cycle is applied, the occurrence of cracks in the ceramic member can be suppressed, and the copper / ceramics joined body has excellent thermal cycle reliability, and the copper / ceramics joined body It is possible to provide an insulated circuit board that is

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Abstract

This copper/ceramic bonded body is obtained by bonding a copper members (12), (13) to one surface and the other surface of a ceramic member (11), respectively, wherein, at the bonding interfaces of the ceramic member (11) and the copper members (12), (13), the maximum value of the indentation hardness of regions of 10 μm to 50 μm from the bonding interfaces of active metal compound layers (21), (31) with the copper members (12), (13) to the sides of the copper members (12), (13) is in a range of 120 mgf/μm2 to 200 mgf/μm2, and the difference between the maximum value H1 of the indentation hardness in the copper member (12) bonded to the one surface and the maximum value H2 of the indentation hardness in the copper member (13) bonded to the other surface is 50 mgf/μm2 or less.

Description

銅／セラミックス接合体、および、絶縁回路基板Copper/Ceramic Bonded Body and Insulated Circuit Board
　この発明は、銅又は銅合金からなる銅部材と、セラミックス部材とが接合されてなる銅／セラミックス接合体、および、セラミックス基板の表面に、銅又は銅合金からなる銅板が接合されてなる絶縁回路基板に関するものである。
　本願は、２０２１年４月１９日に、日本に出願された特願２０２１－０７０２２１号に基づき優先権を主張し、その内容をここに援用する。 The present invention provides a copper/ceramic bonded body in which a copper member made of copper or a copper alloy and a ceramic member are joined together, and an insulating circuit in which a copper plate made of copper or a copper alloy is joined to the surface of a ceramic substrate. It relates to substrates.
This application claims priority based on Japanese Patent Application No. 2021-070221 filed in Japan on April 19, 2021, the content of which is incorporated herein.
　パワーモジュール、ＬＥＤモジュールおよび熱電モジュールにおいては、絶縁層の一方の面に導電材料からなる回路層を形成した絶縁回路基板に、パワー半導体素子、ＬＥＤ素子および熱電素子が接合された構造とされている。
　例えば、風力発電、電気自動車、ハイブリッド自動車等を制御するために用いられる大電力制御用のパワー半導体素子は、動作時の発熱量が多いことから、これを搭載する基板としては、セラミックス基板と、このセラミックス基板の一方の面に導電性の優れた金属板を接合して形成した回路層と、セラミックス基板の他方の面に金属板を接合して形成した放熱用の金属層と、を備えた絶縁回路基板が、従来から広く用いられている。 A power module, an LED module, and a thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are joined to an insulating circuit board in which a circuit layer made of a conductive material is formed on one side of an insulating layer. .
For example, power semiconductor elements for high power control used to control wind power generation, electric vehicles, hybrid vehicles, etc. generate a large amount of heat during operation. A circuit layer formed by bonding a metal plate having excellent conductivity to one surface of the ceramic substrate, and a metal layer for heat dissipation formed by bonding a metal plate to the other surface of the ceramic substrate. Insulated circuit boards have been widely used in the past.
　例えば、特許文献１には、セラミックス基板の一方の面および他方の面に、銅板を接合することにより回路層および金属層を形成した絶縁回路基板が提案されている。この特許文献１においては、セラミックス基板の一方の面および他方の面に、Ａｇ－Ｃｕ－Ｔｉ系ろう材を介在させて銅板を配置し、加熱処理を行うことにより銅板が接合されている（いわゆる活性金属ろう付け法）。 For example, Patent Document 1 proposes an insulated circuit board in which a circuit layer and a metal layer are formed by bonding copper plates to one side and the other side of a ceramic substrate. In this patent document 1, copper plates are arranged on one surface and the other surface of a ceramic substrate with an Ag—Cu—Ti brazing material interposed therebetween, and the copper plates are joined by heat treatment (so-called active metal brazing method).
　また、特許文献２においては、銅又は銅合金からなる銅板と、ＡｌＮ又はＡｌ２Ｏ３からなるセラミックス基板とが、ＡｇおよびＴｉを含む接合材を用いて接合されたパワーモジュール用基板が提案されている。
　さらに、特許文献３には、銅又は銅合金からなる銅板と、窒化ケイ素からなるセラミックス基板とが、ＡｇおよびＴｉを含む接合材を用いて接合されたパワーモジュール用基板が提案されている。
　前述のように、Ｔｉを含む接合材を用いて銅板とセラミックス基板とを接合した場合には、活性金属であるＴｉがセラミックス基板と反応することにより、接合材の濡れ性が向上し、銅板とセラミックス基板との接合強度が向上することになる。 Patent Document 2 proposes a power module substrate in which a copper plate made of copper or a copper alloy and a ceramic substrate made of AlN or Al 2 O 3 are bonded using a bonding material containing Ag and Ti. ing.
Furthermore, Patent Document 3 proposes a power module substrate in which a copper plate made of copper or a copper alloy and a ceramic substrate made of silicon nitride are bonded using a bonding material containing Ag and Ti.
As described above, when a copper plate and a ceramic substrate are bonded using a bonding material containing Ti, Ti, which is an active metal, reacts with the ceramic substrate, thereby improving the wettability of the bonding material and the copper plate. The bonding strength with the ceramic substrate is improved.
日本国特許第３２１１８５６号公報（Ｂ）Japanese Patent No. 3211856 (B) 日本国特許第５７５７３５９号公報（Ｂ）Japanese Patent No. 5757359 (B) 日本国特開２０１８－００８８６９号公報（Ａ）Japanese Patent Application Laid-Open No. 2018-008869 (A)
　ところで、最近では、絶縁回路基板に搭載される半導体素子の発熱温度が高くなる傾向にあり、絶縁回路基板には、従来にも増して、厳しい冷熱サイクルに耐えることができる冷熱サイクル信頼性が求められている。
　ここで、前述のように、Ｔｉを含む接合材を用いて銅板とセラミックス基板とを接合した場合には、銅板側に活性金属であるＴｉが拡散し、ＣｕとＴｉを含む金属間化合物が析出することで、接合界面近傍が硬くなり、冷熱サイクル負荷時にセラミックス部材に割れが生じ、冷熱サイクル信頼性が低下するおそれがあった。 By the way, recently, the heat generation temperature of the semiconductor elements mounted on the insulated circuit board tends to be higher, and the insulated circuit board is required to have higher cooling/heating cycle reliability to withstand severe cooling/heating cycles. It is
Here, as described above, when a copper plate and a ceramic substrate are bonded using a bonding material containing Ti, Ti, which is an active metal, diffuses into the copper plate side, and an intermetallic compound containing Cu and Ti precipitates. As a result, the vicinity of the joint interface becomes hard, cracks may occur in the ceramic member during thermal cycle loading, and there is a risk of deterioration in thermal cycle reliability.
　この発明は、前述した事情に鑑みてなされたものであって、厳しい冷熱サイクルを負荷した場合であっても、セラミックス部材における割れの発生を抑制でき、冷熱サイクル信頼性に優れた銅／セラミックス接合体、および、この銅／セラミックス接合体からなる絶縁回路基板を提供することを目的とする。 The present invention has been made in view of the above-mentioned circumstances. It is an object of the present invention to provide an insulated circuit board made of this copper/ceramic bonded body.
　前述の課題を解決するために、本発明者らが鋭意検討した結果、セラミックス部材の一方の面と他方の面にそれぞれ接合される銅部材の形状、接合材の塗布状況、接合時の液相発生状況等によって、セラミックス部材の一方の面に接合された銅板との接合界面と、セラミックス部材の他方の面に接合された銅板との接合界面と、で構造が異なることが分かった。
　そして、セラミックス部材の一方の面と他方の面にそれぞれ接合された銅部材との接合界面の硬さが異なる場合には、冷熱サイクル負荷時にセラミックス部材に加わる熱応力のバランスが崩れ、セラミックス部材に割れが生じやすくなるとの知見を得た。 In order to solve the above-mentioned problems, the inventors of the present invention conducted intensive studies and found that the shape of the copper member to be bonded to one surface and the other surface of the ceramic member, the application state of the bonding material, and the liquid phase during bonding It was found that the structure of the bonding interface between the copper plate bonded to one surface of the ceramic member and the bonding interface between the copper plate bonded to the other surface of the ceramic member differs depending on the occurrence conditions.
If the hardness of the bonding interface between the copper member bonded to one surface and the other surface of the ceramic member is different, the balance of the thermal stress applied to the ceramic member during the thermal cycle load will be lost, and the ceramic member will be damaged. It was found that cracks are likely to occur.
　本発明は、前述の知見を基になされたものであって、本発明の銅／セラミックス接合体は、銅又は銅合金からなる銅部材と、セラミックス部材とが接合されてなる銅／セラミックス接合体であって、前記セラミックス部材の一方の面および他方の面にそれぞれ前記銅部材が接合されており、前記セラミックス部材と前記銅部材との接合界面において、前記セラミックス部材側には活性金属化合物層が形成されており、前記活性金属化合物層の前記銅部材との界面から前記銅部材側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされ、前記一方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下であることを特徴としている。 The present invention has been made based on the above findings, and the copper/ceramic joined body of the present invention is a copper/ceramic joined body in which a copper member made of copper or a copper alloy and a ceramic member are joined. The copper member is bonded to one surface and the other surface of the ceramic member, respectively, and an active metal compound layer is formed on the ceramic member side at the bonding interface between the ceramic member and the copper member. and the maximum value of indentation hardness in a region from 20 μm to 50 μm from the interface with the copper member of the active metal compound layer to the copper member side is in the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less. The maximum value H1 of the indentation hardness in the copper member joined on the one surface side, and the maximum value H2 of the indentation hardness in the copper member joined on the other surface side. is 50 mgf/μm 2 or less.
　なお、本発明におけるインデンテーション硬さＨとは、バーコビッチ圧子と呼ばれる稜間角が１１４．８°以上１１５．１°以下の三角錐ダイヤモンド圧子を用いて試験荷重を５０００ｍｇｆとして負荷をかけた際の荷重―変位の相関を計測し、以下の式より算出される。
　　ｈｃ＝ｈｔ－０．７５×Ｐ／Ｓ
（ｈｔ：押し込み深さ、Ｐ：荷重、Ｓ：接触剛性（＝dP/ dh|Pmax）、ｈｃ：接触深さ）　接触面積Ａ＝２４．５６×ｈｃ２
　インデンテーション硬さＨ＝Ｐ／Ａ The indentation hardness H in the present invention refers to a test load of 5000 mgf using a triangular pyramidal diamond indenter called a Berkovich indenter having an inter-ridge angle of 114.8° or more and 115.1° or less. It is calculated from the following formula by measuring the load-displacement correlation.
hc = ht - 0.75 x P/S
(ht: push depth, P: load, S: contact stiffness (=dP/dh|Pmax), hc: contact depth) Contact area A = 24.56 x hc 2
Indentation hardness H = P/A
　本発明の銅／セラミックス接合体によれば、前記セラミックス部材の前記一方の面および前記他方の面に接合された銅部材との接合界面において、前記セラミックス部材側には活性金属化合物層が形成されており、前記活性金属化合物層の前記銅部材との界面から前記銅部材側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされているので、活性金属によってセラミックス部材と銅部材とが強固に接合されているとともに、接合界面が必要以上に硬くなることが抑制される。
　そして、前記一方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下とされているので、セラミックス部材の前記一方の面と前記他方の面にそれぞれ接合された銅部材との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス部材の割れの発生を抑制でき、冷熱サイクル信頼性に優れている。
　なお、前記一方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ２とは、それぞれが１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされている。 According to the copper/ceramic joined body of the present invention, an active metal compound layer is formed on the ceramic member side at the joint interface with the copper member joined to the one surface and the other surface of the ceramic member. and the maximum value of indentation hardness in a region from 20 μm to 50 μm from the interface with the copper member of the active metal compound layer toward the copper member is in the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less. Therefore, the ceramic member and the copper member are firmly joined by the active metal, and the joining interface is prevented from being hardened more than necessary.
Then, the maximum value H1 of the indentation hardness of the copper member joined on the one side and the maximum value H2 of the indentation hardness of the copper member joined to the other side Since the difference is 50 mgf/μm 2 or less, there is no large difference in the hardness of the bonding interface between the one surface of the ceramic member and the copper member bonded to the other surface of the ceramic member. It is possible to suppress the occurrence of cracks in the ceramic member at the time, and has excellent thermal cycle reliability.
The maximum value H1 of the indentation hardness of the copper member joined to the one surface side and the maximum value H2 of the indentation hardness of the copper member joined to the other surface side are , are within the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less.
　ここで、本発明の銅／セラミックス接合体においては、前記セラミックス部材と前記銅部材との接合界面において、前記セラミックス部材の前記一方の面側に形成された前記活性金属化合物層の厚さｔａ１、および、前記セラミックス部材の前記他方の面側に形成された前記活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされ、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされていることが好ましい。
　この場合、前記セラミックス部材の前記一方の面側に形成された前記活性金属化合物層の厚さｔａ１、および、前記セラミックス部材の前記他方の面側に形成された前記活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされているので、活性金属によってセラミックス部材と銅部材とが確実に強固に接合されているとともに、接合界面が硬くなることがさらに抑制される。
　そして、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされているので、セラミックス部材の前記一方の面と他方の面にそれぞれ接合された銅部材との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス部材の割れの発生をさらに抑制することができる。 Here, in the copper/ceramic bonded body of the present invention, thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic member at the bonding interface between the ceramic member and the copper member; Further, the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic member is in the range of 0.05 μm or more and 1.2 μm or less, and the thickness ratio ta1/ta2 is 0.7. It is preferable to be in the range of 1.4 or less.
In this case, the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic member and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic member is within the range of 0.05 μm or more and 1.2 μm or less, so that the ceramic member and the copper member are reliably and strongly bonded by the active metal, and the hardening of the bonding interface is further suppressed. .
Since the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper members respectively bonded to the one surface and the other surface of the ceramic member is increased. It is possible to further suppress the occurrence of cracks in the ceramic member under thermal cycle loads.
　また、本発明の銅／セラミックス接合体においては、前記セラミックス部材と前記銅部材との接合界面において、前記銅部材側にはＡｇ－Ｃｕ合金層が形成されており、前記セラミックス部材の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス部材の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされていることが好ましい。この場合、前記セラミックス部材の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス部材の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされているので、セラミックス部材の前記一方の面と前記他方の面にそれぞれ接合された銅部材との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス部材の割れの発生をさらに抑制することができる。 Further, in the copper/ceramic bonded body of the present invention, an Ag—Cu alloy layer is formed on the copper member side at the bonding interface between the ceramic member and the copper member, and the one side of the ceramic member The ratio tb1/tb2 between the thickness tb1 of the Ag—Cu alloy layer formed on the surface side and the thickness tb2 of the Ag—Cu alloy layer formed on the other surface side of the ceramic member is 0. .7 or more and 1.4 or less. In this case, the thickness tb1 of the Ag—Cu alloy layer formed on the one surface side of the ceramic member and the thickness of the Ag—Cu alloy layer formed on the other surface side of the ceramic member Since the ratio tb1/tb2 to tb2 is within the range of 0.7 or more and 1.4 or less, the bonding interface between the copper member bonded to the one surface and the other surface of the ceramic member, respectively A large difference in hardness does not occur, and it is possible to further suppress the occurrence of cracks in the ceramic member during thermal cycle loads.
　さらに、本発明の銅／セラミックス接合体においては、前記セラミックス部材の前記一方の面および前記他方の面にそれぞれ接合された前記銅部材の前記セラミックス部材とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされていることが好ましい。
　この場合、前記銅部材の前記セラミックス部材とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされているので、銅部材全体が硬くなっておらず、この銅部材の表面に他の部材を接合した際に、これらの他の部材との接合信頼性を向上させることができる。 Furthermore, in the copper/ceramic bonded body of the present invention, the copper member bonded to the one surface and the other surface of the ceramic member respectively has a thickness of 10 μm or more and 30 μm or less from the surface opposite to the ceramic member. It is preferable that the average value of the indentation hardness in the region is within the range of 70 mgf/μm 2 or more and 90 mgf/μm 2 or less.
In this case, since the average value of the indentation hardness in the region of 10 μm or more and 30 μm or less from the surface of the copper member opposite to the ceramic member is in the range of 70 mgf/μm 2 or more and 90 mgf/μm 2 or less. , the entire copper member is not hardened, and when other members are joined to the surface of this copper member, the reliability of joining with these other members can be improved.
　本発明の絶縁回路基板は、セラミックス基板の表面に、銅又は銅合金からなる銅板が接合されてなる絶縁回路基板であって、前記セラミックス基板の前記一方の面および前記他方の面にそれぞれ前記銅板が接合されており、前記セラミックス基板と前記銅板との接合界面において、前記セラミックス基板側には活性金属化合物層が形成されており、前記活性金属化合物層の前記銅板との界面から前記銅板側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされ、前記一方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下であることを特徴としている。 The insulated circuit board of the present invention is an insulated circuit board in which a copper plate made of copper or a copper alloy is bonded to the surface of a ceramic substrate, and the copper plate is attached to the one surface and the other surface of the ceramic substrate, respectively. is bonded, and an active metal compound layer is formed on the ceramic substrate side at the bonding interface between the ceramic substrate and the copper plate, and from the interface of the active metal compound layer with the copper plate to the copper plate side The maximum value of the indentation hardness in the region from 20 μm to 50 μm is within the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less, and the maximum indentation hardness of the copper plate bonded to the one surface side The difference between the value H1 and the maximum value H2 of the indentation hardness of the copper plate joined to the other surface is 50 mgf/μm 2 or less.
　本発明の絶縁回路基板によれば、前記セラミックス基板の前記一方の面および前記他方の面に接合された銅板との接合界面において、前記セラミックス基板側には活性金属化合物層が形成されており、前記活性金属化合物層の前記銅板との界面から前記銅板側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされているので、活性金属によってセラミックス基板と銅板とが強固に接合されているとともに、接合界面が硬くなることが抑制される。
　そして、前記一方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下とされているので、セラミックス基板の前記一方の面と前記他方の面にそれぞれ接合された銅板との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス基板の割れの発生を抑制でき、冷熱サイクル信頼性に優れている。 According to the insulated circuit board of the present invention, an active metal compound layer is formed on the ceramic substrate side at the bonding interface between the one surface and the other surface of the ceramic substrate and the copper plate bonded to the other surface, Since the maximum value of the indentation hardness in the region from 20 μm to 50 μm from the interface with the copper plate of the active metal compound layer to the copper plate side is in the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less, The active metal firmly bonds the ceramic substrate and the copper plate, and suppresses hardening of the bonding interface.
The difference between the maximum value H1 of the indentation hardness of the copper plate bonded to the one surface side and the maximum value H2 of the indentation hardness of the copper plate bonded to the other surface side is Since it is set to 50 mgf/μm 2 or less, there is no large difference in the hardness of the bonding interface between the one surface of the ceramic substrate and the copper plate bonded to the other surface of the ceramic substrate, and the ceramic substrate is subjected to a thermal cycle load. It can suppress the occurrence of cracks and has excellent thermal cycle reliability.
　ここで、本発明の絶縁回路基板においては、前記セラミックス基板と前記銅板との接合界面において、前記セラミックス基板の前記一方の面側に形成された活性金属化合物層の厚さｔａ１、および、前記セラミックス基板の前記他方の面側に形成された活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされ、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされていることが好ましい。
　この場合、前記セラミックス基板の前記一方の面側に形成された前記活性金属化合物層の厚さｔａ１、および、前記セラミックス基板の前記他方の面側に形成された前記活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされているので、活性金属によってセラミックス基板と銅板とが確実に強固に接合されているとともに、接合界面が硬くなることがさらに抑制される。
　そして、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされているので、セラミックス基板の前記一方の面と他方の面にそれぞれ接合された銅板との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス基板の割れの発生をさらに抑制することができる。 Here, in the insulated circuit board of the present invention, the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic substrate at the bonding interface between the ceramic substrate and the copper plate, and the ceramics The thickness ta2 of the active metal compound layer formed on the other surface side of the substrate is in the range of 0.05 μm or more and 1.2 μm or less, and the thickness ratio ta1/ta2 is 0.7 or more and 1.4 or less. is preferably within the range of
In this case, the thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic substrate and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic substrate However, since it is in the range of 0.05 μm to 1.2 μm, the ceramic substrate and the copper plate are reliably and strongly bonded by the active metal, and hardening of the bonding interface is further suppressed.
Since the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper plates bonded to the one surface and the other surface of the ceramic substrate , and cracking of the ceramic substrate under thermal cycle load can be further suppressed.
　また、本発明の絶縁回路基板においては、前記セラミックス基板と前記銅板との接合界面において、前記銅板側にはＡｇ－Ｃｕ合金層が形成されており、前記セラミックス部材の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス部材の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされていることが好ましい。
　この場合、前記セラミックス基板の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス基板の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされているので、セラミックス基板の前記一方の面と前記他方の面にそれぞれ接合された銅板との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス基板の割れの発生をさらに抑制することができる。 Further, in the insulated circuit board of the present invention, an Ag—Cu alloy layer is formed on the copper plate side at the bonding interface between the ceramic substrate and the copper plate, and is formed on the one surface side of the ceramic member. A ratio tb1/tb2 between the thickness tb1 of the Ag—Cu alloy layer formed on the surface of the ceramic member and the thickness tb2 of the Ag—Cu alloy layer formed on the other surface of the ceramic member is 0.7 or more and 1 .4 or less is preferable.
In this case, the thickness tb1 of the Ag—Cu alloy layer formed on the one surface side of the ceramic substrate and the thickness of the Ag—Cu alloy layer formed on the other surface side of the ceramic substrate Since the ratio tb1/tb2 to tb2 is within the range of 0.7 or more and 1.4 or less, the hardness of the bonding interface between the copper plates bonded to the one surface and the other surface of the ceramic substrate, respectively. It is possible to further suppress the occurrence of cracks in the ceramic substrate under thermal cycle loads.
　さらに、本発明の絶縁回路基板においては、前記セラミックス基板の前記一方の面および前記他方の面にそれぞれ接合された前記銅板の前記セラミックス基板とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされていることが好ましい。
　この場合、前記銅板の前記セラミックス基板とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされているので、銅板全体が硬くなっておらず、この銅板の表面に他の部材を接合した際に、これらの他の部材との接合信頼性を向上させることができる。 Further, in the insulated circuit board of the present invention, the copper plate bonded to the one surface and the other surface of the ceramic substrate, respectively, has an indentation in an area of 10 μm or more and 30 μm or less from the surface opposite to the ceramic substrate. It is preferable that the average value of the hardness is within the range of 70 mgf/μm 2 or more and 90 mgf/μm 2 or less.
In this case, since the average value of the indentation hardness in the region of 10 μm or more and 30 μm or less from the surface of the copper plate opposite to the ceramic substrate is in the range of 70 mgf/μm 2 or more and 90 mgf/μm 2 or less, The entire copper plate is not hardened, and when other members are joined to the surface of this copper plate, the reliability of joining with these other members can be improved.
　本発明によれば、厳しい冷熱サイクルを負荷した場合であっても、セラミックス部材における割れの発生を抑制でき、冷熱サイクル信頼性に優れた銅／セラミックス接合体、および、この銅／セラミックス接合体からなる絶縁回路基板を提供することができる。 According to the present invention, even when a severe thermal cycle is applied, the occurrence of cracks in the ceramic member can be suppressed, and the copper / ceramics joined body has excellent thermal cycle reliability, and the copper / ceramics joined body It is possible to provide an insulated circuit board that is
本発明の実施形態に係る絶縁回路基板を用いたパワーモジュールの概略説明図である。1 is a schematic explanatory diagram of a power module using an insulated circuit board according to an embodiment of the present invention; FIG. 本発明の実施形態に係る絶縁回路基板の回路層とセラミックス基板との接合界面の拡大説明図である。FIG. 2 is an enlarged explanatory view of a bonding interface between the circuit layer of the insulated circuit board and the ceramic substrate according to the embodiment of the present invention; 本発明の実施形態に係る絶縁回路基板の金属層とセラミックス基板との接合界面の拡大説明図である。FIG. 2 is an enlarged explanatory view of a bonding interface between a metal layer of an insulated circuit board and a ceramic substrate according to an embodiment of the present invention; 本発明の実施形態に係る絶縁回路基板の製造方法のフロー図である。1 is a flowchart of a method for manufacturing an insulated circuit board according to an embodiment of the present invention; FIG. 本発明の実施形態に係る絶縁回路基板の製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the insulation circuit board which concerns on embodiment of this invention.
　以下に、本発明の実施形態について添付した図面を参照して説明する。
　本実施形態に係る銅／セラミックス接合体は、セラミックスからなるセラミックス部材としてのセラミックス基板１１と、銅又は銅合金からなる銅部材としての銅板４２（回路層１２）および銅板４３（金属層１３）とが接合されてなる絶縁回路基板１０である。図１に、本実施形態である絶縁回路基板１０を備えたパワーモジュール１を示す。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
The copper/ceramic bonded body according to the present embodiment includes a ceramic substrate 11 as a ceramic member made of ceramics, and a copper plate 42 (circuit layer 12) and a copper plate 43 (metal layer 13) as copper members made of copper or a copper alloy. is an insulating circuit board 10 formed by bonding the . FIG. 1 shows a power module 1 having an insulated circuit board 10 according to this embodiment.
　このパワーモジュール１は、回路層１２および金属層１３が配設された絶縁回路基板１０と、回路層１２の一方の面（図１において上面）に接合層２を介して接合された半導体素子３と、金属層１３の他方側（図１において下側）に配置されたヒートシンク５と、を備えている。 This power module 1 includes an insulating circuit board 10 on which a circuit layer 12 and a metal layer 13 are arranged, and a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 via a bonding layer 2. and a heat sink 5 arranged on the other side (lower side in FIG. 1) of the metal layer 13 .
　半導体素子３は、Ｓｉ等の半導体材料で構成されている。この半導体素子３と回路層１２は、接合層２を介して接合されている。
　接合層２は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材で構成されている。 The semiconductor element 3 is made of a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded via the bonding layer 2 .
The bonding layer 2 is made of, for example, a Sn--Ag-based, Sn--In-based, or Sn--Ag--Cu-based solder material.
　ヒートシンク５は、前述の絶縁回路基板１０からの熱を放散するためのものである。このヒートシンク５は、銅又は銅合金で構成されており、本実施形態ではりん脱酸銅で構成されている。このヒートシンク５には、冷却用の流体が流れるための流路が設けられている。
　なお、本実施形態においては、ヒートシンク５と金属層１３とが、はんだ材からなるはんだ層７によって接合されている。このはんだ層７は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材で構成されている。 The heat sink 5 is for dissipating heat from the insulating circuit board 10 described above. The heat sink 5 is made of copper or a copper alloy, and is made of phosphorus-deoxidized copper in this embodiment. The heat sink 5 is provided with a channel through which cooling fluid flows.
In addition, in this embodiment, the heat sink 5 and the metal layer 13 are joined by a solder layer 7 made of a solder material. The solder layer 7 is made of, for example, a Sn--Ag-based, Sn--In-based, or Sn--Ag--Cu-based solder material.
　そして、本実施形態である絶縁回路基板１０は、図１に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面（図１において上面）に配設された回路層１２と、セラミックス基板１１の他方の面（図１において下面）に配設された金属層１３と、を備えている。 As shown in FIG. 1, the insulating circuit board 10 of the present embodiment includes a ceramic substrate 11, a circuit layer 12 provided on one surface (upper surface in FIG. 1) of the ceramic substrate 11, and a ceramic substrate. and a metal layer 13 disposed on the other surface (lower surface in FIG. 1) of the substrate 11 .
　セラミックス基板１１は、絶縁性および放熱性に優れた窒化ケイ素（Ｓｉ３Ｎ４）、窒化アルミニウム（ＡｌＮ）、アルミナ（Ａｌ２Ｏ３）等のセラミックスで構成されている。本実施形態では、セラミックス基板１１は、特に放熱性の優れた窒化アルミニウム（ＡｌＮ）で構成されている。また、セラミックス基板１１の厚さは、例えば、０．２ｍｍ以上１．５ｍｍ以下の範囲内に設定されており、本実施形態では、０．６３５ｍｍに設定されている。 The ceramics substrate 11 is made of ceramics such as silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), alumina (Al 2 O 3 ), etc., which are excellent in insulation and heat dissipation. In this embodiment, the ceramic substrate 11 is made of aluminum nitride (AlN), which has excellent heat dissipation properties. The thickness of the ceramic substrate 11 is set within a range of, for example, 0.2 mm or more and 1.5 mm or less, and is set to 0.635 mm in this embodiment.
　回路層１２は、図４に示すように、セラミックス基板１１の一方の面（図４において上面）に、銅又は銅合金からなる銅板４２が接合されることにより形成されている。
　本実施形態においては、回路層１２は、無酸素銅の圧延板を打ち抜いたものが回路パターン状に配置された状態でセラミックス基板１１に接合されることで形成されている。
　なお、回路層１２となる銅板４２の厚さは０．１ｍｍ以上２．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．６ｍｍに設定されている。 As shown in FIG. 4, the circuit layer 12 is formed by bonding a copper plate 42 made of copper or a copper alloy to one surface (upper surface in FIG. 4) of the ceramic substrate 11. As shown in FIG.
In the present embodiment, the circuit layer 12 is formed by punching out a rolled plate of oxygen-free copper, arranging it in a circuit pattern and bonding it to the ceramic substrate 11 .
The thickness of the copper plate 42 that forms the circuit layer 12 is set within a range of 0.1 mm or more and 2.0 mm or less, and is set to 0.6 mm in this embodiment.
　金属層１３は、図４に示すように、セラミックス基板１１の他方の面（図４において下面）に、銅又は銅合金からなる銅板４３が接合されることにより形成されている。
　本実施形態においては、金属層１３は、無酸素銅の圧延板がセラミックス基板１１に接合されることで形成されている。
　なお、金属層１３となる銅板４３の厚さは０．１ｍｍ以上２．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．６ｍｍに設定されている。 As shown in FIG. 4, the metal layer 13 is formed by bonding a copper plate 43 made of copper or a copper alloy to the other surface of the ceramic substrate 11 (the lower surface in FIG. 4).
In this embodiment, the metal layer 13 is formed by bonding a rolled plate of oxygen-free copper to the ceramic substrate 11 .
The thickness of the copper plate 43 that forms the metal layer 13 is set within a range of 0.1 mm or more and 2.0 mm or less, and is set to 0.6 mm in this embodiment.
　セラミックス基板１１と回路層１２との接合界面においては、図２Ａに示すように、セラミックス基板１１側から順に、活性金属化合物層２１、Ａｇ－Ｃｕ合金層２２が形成されている。
　また、回路層１２においては、活性金属化合物層２１の回路層１２との界面から回路層１２側へ２０μｍから５０μｍまでの領域Ｅ１におけるインデンテーション硬さの最大値Ｈ１が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされている。 At the bonding interface between the ceramic substrate 11 and the circuit layer 12, as shown in FIG. 2A, an active metal compound layer 21 and an Ag--Cu alloy layer 22 are formed in order from the ceramic substrate 11 side.
In the circuit layer 12, the maximum value H1 of the indentation hardness in the region E1 from 20 μm to 50 μm from the interface of the active metal compound layer 21 with the circuit layer 12 toward the circuit layer 12 is 120 mgf/μm 2 or more and 200 mgf/μm. It is within the range of μm 2 or less.
　セラミックス基板１１と金属層１３との接合界面においては、図２Ｂに示すように、セラミックス基板１１側から順に、活性金属化合物層３１、Ａｇ－Ｃｕ合金層３２が形成されている。
　また、金属層１３においては、活性金属化合物層３１の金属層１３との界面から金属層１３側へ２０μｍから５０μｍまでの領域Ｅ２におけるインデンテーション硬さの最大値Ｈ２が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされている。 At the joint interface between the ceramic substrate 11 and the metal layer 13, as shown in FIG. 2B, an active metal compound layer 31 and an Ag—Cu alloy layer 32 are formed in order from the ceramic substrate 11 side.
In the metal layer 13, the maximum value H2 of the indentation hardness in the region E2 from 20 μm to 50 μm from the interface with the metal layer 13 of the active metal compound layer 31 to the metal layer 13 side is 120 mgf/μm 2 or more and 200 mgf/μm. It is within the range of μm 2 or less.
　そして、本実施形態においては、セラミックス基板１１の一方の面に形成された回路層１２における前記インデンテーション硬さの最大値Ｈ１と、セラミックス基板１１の他方の面に形成された金属層１３における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下とされている。最大値Ｈ１と最大値Ｈ２との差の下限値は限定されないが、例えば０ｍｇｆ／μｍ２とされている。 In the present embodiment, the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness of the metal layer 13 formed on the other surface of the ceramic substrate 11 The difference from the maximum value H2 of the indentation hardness is 50 mgf/μm 2 or less. Although the lower limit of the difference between the maximum value H1 and the maximum value H2 is not limited, it is set to 0 mgf/μm2, for example.
　また、本実施形態においては、セラミックス基板１１の一方の面側に形成された活性金属化合物層２１の厚さｔａ１、および、セラミックス基板１１の他方の面側に形成された活性金属化合物層３１の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされ、これらの厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされていることが好ましい。
　なお、本実施形態では、接合材４５が活性金属としてＴｉを含有し、セラミックス基板１１が窒化アルミニウムで構成されているため、活性金属化合物層２１，３１は、窒化チタン（ＴｉＮ）で構成される。 In the present embodiment, the thickness ta1 of the active metal compound layer 21 formed on one side of the ceramic substrate 11 and the thickness ta1 of the active metal compound layer 31 formed on the other side of the ceramic substrate 11 are It is preferable that the thickness ta2 is in the range of 0.05 μm or more and 1.2 μm or less, and the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less.
In this embodiment, since the bonding material 45 contains Ti as an active metal and the ceramic substrate 11 is made of aluminum nitride, the active metal compound layers 21 and 31 are made of titanium nitride (TiN). .
　さらに、本実施形態においては、セラミックス基板１１の一方の面側に形成されたＡｇ－Ｃｕ合金層２２の厚さｔｂ１と、セラミックス基板１１の他方の面側に形成されたＡｇ－Ｃｕ合金層３２の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされていることが好ましい。また、Ａｇ－Ｃｕ合金層２２（Ａｇ－Ｃｕ合金層３２）の厚さは、１μｍ以上３０μｍ以下とすることが好ましい。 Furthermore, in the present embodiment, the thickness tb1 of the Ag--Cu alloy layer 22 formed on one side of the ceramic substrate 11 and the thickness tb1 of the Ag--Cu alloy layer 32 formed on the other side of the ceramic substrate 11 It is preferable that the ratio tb1/tb2 to the thickness tb2 of the substrate be within the range of 0.7 or more and 1.4 or less. Further, the thickness of the Ag--Cu alloy layer 22 (Ag--Cu alloy layer 32) is preferably 1 μm or more and 30 μm or less.
　また、本実施形態においては、セラミックス基板１１の一方の面に形成された回路層１２およびセラミックス基板１１の他方の面に形成された金属層１３のセラミックス基板１１とは反対側の表面から１０μｍ以上３０μｍ以下の領域Ｅ３，Ｅ４におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされていることが好ましい。 In the present embodiment, the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11 are separated by 10 μm or more from the surface opposite to the ceramic substrate 11 . It is preferable that the average value of the indentation hardness in the regions E3 and E4 of 30 μm or less is within the range of 70 mgf/μm 2 or more and 90 mgf/μm 2 or less.
　以下に、本実施形態に係る絶縁回路基板１０の製造方法について、図３および図４を参照して説明する。 A method for manufacturing the insulated circuit board 10 according to the present embodiment will be described below with reference to FIGS. 3 and 4. FIG.
（接合材配設工程Ｓ０１）
　回路層１２となる銅板４２と、金属層１３となる銅板４３とを準備する。ここで、回路層１２となる銅板４２は、回路パターン状に配設されたプレス片とされている。
　そして、回路層１２となる銅板４２および金属層１３となる銅板４３の接合面に、接合材４５を塗布し、乾燥させる。ペースト状の接合材４５の塗布厚さは、乾燥後で１０μｍ以上５０μｍ以下の範囲内とすることが好ましい。
　本実施形態では、スクリーン印刷によってペースト状の接合材４５を塗布する。 (Bonding Material Arranging Step S01)
A copper plate 42 to be the circuit layer 12 and a copper plate 43 to be the metal layer 13 are prepared. Here, the copper plate 42 to be the circuit layer 12 is a pressed piece arranged in a circuit pattern.
Then, a bonding material 45 is applied to the bonding surfaces of the copper plate 42 to be the circuit layer 12 and the copper plate 43 to be the metal layer 13 and dried. The coating thickness of the paste-like bonding material 45 is preferably within the range of 10 μm or more and 50 μm or less after drying.
In this embodiment, the paste bonding material 45 is applied by screen printing.
　接合材４５は、Ａｇと活性金属（Ｔｉ，Ｚｒ，Ｎｂ，Ｈｆ）を含有するものとされている。本実施形態では、接合材４５として、Ａｇ－Ｔｉ系ろう材（Ａｇ－Ｃｕ－Ｔｉ系ろう材）を用いている。なお、Ａｇ－Ｔｉ系ろう材（Ａｇ－Ｃｕ－Ｔｉ系ろう材）としては、例えば、Ｃｕを０ｍａｓｓ％以上３２ｍａｓｓ％以下の範囲内、活性金属であるＴｉを０．５ｍａｓｓ％以上２０ｍａｓｓ％以下の範囲で含み、残部がＡｇ及び不可避不純物とされた組成のものを用いることが好ましい。 The bonding material 45 contains Ag and active metals (Ti, Zr, Nb, Hf). In this embodiment, as the bonding material 45, an Ag--Ti based brazing material (Ag--Cu--Ti based brazing material) is used. The Ag--Ti-based brazing material (Ag--Cu--Ti-based brazing material) contains, for example, Cu in the range of 0 mass% or more and 32 mass% or less, and Ti, which is an active metal, in the range of 0.5 mass% or more and 20 mass% or less. It is preferable to use a composition having a composition that is included within the range and that the balance is Ag and unavoidable impurities.
　ここで、ペースト状の接合材４５に含まれるＡｇ粉の比表面積（ＢＥＴ値）を調整することにより、活性金属化合物層２１，３１の回路層１２および金属層１３との界面から回路層１２および金属層１３側へ２０μｍから５０μｍまでの領域Ｅ１，Ｅ２におけるインデンテーション硬さの最大値Ｈ１，Ｈ２を制御する。
　すなわち、Ａｇ粉の比表面積が小さいとペースト状の接合材４５の焼結性が高くなり、後述する加熱工程Ｓ０３において液相が発生し易くなり、活性金属の拡散が促進され、接合界面における前記インデンテーション硬さの最大値が大きくなる。一方、Ａｇ粉の比表面積が大きいとペースト状の接合材４５の焼結性が低くなり、後述する加熱工程Ｓ０３において液相が発生し難くなり、活性金属の拡散が抑制され、接合界面における前記インデンテーション硬さの最大値が小さくなる。
　Ａｇ粉の比表面積の下限は、０．１５ｍ２／ｇ以上とすることが好ましく、０．２５ｍ２／ｇ以上とすることがさらに好ましく、０．４０ｍ２／ｇ以上とすることがより好ましい。また、Ａｇ粉の比表面積の上限は、１．４０ｍ２／ｇ以下とすることが好ましく、１．００ｍ２／ｇ以下とすることがさらに好ましく、０．７５ｍ２／ｇ以下とすることがより好ましい。
　なお、ペースト状の接合材４５に含まれるＡｇ粉の粒径は、Ｄ１０が０．７μｍ以上３．５μｍ以下、かつ、Ｄ１００が４．５μｍ以上２３μｍ以下の範囲内とすることが好ましい。 Here, by adjusting the specific surface area (BET value) of the Ag powder contained in the paste-like bonding material 45, the active metal compound layers 21 and 31 are exposed to the circuit layer 12 and the metal layer 13 from the interface with the circuit layer 12 and the metal layer 13. The maximum values H1 and H2 of the indentation hardness in the regions E1 and E2 from 20 μm to 50 μm toward the metal layer 13 are controlled.
That is, when the specific surface area of the Ag powder is small, the sinterability of the paste-like bonding material 45 is increased, and a liquid phase is likely to occur in the heating step S03 described later, promoting diffusion of the active metal, and increasing the The maximum value of indentation hardness increases. On the other hand, when the specific surface area of the Ag powder is large, the sinterability of the paste-like bonding material 45 becomes low, making it difficult for the liquid phase to occur in the heating step S03 described later, suppressing the diffusion of the active metal, and suppressing the diffusion of the active metal. The maximum value of indentation hardness is reduced.
The lower limit of the specific surface area of Ag powder is preferably 0.15 m 2 /g or more, more preferably 0.25 m 2 /g or more, and more preferably 0.40 m 2 /g or more. The upper limit of the specific surface area of the Ag powder is preferably 1.40 m 2 /g or less, more preferably 1.00 m 2 /g or less, and more preferably 0.75 m 2 /g or less. preferable.
The particle size of the Ag powder contained in the paste-like bonding material 45 is preferably in the range of D10 from 0.7 μm to 3.5 μm and D100 from 4.5 μm to 23 μm.
（積層工程Ｓ０２）
　次に、セラミックス基板１１の一方の面（図４において上面）に、接合材４５を介して回路層１２となる銅板４２を積層するとともに、セラミックス基板１１の他方の面（図４において下面）に、接合材４５を介して金属層１３となる銅板４３を積層する。 (Lamination step S02)
Next, a copper plate 42 to be the circuit layer 12 is laminated on one surface (upper surface in FIG. 4) of the ceramic substrate 11 with a bonding material 45 interposed therebetween, and on the other surface (lower surface in FIG. 4) of the ceramic substrate 11 , a copper plate 43 to be the metal layer 13 is laminated with a bonding material 45 interposed therebetween.
（加熱工程Ｓ０３）
　次に、銅板４２とセラミックス基板１１と銅板４３とを加圧した状態で、真空雰囲気の加熱炉内で加熱し、接合材４５を溶融する。ここでの加圧した状態は、例えば、銅板４２、４３を、それぞれセラミックス基板１１側に向けて押圧した状態を意味している。
　ここで、加熱工程Ｓ０３における加熱温度は、８００℃以上８５０℃以下の範囲内とすることが好ましい。また、７８０℃から加熱温度までの昇温工程および加熱温度での保持工程における温度積分値の合計は、７℃・ｈ以上１２０℃・ｈ以下の範囲内とすることが好ましい。
　また、加熱工程Ｓ０３における加圧荷重は、０．０２９ＭＰａ以上２．９４ＭＰａ以下の範囲内とすることが好ましい。
　さらに、加熱工程Ｓ０３における真空度は、１×１０－６Ｐａ以上５×１０－２Ｐａ以下の範囲内とすることが好ましい。 (Heating step S03)
Next, the copper plate 42, the ceramic substrate 11, and the copper plate 43 are heated in a heating furnace in a vacuum atmosphere to melt the bonding material 45 while being pressurized. The pressurized state here means, for example, a state in which the copper plates 42 and 43 are pressed toward the ceramic substrate 11 side.
Here, the heating temperature in the heating step S03 is preferably within the range of 800° C. or higher and 850° C. or lower. Further, the total temperature integral value in the heating process from 780° C. to the heating temperature and the holding process at the heating temperature is preferably within the range of 7° C.·h or more and 120° C.·h or less.
Moreover, the pressure load in the heating step S03 is preferably in the range of 0.029 MPa or more and 2.94 MPa or less.
Furthermore, the degree of vacuum in the heating step S03 is preferably in the range of 1×10 −6 Pa or more and 5×10 −2 Pa or less.
（冷却工程Ｓ０４）
　そして、加熱工程Ｓ０３の後、冷却を行うことにより、溶融した接合材４５を凝固させて、回路層１２となる銅板４２とセラミックス基板１１、セラミックス基板１１と金属層１３となる銅板４３とを接合する。
　なお、この冷却工程Ｓ０４における冷却速度は、２℃／ｍｉｎ以上２０℃／ｍｉｎ以下の範囲内とすることが好ましい。なお、ここでの冷却速度は加熱温度からＡｇ－Ｃｕ共晶温度である７８０℃までの冷却速度である。 (Cooling step S04)
After the heating step S03, cooling is performed to solidify the molten bonding material 45, thereby bonding the copper plate 42 that will be the circuit layer 12 and the ceramic substrate 11, and the ceramic substrate 11 and the copper plate 43 that will be the metal layer 13. do.
The cooling rate in this cooling step S04 is preferably within the range of 2° C./min or more and 20° C./min or less. The cooling rate here is the cooling rate from the heating temperature to 780° C., which is the Ag—Cu eutectic temperature.
　ここで、回路層１２（銅板４２）側と金属層１３（銅板４３）側とで、冷却速度を調整することにより、活性金属化合物層２１，３１の回路層１２および金属層１３との界面から回路層１２および金属層１３側へ２０μｍから５０μｍまでの領域Ｅ１，Ｅ２におけるインデンテーション硬さの最大値Ｈ１，Ｈ２を制御する。
　すなわち、冷却速度が速い場合には、活性金属の拡散が早期に停止し、接合界面における前記インデンテーション硬さの最大値が小さくなる。一方、冷却速度が遅い場合には、活性金属の拡散が長期に継続し、接合界面における前記インデンテーション硬さの最大値が大きくなる。 Here, by adjusting the cooling rate on the circuit layer 12 (copper plate 42) side and the metal layer 13 (copper plate 43) side, Maximum values H1 and H2 of indentation hardness in regions E1 and E2 from 20 μm to 50 μm toward the circuit layer 12 and metal layer 13 are controlled.
That is, when the cooling rate is high, diffusion of the active metal stops early, and the maximum value of the indentation hardness at the bonding interface becomes small. On the other hand, when the cooling rate is slow, diffusion of the active metal continues for a long time, and the maximum value of the indentation hardness at the bonding interface increases.
　なお、冷却工程Ｓ０４において、回路層１２（銅板４２）側と金属層１３（銅板４３）側のいずれか一方に、不活性ガスを流すことにより、回路層１２（銅板４２）側と金属層１３（銅板４３）側とで冷却速度を調整することが可能となる。
　また、加熱工程Ｓ０３および冷却工程Ｓ０４において、ＳＰＳ（放電プラズマ焼結）法を適用した場合には、回路層１２（銅板４２）側の電極と、金属層１３（銅板４３）側の電極とで、冷却水の流量を調整することにより、回路層１２（銅板４２）側と金属層１３（銅板４３）側とで冷却速度を調整することが可能となる。 In the cooling step S04, by flowing an inert gas to either the circuit layer 12 (copper plate 42) side or the metal layer 13 (copper plate 43) side, the circuit layer 12 (copper plate 42) side and the metal layer 13 side are cooled. It becomes possible to adjust the cooling rate on the (copper plate 43) side.
In addition, in the heating step S03 and the cooling step S04, when the SPS (discharge plasma sintering) method is applied, the electrode on the circuit layer 12 (copper plate 42) side and the electrode on the metal layer 13 (copper plate 43) side By adjusting the flow rate of the cooling water, it is possible to adjust the cooling rate on the circuit layer 12 (copper plate 42) side and the metal layer 13 (copper plate 43) side.
　以上のように、接合材配設工程Ｓ０１、積層工程Ｓ０２、加熱工程Ｓ０３、冷却工程Ｓ０４によって、本実施形態である絶縁回路基板１０が製造されることになる。 As described above, the insulated circuit board 10 of the present embodiment is manufactured through the bonding material disposing step S01, the laminating step S02, the heating step S03, and the cooling step S04.
（ヒートシンク接合工程Ｓ０５）
　次に、絶縁回路基板１０の金属層１３の他方の面側にヒートシンク５を接合する。
　絶縁回路基板１０とヒートシンク５とを、はんだ材を介して積層して加熱炉に装入し、はんだ層７を介して絶縁回路基板１０とヒートシンク５とをはんだ接合する。 (Heat-sink bonding step S05)
Next, the heat sink 5 is bonded to the other side of the metal layer 13 of the insulated circuit board 10 .
The insulating circuit board 10 and the heat sink 5 are laminated with a solder material interposed therebetween and placed in a heating furnace.
（半導体素子接合工程Ｓ０６）
　次に、絶縁回路基板１０の回路層１２の一方の面に、半導体素子３をはんだ付けにより接合する。
　前述の工程により、図１に示すパワーモジュール１が製出される。 (Semiconductor element bonding step S06)
Next, the semiconductor element 3 is soldered to one surface of the circuit layer 12 of the insulating circuit board 10 .
The power module 1 shown in FIG. 1 is produced by the above-described steps.
　以上のような構成とされた本実施形態の絶縁回路基板１０（銅／セラミックス接合体）によれば、セラミックス基板１１の一方の面に形成された回路層１２および他方の面に形成された金属層１３との接合界面において、セラミックス基板１１側には活性金属化合物層２１，３１が形成されており、活性金属化合物層２１，３１の回路層１２および金属層１３との界面から回路層１２および金属層１３側へ２０μｍから５０μｍまでの領域Ｅ１，Ｅ２におけるインデンテーション硬さの最大値Ｈ１，Ｈ２が１２０ｍｇｆ／μｍ２以上とされているので、接合材４５の活性金属が十分に反応しており、セラミックス基板１１と回路層１２および金属層１３とが強固に接合されている。
　一方、活性金属化合物層２１，３１の回路層１２および金属層１３との界面から回路層１２および金属層１３側へ２０μｍから５０μｍまでの領域Ｅ１，Ｅ２におけるインデンテーション硬さの最大値Ｈ１，Ｈ２が２００ｍｇｆ／μｍ２以下とされているので、接合界面が必要以上に硬くなることを抑制でき、冷熱サイクル信頼性を向上させることができる。 According to the insulating circuit board 10 (copper/ceramic bonded body) of the present embodiment configured as described above, the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer formed on the other surface Active metal compound layers 21 and 31 are formed on the ceramic substrate 11 side at the bonding interface with the layer 13, and from the interface between the active metal compound layers 21 and 31 and the circuit layer 12 and the metal layer 13, the circuit layer 12 and the metal layer 13 are formed. Since the maximum values H1 and H2 of the indentation hardness in the regions E1 and E2 from 20 μm to 50 μm toward the metal layer 13 side are 120 mgf/μm 2 or more, the active metal of the bonding material 45 reacts sufficiently. , the ceramic substrate 11, the circuit layer 12 and the metal layer 13 are firmly bonded.
On the other hand, maximum values H1 and H2 of indentation hardness in regions E1 and E2 from 20 μm to 50 μm from the interfaces of the active metal compound layers 21 and 31 with the circuit layer 12 and the metal layer 13 toward the circuit layer 12 and the metal layer 13. is set to 200 mgf/μm 2 or less, it is possible to suppress the bonding interface from becoming harder than necessary, and to improve the thermal cycle reliability.
　なお、セラミックス基板１１と回路層１２および金属層１３とをさらに強固に接合するためには、接合界面の前記インデンテーション硬さの最大値Ｈ１，Ｈ２を１２５ｍｇｆ／μｍ２以上とすることが好ましく、１３０ｍｇｆ／μｍ２以上とすることがさらに好ましい。
　また、接合界面が必要以上に硬くなることをさらに抑制するためには、接合界面の前記インデンテーション硬さの最大値Ｈ１，Ｈ２を１８０ｍｇｆ／μｍ２以下とすることが好ましく、１５０ｍｇｆ／μｍ２以下とすることがより好ましい。 In order to bond the ceramic substrate 11 to the circuit layer 12 and the metal layer 13 more firmly, the maximum values H1 and H2 of the indentation hardness of the bonding interface are preferably 125 mgf/μm 2 or more. More preferably, it is 130 mgf/μm 2 or more.
Further, in order to further suppress the bonding interface from becoming unnecessarily hard, the maximum values H1 and H2 of the indentation hardness of the bonding interface are preferably 180 mgf/μm 2 or less, and 150 mgf/μm 2 or less. is more preferable.
　そして、本実施形態においては、セラミックス基板１１の一方の面に形成された回路層１２における前記インデンテーション硬さの最大値Ｈ１と、セラミックス基板１１の他方の面に形成された金属層１３における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下とされているので、セラミックス基板１１の一方の面に形成された回路層１２とセラミックス基板１１の他方の面に形成された金属層１３との接合界面の硬さに大きな差が生じておらず、冷熱サイクル負荷時におけるセラミックス基板１１の割れの発生を抑制でき、冷熱サイクル信頼性に優れている。 In the present embodiment, the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness of the metal layer 13 formed on the other surface of the ceramic substrate 11 Since the difference from the maximum value H2 of the indentation hardness is 50 mgf/μm 2 or less, the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal formed on the other surface of the ceramic substrate 11 There is no large difference in the hardness of the bonding interface with the layer 13, cracking of the ceramic substrate 11 can be suppressed under a thermal cycle load, and the thermal cycle reliability is excellent.
　なお、冷熱サイクル信頼性をさらに向上させるためには、セラミックス基板１１の一方の面に形成された回路層１２における前記インデンテーション硬さの最大値Ｈ１と、セラミックス基板１１の他方の面に形成された金属層１３における前記インデンテーション硬さの最大値Ｈ２との差を４０ｍｇｆ／μｍ２以下とすることが好ましく、３０ｍｇｆ／μｍ２以下とすることがより好ましい。 In order to further improve the thermal cycle reliability, the maximum value H1 of the indentation hardness of the circuit layer 12 formed on one surface of the ceramic substrate 11 and the maximum value H1 of the indentation hardness formed on the other surface of the ceramic substrate 11 The difference from the maximum value H2 of the indentation hardness of the metal layer 13 is preferably 40 mgf/μm 2 or less, more preferably 30 mgf/μm 2 or less.
　また、本実施形態において、セラミックス基板１１の一方の面に形成された回路層１２側に形成された活性金属化合物層２１の厚さｔａ１、および、セラミックス基板１１の他方の面に形成された金属層１３側に形成された活性金属化合物層３１の厚さｔａ２が、０．０５μｍ以上とされている場合には、接合材４５の活性金属がセラミックス基板１１と十分に反応しており、セラミックス基板１１と回路層１２および金属層１３とがさらに強固に接合されている。
　一方、活性金属化合物層２１の厚さｔａ１および活性金属化合物層３１の厚さｔａ２が１．２μｍ以下とされている場合には、接合界面が必要以上に硬くなることを抑制でき、冷熱サイクル信頼性をさらに向上させることができる。 Further, in the present embodiment, the thickness ta1 of the active metal compound layer 21 formed on one side of the ceramic substrate 11 on the side of the circuit layer 12, and the thickness ta1 of the metal layer 21 formed on the other side of the ceramic substrate 11 When the thickness ta2 of the active metal compound layer 31 formed on the layer 13 side is 0.05 μm or more, the active metal of the bonding material 45 sufficiently reacts with the ceramic substrate 11, and the ceramic substrate 11, the circuit layer 12 and the metal layer 13 are joined more firmly.
On the other hand, when the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 are set to 1.2 μm or less, it is possible to suppress the bonding interface from becoming unnecessarily hard, thereby improving the reliability of the thermal cycle. It is possible to further improve the performance.
　なお、セラミックス基板１１と回路層１２および金属層１３とをさらに強固に接合するためには、活性金属化合物層２１の厚さｔａ１および活性金属化合物層３１の厚さｔａ２を０．０８μｍ以上とすることが好ましく、０．１５μｍ以上とすることがさらに好ましい。
　また、接合界面が必要以上に硬くなることをさらに抑制するためには、活性金属化合物層２１の厚さｔａ１および活性金属化合物層３１の厚さｔａ２を１．０μｍ以下とすることが好ましく、０．６μｍ以下とすることがより好ましい。 In order to bond the ceramic substrate 11 to the circuit layer 12 and the metal layer 13 more firmly, the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 are set to 0.08 μm or more. is preferred, and 0.15 μm or more is more preferred.
Further, in order to further suppress the bonding interface from becoming unnecessarily hard, it is preferable to set the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 to 1.0 μm or less. 0.6 μm or less is more preferable.
　さらに、本実施形態において、活性金属化合物層２１の厚さｔａ１および活性金属化合物層３１の厚さｔａ２の厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされている場合には、セラミックス基板１１の一方の面に形成された回路層１２とセラミックス基板１１の他方の面に形成された金属層１３との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス基板１１の割れの発生をさらに抑制することができる。
　なお、冷熱サイクル負荷時におけるセラミックス基板１１の割れの発生をさらに抑制するためには、活性金属化合物層２１の厚さｔａ１および活性金属化合物層３１の厚さｔａ２の厚さ比ｔａ１／ｔａ２を０．８以上１．２以下の範囲内とすることがさらに好ましく、０．９以上１．１以下の範囲内とすることがより好ましい。 Further, in the present embodiment, when the thickness ratio ta1/ta2 of the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 is in the range of 0.7 or more and 1.4 or less. Therefore, there is no large difference in the hardness of the bonding interface between the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11. It is possible to further suppress the occurrence of cracks in the ceramic substrate 11 in .
In order to further suppress the occurrence of cracks in the ceramic substrate 11 under thermal cycle load, the thickness ratio ta1/ta2 of the thickness ta1 of the active metal compound layer 21 and the thickness ta2 of the active metal compound layer 31 should be set to 0. 0.8 or more and 1.2 or less, and more preferably 0.9 or more and 1.1 or less.
　また、本実施形態において、セラミックス基板１１の一方の面側に形成されたＡｇ－Ｃｕ合金層２２の厚さｔｂ１と、セラミックス基板１１の他方の面側に形成されたＡｇ－Ｃｕ合金層３２の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされている場合には、セラミックス基板１１の一方の面に形成された回路層１２とセラミックス基板１１の他方の面に形成された金属層１３との接合界面の硬さに大きな差が生じず、冷熱サイクル負荷時におけるセラミックス基板１１の割れの発生をさらに抑制することができる。
　なお、冷熱サイクル負荷時におけるセラミックス基板１１の割れの発生をさらに抑制するためには、Ａｇ－Ｃｕ合金層２２の厚さｔｂ１とＡｇ－Ｃｕ合金層３２の厚さｔｂ２との厚さ比ｔｂ１／ｔｂ２を０．８以上１．２以下の範囲内とすることがさらに好ましく、０．９以上１．１以下の範囲内とすることがより好ましい。 Further, in the present embodiment, the thickness tb1 of the Ag—Cu alloy layer 22 formed on one side of the ceramic substrate 11 and the thickness tb1 of the Ag—Cu alloy layer 32 formed on the other side of the ceramic substrate 11 are When the ratio tb1/tb2 to the thickness tb2 is in the range of 0.7 or more and 1.4 or less, the circuit layer 12 formed on one surface of the ceramics substrate 11 and the other surface of the ceramics substrate 11 There is no large difference in the hardness of the joint interface with the metal layer 13 formed on the surface of the ceramic substrate 11, and the occurrence of cracks in the ceramic substrate 11 under thermal cycle load can be further suppressed.
In order to further suppress the occurrence of cracks in the ceramic substrate 11 under thermal cycle load, the thickness ratio tb1/ tb2 is more preferably in the range of 0.8 or more and 1.2 or less, and more preferably in the range of 0.9 or more and 1.1 or less.
　さらに、本実施形態において、セラミックス基板１１の一方の面に形成された回路層１２およびセラミックス基板１１の他方の面に形成された金属層１３のセラミックス基板１１とは反対側の表面から１０μｍ以上３０μｍ以下の領域Ｅ３，Ｅ４におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされている場合には、回路層１２全体および金属層１３全体が硬くなっておらず、回路層１２の表面に接合した半導体素子３、および、金属層１３の表面に接合したヒートシンク５との接合信頼性を向上させることができる。 Furthermore, in the present embodiment, the circuit layer 12 formed on one surface of the ceramic substrate 11 and the metal layer 13 formed on the other surface of the ceramic substrate 11 are separated from the surface opposite to the ceramic substrate 11 by 10 μm or more and 30 μm from the surface opposite to the ceramic substrate 11 . When the average value of the indentation hardness in the following regions E3 and E4 is within the range of 70 mgf /μm2 or more and 90 mgf/μm2 or less, the circuit layer 12 as a whole and the metal layer 13 as a whole are hardened. Moreover, the reliability of bonding between the semiconductor element 3 bonded to the surface of the circuit layer 12 and the heat sink 5 bonded to the surface of the metal layer 13 can be improved.
　以上、本発明の実施形態について説明したが、本発明はこれに限定されることはなく、その発明の技術的思想を逸脱しない範囲で適宜変更可能である。
　例えば、本実施形態では、絶縁回路基板に半導体素子を搭載してパワーモジュールを構成するものとして説明したが、これに限定されることはない。例えば、絶縁回路基板の回路層にＬＥＤ素子を搭載してＬＥＤモジュールを構成してもよいし、絶縁回路基板の回路層に熱電素子を搭載して熱電モジュールを構成してもよい。 Although the embodiment of the present invention has been described above, the present invention is not limited to this, and can be modified as appropriate without departing from the technical idea of the invention.
For example, in the present embodiment, a power module is configured by mounting a semiconductor element on an insulated circuit board, but the present invention is not limited to this. For example, an LED module may be configured by mounting an LED element on the circuit layer of the insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on the circuit layer of the insulating circuit board.
　また、本実施形態の絶縁回路基板では、セラミックス基板として、窒化アルミニウム（ＡｌＮ）で構成されたものを例に挙げて説明したが、これに限定されることはなく、アルミナ（Ａｌ２Ｏ３）、窒化ケイ素（Ｓｉ３Ｎ４）等の他のセラミックス基板を用いたものであってもよい。 In addition, in the insulating circuit board of the present embodiment , the ceramic substrate is made of aluminum nitride ( AlN). , other ceramic substrates such as silicon nitride (Si 3 N 4 ) may be used.
　さらに、本実施形態では、接合材に含まれる活性金属としてＴｉを例に挙げて説明したが、これに限定されることはなく、Ｔｉ，Ｚｒ，Ｈｆ，Ｎｂから選択される１種又は２種以上の活性金属を含んでいればよい。なお、これらの活性金属は、水素化物として含まれていてもよい。 Furthermore, in the present embodiment, Ti was used as an example of the active metal contained in the bonding material. It suffices if it contains the above active metals. These active metals may be contained as hydrides.
　以下に、本発明の効果を確認すべく行った確認実験の結果について説明する。 The results of confirmation experiments conducted to confirm the effects of the present invention are described below.
　まず、表１記載のセラミックス基板（４０ｍｍ×４０ｍｍ）を準備した。なお、厚さは、ＡｌＮおよびＡｌ２Ｏ３は０．６３５ｍｍ、Ｓｉ３Ｎ４は０．３２ｍｍとした。
　また、回路層となる銅板として、無酸素銅からなり、表１に示す厚さの３７ｍｍ×１８ｍｍの銅片を２つ準備した。さらに、金属層となる銅板として、無酸素銅からなり、表１に示す厚さの３７ｍｍ×３７ｍｍの銅板を準備した。 First, a ceramic substrate (40 mm×40 mm) shown in Table 1 was prepared. The thickness of AlN and Al 2 O 3 was 0.635 mm, and the thickness of Si 3 N 4 was 0.32 mm.
In addition, two copper pieces of 37 mm×18 mm having a thickness shown in Table 1 and made of oxygen-free copper were prepared as a copper plate serving as a circuit layer. Furthermore, a copper plate made of oxygen-free copper and having a thickness of 37 mm×37 mm as shown in Table 1 was prepared as a copper plate serving as a metal layer.
　回路層となる銅板に、表１に示すＢＥＴ値のＡｇ粉を含む接合材を、乾燥後の目標厚さが３０μｍとなるよう塗布した。
　金属層となる銅板に、表１に示すＢＥＴ値のＡｇ粉を含む接合材を、乾燥後の目標厚さが３０μｍとなるよう塗布した。
　なお、接合材はペースト材を用い、Ａｇ，Ｃｕ，活性金属の量は表１の通りとした。また、Ａｇ粉のＢＥＴ値（比表面積）はＱＵＡＮＴＡＣＨＲＲＯＭＥ社製ＡＵＴＯＳＯＲＢ－１を用い、前処理として１５０℃で３０分加熱の真空脱気を行い、Ｎ２吸着、液体窒素７７Ｋ、ＢＥＴ多点法で測定した。 A bonding material containing Ag powder having a BET value shown in Table 1 was applied to a copper plate serving as a circuit layer so that the target thickness after drying was 30 μm.
A bonding material containing Ag powder having a BET value shown in Table 1 was applied to a copper plate serving as a metal layer so as to have a target thickness of 30 μm after drying.
A paste material was used as the bonding material, and the amounts of Ag, Cu, and active metal were as shown in Table 1. In addition, the BET value (specific surface area) of the Ag powder was measured by using AUTOSORB-1 manufactured by QUANTACHRROME, vacuum deaeration by heating at 150 ° C. for 30 minutes as pretreatment, N 2 adsorption, liquid nitrogen 77 K, BET multipoint method. It was measured.
　セラミックス基板の一方の面に、回路層となる銅板を積層した。このとき、２つの銅片を、間隔１ｍｍを開けて配置した。
　また、セラミックス基板の他方の面に、金属層となる銅板を積層した。 A copper plate serving as a circuit layer was laminated on one surface of the ceramic substrate. At this time, two copper pieces were arranged with an interval of 1 mm.
A copper plate serving as a metal layer was laminated on the other surface of the ceramic substrate.
　この積層体を、積層方向に加圧した状態で加熱し、接合材を溶融した。このとき、加圧荷重を０．１９６ＭＰａとし，温度積分値は表２の通りとした。
　そして、加熱した積層体を冷却することにより、回路層となる銅板とセラミックス基板と金属層となる金属板を接合し、絶縁回路基板（銅／セラミックス接合体）を得た。
　なお、実施例では、ＳＰＳ（放電プラズマ焼結）法により接合を行い、回路層側の電極と、金属層側の電極とで、冷却水の流量を調整することにより、表２に示す冷却速度となるよう調整した。 This laminate was heated while being pressed in the lamination direction to melt the bonding material. At this time, the pressure load was set to 0.196 MPa, and the temperature integral value was set as shown in Table 2.
Then, by cooling the heated laminate, the copper plate serving as the circuit layer, the ceramic substrate, and the metal plate serving as the metal layer were bonded to obtain an insulated circuit substrate (copper/ceramic bonded body).
In the examples, the bonding was performed by the SPS (discharge plasma sintering) method, and the cooling rate shown in Table 2 was obtained by adjusting the flow rate of the cooling water between the electrode on the circuit layer side and the electrode on the metal layer side. was adjusted to be
　得られた絶縁回路基板（銅／セラミックス接合体）について、インデンテーション硬さ、活性金属化合物層、Ａｇ－Ｃｕ合金層、冷熱サイクル信頼性を、以下のようにして評価した。 The indentation hardness, active metal compound layer, Ag-Cu alloy layer, and thermal cycle reliability of the resulting insulated circuit board (copper/ceramic bonded body) were evaluated as follows.
（インデンテーション硬さ）
　得られた絶縁回路基板（銅／セラミックス接合体）を積層方向に切断し、セラミックス基板と回路層および金属層の接合界面において、上述した方法にて活性金属化合物層の回路層および金属層との界面から回路層および金属層側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さをそれぞれ５箇所で測定及び算出し、その最大値を求めた。
　また、回路層および金属層のセラミックス基板とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さをそれぞれ５箇所で測定及び算出し、その平均値を算出した。 (indentation hardness)
The resulting insulated circuit board (copper/ceramic bonded body) was cut in the lamination direction, and the active metal compound layer was bonded to the circuit layer and metal layer at the bonding interface between the ceramic board and the circuit layer and metal layer by the method described above. The indentation hardness in the regions from 20 μm to 50 μm from the interface to the circuit layer side and the metal layer side was measured and calculated at five points, and the maximum value was obtained.
Further, the indentation hardness in the regions of 10 μm or more and 30 μm or less from the surface of the circuit layer and the metal layer on the side opposite to the ceramic substrate was measured and calculated at five points, and the average value was calculated.
（活性金属化合物層）
　回路層とセラミックス基板との接合界面、および、セラミックス基板と金属層との接合界面の断面を、走査型電子顕微鏡（カールツァイスＮＴＳ社製ＵＬＴＲＡ５５、加速電圧１．８ｋＶ）を用いて倍率３００００倍で測定し、エネルギー分散型Ｘ線分析法により、Ｎ、Ｏ及び活性金属元素の元素マッピングを取得した。活性金属元素とＮまたはＯが同一領域に存在する場合に活性金属化合物層が有ると判断した。
　それぞれ５視野で観察を行い、活性金属元素とＮまたはＯが同一領域に存在する範囲の面積を測定した幅で割ったものの平均値を「活性金属化合物層の厚さ」とした。 (Active metal compound layer)
A cross-section of the bonding interface between the circuit layer and the ceramic substrate and the bonding interface between the ceramic substrate and the metal layer was examined using a scanning electron microscope (ULTRA55 manufactured by Carl Zeiss NTS, acceleration voltage 1.8 kV) at a magnification of 30,000. The elemental mapping of N, O and active metal elements was obtained by energy dispersive X-ray spectroscopy. It was determined that there was an active metal compound layer when the active metal element and N or O were present in the same region.
Five fields of view were observed, and the average value obtained by dividing the area of the range where the active metal element and N or O existed in the same region by the measured width was taken as the "thickness of the active metal compound layer."
（Ａｇ－Ｃｕ合金層）
　回路層とセラミックス基板との接合界面、および、セラミックス基板と金属層との接合界面の断面を、ＥＰＭＡ装置を用いて、５視野でライン分析を行った。
　そして、Ａｇ＋Ｃｕ＋活性金属＝１００質量％としたとき、Ａｇ濃度が１５質量％以上である領域をＡｇ－Ｃｕ合金層とし、その厚さを測定した。それぞれ５視野での測定値の平均をＡｇ－Ｃｕ合金層の厚さとして表に記載した。 (Ag—Cu alloy layer)
A cross-section of the bonding interface between the circuit layer and the ceramic substrate and the bonding interface between the ceramic substrate and the metal layer were subjected to line analysis in five fields of view using an EPMA device.
Then, when Ag+Cu+active metal=100% by mass, a region having an Ag concentration of 15% by mass or more was defined as an Ag—Cu alloy layer, and its thickness was measured. The average of the measured values in each of the five fields of view is shown in the table as the thickness of the Ag--Cu alloy layer.
（冷熱サイクル信頼性）
　上述の絶縁回路基板を、セラミックス基板の材質に応じて、下記の冷熱サイクルを負荷し、ＳＡＴ検査によりセラミックス割れの有無を判定した。評価結果を表２に示す。表２のセラミックス割れの発生回数は、セラミックス割れが発生するまでに要した冷熱サイクル数を意味している。
　ＡｌＮ，Ａｌ２Ｏ３の場合：－４０℃×５ｍｉｎ、１５０℃×５ｍｉｎの負荷を１サイクルとし、５００サイクルまで５０サイクル毎にＳＡＴ検査。
　Ｓｉ３Ｎ４の場合：－４０℃×５ｍｉｎ、１５０℃×５ｍｉｎの負荷を１サイクルとし、２０００サイクルまで２００サイクル毎にＳＡＴ検査。 (Cold/heat cycle reliability)
Depending on the material of the ceramic substrate, the insulating circuit substrate described above was subjected to the following cooling and heating cycles, and the presence or absence of cracks in the ceramics was determined by SAT inspection. Table 2 shows the evaluation results. The number of occurrences of ceramic cracks in Table 2 means the number of thermal cycles required until ceramic cracks occur.
In the case of AlN and Al 2 O 3 : One cycle is a load of −40° C.×5 min and 150° C.×5 min, and SAT inspection is performed every 50 cycles up to 500 cycles.
In the case of Si 3 N 4 : One cycle is a load of −40° C.×5 min and 150° C.×5 min, and SAT inspection is performed every 200 cycles up to 2000 cycles.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　セラミックス基板としてＡｌＮを用いた本発明例１－３および比較例１，２を比較すると、回路層側のインデンテーション硬さＨ１および金属層側のインデンテーション硬さＨ２の最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされるとともに、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が５０ｍｇｆ／μｍ２以下とされた本発明例１－３は、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が６１ｍｇｆ／μｍ２とされた比較例１、および、金属層側のインデンテーション硬さＨ２の最大値が２１７ｍｇｆ／μｍ２とされた比較例２に比べて、冷熱サイクル信頼性に優れていることが確認される。 Comparing Inventive Examples 1-3 and Comparative Examples 1 and 2 using AlN as a ceramic substrate, the maximum values of the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side were 120 mgf/μm 2 . Inventive Example 1-3 in which the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side was set to 50 mgf /μm2 or less. Comparative Example 1 in which the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side was 61 mgf/μm 2 , and the maximum value of the indentation hardness H2 on the metal layer side was It is confirmed that the cooling/heating cycle reliability is superior to that of Comparative Example 2 with 217 mgf/μm 2 .
　セラミックス基板としてＳｉ３Ｎ４を用いた本発明例４－６および比較例３，４を比較すると、回路層側のインデンテーション硬さＨ１および金属層側のインデンテーション硬さＨ２の最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされるとともに、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が５０ｍｇｆ／μｍ２以下とされた本発明例４－６は、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が６２ｍｇｆ／μｍ２とされた比較例３、および、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が５５ｍｇｆ／μｍ２とされた比較例４に比べて、冷熱サイクル信頼性に優れていることが確認される。 Comparing Inventive Examples 4-6 and Comparative Examples 3 and 4 using Si 3 N 4 as the ceramic substrate, the maximum values of the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side were 120 mgf. /μm 2 or more and 200 mgf/μm 2 or less, and the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side is 50 mgf/μm 2 or less. 4-6 are Comparative Example 3 in which the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side was 62 mgf/μm 2 , and the indentation hardness H1 on the circuit layer side Compared to Comparative Example 4 in which the difference in indentation hardness H2 on the metal layer side was 55 mgf/μm 2 , it is confirmed that the thermal cycle reliability is superior.
　セラミックス基板としてＡｌ２Ｏ３を用いた本発明例７，８および比較例５を比較すると、回路層側のインデンテーション硬さＨ１および金属層側のインデンテーション硬さＨ２の最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされるとともに、回路層側のインデンテーション硬さＨ１と金属層側のインデンテーション硬さＨ２の差が５０ｍｇｆ／μｍ２以下とされた本発明例７，８は、金属層側のインデンテーション硬さＨ２の最大値が９４ｍｇｆ／μｍ２とされた比較例５に比べて、冷熱サイクル信頼性に優れていることが確認される。 When comparing Inventive Examples 7 and 8 using Al 2 O 3 as the ceramic substrate and Comparative Example 5, the maximum values of the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side were 120 mgf/μm. Inventive Example 7, in which the difference between the indentation hardness H1 on the circuit layer side and the indentation hardness H2 on the metal layer side was set to 50 mgf /μm2 or less. 8 is superior in thermal cycle reliability compared to Comparative Example 5 in which the maximum value of the indentation hardness H2 on the metal layer side was 94 mgf/μm 2 .
　以上の確認実験の結果から、本発明例によれば、厳しい冷熱サイクルを負荷した場合であっても、セラミックス基板（セラミックス部材）における割れの発生を抑制でき、冷熱サイクル信頼性に優れた絶縁回路基板（銅／セラミックス接合体）を提供可能であることが確認された。 From the results of the above confirmation experiments, according to the example of the present invention, it is possible to suppress the occurrence of cracks in the ceramic substrate (ceramic member) even when a severe thermal cycle is applied, and the insulation circuit has excellent thermal cycle reliability. It was confirmed that the substrate (copper/ceramic joint) can be provided.
　本発明によれば、厳しい冷熱サイクルを負荷した場合であっても、セラミックス部材における割れの発生を抑制でき、冷熱サイクル信頼性に優れた銅／セラミックス接合体、および、この銅／セラミックス接合体からなる絶縁回路基板を提供することができる。 According to the present invention, even when a severe thermal cycle is applied, the occurrence of cracks in the ceramic member can be suppressed, and the copper / ceramics joined body has excellent thermal cycle reliability, and the copper / ceramics joined body It is possible to provide an insulated circuit board that is
　１　　パワーモジュール
　１０　　絶縁回路基板（銅／セラミックス接合体）
　１１　　セラミックス基板（セラミックス部材）
　１２　　回路層（銅部材）
　１３　　金属層（銅部材）
　２１，３１　　活性金属化合物層
　２２，３２　　Ａｇ－Ｃｕ合金層 1 power module 10 insulated circuit board (copper/ceramic joint)
11 Ceramic substrate (ceramic member)
12 circuit layer (copper member)
13 metal layer (copper member)
21,31 Active metal compound layer 22,32 Ag-Cu alloy layer

Claims (8)

  1. 　銅又は銅合金からなる銅部材と、セラミックス部材とが接合されてなる銅／セラミックス接合体であって、
    　前記セラミックス部材の一方の面および他方の面にそれぞれ前記銅部材が接合されており、
    　前記セラミックス部材と前記銅部材との接合界面において、前記セラミックス部材側には活性金属化合物層が形成されており、
    　前記活性金属化合物層の前記銅部材との界面から前記銅部材側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされ、
    　前記一方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅部材における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下であることを特徴とする銅／セラミックス接合体。     A copper/ceramic joined body obtained by joining a copper member made of copper or a copper alloy and a ceramic member,
    The copper member is bonded to one surface and the other surface of the ceramic member, respectively,
    An active metal compound layer is formed on the ceramic member side at the bonding interface between the ceramic member and the copper member,
    The maximum value of indentation hardness in a region from 20 μm to 50 μm from the interface with the copper member of the active metal compound layer to the copper member side is in the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less,
    The difference between the maximum value H1 of the indentation hardness of the copper member bonded to the one surface side and the maximum value H2 of the indentation hardness of the copper member bonded to the other surface side is A copper/ceramic bonded body characterized by having a density of 50 mgf/μm 2 or less.
  2. 　前記セラミックス部材の前記一方の面側に形成された前記活性金属化合物層の厚さｔａ１、および、前記セラミックス部材の前記他方の面側に形成された前記活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされ、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされていることを特徴とする請求項１に記載の銅／セラミックス接合体。 The thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic member and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic member are 0 The copper/ceramic bonding according to claim 1, wherein the thickness is in the range of 0.05 µm or more and 1.2 µm or less, and the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less. body.
  3. 　前記セラミックス部材と前記銅部材との接合界面において、前記銅部材側にはＡｇ－Ｃｕ合金層が形成されており、
    　前記セラミックス部材の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス部材の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされていることを特徴とする請求項１または請求項２に記載の銅／セラミックス接合体。     At the bonding interface between the ceramic member and the copper member, an Ag—Cu alloy layer is formed on the copper member side,
    thickness tb1 of the Ag—Cu alloy layer formed on the one surface side of the ceramic member and thickness tb2 of the Ag—Cu alloy layer formed on the other surface side of the ceramic member 3. The copper/ceramic joined body according to claim 1, wherein the ratio tb1/tb2 is in the range of 0.7 to 1.4.
  4. 　前記セラミックス部材の前記一方の面および前記他方の面にそれぞれ接合された前記銅部材の前記セラミックス部材とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされていることを特徴とする請求項１から請求項３のいずれか一項に記載の銅／セラミックス接合体。 An average value of indentation hardness in a region of 10 μm or more and 30 μm or less from the surface of the copper member bonded to the one surface and the other surface of the ceramic member, which is opposite to the surface of the ceramic member, is 70 mgf/μm 4. The copper/ceramic joined body according to any one of claims 1 to 3, characterized in that it is in the range of 2 or more and 90 mgf/μm 2 or less.
  5. 　セラミックス基板の表面に、銅又は銅合金からなる銅板が接合されてなる絶縁回路基板であって、
    　前記セラミックス基板の前記一方の面および前記他方の面にそれぞれ前記銅板が接合されており、
    　前記セラミックス基板と前記銅板との接合界面において、前記セラミックス基板側には活性金属化合物層が形成されており、
    　前記活性金属化合物層の前記銅板との界面から前記銅板側へ２０μｍから５０μｍまでの領域におけるインデンテーション硬さの最大値が１２０ｍｇｆ／μｍ２以上２００ｍｇｆ／μｍ２以下の範囲内とされ、
    　前記一方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ１と、前記他方の面側に接合された前記銅板における前記インデンテーション硬さの最大値Ｈ２との差が５０ｍｇｆ／μｍ２以下であることを特徴とする絶縁回路基板。     An insulated circuit board formed by bonding a copper plate made of copper or a copper alloy to the surface of a ceramic substrate,
    The copper plate is bonded to each of the one surface and the other surface of the ceramic substrate,
    At the bonding interface between the ceramic substrate and the copper plate, an active metal compound layer is formed on the ceramic substrate side,
    The maximum value of the indentation hardness in a region from 20 μm to 50 μm from the interface with the copper plate of the active metal compound layer to the copper plate side is in the range of 120 mgf/μm 2 or more and 200 mgf/μm 2 or less,
    The difference between the maximum value H1 of the indentation hardness of the copper plate bonded to the one surface side and the maximum value H2 of the indentation hardness of the copper plate bonded to the other surface side is 50 mgf/ An insulated circuit board characterized by having a thickness of μm 2 or less.
  6. 　前記セラミックス基板の前記一方の面側に形成された活性金属化合物層の厚さｔａ１、および、前記セラミックス基板の前記他方の面側に形成された活性金属化合物層の厚さｔａ２が、０．０５μｍ以上１．２μｍ以下の範囲内とされ、厚さ比ｔａ１／ｔａ２が０．７以上１．４以下の範囲内とされていることを特徴とする請求項５に記載の絶縁回路基板。 The thickness ta1 of the active metal compound layer formed on the one surface side of the ceramic substrate and the thickness ta2 of the active metal compound layer formed on the other surface side of the ceramic substrate are 0.05 μm. 6. The insulated circuit board according to claim 5, wherein the thickness is in the range of 1.2 [mu]m or more, and the thickness ratio ta1/ta2 is in the range of 0.7 or more and 1.4 or less.
  7. 　前記セラミックス基板と前記銅板との接合界面において、前記銅板側にはＡｇ－Ｃｕ合金層が形成されており、
    　前記セラミックス基板の前記一方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ１と、前記セラミックス基板の前記他方の面側に形成された前記Ａｇ－Ｃｕ合金層の厚さｔｂ２との比ｔｂ１／ｔｂ２が、０．７以上１．４以下の範囲内とされていることを特徴とする請求項５または請求項６に記載の絶縁回路基板。     At the bonding interface between the ceramic substrate and the copper plate, an Ag—Cu alloy layer is formed on the copper plate side,
    thickness tb1 of the Ag--Cu alloy layer formed on the one surface side of the ceramic substrate and thickness tb2 of the Ag--Cu alloy layer formed on the other surface side of the ceramic substrate 7. The insulated circuit board according to claim 5, wherein the ratio tb1/tb2 is in the range of 0.7 to 1.4.
  8. 　前記セラミックス基板の前記一方の面および前記他方の面にそれぞれ接合された前記銅板の前記セラミックス基板とは反対側の表面から１０μｍ以上３０μｍ以下の領域におけるインデンテーション硬さの平均値が７０ｍｇｆ／μｍ２以上９０ｍｇｆ／μｍ２以下の範囲内とされていることを特徴とする請求項５から請求項７のいずれか一項に記載の絶縁回路基板。 An average value of indentation hardness in a region of 10 μm or more and 30 μm or less from the surface of the copper plate bonded to the one surface and the other surface of the ceramic substrate opposite to the ceramic substrate is 70 mgf/μm 2 8. The insulating circuit board according to any one of claims 5 to 7, wherein the thickness is in the range of 90 mgf/μm 2 or less.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207587A (en) * 2002-12-26 2004-07-22 Dowa Mining Co Ltd Metal-ceramics bonding substrate and its manufacturing method
JP2014090144A (en) * 2012-10-31 2014-05-15 Denki Kagaku Kogyo Kk Ceramic circuit board, and method of manufacturing the same
WO2017056360A1 (en) * 2015-09-28 2017-04-06 株式会社 東芝 Circuit substrate and semiconductor device
JP2018008869A (en) * 2016-06-30 2018-01-18 三菱マテリアル株式会社 Copper-ceramic bonded body and insulation circuit board
WO2018021472A1 (en) * 2016-07-28 2018-02-01 株式会社 東芝 Bonding body, circuit board and semiconductor device
JP2019033131A (en) * 2017-08-04 2019-02-28 デンカ株式会社 Ceramic circuit board
WO2021033421A1 (en) * 2019-08-21 2021-02-25 三菱マテリアル株式会社 Copper/ceramic assembly, insulated circuit board, method for producing copper/ceramic assembly, and method for producing insulated circuit board
WO2021124923A1 (en) * 2019-12-19 2021-06-24 三菱マテリアル株式会社 Copper/ceramic joined body and insulated circuit board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207587A (en) * 2002-12-26 2004-07-22 Dowa Mining Co Ltd Metal-ceramics bonding substrate and its manufacturing method
JP2014090144A (en) * 2012-10-31 2014-05-15 Denki Kagaku Kogyo Kk Ceramic circuit board, and method of manufacturing the same
WO2017056360A1 (en) * 2015-09-28 2017-04-06 株式会社 東芝 Circuit substrate and semiconductor device
JP2018008869A (en) * 2016-06-30 2018-01-18 三菱マテリアル株式会社 Copper-ceramic bonded body and insulation circuit board
WO2018021472A1 (en) * 2016-07-28 2018-02-01 株式会社 東芝 Bonding body, circuit board and semiconductor device
JP2019033131A (en) * 2017-08-04 2019-02-28 デンカ株式会社 Ceramic circuit board
WO2021033421A1 (en) * 2019-08-21 2021-02-25 三菱マテリアル株式会社 Copper/ceramic assembly, insulated circuit board, method for producing copper/ceramic assembly, and method for producing insulated circuit board
WO2021124923A1 (en) * 2019-12-19 2021-06-24 三菱マテリアル株式会社 Copper/ceramic joined body and insulated circuit board

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