WO2022218075A1 - Uci的级联确定方法、装置、终端及网络侧设备 - Google Patents

Uci的级联确定方法、装置、终端及网络侧设备 Download PDF

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Publication number
WO2022218075A1
WO2022218075A1 PCT/CN2022/080613 CN2022080613W WO2022218075A1 WO 2022218075 A1 WO2022218075 A1 WO 2022218075A1 CN 2022080613 W CN2022080613 W CN 2022080613W WO 2022218075 A1 WO2022218075 A1 WO 2022218075A1
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Prior art keywords
uci
order
priority
bits
bit concatenation
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PCT/CN2022/080613
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English (en)
French (fr)
Inventor
沈姝伶
高雪娟
司倩倩
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大唐移动通信设备有限公司
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Priority claimed from CN202110412070.8A external-priority patent/CN115225198B/zh
Application filed by 大唐移动通信设备有限公司 filed Critical 大唐移动通信设备有限公司
Priority to EP22787305.6A priority Critical patent/EP4325752A4/en
Priority to US18/555,249 priority patent/US20240196404A1/en
Publication of WO2022218075A1 publication Critical patent/WO2022218075A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0028—Formatting
    • H04L1/0031—Multiple signaling transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/20—Control channels or signalling for resource management
    • H04W72/21—Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0027—Scheduling of signalling, e.g. occurrence thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/1607—Details of the supervisory signal
    • H04L1/1671—Details of the supervisory signal the supervisory signal being transmitted together with control information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1854—Scheduling and prioritising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1861—Physical mapping arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/50—Allocation or scheduling criteria for wireless resources
    • H04W72/56—Allocation or scheduling criteria for wireless resources based on priority criteria
    • H04W72/566—Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient

Definitions

  • the present disclosure relates to the field of communication technologies, and in particular, to a method, apparatus, terminal, and network-side device for determining a UCI cascade.
  • Uplink Control Information includes Hybrid Automatic Repeat reQuest-ACKnowledge (HARQ-ACK), Scheduling Request (SR) and Channel Situation Information (CSI), etc. .
  • HARQ-ACK Hybrid Automatic Repeat reQuest-ACKnowledge
  • SR Scheduling Request
  • CSI Channel Situation Information
  • UCI is carried on the Physical Uplink Control Channel (PUCCH) for transmission.
  • PUCCH Physical Uplink Control Channel
  • PUSCH Physical Uplink Shared Channel
  • the UCI will also be piggybacked. transmitted on PUSCH.
  • the bit concatenation order corresponding to different UCI types with the same priority is as follows: when HARQ-ACK and SR are multiplexed for transmission on PUCCH, the UCI bit concatenation order is HARQ-ACK first and then SR; When multiplexing, SR and CSI are transmitted on PUCCH, the UCI bit concatenation order is HARQ-ACK first, then SR and last CSI; if at least one CSI is divided into two CSI parts for transmission, CSI part1 is concatenated in HARQ-ACK and SR After joint coding, CSI part2 is independently coded.
  • the purpose of the embodiments of the present disclosure is to provide a method, apparatus, terminal, and network-side device for determining concatenation, so as to solve the problem that the concatenation order of UCI bits with different priorities cannot be determined in the related art.
  • an embodiment of the present disclosure provides a method for determining the cascade of uplink control information UCI, and the method includes:
  • the terminal determines, according to the first rule, the bit concatenation sequence of UCIs of different priorities jointly coded on the first uplink channel; wherein the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is preferentially determined according to the UCI type, wherein the bit concatenation order of UCI is determined according to the priority order within the same UCI type;
  • the terminal sends the UCI concatenated according to the bit concatenation sequence on the first uplink channel.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the method also includes:
  • the terminal determines the bit mapping sequence of the UCI according to the second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the embodiment of the present disclosure also provides a method for determining the cascade of uplink control information UCI, the method includes:
  • the network side device receives the UCI jointly coded with different priorities on the first uplink channel
  • the network side device determines the bit concatenation sequence of UCIs with different priorities according to the first rule; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the method also includes:
  • the network side device determines the bit mapping order of the UCI according to the second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • An embodiment of the present disclosure further provides a terminal, including a memory, a transceiver, and a processor:
  • a memory for storing a computer program
  • a transceiver for sending and receiving data under the control of the processor
  • a processor for reading the computer program in the memory and performing the following operations:
  • the bit concatenation sequence of the uplink control information UCI of different priorities jointly encoded on the first uplink channel is determined; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is preferentially determined according to the UCI type, wherein the bit concatenation order of UCI is determined according to the priority order within the same UCI type;
  • the UCI concatenated according to the bit concatenation sequence is sent on the first uplink channel.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the processor is further configured to read the computer program in the memory and perform the following operations:
  • the bit mapping order of the UCI is determined; wherein, the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • An embodiment of the present disclosure further provides an apparatus for cascading determination of uplink control information UCI, which is applied to a terminal, and the apparatus includes:
  • a first determining unit configured to determine, according to a first rule, a bit concatenation sequence of UCIs of different priorities jointly coded on the first uplink channel; wherein the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • a sending unit configured to send the UCI concatenated according to the bit concatenation sequence on the first uplink channel.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the device also includes:
  • a third determining unit configured to determine the bit mapping order of the UCI according to a second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • An embodiment of the present disclosure further provides a network-side device, including a memory, a transceiver, and a processor:
  • a memory for storing a computer program
  • a transceiver for sending and receiving data under the control of the processor
  • a processor for reading the computer program in the memory and performing the following operations:
  • the bit concatenation sequence of UCIs with different priorities is determined; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the processor is further configured to read the computer program in the memory and perform the following operations:
  • the bit mapping order of the UCI is determined; wherein, the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the embodiment of the present disclosure also provides a cascade determination device for uplink control information UCI, which is applied to network side equipment, including:
  • a receiving unit configured to receive the UCI jointly coded with different priorities on the first uplink channel
  • the second determining unit is used to determine the bit concatenation order of UCIs of different priorities according to the first rule; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the first rule when the first rule is to determine the bit concatenation order of UCI according to priority order, the first rule further includes: determining the bit concatenation order of UCI according to UCI type within the same priority.
  • the priority of the UCI includes: high priority and low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the device also includes:
  • a fourth determining unit configured to determine the bit mapping order of the UCI according to a second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • Embodiments of the present disclosure further provide a processor-readable storage medium, where a computer program is stored in the processor-readable storage medium, and the computer program is used to cause the processor to execute the above method.
  • the terminal when the terminal transmits UCI with different priorities on the first uplink channel by using joint coding, the terminal preferentially determines the bit level of UCI according to the priority order Alternatively, the terminal determines the UCI bit concatenation order according to the UCI type, and the UCI bit concatenation order is determined according to the priority order within the same UCI type, thereby ensuring that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • FIG. 1 shows a block diagram of a wireless communication system to which an embodiment of the present disclosure can be applied
  • FIG. 2 shows one of the schematic diagrams of the steps of the cascade determination method provided by the embodiment of the present disclosure
  • FIG. 3 shows the second schematic diagram of the steps of the cascade determination method provided by the embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a terminal provided by an embodiment of the present disclosure.
  • FIG. 5 shows one of the schematic structural diagrams of a cascade determination device provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a network side device provided by an embodiment of the present disclosure.
  • FIG. 7 shows the second schematic structural diagram of the cascade determination device provided by the embodiment of the present disclosure.
  • FIG. 1 shows a block diagram of a wireless communication system to which an embodiment of the present disclosure can be applied.
  • the wireless communication system includes a terminal 11 and a network-side device 12 .
  • the terminal 11 may also be referred to as a terminal device or a user terminal (User Equipment, UE). It should be noted that, the embodiment of the present disclosure does not limit the specific type of the terminal 11 .
  • the network side device 12 may be a base station or a core network. It should be noted that, in the embodiments of the present disclosure, only a base station in an NR system is used as an example, but the specific type of the base station is not limited.
  • the term "and/or" describes the association relationship of associated objects, and indicates that there can be three kinds of relationships. For example, A and/or B can indicate that A exists alone, A and B exist at the same time, and B exists alone these three situations.
  • the character “/” generally indicates that the associated objects are an "or" relationship.
  • the term “plurality” refers to two or more than two, and other quantifiers are similar.
  • the applicable system may be a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, a wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) general packet Wireless service (general packet radio service, GPRS) system, long term evolution (long term evolution, LTE) system, LTE frequency division duplex (frequency division duplex, FDD) system, LTE time division duplex (time division duplex, TDD) system, Long term evolution advanced (LTE-A) system, universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX) system, 5G New Radio (New Radio, NR) system, etc.
  • GSM global system of mobile communication
  • CDMA code division multiple access
  • WCDMA wideband Code Division Multiple Access
  • General packet Wireless service general packet Radio service
  • GPRS general packet Wireless service
  • LTE long term evolution
  • LTE long term evolution
  • FDD frequency division duplex
  • TDD time division duplex
  • LTE-A Long term evolution advanced
  • the terminal involved in the embodiments of the present disclosure may be a device that provides voice and/or data connectivity to a user, a handheld device with a wireless connection function, or other processing device connected to a wireless modem.
  • the name of the terminal device may be different.
  • the terminal device may be called user equipment (User Equipment, UE).
  • Wireless terminal equipment can communicate with one or more core networks (Core Network, CN) via a radio access network (Radio Access Network, RAN).
  • RAN Radio Access Network
  • "telephone) and computers with mobile terminal equipment eg portable, pocket-sized, hand-held, computer-built or vehicle-mounted mobile devices, which exchange language and/or data with the radio access network.
  • a wireless terminal device may also be referred to as a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, an access point , a remote terminal device (remote terminal), an access terminal device (access terminal), a user terminal device (user terminal), a user agent (user agent), and a user device (user device), which are not limited in the embodiments of the present disclosure.
  • the network side device involved in the embodiments of the present disclosure may be a base station, and the base station may include a plurality of cells providing services for the terminal.
  • the base station may also be called an access point, or may be a device in the access network that communicates with wireless terminal equipment through one or more sectors on the air interface, or other names.
  • the network device can be used to exchange received air frames with Internet Protocol (IP) packets, and act as a router between the wireless terminal device and the rest of the access network, which can include the Internet. Protocol (IP) communication network.
  • IP Internet Protocol
  • the network devices may also coordinate attribute management for the air interface.
  • the network device involved in the embodiments of the present disclosure may be a network device (Base Transceiver Station, BTS) in the Global System for Mobile Communications (GSM) or Code Division Multiple Access (Code Division Multiple Access, CDMA). ), it can also be a network device (NodeB) in Wide-band Code Division Multiple Access (WCDMA), or it can be an evolved network device in a long term evolution (LTE) system (evolutional Node B, eNB or e-NodeB), 5G base station (gNB) in 5G network architecture (next generation system), or Home evolved Node B (HeNB), relay node (relay node) , a home base station (femto), a pico base station (pico), etc., which are not limited in the embodiments of the present disclosure.
  • a network device may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be geographically separated.
  • One or more antennas can be used between the network side device and the terminal to perform multiple input multiple output (Multi Input Multi Output, MIMO) transmission, and the MIMO transmission can be single user MIMO (Single User MIMO, SU-MIMO) or multi-user MIMO (Multiple User MIMO, MU-MIMO).
  • MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, or diversity transmission, precoding transmission, or beamforming transmission.
  • an embodiment of the present disclosure provides a method for cascading determination of uplink control information UCI, and the method includes:
  • Step 201 the terminal determines, according to a first rule, the bit concatenation sequence of UCIs of different priorities jointly coded on the first uplink channel; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is preferentially determined according to the UCI type, wherein the bit concatenation order of UCI is determined according to the priority order within the same UCI type;
  • Step 202 the terminal sends the UCI concatenated according to the bit concatenation sequence on the first uplink channel.
  • the UCI type includes HARQ-ACK, SR, and CSI. It should be noted that the jointly encoded UCI on the first uplink channel includes at least HARQ-ACK.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the first rule when the first rule is to determine the bit concatenation order of UCI preferentially according to the priority order, the first rule further includes: within the same priority, the UCI type is determined according to the UCI type. Bit concatenation order.
  • the priority of the UCI includes: a high priority (also referred to as a first priority) and a low priority (also referred to as a second priority);
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • determining the bit concatenation order of the UCI according to the UCI type includes: determining the bit concatenation order of the UCI according to the existing concatenation order of the UCI type. For example, when HARQ-ACK and SR are multiplexed and transmitted on PUCCH, the bit concatenation order of UCI is HARQ-ACK first and then SR. When HARQ-ACK, SR and CSI are multiplexed and transmitted on PUCCH, the UCI bit concatenation order is HARQ-ACK first, then SR and last CSI. If at least one CSI is divided into two CSI parts for transmission, the CSI part 1 level Jointly coded after HARQ-ACK and SR, CSI part2 is coded independently.
  • the method further includes:
  • the terminal determines the bit mapping sequence of the UCI according to the second rule; wherein the second rule includes:
  • the high-order bits of the UCI are first mapped, and then the low-order bits of the UCI are mapped; it can also be called that the UCI adopts the high-order bits first and then the low-order bits;
  • the low-order bits of the UCI are mapped first, and then the high-order bits of the UCI are mapped; it may also be called that the UCI adopts the low-order bits first and then the high-order bits.
  • the terminal when the terminal uses joint coding to transmit UCI with different priorities on the first uplink channel, the terminal preferentially determines the bit concatenation order of UCI according to the priority order, or the terminal preferentially determines the bit concatenation order of UCI according to the UCI type, Within the same UCI type, the bit concatenation sequence of UCI is determined according to the priority order; thus, it is ensured that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • Example 1 Determine the bit concatenation order of UCI in priority order
  • the terminal multiplexes and transmits HARQ-ACK, SR and CSI with two priorities on the PUCCH.
  • the terminals are sorted by priority. In this example, if the terminal concatenates the UCI bits of low priority after the UCI bits of high priority.
  • the terminal concatenates the UCI bits of low priority after the UCI bits of high priority.
  • the terminal concatenates the UCI bits of low priority after the UCI bits of high priority.
  • HARQ-ACK, SR, and CSI are sequentially concatenated according to the UCI type.
  • the final determined UCI bit concatenation sequence is HP HARQ-ACK, HP SR, HP CSI, LP HARQ-ACK, LP SR, LP CSI.
  • the finally determined UCI bit concatenation sequence is LP HARQ-ACK, LP SR, LP CSI, HP HARQ-ACK, HP SR, HP CSI.
  • the bit concatenation sequence is HP HARQ-ACK, HP SR, LP HARQ-ACK, LP SR or LP HARQ-ACK, LP SR, HP HARQ-ACK, HP SR.
  • the bit concatenation sequence is HP HARQ-ACK, LP HARQ-ACK or LP HARQ-ACK, HP HARQ-ACK.
  • the UCI adopts high-order bit mapping first and then low-order bit mapping, that is, multiple UCI bit sequences with different priorities are cascaded and combined from left to right.
  • each of HARQ-ACK is 3 bits
  • each of SR is 1 bit
  • each of CSI is 5 bits
  • the concatenated UCI bit sequence is a 0 , a 1 , a 2 , . . . , a 17 .
  • a 0 , a 1 , a 2 map the bit sequence of HP HARQ-ACK
  • a 3 maps the bit sequence of HP SR
  • a 4 ,...,a 8 maps the bit sequence of HP CSI
  • a 9 , a 10 a 11 map
  • the bit sequence of LP HARQ-ACK, a 12 maps the bit sequence of LP SR, and a 13 , . . . , a 17 maps the bit sequence of LP CSI.
  • UCI adopts the mapping of low-order bits first and then high-order bits, that is, multiple UCI bit sequences with different priorities are cascaded and combined from right to left.
  • a 2 , a 1 , a 0 map the bit sequence of HP HARQ-ACK
  • a 3 maps the bit sequence of HP SR
  • a 8 maps the bit sequence of HP CSI
  • a 11 maps the bit sequence of HP SR
  • a 10 maps the bit sequence of HP CSI
  • a 9 The bit sequence of LP HARQ-ACK is mapped, a 12 is mapped to the bit sequence of LP SR, and a 17 , . . . , a 13 is mapped to the bit sequence of LP CSI.
  • the sequence of the concatenated mapping of other UCI bits in this embodiment is the same, and is not enumerated here.
  • Example 2 The bit concatenation order of UCI is determined preferentially according to UCI type
  • the terminal multiplexes and transmits HARQ-ACK, SR and CSI with two priorities on the PUCCH.
  • Terminals are first sorted by UCI type, and within the same UCI type, terminals are sorted by priority. In this example, if the terminal concatenates the low-priority UCI bits after the high-priority UCI bits, the final determined UCI bit concatenation order is HP HARQ-ACK, LP HARQ-ACK, HP SR, LP SR, HP CSI, LP CSI.
  • the final UCI bit concatenation order is LP HARQ-ACK, HP HARQ-ACK, LP SR, HP SR, LP CSI, HP CSI.
  • the bit concatenation order is HP HARQ-ACK, LP HARQ-ACK, HP SR, LP SR or LP HARQ-ACK, HP HARQ-ACK, LP SR, HP SR.
  • the terminal multiplexes and transmits HARQ-ACK with two priorities on the PUCCH.
  • the bit concatenation order is HP HARQ-ACK, LP HARQ-ACK or LP HARQ-ACK, HP HARQ-ACK.
  • the UCI adopts high-order bit mapping first and then low-order bit mapping, that is, multiple UCI bit sequences with different priorities are cascaded and combined from left to right.
  • each of HARQ-ACK is 3 bits
  • each of SR is 1 bit
  • each of CSI is 5 bits
  • the concatenated UCI bit sequence is a 0 , a 1 , a 2 , . . . , a 17 .
  • a 0 , a 1 , a 2 map the bit sequence of HP HARQ-ACK, a 3 , a 4 , a 5 map the bit sequence of LP HARQ-ACK, a 6 map the bit sequence of HP SR, a 7 map the bit sequence of LP SR
  • the sequences, a 8 ,...,a 12 map the bit sequence of HP CSI, and a 13 ,...,a 17 map the bit sequence of LP CSI.
  • UCI adopts the mapping of low-order bits first and then high-order bits, that is, multiple UCI bit sequences with different priorities are cascaded and combined from right to left.
  • a 2 , a 1 , a 0 map the bit sequence of HP HARQ-ACK
  • a 5 , a 4 , a 3 map the bit sequence of LP HARQ-ACK
  • a 6 maps the bit sequence of HP SR
  • a 7 maps the bit sequence of LP SR
  • the bit sequence, a 12 ,...,a 8 maps the bit sequence of HP CSI
  • a 17 ,...,a 13 maps the bit sequence of LP CSI.
  • the other UCI bit concatenated mapping sequences in this example are the same, and will not be enumerated here.
  • the terminal multiplexes one or more UCIs with two priorities on the PUSCH.
  • UCI includes at least: HARQ-ACK.
  • the manner of determining the UCI bit concatenation sequence and the mapping sequence is the same as that of Example 1 and Example 2.
  • an embodiment of the present disclosure further provides a method for cascading determination of uplink control information UCI, and the method includes:
  • Step 301 the network side device receives the UCI jointly coded with different priorities on the first uplink channel
  • Step 302 the network side device determines the bit concatenation sequence of UCIs with different priorities according to a first rule; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the UCI type includes HARQ-ACK, SR, and CSI. It should be noted that the jointly encoded UCI on the first uplink channel includes at least HARQ-ACK.
  • the bit concatenation sequence of the UCI is determined according to the first rule.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the first rule when the first rule is to determine the bit concatenation order of UCI preferentially according to the priority order, the first rule further includes: within the same priority, the UCI type is determined according to the UCI type. Bit concatenation order.
  • the priority of the UCI includes: a high priority (also referred to as a first priority) and a low priority (also referred to as a second priority);
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • determining the bit concatenation order of the UCI according to the UCI type includes: determining the bit concatenation order of the UCI according to the existing concatenation order of the UCI type. For example, when HARQ-ACK and SR are multiplexed and transmitted on PUCCH, the bit concatenation order of UCI is HARQ-ACK first and then SR. When HARQ-ACK, SR and CSI are multiplexed and transmitted on PUCCH, the UCI bit concatenation order is HARQ-ACK first, then SR and last CSI. If at least one CSI is divided into two CSI parts for transmission, the CSI part 1 level Jointly coded after HARQ-ACK and SR, CSI part2 is coded independently.
  • the method further includes:
  • the network side device determines the bit mapping order of the UCI according to the second rule; wherein the second rule includes:
  • the high-order bits of the UCI are first mapped, and then the low-order bits of the UCI are mapped; it can also be called that the UCI adopts the high-order bits first and then the low-order bits;
  • the low-order bits of the UCI are mapped first, and then the high-order bits of the UCI are mapped; it may also be called that the UCI adopts the low-order bits first and then the high-order bits.
  • the network-side device when the network-side device receives multiple UCIs jointly coded with different priorities on the first uplink channel, the network-side device preferentially determines the bit concatenation sequence of UCI according to the priority order, or the network-side device preferentially determines the UCI type according to the UCI type.
  • the bit concatenation sequence of UCI the same UCI type internally determines the bit concatenation sequence of UCI according to the priority order, so as to ensure that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • an embodiment of the present disclosure further provides a terminal, including a memory 420, a transceiver 410, and a processor 400:
  • the memory 420 is used to store computer programs; the transceiver 410 is used to send and receive data under the control of the processor 400; the processor 400 is used to read the computer program in the memory 420 and perform the following operations:
  • the bit concatenation sequence of the uplink control information UCI of different priorities jointly encoded on the first uplink channel is determined; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is preferentially determined according to the UCI type, wherein the bit concatenation order of UCI is determined according to the priority order within the same UCI type;
  • the UCI concatenated according to the bit concatenation sequence is sent on the first uplink channel.
  • the first rule further includes: determining the bit level of UCI according to the UCI type within the same priority connection order.
  • the priority of the UCI includes: a high priority and a low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the processor 400 is further configured to read the computer program in the memory and perform the following operations:
  • the bit mapping order of the UCI is determined; wherein, the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 400 and various circuits of memory represented by memory 420 linked together.
  • the bus architecture may also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 410 may be a number of elements, including a transmitter and a receiver, providing means for communicating with various other devices over transmission media including wireless channels, wired channels, fiber optic cables, and the like Transmission medium.
  • the user interface 430 may also be an interface capable of externally connecting the required equipment, and the connected equipment includes but is not limited to a keypad, a display, a speaker, a microphone, a joystick, and the like.
  • the processor 400 is responsible for managing the bus architecture and general processing, and the memory 420 may store data used by the processor 400 in performing operations.
  • the processor 400 may be a central processor (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA) or a complex programmable logic device ( Complex Programmable Logic Device, CPLD), the processor can also adopt a multi-core architecture.
  • CPU central processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • CPLD Complex Programmable Logic Device
  • the processor is configured to execute any one of the methods provided by the embodiments of the present disclosure according to the obtained executable instructions by invoking the computer program stored in the memory.
  • the processor and memory may also be physically separated.
  • the terminal when the terminal uses joint coding to transmit UCIs of different priorities on the first uplink channel, the terminal preferentially determines the bit concatenation order of UCI according to the priority order, or the terminal preferentially determines the bit concatenation order of UCI according to the UCI type In the same UCI type, the bit concatenation order of UCI is determined according to the priority order; thus, it is ensured that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • the implementation of the terminal can refer to the implementation of the method, and the repetition will not be repeated.
  • an embodiment of the present disclosure further provides an apparatus for determining a cascade of uplink control information UCI, which is applied to a terminal, and the apparatus includes:
  • a first determining unit 501 configured to determine, according to a first rule, a bit concatenation sequence of UCIs of different priorities jointly coded on the first uplink channel; wherein the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is preferentially determined according to the UCI type, wherein the bit concatenation order of UCI is determined according to the priority order within the same UCI type;
  • the sending unit 502 is configured to send the UCI concatenated according to the bit concatenation sequence on the first uplink channel.
  • the first rule further includes: determining the bit level of UCI according to the UCI type within the same priority connection order.
  • the priority of the UCI includes: a high priority and a low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the device further includes:
  • a third determining unit configured to determine the bit mapping order of the UCI according to a second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the terminal when the terminal uses joint coding to transmit UCIs of different priorities on the first uplink channel, the terminal preferentially determines the bit concatenation order of UCI according to the priority order, or the terminal preferentially determines the bit concatenation order of UCI according to the UCI type In the same UCI type, the bit concatenation order of UCI is determined according to the priority order; thus, it is ensured that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • the implementation of the cascade determination device can refer to the implementation of the method, and the repetition will not be repeated.
  • an embodiment of the present disclosure further provides a network-side device, including a memory 620, a transceiver 610, and a processor 600:
  • the memory 620 is used to store computer programs; the transceiver 610 is used to send and receive data under the control of the processor 600; the processor 600 is used to read the computer programs in the memory 620 and perform the following operations:
  • the bit concatenation sequence of UCIs with different priorities is determined; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the first rule further includes: determining the bit level of UCI according to the UCI type within the same priority connection order.
  • the priority of the UCI includes: a high priority and a low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the processor is further configured to read the computer program in the memory and perform the following operations:
  • the bit mapping order of the UCI is determined; wherein, the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 600 and various circuits of memory represented by memory 620 are linked together.
  • the bus architecture may also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 610 may be multiple elements, ie, including transmitters and receivers, providing means for communicating with various other devices over transmission media including wireless channels, wired channels, fiber optic cables, and the like.
  • the processor 600 is responsible for managing the bus architecture and general processing, and the memory 620 may store data used by the processor 600 in performing operations.
  • the processor 600 may be a central processor (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA) or a complex programmable logic device (Complex Programmable Logic Device). , CPLD), the processor can also use a multi-core architecture.
  • CPU central processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • FPGA field programmable gate array
  • CPLD Complex Programmable Logic Device
  • the network-side device when the network-side device receives multiple UCIs jointly encoded with different priorities on the first uplink channel, the network-side device preferentially determines the bit concatenation sequence of the UCI according to the priority order, or the network-side device preferentially determines the bit concatenation order of the UCI according to the priority order.
  • the type determines the bit concatenation order of UCI, and within the same UCI type, the bit concatenation order of UCI is determined according to the priority order, thereby ensuring that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • the implementation of the network side device may refer to the implementation of the method, and the repetition will not be repeated.
  • an embodiment of the present disclosure further provides a cascade determination device for uplink control information UCI, which is applied to a network side device, including:
  • a receiving unit 701 configured to receive the UCI jointly coded with different priorities on the first uplink channel
  • the second determining unit 702 is configured to determine the bit concatenation sequence of UCIs with different priorities according to a first rule; wherein, the first rule includes:
  • the bit concatenation order of UCI is determined in priority order
  • the bit concatenation order of UCI is determined preferentially according to the UCI type, wherein, within the same UCI type, the bit concatenation order of UCI is determined according to the priority order.
  • the first rule further includes: determining the bit level of UCI according to the UCI type within the same priority connection order.
  • the priority of the UCI includes: a high priority and a low priority
  • the bit concatenation order of UCI is determined according to the priority order, including:
  • the bit concatenation order of UCI is determined as follows: the bits of UCI with low priority are concatenated after the bits of UCI with high priority; or, the bits of UCI with high priority are concatenated in UCI with low priority after the bits.
  • the device further includes:
  • a fourth determining unit configured to determine the bit mapping order of the UCI according to a second rule; wherein the second rule includes:
  • the low-order bits of the UCI are first mapped, and then the high-order bits of the UCI are mapped.
  • the first uplink channel includes at least one of the following:
  • Physical uplink shared channel PUSCH.
  • the network-side device when the network-side device receives multiple UCIs jointly encoded with different priorities on the first uplink channel, the network-side device preferentially determines the bit concatenation sequence of the UCI according to the priority order, or the network-side device preferentially determines the bit concatenation order of the UCI according to the priority order.
  • the type determines the bit concatenation order of UCI, and within the same UCI type, the bit concatenation order of UCI is determined according to the priority order, thereby ensuring that UCIs with different priorities are multiplexed and transmitted on the uplink channel.
  • the implementation of the cascade determination device can refer to the implementation of the method, and the repetition will not be repeated.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a processor-readable storage medium.
  • the technical solutions of the present disclosure can be embodied in the form of software products in essence, or the parts that contribute to related technologies, or all or part of the technical solutions, and the computer software products are stored in a storage medium.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .
  • Embodiments of the present disclosure further provide a processor-readable storage medium, where a computer program is stored in the processor-readable storage medium, and the computer program is used to cause the processor to execute the above method.
  • the processor-readable storage medium can be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic storage (eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (eg, CD, DVD, BD, HVD, etc.), and semiconductor memory (eg, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state disk (SSD)), etc.
  • magnetic storage eg, floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.
  • optical storage eg, CD, DVD, BD, HVD, etc.
  • semiconductor memory eg, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid
  • embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.
  • processor-executable instructions may also be stored in a processor-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the processor-readable memory result in the manufacture of means including the instructions product, the instruction means implements the functions specified in the flow or flow of the flowchart and/or the block or blocks of the block diagram.
  • processor-executable instructions can also be loaded onto a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process that Execution of the instructions provides steps for implementing the functions specified in the flowchart or blocks and/or the block or blocks of the block diagrams.
  • modules can all be implemented in the form of software calling through processing elements; they can also all be implemented in hardware; some modules can also be implemented in the form of calling software through processing elements, and some modules can be implemented in hardware.
  • the determination module may be a separately established processing element, or may be integrated into a certain chip of the above-mentioned device to be implemented, in addition, it may also be stored in the memory of the above-mentioned device in the form of program code, and a certain processing element of the above-mentioned device may Call and execute the function of the above determined module.
  • the implementation of other modules is similar. In addition, all or part of these modules can be integrated together, and can also be implemented independently.
  • the processing element described here may be an integrated circuit with signal processing capability. In the implementation process, each step of the above-mentioned method or each of the above-mentioned modules can be completed by an integrated logic circuit of hardware in the processor element or an instruction in the form of software.
  • each module, unit, sub-unit or sub-module may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuit (ASIC), or, one or Multiple microprocessors (digital signal processors, DSP), or, one or more field programmable gate arrays (Field Programmable Gate Array, FPGA), etc.
  • ASIC Application Specific Integrated Circuit
  • DSP digital signal processors
  • FPGA Field Programmable Gate Array
  • the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processors that can call program codes.
  • CPU central processing unit
  • these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).
  • SOC system-on-a-chip

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Abstract

本公开提供一种UCI的级联确定方法、装置、终端及网络侧设备，该方法包括：终端根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：优先按照优先级顺序确定UCI的比特级联顺序；或者，优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；所述终端在所述第一上行信道上发送按照比特级联顺序级联后的UCI。

Description

UCI的级联确定方法、装置、终端及网络侧设备
相关申请的交叉引用
本公开主张在2021年4月16日在中国提交的中国专利申请号No.202110412070.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信技术领域，尤其是指一种UCI的级联确定方法、装置、终端及网络侧设备。
背景技术
上行控制信息(Uplink Control Information,UCI)包括混合自动重传请求确认(Hybrid Automatic Repeat reQuest–ACKnowledge，HARQ-ACK)、调度请求(Scheduling Request，SR)和信道状态信息(Channel Situation Information，CSI)等。通常UCI承载在物理上行控制信道(Physical Uplink Control Channel，PUCCH)上进行传输，当PUCCH和物理上行共享信道(Physical Uplink Shared Channel，PUSCH)在时域上发生冲突时，部分情况下UCI也会捎带在PUSCH上传输。
高可靠低时延通信(Ultra-Reliable Low Latency Communication，URLLC)的研究过程中，考虑到不同类型业务传输的紧急程度不同，定义了两级优先级，即高优先级(High Priority，HP)和低优先级(Low Priority，LP)。目前Rel-15/16(Release 15/16)协议中仅支持相同优先级的多种UCI类型在同一个上行信道进行传输。相关技术中，相同优先级的不同UCI类型对应的比特级联顺序如下：当HARQ-ACK和SR复用在PUCCH上传输时，UCI比特级联顺序为先HARQ-ACK后SR；当HARQ-ACK、SR以及CSI复用在PUCCH上传输时，UCI比特级联顺序为先HARQ-ACK后SR最后CSI；如果至少一个CSI分为两个CSI part传输时，CSI part1级联在HARQ-ACK和SR之后联合编码，CSI part2独立编码。
Rel-17 URLLC的研究过程中已经允许不同优先级的UCI复用在同一个 上行信道传输，但具体的编码方式仍在讨论中，所有UCI联合编码是候选方案之一。当采用联合编码时，需要确定多种不同优先级UCI比特的级联顺序，暂时还没有明确的技术方案。
发明内容
本公开实施例的目的在于提供一种级联确定方法、装置、终端及网络侧设备，以解决相关技术中多种不同优先级UCI比特的级联顺序无法确定的问题。
为了解决上述问题，本公开实施例提供一种上行控制信息UCI的级联确定方法，该方法包括：
终端根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
所述终端在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述方法还包括：
所述终端根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种上行控制信息UCI的级联确定方法，该方法包括：
网络侧设备在第一上行信道上接收不同优先级联合编码的UCI；
网络侧设备根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述方法还包括：
所述网络侧设备根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种终端，包括存储器，收发机，处理器：
存储器，用于存储计算机程序；收发机，用于在所述处理器的控制下收发数据；处理器，用于读取所述存储器中的计算机程序并执行以下操作：
根据第一规则，确定在第一上行信道上联合编码的不同优先级的上行控制信息UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述处理器还用于读取所述存储器中的计算机程序并执行以下操作：
根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种上行控制信息UCI的级联确定装置，应用于终端，该装置包括：
第一确定单元，用于根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
发送单元，用于在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述装置还包括：
第三确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种网络侧设备，包括存储器，收发机，处理器：
存储器，用于存储计算机程序；收发机，用于在所述处理器的控制下收 发数据；处理器，用于读取所述存储器中的计算机程序并执行以下操作：
在第一上行信道上接收不同优先级联合编码的上行控制信息UCI；
根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述处理器还用于读取所述存储器中的计算机程序并执行以下操作：
根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种上行控制信息UCI的级联确定装置，应用于网络侧设备，包括：
接收单元，用于在第一上行信道上接收不同优先级联合编码的UCI；
第二确定单元，用于根据第一规则，确定不同优先级的UCI的比特级联 顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
其中，所述装置还包括：
第四确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例还提供一种处理器可读存储介质，所述处理器可读存储介质存储有计算机程序，所述计算机程序用于使所述处理器执行如上所述的方法。
本公开的上述技术方案至少具有如下有益效果：
本公开实施例的UCI的级联确定方法、装置、终端及网络侧设备中，终端采用联合编码在第一上行信道上传输不同优先级的UCI时，终端优先按照优先级顺序确定UCI的比特级联顺序，或者，终端优先按照UCI类型确定 UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本公开实施例可应用的一种无线通信系统的框图；
图2表示本公开实施例提供的级联确定方法的步骤示意图之一；
图3表示本公开实施例提供的级联确定方法的步骤示意图之二；
图4表示本公开实施例提供的终端的结构示意图；
图5表示本公开实施例提供的级联确定装置的结构示意图之一；
图6表示本公开实施例提供的网络侧设备的结构示意图；
图7表示本公开实施例提供的级联确定装置的结构示意图之二。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
图1示出本公开实施例可应用的一种无线通信系统的框图。无线通信系统包括终端11和网络侧设备12。其中，终端11也可以称作终端设备或者用户终端(User Equipment，UE)。需要说明的是，在本公开实施例并不限定终端11的具体类型。网络侧设备12可以是基站或核心网，需要说明的是，在本公开实施例中仅以NR系统中的基站为例，但是并不限定基站的具体类型。
本公开实施例中术语“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
本公开实施例中术语“多个”是指两个或两个以上，其它量词与之类似。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，并不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供的技术方案可以适用于多种系统，尤其是5G系统。例如适用的系统可以是全球移动通讯(global system of mobile communication，GSM)系统、码分多址(code division multiple access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)通用分组无线业务(general packet radio service，GPRS)系统、长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)系统、高级长期演进(long term evolution advanced，LTE-A)系统、通用移动系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)系统、5G新空口(New Radio,NR)系统等。这多种系统中均包括终端设备和网络设备。系统中还可以包括核心网部分，例如演进的分组系统(Evloved Packet System,EPS)、5G系统(5GS)等。
本公开实施例涉及的终端，可以是指向用户提供语音和/或数据连通性的设备，具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备等。在不同的系统中，终端设备的名称可能也不相同，例如在5G系统中，终端设备可以称为用户设备(User Equipment，UE)。无线终端设备可以经无线接入网(Radio Access Network,RAN)与一个或多个核心网(Core Network,CN)进行通信，无线终端设备可以是移动终端设备，如移动电话(或称为“蜂窝”电话)和具有移动终端设备的计算机，例如，可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置，它们与无线接入网交换语言和/或数据。例如，个人通信业务(Personal Communication Service，PCS)电话、无绳电话、会话发起协议(Session Initiated Protocol，SIP)话机、无线本地环路(Wireless Local Loop，WLL)站、个人数字助理(Personal Digital Assistant，PDA)等设备。无线终端设备也可以称为系统、订户单元(subscriber unit)、订户站(subscriber station)，移动站(mobile station)、移动台(mobile)、 远程站(remote station)、接入点(access point)、远程终端设备(remote terminal)、接入终端设备(access terminal)、用户终端设备(user terminal)、用户代理(user agent)、用户装置(user device)，本公开实施例中并不限定。
本公开实施例涉及的网络侧设备，可以是基站，该基站可以包括多个为终端提供服务的小区。根据具体应用场合不同，基站又可以称为接入点，或者可以是接入网中在空中接口上通过一个或多个扇区与无线终端设备通信的设备，或者其它名称。网络设备可用于将收到的空中帧与网际协议(Internet Protocol，IP)分组进行相互更换，作为无线终端设备与接入网的其余部分之间的路由器，其中接入网的其余部分可包括网际协议(IP)通信网络。网络设备还可协调对空中接口的属性管理。例如，本公开实施例涉及的网络设备可以是全球移动通信系统(Global System for Mobile communications，GSM)或码分多址接入(Code Division Multiple Access，CDMA)中的网络设备(Base Transceiver Station，BTS)，也可以是带宽码分多址接入(Wide-band Code Division Multiple Access，WCDMA)中的网络设备(NodeB)，还可以是长期演进(long term evolution，LTE)系统中的演进型网络设备(evolutional Node B，eNB或e-NodeB)、5G网络架构(next generation system)中的5G基站(gNB)，也可以是家庭演进基站(Home evolved Node B，HeNB)、中继节点(relay node)、家庭基站(femto)、微微基站(pico)等，本公开实施例中并不限定。在一些网络结构中，网络设备可以包括集中单元(centralized unit，CU)节点和分布单元(distributed unit，DU)节点，集中单元和分布单元也可以地理上分开布置。
网络侧设备与终端之间可以各自使用一或多根天线进行多输入多输出(Multi Input Multi Output,MIMO)传输，MIMO传输可以是单用户MIMO(Single User MIMO,SU-MIMO)或多用户MIMO(Multiple User MIMO,MU-MIMO)。根据根天线组合的形态和数量，MIMO传输可以是2D-MIMO、3D-MIMO、FD-MIMO或massive-MIMO，也可以是分集传输或预编码传输或波束赋形传输等。
如图2所示，本公开实施例提供一种上行控制信息UCI的级联确定方法，该方法包括：
步骤201，终端根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
步骤202，所述终端在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
本公开实施例中，所述UCI类型包括HARQ-ACK，SR，CSI。需要说明的是，第一上行信道上联合编码的UCI至少包括HARQ-ACK。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开的至少一个实施例中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级(也可以称为第一优先级)和低优先级(也可以称为第二优先级)；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
本公开的至少一个实施例中，按照UCI类型确定UCI的比特级联顺序包括：按照现有的UCI类型的级联顺序确定UCI的比特级联顺序。例如，当HARQ-ACK和SR复用在PUCCH上传输时，UCI的比特级联顺序为先HARQ-ACK后SR。当HARQ-ACK、SR以及CSI复用在PUCCH上传输时，UCI比特级联顺序为先HARQ-ACK后SR最后CSI，如果至少一个CSI分为两个CSI部分(part)传输时，CSI part1级联在HARQ-ACK和SR之后联合编码，CSI part2独立编码。
进一步的，本公开的至少一个实施例中，所述方法还包括：
所述终端根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；也可以称为UCI采用先高比特位后低比特位映射；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位；也可以称为UCI采用先低比特位后高比特位映射。
综上，终端采用联合编码在第一上行信道上传输不同优先级的UCI时，终端优先按照优先级顺序确定UCI的比特级联顺序，或者，终端优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
为了更清楚的描述本公开实施例提供的级联确定方法，下面结合几个示例进行说明。
示例一，优先按照优先级顺序确定UCI的比特级联顺序；
终端在PUCCH上复用传输两种优先级的HARQ-ACK、SR和CSI。首先终端按照优先级进行排序，在本示例中，如果终端将低优先级的UCI比特级联在高优先级的UCI比特之后。在相同优先级UCI内部，按照UCI类型将HARQ-ACK、SR、CSI依次级联。此时，最终确定的UCI比特级联顺序为HP HARQ-ACK、HP SR、HP CSI、LP HARQ-ACK、LP SR、LP CSI。如果将高优先级的UCI比特级联在低优先级的UCI比特之后。此时，最终确定的UCI比特级联顺序为LP HARQ-ACK、LP SR、LP CSI、HP HARQ-ACK、HP SR、HP CSI。
或者，如果终端在PUCCH上复用传输两种优先级的HARQ-ACK、SR，比特级联顺序为HP HARQ-ACK、HP SR、LP HARQ-ACK、LP SR或者LP HARQ-ACK、LP SR、HP HARQ-ACK、HP SR。
或者，如果终端在PUCCH上复用传输两种优先级的HARQ-ACK，比特级联顺序为HP HARQ-ACK、LP HARQ-ACK或者LP HARQ-ACK、HP HARQ-ACK。
本示例中，以第一种情况为例，如果UCI采用先高比特位映射后低比特位映射，即不同优先级的多种UCI比特序列从左到右依次级联组合。假设本示例中HARQ-ACK各3bits，SR各1bit，CSI各5bits，则级联后的UCI比特序列为a 0,a 1,a 2,……,a 17。a 0,a 1,a 2映射HP HARQ-ACK的比特序列，a 3映射HP SR的比特序列，a 4,……,a 8映射HP CSI的比特序列，a 9,a 10,a 11映射LP HARQ-ACK的比特序列，a 12映射LP SR的比特序列，a 13,……,a 17映射LP CSI的比特序列。反之，如果UCI采用先低比特位后高比特位映射，即不同优先级的多种UCI比特序列从右到左依次级联组合。则a 2,a 1,a 0映射HP HARQ-ACK的比特序列，a 3映射HP SR的比特序列，a 8,……,a 4映射HP CSI的比特序列，a 11,a 10,a 9映射LP HARQ-ACK的比特序列，a 12映射LP SR的比特序列，a 17,……,a 13映射LP CSI的比特序列。本实施例中的其他UCI比特级联映射顺序同理，在此不一一枚举。
示例二，优先按照UCI类型确定UCI的比特级联顺序
终端在PUCCH上复用传输两种优先级的HARQ-ACK、SR和CSI。终端首先按照UCI类型进行排序，在相同UCI类型内部，终端按照优先级进行排序。本示例中，如果终端将低优先级的UCI比特级联在高优先级的UCI比特之后，则最终确定的UCI比特级联顺序为HP HARQ-ACK、LP HARQ-ACK、HP SR、LP SR、HP CSI、LP CSI。如果终端将高优先级的UCI比特级联在低优先级的UCI比特之后，则最终确定的UCI比特级联顺序为LP HARQ-ACK、HP HARQ-ACK、LP SR、HP SR、LP CSI、HP CSI。
或者，如果终端在PUCCH上复用传输两种优先级的HARQ-ACK、SR。比特级联顺序为HP HARQ-ACK、LP HARQ-ACK、HP SR、LP SR或者LP HARQ-ACK、HP HARQ-ACK、LP SR、HP SR。
或者，如果终端在PUCCH上复用传输两种优先级的HARQ-ACK。比特级联顺序为HP HARQ-ACK、LP HARQ-ACK或者LP HARQ-ACK、HP HARQ-ACK。
本示例中，以第一种情况为例，如果UCI采用先高比特位映射后低比特位映射，即不同优先级的多种UCI比特序列从左到右依次级联组合。假设本示例中HARQ-ACK各3bits，SR各1bit，CSI各5bits，则级联后的UCI比特 序列为a 0,a 1,a 2,……,a 17。a 0,a 1,a 2映射HP HARQ-ACK的比特序列，a 3,a 4,a 5映射LP HARQ-ACK的比特序列，a 6映射HP SR的比特序列，a 7映射LP SR的比特序列，a 8,……,a 12映射HP CSI的比特序列，a 13,……,a 17映射LP CSI的比特序列。反之，如果UCI采用先低比特位后高比特位映射，即不同优先级的多种UCI比特序列从右到左依次级联组合。则a 2,a 1,a 0映射HP HARQ-ACK的比特序列，a 5,a 4,a 3映射LP HARQ-ACK的比特序列，a 6映射HP SR的比特序列，a 7映射LP SR的比特序列，a 12,……,a 8映射HP CSI的比特序列，a 17,……,a 13映射LP CSI的比特序列。本示例中的其他UCI比特级联映射顺序同理，在此不一一枚举。
示例三
终端在PUSCH上复用两种优先级的一种或多种UCI。UCI至少包括：HARQ-ACK。UCI比特级联顺序及映射顺序确定方式和示例1、示例2相同。
如图3所示，本公开实施例还提供一种上行控制信息UCI的级联确定方法，该方法包括：
步骤301，网络侧设备在第一上行信道上接收不同优先级联合编码的UCI；
步骤302，网络侧设备根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
本公开实施例中，所述UCI类型包括HARQ-ACK，SR，CSI。需要说明的是，第一上行信道上联合编码的UCI至少包括HARQ-ACK。
当网络侧设备在第一上行信道接收多种不同优先级联合编码的UCI时，按照第一规则确定UCI的比特级联顺序。
其中，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开的至少一个实施例中，在所述第一规则为优先按照优先级顺序确 定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
其中，所述UCI的优先级包括：高优先级(也可以称为第一优先级)和低优先级(也可以称为第二优先级)；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
本公开的至少一个实施例中，按照UCI类型确定UCI的比特级联顺序包括：按照现有的UCI类型的级联顺序确定UCI的比特级联顺序。例如，当HARQ-ACK和SR复用在PUCCH上传输时，UCI的比特级联顺序为先HARQ-ACK后SR。当HARQ-ACK、SR以及CSI复用在PUCCH上传输时，UCI比特级联顺序为先HARQ-ACK后SR最后CSI，如果至少一个CSI分为两个CSI部分(part)传输时，CSI part1级联在HARQ-ACK和SR之后联合编码，CSI part2独立编码。
进一步的，本公开的至少一个实施例中，所述方法还包括：
所述网络侧设备根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；也可以称为UCI采用先高比特位后低比特位映射；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位；也可以称为UCI采用先低比特位后高比特位映射。
综上，当网络侧设备在第一上行信道接收多种不同优先级联合编码的UCI时，网络侧设备优先按照优先级顺序确定UCI的比特级联顺序，或者，网络侧设备优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
如图4所示，本公开实施例还提供一种终端，包括存储器420，收发机 410，处理器400：
存储器420，用于存储计算机程序；收发机410，用于在所述处理器400的控制下收发数据；处理器400，用于读取所述存储器420中的计算机程序并执行以下操作：
根据第一规则，确定在第一上行信道上联合编码的不同优先级的上行控制信息UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
作为一个可选实施例，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
作为一个可选实施例，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
作为一个可选实施例，，所述处理器400还用于读取所述存储器中的计算机程序并执行以下操作：
根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
作为一个可选实施例，，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
其中，在图4中，总线架构可以包括任意数量的互联的总线和桥，具体 由处理器400代表的一个或多个处理器和存储器420代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机410可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元，这些传输介质包括，这些传输介质包括无线信道、有线信道、光缆等传输介质。针对不同的用户设备，用户接口430还可以是能够外接内接需要设备的接口，连接的设备包括但不限于小键盘、显示器、扬声器、麦克风、操纵杆等。
处理器400负责管理总线架构和通常的处理，存储器420可以存储处理器400在执行操作时所使用的数据。
可选的，处理器400可以是中央处埋器(CPU)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)，处理器也可以采用多核架构。
处理器通过调用存储器存储的计算机程序，用于按照获得的可执行指令执行本公开实施例提供的任一所述方法。处理器与存储器也可以物理上分开布置。
本公开实施例中终端采用联合编码在第一上行信道上传输不同优先级的UCI时，终端优先按照优先级顺序确定UCI的比特级联顺序，或者，终端优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
需要说明的是，由于终端解决问题的原理与本公开实施例中级联确定方法相似，因此该终端的实施可以参见方法的实施，重复之处不再敷述。
如图5所示，本公开实施例还提供一种上行控制信息UCI的级联确定装置，应用于终端，该装置包括：
第一确定单元501，用于根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
发送单元502，用于在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
作为一个可选实施例，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
作为一个可选实施例，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
作为一个可选实施例，所述装置还包括：
第三确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
作为一个可选实施例，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施例中终端采用联合编码在第一上行信道上传输不同优先级的UCI时，终端优先按照优先级顺序确定UCI的比特级联顺序，或者，终端优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
需要说明的是，由于级联确定装置解决问题的原理与本公开实施例中级 联确定方法相似，因此该级联确定装置的实施可以参见方法的实施，重复之处不再敷述。
如图6所示，本公开实施例还提供一种网络侧设备，包括存储器620，收发机610，处理器600：
存储器620，用于存储计算机程序；收发机610，用于在所述处理器600的控制下收发数据；处理器600，用于读取所述存储器620中的计算机程序并执行以下操作：
在第一上行信道上接收不同优先级联合编码的上行控制信息UCI；
根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
作为一个可选实施例，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
作为一个可选实施例，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
作为一个可选实施例，所述处理器还用于读取所述存储器中的计算机程序并执行以下操作：
根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
作为一个可选实施例，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
其中，在图6中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器600代表的一个或多个处理器和存储器620代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机610可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元，这些传输介质包括无线信道、有线信道、光缆等传输介质。处理器600负责管理总线架构和通常的处理，存储器620可以存储处理器600在执行操作时所使用的数据。
处理器600可以是中央处埋器(CPU)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)，处理器也可以采用多核架构。
本公开实施中，当网络侧设备在第一上行信道接收多种不同优先级联合编码的UCI时，网络侧设备优先按照优先级顺序确定UCI的比特级联顺序，或者，网络侧设备优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
需要说明的是，由于网络侧设备解决问题的原理与本公开实施例中级联确定方法相似，因此该网络侧设备的实施可以参见方法的实施，重复之处不再敷述。
如图7所示，本公开实施例还提供一种上行控制信息UCI的级联确定装置，应用于网络侧设备，包括：
接收单元701，用于在第一上行信道上接收不同优先级联合编码的UCI；
第二确定单元702，用于根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
优先按照优先级顺序确定UCI的比特级联顺序；
或者，
优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
作为一个可选实施例，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
作为一个可选实施例，所述UCI的优先级包括：高优先级和低优先级；
其中，按照优先级顺序确定UCI的比特级联顺序，包括：
按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
作为一个可选实施例，所述装置还包括：
第四确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
先映射所述UCI的高比特位，再映射所述UCI的低比特位；
或者，
先映射所述UCI的低比特位，再映射所述UCI的高比特位。
作为一个可选实施例，所述第一上行信道包括下述至少一项：
物理上行控制信道PUCCH；
物理上行共享信道PUSCH。
本公开实施中，当网络侧设备在第一上行信道接收多种不同优先级联合编码的UCI时，网络侧设备优先按照优先级顺序确定UCI的比特级联顺序，或者，网络侧设备优先按照UCI类型确定UCI的比特级联顺序，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；从而确保不同优先级的UCI在上行信道上进行复用传输。
需要说明的是，由于级联确定装置解决问题的原理与本公开实施例中级联确定方法相似，因此该级联确定装置的实施可以参见方法的实施，重复之处不再敷述。
需要说明的是，本公开实施例中对单元的划分是示意性的，仅仅为一种 逻辑功能划分，实际实现时可以有另外的划分方式。另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对相关技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本公开实施例还提供一种处理器可读存储介质，所述处理器可读存储介质存储有计算机程序，所述计算机程序用于使所述处理器执行如上所述的方法。所述处理器可读存储介质可以是处理器能够存取的任何可用介质或数据存储设备，包括但不限于磁性存储器(例如软盘、硬盘、磁带、磁光盘(MO)等)、光学存储器(例如CD、DVD、BD、HVD等)、以及半导体存储器(例如ROM、EPROM、EEPROM、非易失性存储器(NAND FLASH)、固态硬盘(SSD))等。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机可执行指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机可执行指令到通用计算机、专用计 算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些处理器可执行指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的处理器可读存储器中，使得存储在该处理器可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些处理器可执行指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
需要说明的是，应理解以上各个模块的划分仅仅是一种逻辑功能的划分，实际实现时可以全部或部分集成到一个物理实体上，也可以物理上分开。且这些模块可以全部以软件通过处理元件调用的形式实现；也可以全部以硬件的形式实现；还可以部分模块通过处理元件调用软件的形式实现，部分模块通过硬件的形式实现。例如，确定模块可以为单独设立的处理元件，也可以集成在上述装置的某一个芯片中实现，此外，也可以以程序代码的形式存储于上述装置的存储器中，由上述装置的某一个处理元件调用并执行以上确定模块的功能。其它模块的实现与之类似。此外这些模块全部或部分可以集成在一起，也可以独立实现。这里所述的处理元件可以是一种集成电路，具有信号的处理能力。在实现过程中，上述方法的各步骤或以上各个模块可以通过处理器元件中的硬件的集成逻辑电路或者软件形式的指令完成。
例如，各个模块、单元、子单元或子模块可以是被配置成实施以上方法的一个或多个集成电路，例如：一个或多个特定集成电路(Application Specific Integrated Circuit，ASIC)，或，一个或多个微处理器(digital signal processor，DSP)，或，一个或者多个现场可编程门阵列(Field Programmable Gate Array，FPGA)等。再如，当以上某个模块通过处理元件调度程序代码的形式实现时，该处理元件可以是通用处理器，例如中央处理器(Central Processing Unit， CPU)或其它可以调用程序代码的处理器。再如，这些模块可以集成在一起，以片上系统(system-on-a-chip，SOC)的形式实现。
本公开的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例，例如除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，说明书以及权利要求中使用“和/或”表示所连接对象的至少其中之一，例如A和/或B和/或C，表示包含单独A，单独B，单独C，以及A和B都存在，B和C都存在，A和C都存在，以及A、B和C都存在的7种情况。类似地，本说明书以及权利要求中使用“A和B中的至少一个”应理解为“单独A，单独B，或A和B都存在”。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (31)

  1. 一种上行控制信息UCI的级联确定方法，该方法包括：
    终端根据第一规则，确定在第一上行信道上联合编码的不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
    所述终端在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
  2. 根据权利要求1所述的方法，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  3. 根据权利要求1或2所述的方法，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  4. 根据权利要求1或2所述的方法，其中，所述方法还包括：
    所述终端根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  5. 根据权利要求1所述的方法，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  6. 一种上行控制信息UCI的级联确定方法，该方法包括：
    网络侧设备在第一上行信道上接收不同优先级联合编码的UCI；
    网络侧设备根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
  7. 根据权利要求6所述的方法，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  8. 根据权利要求6或7所述的方法，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  9. 根据权利要求6或7所述的方法，其中，所述方法还包括：
    所述网络侧设备根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  10. 根据权利要求6所述的方法，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  11. 一种终端，包括存储器，收发机，处理器：
    存储器，用于存储计算机程序；收发机，用于在所述处理器的控制下收 发数据；处理器，用于读取所述存储器中的计算机程序并执行以下操作：
    根据第一规则，确定在第一上行信道上联合编码的不同优先级的上行控制信息UCI的比特级联顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
    在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
  12. 根据权利要求11所述的终端，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  13. 根据权利要求11或12所述的终端，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  14. 根据权利要求11或12所述的终端，其中，所述处理器还用于读取所述存储器中的计算机程序并执行以下操作：
    根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  15. 根据权利要求11所述的终端，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  16. 一种上行控制信息UCI的级联确定装置，应用于终端，该装置包括：
    第一确定单元，用于根据第一规则，确定在第一上行信道上联合编码的 不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序；
    发送单元，用于在所述第一上行信道上发送按照比特级联顺序级联后的UCI。
  17. 根据权利要求16所述的装置，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  18. 根据权利要求16或17所述的装置，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  19. 根据权利要求16或17所述的装置，其中，所述装置还包括：
    第三确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  20. 根据权利要求16所述的装置，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  21. 一种网络侧设备，包括存储器，收发机，处理器：
    存储器，用于存储计算机程序；收发机，用于在所述处理器的控制下收发数据；处理器，用于读取所述存储器中的计算机程序并执行以下操作：
    在第一上行信道上接收不同优先级联合编码的上行控制信息UCI；
    根据第一规则，确定不同优先级的UCI的比特级联顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
  22. 根据权利要求21所述的网络侧设备，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  23. 根据权利要求21或22所述的网络侧设备，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  24. 根据权利要求21或22所述的网络侧设备，其中，所述处理器还用于读取所述存储器中的计算机程序并执行以下操作：
    根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  25. 根据权利要求21所述的网络侧设备，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  26. 一种上行控制信息UCI的级联确定装置，应用于网络侧设备，包括：
    接收单元，用于在第一上行信道上接收不同优先级联合编码的UCI；
    第二确定单元，用于根据第一规则，确定不同优先级的UCI的比特级联 顺序；其中，所述第一规则包括：
    优先按照优先级顺序确定UCI的比特级联顺序；
    或者，
    优先按照UCI类型确定UCI的比特级联顺序，其中，相同UCI类型内部按照优先级顺序确定UCI的比特级联顺序。
  27. 根据权利要求26所述的装置，其中，在所述第一规则为优先按照优先级顺序确定UCI的比特级联顺序的情况下，所述第一规则还包括：相同优先级内部按照UCI类型确定UCI的比特级联顺序。
  28. 根据权利要求26或27所述的装置，其中，所述UCI的优先级包括：高优先级和低优先级；
    其中，按照优先级顺序确定UCI的比特级联顺序，包括：
    按照优先级顺序，确定UCI的比特级联顺序为：低优先级的UCI的比特级联在高优先级的UCI的比特之后；或者，高优先级的UCI的比特级联在低优先级的UCI的比特之后。
  29. 根据权利要求26或27所述的装置，其中，所述装置还包括：
    第四确定单元，用于根据第二规则，确定所述UCI的比特映射顺序；其中，第二规则包括：
    先映射所述UCI的高比特位，再映射所述UCI的低比特位；
    或者，
    先映射所述UCI的低比特位，再映射所述UCI的高比特位。
  30. 根据权利要求26所述的装置，其中，所述第一上行信道包括下述至少一项：
    物理上行控制信道PUCCH；
    物理上行共享信道PUSCH。
  31. 一种处理器可读存储介质，所述处理器可读存储介质存储有计算机程序，所述计算机程序用于使所述处理器执行如权利要求1至5任一项所述的方法；或者，所述计算机程序用于使所述处理器执行如权利要求6至10任一项所述的方法。
PCT/CN2022/080613 2021-04-16 2022-03-14 Uci的级联确定方法、装置、终端及网络侧设备 WO2022218075A1 (zh)

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