WO2022214083A1

WO2022214083A1 - Multi-fast charging protocol control circuit, control method, chip, and electronic device

Info

Publication number: WO2022214083A1
Application number: PCT/CN2022/085879
Authority: WO
Inventors: 汤厚涛
Original assignee: 深圳英集芯科技股份有限公司
Priority date: 2021-04-09
Filing date: 2022-04-08
Publication date: 2022-10-13
Also published as: CN112803558A; CN112803558B; CN115207999A

Abstract

The present application provides a multi-fast charging protocol control circuit, comprising a charging logic control module, a first voltage measurement module, a second voltage measurement module, an AFSCP sending module, a VOOC sending module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, a switch G1, a switch G2, and a switch G3. The charging logic control module is configured to control the voltage measurement modules to measure voltages of the DP interface and the DM interface, to perform timing by means of the timer module, to control the on/off of the switches according to the voltage measurement results, the timing result and the current of the VBUS interface, to communicate with a load device using a corresponding communication protocol, and to charge the load device by means of the VBUS interface. The multi-fast charging protocol control circuit provided by the present application can realize the fast charging of a plurality of fast charging protocols, can implement the supporting of a plurality of fast charging protocols by a single chip when applied to a fast charging protocol chip, is flexible in application, and reduces cost.

Description

Multi-fast charging protocol control circuit, control method, chip and electronic device

This application claims the priority of the Chinese patent application filed on April 9, 2021 with the application number 2021103850008 and the application name "Multi-fast charging protocol control circuit, control method, chip and electronic equipment", the entire content of which is Incorporated herein by reference.

technical field

The present application relates to the technical field of fast charging, and in particular, to a multi-fast charging protocol control circuit, a control method, a chip and an electronic device.

Background technique

With the rapid popularization of fast charging technology, more and more mobile phone manufacturers have launched their own private fast charging protocols. At present, the mainstream protocols on the market include the Quick Charge (QC) 3.0/2.0 protocol, the Dedicated Charging Ports (DCP) protocol, the Fast Charge Protocol (FCP) protocol, the ultra-fast charging protocol ( Super Fast Charge, SCP) protocol, adaptive fast charging protocol (Adaptive Fast, AFC) and other fast charging protocols. The traditional fast charging protocol chip usually only supports a single fast charging protocol, and cannot realize the fast charging of multiple fast charging protocols through a single fast charging protocol chip, which causes some mobile phones or electronic devices to be unable to fast charge, and there is a protocol compatibility problem. .

SUMMARY OF THE INVENTION

The present application provides a multi-fast charging protocol control circuit, control method, chip and electronic device, in order to solve the protocol compatibility problem caused by the inability of a single fast charging protocol chip to support multiple fast charging protocols in traditional fast charging protocol chips.

In the first aspect, an embodiment of the present application provides a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module, a VOOC sending module, a DP interface, a DM interface, VBUS interface, GND interface, timer module, switch G1, switch G2, switch G3;

The charging logic control module is connected to the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module and the AFSCP The first port of the sending module, the first port of the VOOC sending module, the control port of the switch G1, the control port of the switch G2 and the control port of the switch G3, the first port of the first voltage detection module. After the second port is combined with the first port of the switch G1, the DP interface is connected to the first port of the switch G2. The second port of the switch G1 is connected to the second port of the VOOC sending module. The second port of the second voltage detection module and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2, and the second port of the switch G3 is connected to the AFSCP sending module the second port;

The DP interface, the DM interface, the VBUS interface, and the GND interface are used to connect a load device, and the VOOC sending module is used to perform a VOOC protocol with the load device under the control of the charging logic control module communication, the AFSCP sending module is used for AFC/SCP/FCP protocol communication with the load device under the control of the charging logic control module, and the charging logic control module is used to control the first voltage detection module to detect The voltage of the DP interface, the second voltage detection module is controlled to detect the voltage of the DM interface, the timer module is used for timing, and the switch is controlled according to the voltage detection result, the timing result and the current of the VBUS interface G1, the switch G2 and the switch G3 are turned on and off to adjust the channel state of the multi-fast charging protocol control circuit, and use the corresponding communication protocol to communicate with the load device, and communicate with the load device through the VBUS interface. The load device is charged.

In a second aspect, the present application provides a control method for a multi-fast charging protocol control circuit, the multi-fast charging protocol control circuit includes the multi-fast charging protocol control circuit as described in the first aspect, and the control method includes the following steps:

When performing fast charging protocol communication with the load device through the multi-fast charging protocol control circuit, the charging logic control module adopts the DCP fast charging protocol by default, and controls the channel state of the multi-fast charging protocol control circuit to be the first state;

When the charging logic control module determines the voltage change of the DP interface or the DM interface according to the voltage detection result of the first voltage detection module or the second voltage detection module, the timer module starts to count the time t1;

If the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the t1 time period, the charging logic control module controls the multi-fast charging protocol control circuit after the t1 time period The channel state of , is the second state, the switch G2 is closed, and the DP interface and the DM interface are short-circuited;

When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines, according to the voltage detection result of the first voltage detection module, that the DP interface voltage is Within the set voltage range, the timer module starts to count the time t2;

If within the time t2, the charging logic control module determines that the voltage of the DP interface is always within the preset voltage range according to the voltage detection result of the first voltage detection module;

Then after the time t2, the charging logic control module controls the channel state of the multi-fast charging protocol control circuit to be the third state, the switch G2 is turned off, and the short circuit between the DP interface and the DM interface is disconnected. ;

The charging logic control module controls the switch G1 and the switch G3 to close, and judges whether the DM interface is less than a first preset voltage value according to the voltage detection result of the second voltage detection module;

If so, the timer module starts timing t3 time;

If within the time t3, the charging logic control module determines that the voltage of the DM interface is always less than the first preset voltage value according to the voltage detection result of the second voltage detection module, then the QC handshake is successful; otherwise, the QC handshake is successful. , QC handshake failed;

If the QC handshake is successful, then after the time t3, detect whether the AFC/SCP/FCP data packet is received on the DM interface;

If received, communicate with the load device through AFC/SCP/FCP protocol through the AFSCP sending module;

If not received, the charging logic control module adopts the QC fast charging protocol, and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module;

If the QC handshake fails, after the time t3, the charging logic control module detects whether the current of the VBUS interface is greater than the preset current value;

If so, the timer module starts timing t4 time;

If within the time t4, the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value, the VOOC sending module communicates with the load device through the VOOC protocol.

In a third aspect, the present application provides a multi-fast charging protocol control chip, including the multi-fast charging protocol control circuit described in the first aspect.

In a fourth aspect, the present application provides an electronic device, including the multi-fast charging protocol control chip as described in the third aspect.

It can be seen that the present application provides a multi-fast charging protocol control circuit, including a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmission module, a VOOC transmission module, a DP interface, a DM interface, and a VBUS interface. , GND interface, timer module, switch G1, switch G2, switch G3, and the charging logic control module is used to control the first voltage detection module and the second voltage detection module to detect the voltage of the DP interface and the DM interface respectively. Timing, according to the voltage detection results, timing results and the current of the VBUS interface to control the on-off of the switch G1, the switch G2, and the switch G3, and use the corresponding communication protocol to communicate with the load device, and to charge the load device through the VBUS interface. It can be seen that the multi-fast charging protocol control circuit provided in this application can realize fast charging of various fast charging protocols, and when applied to a fast charging protocol chip, a single chip can support various fast charging protocols, and the application is flexible and cost saving.

Description of drawings

1 is a circuit schematic diagram of a multi-fast charging protocol control circuit provided by the present application;

2 is a circuit schematic diagram of a voltage detection module provided by the present application;

3 is a circuit schematic diagram of another multi-fast charging protocol control circuit provided by the present application;

4 is a circuit schematic diagram of a data voltage output module provided by the present application;

5 is a circuit schematic diagram of another multi-fast charging protocol control circuit provided by the present application;

6 is a circuit schematic diagram of another multi-fast charging protocol control circuit provided by the present application;

7 is a schematic flowchart of a control method of a multi-fast charging protocol control circuit provided by the present application;

FIG. 8 is a schematic flowchart of another control method of a multi-fast charging protocol control circuit provided by the present application.

The present application will be further described below with reference to the accompanying drawings and embodiments.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

Example 1:

1, this embodiment provides a multi-fast charging protocol control circuit, a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module (ie, an FCP/SCP/AFC protocol sending module), Flash charge VOOC sending module, data positive signal (Data Positive, DP) interface, data negative signal (Data Minus, DM) interface, voltage positive VBUS interface, voltage negative GND interface, timer module, switch G1, switch G2, switch G3 ;

The multi-fast charging protocol control circuit described in the embodiments of the present application can be applied to the fast charging protocol control chip at the power adapter end.

Specifically, in terms of using the corresponding fast charging protocol to communicate with the load device, the charging logic control module can specifically be used to control the VOOC sending module to communicate with the load device through the DP interface with the VOOC protocol, and to control the AFSCP sending module to communicate with the load device through the DM interface. AFC/SCP/FCP protocol communication.

The charging logic control module controls the two voltage detection modules (the first voltage detection module and the second voltage detection module) to detect the voltage of the DP interface and the DM interface, which may include configuring the voltage detection module to A range of voltages is detected.

In the specific implementation, when the multi-fast charging protocol circuit rapidly charges the load device, the charging logic control module can use a fast charging protocol as the initial fast charging protocol by default, and then can determine whether it needs to be switched according to the protocol communication with the load device. Using other fast charging protocols, for example, the charging logic control module can use the DCP protocol by default. After connecting with the load device, it can adjust the path status of the multi-fast charging protocol control circuit and perform a protocol handshake with the load device to confirm whether the fast charging protocol needs to be switched.

For example, when the DCP fast charging protocol is adopted by default, the charging logic control module confirms the connection with the load device according to the voltage detection result of the voltage detection module (for example, according to the voltage detection result of the first voltage detection module or the second voltage detection module) After determining that the voltage of the DP interface or the DM interface changes for a period of time), the charging logic control module can control the switch G2 to close, so that the DP interface and the DM interface are short-circuited, and the load device is notified that the DCP protocol is used.

After the load device detects that the DP interface and the DM interface are short-circuited, it can be determined that the power adapter adopts the DCP fast charging protocol. If the load device needs to adopt other fast charging protocols, it can control the voltage output to the DP interface and DM interface accordingly. , the charging logic control module can determine whether to switch the adopted fast charging protocol through the voltage detection result.

For example, according to the voltage detection result of the first voltage detection module, the charging logic control module determines that the voltage value on the DP interface is within the preset voltage value range for a specific time, and can control the disconnection switch G2 to disconnect the DP interface and the Short-circuit the DM interface, enable switch G1 and switch G3, and perform QC protocol handshake with the load device. Specifically, it can be determined whether the QC handshake is successful by detecting whether the voltage on the DM interface meets the preset conditions. Switch G1 and switch G3 are enabled. At this time, the AFSCP sending module and the VOOC sending module can communicate with the load device through the DP interface and DM interface under the control of the charging logic control module. If the QC handshake is successful, it can be Further, according to whether the DM interface receives AFC/SCP/FCP data packets, determine whether to use the AFC/SCP/FCP fast charging protocol or the QC fast charging protocol, or after the QC handshake fails, determine whether to use VOOC fast charging based on the current value on VBUS. charging agreement. After determining the adopted fast charging protocol, the charging logic control module can adjust the output voltage on VBUS according to the voltage detection result, and then realize fast charging supporting multiple fast charging protocols through the above-mentioned multi-fast charging logic control circuit.

Specifically, when VOOC protocol communication or AFC/SCP/FCP protocol communication is performed with the load, the AFSCP sending module and the VOOC sending module are used to send signals (specifically, the AFSCP sending module can be controlled by the charging logic control module to output a specific voltage signal to the DM interface, control the VOOC sending module to output a specific voltage signal to the DP interface), and the charging logic control module is used to determine the signal from the load device according to the voltage detection result.

In a possible example, referring to FIG. 2 , the first voltage detection module includes a voltage comparator CMP1, a voltage comparator CMP2, and a voltage comparator CMP3, and the second voltage detection module includes a voltage comparator CMP4, a voltage comparator CMP5, voltage comparator CMP6; the first input terminal of the voltage comparator CMP1, the first input terminal of the voltage comparator CMP2, the first input terminal of the voltage comparator CMP3, the first input terminal of the switch G1 After the ports are combined, the DP interface and the first port of the switch G2 are connected; the first input terminal of the voltage comparator CMP4, the first input terminal of the voltage comparator CMP5, the voltage comparator CMP6 The first input end and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2; the output end of the voltage comparator CMP1 and the output end of the voltage comparator CMP2 , The output terminal of the voltage comparator CMP3, the output terminal of the voltage comparator CMP4, the output terminal of the voltage comparator CMP5, and the output terminal of the voltage comparator CMP6 are connected to the charging logic control module.

Among them, the voltage comparator CMP1, the voltage comparator CMP2, the voltage comparator CMP3 are used to detect the voltage on the DP interface, the voltage comparator CMP4, the voltage comparator CMP5, and the voltage comparator CMP6 are used to detect the voltage on the DM interface, and the charging logic The control module can determine the voltages on the DP interface and the DM interface respectively according to the voltage detection result of the comparator.

2, in this example, the first voltage detection module further includes: a data selector D1 and a data selector D2, and the second voltage detection module further includes: a data selector D3 and a data selector D4;

The second input terminal of the voltage comparator CMP1 is connected to the output terminal of the data selector D1, the second input terminal of the voltage comparator CMP2 is connected to the output terminal of the data selector D2, and the voltage comparator CMP3 The input voltage of the second input terminal of the data selector D1 is the first input voltage, the input voltage of the first input terminal of the data selector D1 is the second input voltage, and the input voltage of the second input terminal of the data selector D1 is the third input voltage , the input voltage of the first input terminal of the data selector D2 is the fourth input voltage, and the input voltage of the second input terminal of the data selector D2 is the fifth input voltage;

The second input terminal of the voltage comparator CMP4 is connected to the output terminal of the data selector D3, the second input terminal of the voltage comparator CMP5 is connected to the output terminal of the data selector D4, and the voltage comparator CMP6 The input voltage of the second input terminal of the data selector D3 is the sixth input voltage, the input voltage of the first input terminal of the data selector D3 is the seventh input voltage, the input voltage of the second input terminal of the data selector D3 is the eighth input voltage, The input voltage of the first input terminal of the data selector D4 is the ninth input voltage, and the input voltage of the second input terminal of the data selector D4 is the tenth input voltage.

Wherein, the first input voltage and the sixth input voltage may be 0.325V, the second input voltage and the seventh input voltage may be 2.9V, the third input voltage, the fourth input voltage, the eighth input voltage and the ninth input voltage may be is 2.0V, the fifth input voltage may be 1.2V, and the tenth input voltage may be 1.5V.

One input terminal of the voltage comparator is connected to the output terminal of a data selector, and the voltage values of the two input terminals of the data selector are different, that is to say, one input terminal of the voltage comparator can be selected to be connected to different input voltages , so that the detection of voltages in different voltage value ranges can be realized through the same voltage detection module.

For example, when the input voltage of the second input terminal of the voltage comparator CMP2 is 2.0V (that is, the selection of the data selector D2 is 2.0V), and the input voltage of the second input terminal of the voltage comparator CMP3 is 0.325V, the first voltage detection The module can detect voltages less than 0.325V, 0.325V～2.0V, and voltages greater than 2.0V (determined by the outputs of the voltage comparator CMP2 and the voltage comparator CMP3), and when the input of the second input terminal of the voltage comparator CMP2 When the voltage is 1.2V (that is, the data selector D2 selects 1.2V), the first voltage detection module can detect voltages less than 0.325V, voltages between 0.325V and 1.2V, and voltages greater than 1.2V.

In the specific implementation, when different fast charging protocol modes are used to fast charge the load device, the voltage selected by the input terminal of the voltage comparator may also be different. For example, when the DCP fast charging protocol is adopted, the input voltage of the second input terminals of the voltage comparator CMP1 and the voltage comparator CMP4 can be 2.9V, and the input voltage of the second input terminal of the voltage comparator CMP2 and the voltage comparator CMP5 can be 2.0V.

When the handshake between the charging logic module and the load device QC is successful, and it is confirmed that the QC fast charging protocol needs to be adopted, the input voltage of the voltage comparator CMP1 and the voltage comparator CMP4 can be set to 2.0V. Therefore, the charging logic control module can control the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module, wherein the relationship between the voltage of the DP interface and the DM interface and the VBUS output voltage is shown in Table 1 below.

The adapter voltage is the VBUS output voltage, the first input terminal of each voltage comparator is the non-inverting input terminal, and the second input terminal is the inverting input terminal. When the voltage of the non-inverting input terminal of the voltage comparator is greater than the voltage of the inverting input terminal , the signal at the output of the voltage comparator is 0, otherwise it is 1.

For example, when the output signals of the voltage comparator CMP1 and the voltage comparator CMP3 are 0 and 1 respectively, and the output information of the voltage comparator CMP4 and the voltage comparator CMP6 are both 1, the charging logic control module adjusts the output of the VBUS interface The voltage is 5V. When the DP interface voltage and the DM interface voltage are both 0V, the adapter voltage is default and the default state is maintained. When the DP interface voltage is 0.6V and the DM interface voltage is 3.3V, the adapter voltage is Continuous mode, namely QC3. 0 mode.

Table 1 QC protocol output voltage control logic table

In a possible example, referring to FIG. 3 , the multi-fast charging protocol control circuit further includes: a first data voltage output module and a second data voltage output module;

The charging logic control module is connected to the control port of the first data voltage output module, the control port of the second data voltage output module, the first port of the first data voltage output module, the first voltage detection module The second port of the module and the first port of the switch G1 are combined and connected to the DP interface and the first port of the switch G2, and the second data voltage outputs the first port of the module, the second voltage The second port of the detection module and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2;

The first data voltage output module is used to provide the output voltage of the DP interface, the second data voltage output module is used to provide the output voltage of the DM interface, and the charging logic control module is further used to control the The output voltage of the first data voltage output module and the second data voltage output module.

In specific implementation, the charging logic control module may control the output voltages of the two data voltage output modules to control the two data voltage output modules to output a voltage with a specific voltage value to the DP interface or the DM interface, or control the two data voltage output modules. Do not output voltage to the outside.

Specifically, when the multi-fast charging protocol control circuit adopts the DCP mode for charging, the charging logic control module can notify the load device of the specific fast charging mode by controlling the output voltages of the two data voltage output modules, for example, by controlling the first data voltage The voltages output by the output module and the second data voltage output module to the DP interface and the DM interface are both 2.7V, and the load device is notified to adopt the APPLE2.4A mode.

In this example, referring to FIG. 4 , the first data voltage output module includes a data selector D5 and an analog switch OP1, and the second data voltage output module includes a data selector D6 and an analog switch OP2;

The input voltage of the first input terminal of the data selector D5 is the eleventh input voltage, the input voltage of the second input terminal of the data selector D5 is the twelfth input voltage, and the output terminal of the data selector D5 is connected to The first port of the analog switch OP1, the second port of the analog switch OP1, the second port of the first voltage detection module, and the first port of the switch G1 are combined and connected to the DP interface and all the first port of the switch G2, the charging logic control module is connected to the control port of the data selector D5 and the control port of the analog switch OP1;

The input voltage of the first input terminal of the data selector D6 is the thirteenth input voltage, the input voltage of the second input terminal of the data selector D6 is the fourteenth input voltage, and the output terminal of the data selector D6 is connected to The first port of the analog switch OP2, the second port of the analog switch OP2, the second port of the second voltage detection module, and the first port of the switch G3 are combined and connected to the DM interface and all The second port of the switch G2, the charging logic control module is connected to the control port of the data selector D6 and the control port of the analog switch OP2.

Wherein, the eleventh input voltage and the thirteenth input voltage may be 2.7V, and the twelfth input voltage and the fourteenth input voltage may be 2.0V.

In specific implementation, the charging logic control module can respectively control whether the first data voltage output module and the second voltage output module output data voltage through the control ports of the two analog switches, and can control the two data selectors D5 and D6, the values of the output voltages of the above two data voltage output modules can be controlled respectively. For example, the charging logic control module controls the data selector D5 to select a voltage of 2.7V, and controls the analog switch OP1 to open, then the first data voltage output module can output a voltage of 2.7V to the DP interface. When the DCP fast charging protocol is adopted, the charging logic control module can control the output voltage values of the above two data voltage output modules according to the specific fast charging mode. Specifically, the output voltage values of the two data voltage output modules are related to the fast charging mode. The corresponding relationship of the modes can be: the output voltage of the first data voltage output module is 2.0V, the output voltage of the second data voltage output module is 2.7V, corresponding to the APPLE 1A fast charging mode; the output voltage of the first data voltage output module is 2.7V, the output voltage of the second data voltage The output voltage of the voltage output module is 2.0V, corresponding to the APPLE 2A fast charging mode; the output voltage of the first data voltage output module is 2.7V, and the output voltage of the second data voltage output module is 2.7V, corresponding to the APPLE 2.4A fast charging mode.

In a possible example, referring to FIG. 5 , the multi-fast charging protocol control circuit further includes: a resistor R1, a resistor R2, an NMOS transistor N1, and an NMOS transistor N2;

The first port of the resistor R1, the second port of the first voltage detection module, and the first port of the switch G1 are combined to connect to the DP interface and the first port of the switch G2, and the resistor The second port of R1 is connected to the drain of the NMOS transistor N1, and the source of the NMOS transistor N1 is grounded;

The first port of the resistor R2, the second port of the second voltage detection module, and the first port of the switch G3 are combined to connect to the DM interface and the second port of the switch G2, and the resistor The second port of R2 is connected to the drain of the NMOS transistor N2, and the source of the NMOS transistor N2 is grounded;

The charging logic control module is connected to the gate of the NMOS transistor N1 and the gate of the NMOS transistor N2;

The charging logic control module is further configured to control the gate voltage of the NMOS transistor N1 and the gate voltage of the NMOS transistor N2.

Among them, resistor R1 and resistor R2 can be used as bleeder resistors. By setting resistor R1 and resistor R2, it can match the impedance requirements of the DP interface or DM interface in the charging specification corresponding to the DCP fast charging protocol.

In the specific implementation, the charging logic control module can control the conduction state of the NMOS transistor N1 and the NMOS transistor N2 by controlling the gate voltages of the NMOS transistor N1 and the NMOS transistor N2, thereby realizing the control of whether the resistor R1 and the resistor R2 are grounded. .

For example, when the DM resistor needs to be pulled down, that is, the resistor R2 needs to be grounded, the charging logic control module can make the NMOS transistor N2 turn on by controlling the gate voltage of the NMOS transistor N2.

In a possible example, the charging logic control module includes an S0 port, an S1 port, and an S2 port;

The S0 port is connected to the control port of the switch G1, the S1 port is connected to the control port of the switch G2, and the S2 port is connected to the control port of the switch G3;

The charging logic control module is configured to control the on-off of the switch G1 through the S0 port, control the on-off of the switch G2 through the S1 port, and control the on-off of the switch G3 through the S2 port.

In a possible example, the charging logic control module includes an S3 port, an S4 port, an S5 port, and an S6 port;

The S3 port is connected to the control port of the data selector D1, the S4 port is connected to the control port of the data selector D2, the S5 port is connected to the control port of the data selector D3, and the S6 port is connected the control port of the data selector D4;

The charging logic control module is used to control the voltage selected by the data selector D1 through the S3 port, control the voltage selected by the data selector D2 through the S4 port, and control the input voltage through the S5 port. The data selector D3 selects the input voltage, and controls the data selector D4 to select the input voltage through the S6 port.

In a possible example, the charging logic control module includes an S7 port, an S8 port, an S9 port, and an S10 port;

The S7 port is connected to the control port of the data selector D5, the S8 port is connected to the control port of the analog switch OP1, the S9 port is connected to the control port of the data selector D6, and the S10 port is connected to all The control port of the analog switch OP2;

The charging logic control module is used to control the voltage of the data selector D5 to select the input through the S7 port, to control the voltage of the data selector D6 to select the input through the S9 port, and to control the voltage of the data selector D6 to select the input through the S8 port. The on-off of the analog switch OP1 is controlled, and the on-off of the analog switch OP2 is controlled through the S10 port.

In a possible example, the charging logic control module includes an S11 port and an S12 port;

The S11 port is connected to the gate of the NMOS transistor N1, and the S12 port is connected to the gate of the NMOS transistor N2;

The charging logic control module is configured to control the gate voltage of the NMOS transistor N1 through the S11 port, and control the gate voltage of the NMOS transistor N2 through the S12 port.

Specifically, referring to FIG. 6 , in practical applications, the multi-fast charging protocol control circuit can be specifically shown in FIG. 6 . The multi-fast charging protocol control circuit includes: a charging logic control module, an analog switch OP1, an analog switch OP2, a switch G1, Switch G2, Switch G3, Data Selector D1, Data Selector D2, Data Selector D3, Data Selector D4, Data Selector D5, Data Selector D6, Voltage Comparator CMP1, Voltage Comparator CMP2, Voltage Comparator CMP3 , voltage comparator CMP4, voltage comparator CMP5, voltage comparator CMP6, AFSCP sending module, VOOC sending module, resistor R1, resistor R2, NMOS tube N1, NMOS tube N2, DP interface, DM interface, VBUS interface, GND interface, Timer module; the charging logic control module includes S0 port, S1 port, S2 port, S3 port, S4 port, S5 port, S6 port, S7 port, S8 port, S9 port, S10 port, S11 port, S12 port.

The charging logic module is connected to the output terminal of the voltage comparator CMP1, the output terminal of the voltage comparator CMP2, the output terminal of the voltage comparator CMP3, the output terminal of the voltage comparator CMP4, the output terminal of the voltage comparator CMP5, and the voltage comparator CMP6. The output end, VBUS interface, GND interface, timer module, the first port of the VOOC sending module, the first port of the AFSCP sending module;

The S3 port of the charging logic control module is connected to the control port of switch G1, the S4 port is connected to the control port of switch G2, the S8 port is connected to the control port of switch G3, the S9 port is connected to the control port of the data selector D1, and the S10 port is connected to the data selector D2 The control port of the S11 port is connected to the control port of the data selector D3, the S12 port is connected to the control port of the data selector D4, the S0 port is connected to the control port of the data selector D5, the S1 port is connected to the control port of the analog switch OP1, and the S5 port is connected to the control port of the data selector D5. The control port of the data selector D6, the S6 port is connected to the control port of the analog switch OP2, the S2 port is connected to the gate of the NMOS transistor N1, and the S7 port is connected to the gate of the NMOS transistor N2;

The input voltage of the first input end of the data selector D5 is 2.7V, the input voltage of the second input end of the data selector D5 is 2.0V, and the output end of the data selector D5 is connected to the first port of the analog switch OP1; the data selector D6 The input voltage of the first input end of the data selector D6 is 2.7V, the input voltage of the second input end of the data selector D6 is 2.0V, and the output end of the data selector D6 is connected to the first port of the analog switch OP2;

The second port of the analog switch OP1, the first input end of the voltage comparator CMP1, the first input end of the voltage comparator CMP2, the first input end of the voltage comparator CMP3, the first port of the resistor R1, the first port of the switch G1 After the ports are combined, connect the DP interface and the first port of the switch G2, the second port of the analog switch OP2, the first input end of the voltage comparator CMP4, the first input end of the voltage comparator CMP5, and the first input end of the voltage comparator CMP6. The input end, the first port of the resistor R2, and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2;

The second input terminal of the voltage comparator CMP1 is connected to the output terminal of the data selector D1, the second input terminal of the voltage comparator CMP2 is connected to the output terminal of the data selector D2, and the input voltage of the second input terminal of the voltage comparator CMP3 is 0.325V , the input voltage of the first input terminal of the data selector D1 is 2.9V, the input voltage of the second input terminal of the data selector D1 is 2.0V, the input voltage of the first input terminal of the data selector D2 is 2.0V, and the data selector D2 The input voltage of the second input end of the voltage comparator CMP4 is connected to the output end of the data selector D3, the second input end of the voltage comparator CMP5 is connected to the output end of the data selector D4, and the voltage comparator The input voltage of the second input terminal of CMP6 is 0.325V, the input voltage of the first input terminal of the data selector D3 is 2.9V, the input voltage of the second input terminal of the data selector D3 is 2.0V, and the input voltage of the first input terminal of the data selector D4 is 2.0V. The input voltage of the second input terminal of the data selector D4 is 2.0V, and the input voltage of the second input terminal of the data selector D4 is 1.5V.

The second port of the resistor R1 is connected to the drain of the NMOS transistor N1, and the source of the NMOS transistor N1 is grounded; the second port of the resistor R2 is connected to the drain of the NMOS transistor N2, and the source of the NMOS transistor N2 is grounded;

The second port of the switch G1 is connected to the second port of the VOOC sending module, and the second port of the switch G3 is connected to the second port of the AFSCP sending module;

The charging logic control module can adjust the channel status of the multi-fast charging protocol control circuit according to the voltage detection result of the voltage detection module, the timing result of the timer module and the current on the VBUS interface, such as controlling the on-off of each switch, the switching of each selector. The output and the gate voltage of the NMOS transistor, etc., can communicate with the load device by adjusting the channel state (for example, by short-circuiting the DP and DM interfaces to notify the load device to adopt the DCP protocol, and detect the voltage value on the DP and DM to perform protocol handshake with the load device. Determine the fast charging protocol used, and control the VOOC sending module or AFSCP sending module to communicate with the load device with VOOC protocol or AFC/SCP/FCP protocol), and further use the corresponding fast charge protocol to quickly charge the load device through the VBUS interface. .

It can be seen that a multi-fast charging protocol control circuit provided by this application includes a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP transmission module, a VOOC transmission module, a DP interface, a DM interface, and a VBUS interface, GND interface, timer module, switch G1, switch G2, switch G3, and the charging logic control module is used to control the first voltage detection module and the second voltage detection module to detect the voltage of the DP interface and the DM interface, respectively, through the timer module. Carry out timing, control the on-off of switch G1, switch G2, and switch G3 according to the voltage detection result, timing result and the current of the VBUS interface, and use the corresponding communication protocol to communicate with the load device and charge the load device through the VBUS interface. It can be seen that the multi-fast charging protocol control circuit provided in this application can realize fast charging of various fast charging protocols, and when applied to a fast charging protocol chip, a single chip can support various fast charging protocols, and the application is flexible and cost saving. It is beneficial to solve the device compatibility problem caused by the fact that a single chip cannot support multiple fast charging protocols.

Example 2:

Referring to FIG. 7 , this embodiment provides a control method for a multi-fast charging protocol control circuit, which is applied to the multi-fast charging protocol control circuit in the above-mentioned Embodiment 1. The method includes:

S201, the charging logic control module adopts the DCP fast charging protocol by default, and controls the channel state of the multi-fast charging protocol control circuit to be a first state.

In the specific implementation, when the multi-fast charging protocol control circuit communicates with the load device through the fast charging protocol, the charging logic control module can use the DCP fast charging protocol by default, and the first state of the multi-fast charging protocol control circuit adopts the DCP protocol to Circuit state when the load device is fast charging.

S202, when the charging logic control module determines the voltage change of the DP interface or the DM interface according to the voltage detection results of the first voltage detection module and the second voltage detection module, the timer module starts to count time t1.

S203 , if the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the time t1, then after the time t1, the charging logic control module controls the multi-fast charging protocol The on state of the control circuit is the second state.

Wherein, in the second state, the switch G2 is closed, and the DP interface and the DM interface are short-circuited.

In S202 and 203, the charging logic control module determines that the voltage of the DP interface or the DM interface changes according to the voltage detection result, and it can be determined that the load device is connected, and then the switch G2 can be controlled to close, so that the DP interface and the DM interface are short-circuited, and the notification The fast charging protocol adopted by the load device is the DCP fast charging protocol.

S204, when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines the DP interface voltage according to the voltage detection result of the first voltage detection module Within the preset voltage range, the timer module starts to count time t2.

S205, if within the time t2, the charging logic control module determines, according to the voltage detection result of the first voltage detection module, that the voltage of the DP interface is always within the preset voltage range.

In S204 and S205, the load device can notify the fast charging protocol supported by the charging logic control module at the charging adapter end by loading the voltage of the preset voltage value on the DP interface or the DM interface, and the charging logic control module determines the load device according to the voltage detection result. Whether the voltage applied to the DP interface is within the preset voltage range, and then it is determined whether the subsequent fast charging protocol handshake steps need to be continued. The preset voltage range here can be determined by the QC fast charging protocol. If the charging logic control module determines that the voltage value on the DP interface is within the preset voltage range, the subsequent steps of the QC protocol handshake can be continued. In addition, since the DP interface and the DM interface are short-circuited at this time, the voltage of the DM interface actually changes with the voltage of the DP interface, and the voltages of the DP interface and the DM interface are the same.

S206, after the time t2, the charging logic control module controls the channel state of the multi-fast charging protocol control circuit to be a third state.

Wherein, in the third state, the switch G2 is disconnected, and the short circuit between the DP interface and the DM interface is disconnected.

S207, the charging logic control module controls the switch G1 and the switch G3 to close, and determines whether the DM interface is less than a first preset voltage value according to the voltage detection result of the second voltage detection module.

Wherein, the first preset voltage value may be 0.325V.

In the specific implementation, since the short connection between the DP interface and the DM interface is disconnected, the voltage of the DM interface will no longer change with the voltage of the DM interface, the NMOS transistor N2 is turned on, and the voltage value of the DM interface decreases.

S208, if yes, the timer module starts to count time t3.

S209, if within the time t3, the charging logic control module determines that the voltage of the DM interface is always lower than the first preset voltage value according to the voltage detection result of the second voltage detection module, then the QC handshake is successful , otherwise, the QC handshake fails.

S210, if the QC handshake is successful, after the time t3, detect whether an AFC/SCP/FCP data packet is received on the DM interface.

In the specific implementation, AFC data packets, SCP data packets, and FCP data packets correspond to different voltage pulse sequences, respectively, and the charging logic module detects whether AFC/SCP/FCP data packets are received on the DM interface. Specifically, according to the second voltage detection module The voltage detection result of the DM interface determines the voltage pulse sequence on the DM interface, and decodes the voltage pulse sequence to determine whether an AFC/SCP/FCP data packet is received.

S211, if received, perform AFC/SCP/FCP protocol communication with the load device through the AFSCP sending module.

In the specific implementation, since the voltage applied by the load device to the DM interface is different when the three fast charging protocols of AFC/SCP/FCP are used, the charging logic control module can determine what needs to be done with the load device according to the detected data packets. A fast charging protocol communication.

S212, if not received, the charging logic control module adopts the QC fast charging protocol, and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module.

S213, if the QC handshake fails, after the time t3, the charging logic control module detects whether the current of the VBUS interface is greater than a preset current value.

S214, if yes, the timer module starts to count time t4.

S215 , if within the time t4 , the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value, perform VOOC protocol communication with the load device through the VOOC sending module.

In a possible example, the method further includes: when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module changes according to the first voltage detection module The voltage detection result of the voltage detection module determines that the DP interface voltage is not within the preset voltage range; or, if within the time t2, the charging logic control module detects the voltage according to the first voltage detection module As a result, it is determined that the voltage of the DP interface is not within the preset voltage range; then the charging logic control module controls the channel state of the multi-fast charging protocol control circuit to be the second state.

In the specific implementation, if the voltage applied by the load device to the DP interface does not meet the relevant requirements of the QC fast charging protocol, the charging logic control module can control the channel state of the multi-fast charging protocol control circuit to return to the short-circuited state of the DP interface and the DM interface. status, re-detect the voltage of the DP interface, when it is detected that the voltage of the DP interface meets the relevant requirements of the QC fast charging protocol, you can continue to the next steps.

In a possible example, when the voltage change of the DP interface or the DM interface is determined, after the timer module starts to count the time t1, the method further includes: if the first voltage is within the time t1 When the voltage detection results of the detection module and the second voltage detection module change, the timer module is set to zero, and the time t1 is restarted.

In a possible example, the charging logic control module adopts the QC fast charging protocol, and adjusts the output voltage of the VBUS interface according to the voltage detection result of the voltage detection module, including:

The charging logic control module determines whether the voltage of the DM interface is greater than a second preset voltage value according to the voltage detection result of the second voltage detection module;

If not, adjusting the output voltage of the VBUS interface to the first output voltage value;

If so, determine whether the voltage of the DP interface is greater than a third preset voltage value according to the voltage detection result of the first voltage detection module;

If not, adjusting the output voltage of the VBUS interface to the second output voltage value;

If so, determine whether the voltage of the DM interface is greater than a fourth preset voltage value according to the voltage detection result of the second voltage detection module;

If so, adjust the output voltage of the VBUS interface to a third output voltage value;

If not, adjusting the output voltage of the VBUS interface to be the fourth output voltage value;

After each adjustment of the output voltage of the VBUS interface, determine whether the voltage of the DP interface is greater than a fifth preset voltage value according to the voltage detection result of the first voltage detection module;

If so, execute the step of judging whether the voltage of the DM interface is greater than the second preset voltage value according to the voltage detection result of the second voltage detection module;

If not, the charging logic control module adopts the DCP fast charging protocol, and controls the channel state of the multi-fast charging protocol circuit to be the first state.

In specific implementation, the second preset voltage value and the fifth preset voltage value may be 0.325V, the third preset voltage value and the fourth preset voltage value may be 2V, the first output voltage value may be 5V, and the second preset voltage value may be 5V. The output voltage value may be 12V, the third output voltage value may be 20V, and the fourth output voltage value may be 9V.

In practical application, referring to FIG. 8 , the control method of the multi-fast charging protocol control circuit of the present application may specifically include the following steps, which may be specifically applied to the multi-fast charging protocol control circuit shown in FIG. 6 :

Step 1. Start, go to Step 2.

Step 2. The APPLE 2.4A mode is adopted by default, and step 3 is executed.

Among them, when the APPLE 2.4A mode is adopted by default, the charging logic controller controls the input voltage of the analog switch OP1 and the analog switch OP2 to select 2.7V by default, and the voltage of the second input terminal of the voltage comparator CMP1 and the voltage comparator CMP4 is selected 2.9V, The voltage of the second input terminal of the voltage comparator CMP5 is 1.5V, and the analog switch OP1 and the analog switch OP2 are turned on.

Among them, when the analog switch is turned on, through the control of the data selectors D5 and D6, the voltage can be output to the DP interface or the DM interface, and when the analog switch is turned off, no voltage can be output to the DP interface and the DM interface. The charging logic module controls each component through the port corresponding to each component, for example, controls the data selector D1 and the data selector D3 through the S9 port and the S11 port, so that the second input of the voltage comparator CMP1 and the voltage comparator CMP4 The terminal voltages are all selected at 2.9V. In practical applications, the voltage of the second input terminal of the voltage comparator CMP5 can also be 2.0V. Through the voltage setting of the input terminal of the voltage comparator, the charging logic control module can determine whether a load device is inserted according to the output signal of each voltage comparator. .

When the DCP fast charging protocol is used for fast charging, the multi-fast charging protocol control module can specifically control the voltage output by the two analog switches to the DP interface and the DM interface to notify the fast charging mode adopted by the load device, such as the above-mentioned analog switches OP1 and DM. The voltages output by the analog switch OP2 to the DP interface and the DM interface are both 2.7V, which means that the load device is notified that the APPLE 2.4A fast charge mode is used.

Step 3. If the voltage change of the DP interface or the DM interface is detected, go to Step 4.

In the specific implementation, the charging logic control module detects the voltage change of the DP interface or the DM interface through the output signal of each voltage comparator. When the voltage change of the DP interface or the DM interface is detected, that is, as long as the output signal of one voltage comparator jumps , it can be determined that a loaded device is connected.

Step 4 , start the timer module to start timing t1 , and perform step 5 .

In the specific implementation, when the output signal of any voltage comparator jumps, the timer module is set to 0 and starts to count the time t1 again.

Step 5: Determine whether the time t1 time counted by the timer module is over, if yes, go to Step 6, otherwise continue to go to Step 5.

Step 6. Adjust the channel status of the multi-fast charging protocol control circuit, short-circuit the DP interface and the DM interface, and go to Step 7.

In the specific implementation, the charging logic control module controls the switch G2 to be closed, the DP interface and the DM interface are short-circuited, and also controls the analog switch OP1 and the analog switch OP2 to close, and controls the voltage comparator CMP2 to select the second input terminal voltage of 1.2V, and the voltage comparison The voltage of the second input terminal of the comparator CMP4 is selected as 2.0V, and the voltage of the second input terminal of the voltage comparator CMP5 is selected as 1.5V.

In addition, in step 6, the charging logic control module can also control the gate voltage of the NMOS transistor N1 so that the NMOS transistor N1 is turned on, the pull-down of the DP resistor is turned on, and one end of the resistor R1 is grounded.

Among them, the selection of the voltage of the second input terminal of the voltage comparator CMP4 and the voltage comparator CMP5 can be used to subsequently detect whether the FCP/SCP/AFC data packet is received on the DM interface. This is because the above three types of FCP, SCP and AFC are used. During the fast charging protocol, the voltage applied by the load device to the DM interface is different, so different fast charging protocols can be identified through the voltage comparator CMP4 and the voltage comparator CMP5.

Step 7. Determine whether the DP interface voltage is greater than 0.325V and less than 2V. If so, go to Step 8; otherwise, return to Step 6.

In this example, step 7 is performed when a voltage jump of the DP interface or the DM interface is detected.

Step 8. Start the timer module to start timing for 1.25S, and go to Step 9.

Step 9. Determine whether the voltage of the DP interface is greater than 0.325V and less than 2V. If so, go to Step 10, otherwise, return to Step 6.

Step 10: Determine whether the timer module reaches the timing time of 1.25S, if so, go to Step 11, otherwise, return to Step 9.

Among them, the above steps 7 to 10 determine whether the voltage of the DP interface is greater than 0.325V and less than 2V for 1.25S. If the DP voltage detected within 1.25S of the timer module is always greater than 0.325V and less than 2.0V, Then, after the timer module reaches the timing time of 1.25S, the subsequent step 11 is performed.

In the specific implementation, the charging adapter terminal short-circuits the DP interface and the DM interface, and after notifying the load device of the DCP protocol adopted, the load device can also communicate with the charging adapter terminal through the voltage on the DP interface and the DM interface. In step 10, it can be determined that the voltage loaded by the load device on the DP interface is greater than 0.325V and less than 2.0V, wherein because the DP interface and the DM interface are short-circuited, the voltages of the DP interface and the DM interface are the same.

Step 11 , disconnect the short-circuit of the DP interface and the DM interface, control the NMOS transistor N2 to be turned on, turn on the pull-down of the DM resistor, and perform step 12 .

In the specific implementation, in step 11, the charging logic control module controls the switch G2 to be turned off, that is, the short circuit between the DP interface and the DM interface is disconnected, then the voltage of the DM interface will no longer change with the voltage of the DM interface, and the charging logic control module controls The gate voltage of the NMOS transistor N2 turns on the NMOS transistor N2, the resistor R2 is grounded, and the detected voltage value of the DM interface is maintained at a low level.

Step 12, determine whether the DM interface voltage is less than 0.325V, if yes, go to Step 13.

Step 13, determine whether the QC protocol handshake is successful, if yes, go to step 14, if not, go to step 23.

Among them, judging whether the handshake of the QC protocol is successful may specifically include: starting the timer module to start timing for 10mS, and detecting whether the voltage of the DM interface is less than 0.325V during the timing of 10mS, and if so, after the timer t3 time expires, determine the handshake of the QC protocol Success, otherwise, it is identified as QC protocol handshake failure.

Step 14: Determine whether AFC/SCP/FCP data packets are received on the DM interface, if yes, go to Step 27; otherwise, go to Step 15.

In the specific implementation, steps 15 to 21 are the process of communicating with the load device to determine the VBUS output voltage when the QC fast charging protocol is used to fast charge the load device.

Step 15, determine whether the DM interface voltage is greater than 0.325V, if yes, go to Step 17, otherwise go to Step 16.

Step 16 , determine that the QC fast charging request from the load device is received, request a 5V charging voltage, and perform step 22 .

In the specific implementation, the charging logic control module can determine the charging voltage requested by the load device according to the detected voltage values on the DP interface and the DM interface, and further, can control the VBUS to output the requested charging voltage to quickly charge the load device.

Step 17: Determine whether the DP interface voltage is greater than 2V, if yes, go to Step 19, otherwise go to Step 18.

Step 18: Determine that the QC fast charging request from the load device is received, request a 12V charging voltage, and perform step 22.

Step 19, determine whether the DM interface voltage is greater than 2V, if yes, go to Step 20, otherwise go to Step 21.

Step 20 , determine that a QC fast charging request from the load device is received, request a 20V charging voltage, and perform step 22 .

Step 21 , determine that the QC fast charging request from the load device is received, request a 9V charging voltage, and perform step 22 .

Step 22: Determine whether the voltage of the DP interface is greater than 0.325V, if so, go to Step 15; otherwise, return to Step 1.

In the specific implementation, if the charging logic control module determines that the voltage of the DP interface is not greater than 0.325V according to the voltage detection result, it will exit the QC fast charging mode, and control the channel state of the multi-fast charging protocol control circuit to return to the original APPLE 2.4A mode .

Step 23 , determine whether the VBUS interface current is greater than 1A, if yes, go to Step 24 , otherwise continue to go to Step 23 .

Step 24 , start the timer module to start timing for 2S, and execute step 25 .

Step 25: Determine whether the timer module has reached the timing time of 2S, if yes, go to Step 26, otherwise continue to go to Step 25.

Step 26 , perform VOOC protocol communication with the load device through the VOOC sending module.

Step 27: Perform AFC/SCP/FCP protocol communication with the load device through the AFSCP sending module.

It can be seen that the control method of the multi-fast charging protocol control circuit provided in this application is applied to the design of charging chips, and a single protocol chip can be compatible with multiple fast charging protocols, thereby saving chip design costs and chip application costs.

The above are only part of the embodiments of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made. It should be regarded as the protection scope of this application.

Claims

A multi-fast charging protocol control circuit, characterized in that it includes: a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP protocol module, a VOOC protocol module, a DP interface, a DM interface, a VBUS interface, a GND Interface, timer module, switch G1, switch G2, switch G3;

The charging logic control module is connected to the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module, and the AFSCP The first port of the sending module, the first port of the VOOC sending module, the control port of the switch G1, the control port of the switch G2 and the control port of the switch G3, the first port of the first voltage detection module. After the second port is combined with the first port of the switch G1, the DP interface is connected to the first port of the switch G2. The second port of the switch G1 is connected to the second port of the VOOC sending module. The second port of the second voltage detection module and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2, and the second port of the switch G3 is connected to the AFSCP sending module the second port;

The DP interface, the DM interface, the VBUS interface, and the GND interface are used to connect a load device, and the VOOC sending module is used to perform a VOOC protocol with the load device under the control of the charging logic control module communication, the AFSCP sending module is used for AFC/SCP/FCP protocol communication with the load device under the control of the charging logic control module, and the charging logic control module is used to control the first voltage detection module to detect The voltage of the DP interface, the second voltage detection module is controlled to detect the voltage of the DM interface, the timer module is used for timing, and the switch is controlled according to the voltage detection result, the timing result and the current of the VBUS interface G1, the switch G2 and the switch G3 are turned on and off to adjust the channel state of the multi-fast charging protocol control circuit, and use the corresponding communication protocol to communicate with the load device, and communicate with the load device through the VBUS interface. The load device is charged.
The multi-fast charging protocol control circuit according to claim 1, wherein the first voltage detection module comprises a voltage comparator CMP1, a voltage comparator CMP2, and a voltage comparator CMP3, and the second voltage detection module comprises a voltage comparator CMP1, a voltage comparator CMP2, and a voltage comparator CMP3 Comparator CMP4, voltage comparator CMP5, voltage comparator CMP6;

The first input terminal of the voltage comparator CMP1, the first input terminal of the voltage comparator CMP2, the first input terminal of the voltage comparator CMP3, and the first port of the switch G1 are combined and connected to the DP interface and the first port of the switch G2;

The first input terminal of the voltage comparator CMP4, the first input terminal of the voltage comparator CMP5, the first input terminal of the voltage comparator CMP6, and the first port of the switch G3 are combined and connected to the a DM interface and the second port of the switch G2;

the output terminal of the voltage comparator CMP1, the output terminal of the voltage comparator CMP2, the output terminal of the voltage comparator CMP3, the output terminal of the voltage comparator CMP4, the output terminal of the voltage comparator CMP5, The output end of the voltage comparator CMP6 is connected to the charging logic control module.
The multi-fast charging protocol control circuit according to claim 2, wherein the first voltage detection module further comprises: a data selector D1 and a data selector D2, and the second voltage detection module further comprises: a data selector D3, data selector D4;

The second input terminal of the voltage comparator CMP1 is connected to the output terminal of the data selector D1, the second input terminal of the voltage comparator CMP2 is connected to the output terminal of the data selector D2, and the voltage comparator CMP3 The input voltage of the second input terminal of the data selector D1 is the first input voltage, the input voltage of the first input terminal of the data selector D1 is the second input voltage, and the input voltage of the second input terminal of the data selector D1 is the third input voltage , the input voltage of the first input terminal of the data selector D2 is the fourth input voltage, and the input voltage of the second input terminal of the data selector D2 is the fifth input voltage;

The second input terminal of the voltage comparator CMP4 is connected to the output terminal of the data selector D3, the second input terminal of the voltage comparator CMP5 is connected to the output terminal of the data selector D4, and the voltage comparator CMP6 The input voltage of the second input terminal of the data selector D3 is the sixth input voltage, the input voltage of the first input terminal of the data selector D3 is the seventh input voltage, the input voltage of the second input terminal of the data selector D3 is the eighth input voltage, The input voltage of the first input terminal of the data selector D4 is the ninth input voltage, and the input voltage of the second input terminal of the data selector D4 is the tenth input voltage.
The multi-fast charging protocol control circuit according to claim 1, wherein the multi-fast charging protocol control circuit further comprises: a first data voltage output module and a second data voltage output module;

The charging logic control module is connected to the control port of the first data voltage output module, the control port of the second data voltage output module, the first port of the first data voltage output module, the first voltage detection module The second port of the module and the first port of the switch G1 are combined and connected to the DP interface and the first port of the switch G2, and the second data voltage outputs the first port of the module, the second voltage The second port of the detection module and the first port of the switch G3 are combined and connected to the DM interface and the second port of the switch G2;

The first data voltage output module is used to provide the output voltage of the DP interface, the second data voltage output module is used to provide the output voltage of the DM interface, and the charging logic control module is further used to control the The output voltage of the first data voltage output module and the second data voltage output module.
The multi-fast charge protocol control circuit according to claim 4, wherein the first data voltage output module includes a data selector D5 and an analog switch OP1, and the second data voltage output module includes a data selector D6 and analog switch OP2;

The input voltage of the first input terminal of the data selector D5 is the eleventh input voltage, the input voltage of the second input terminal of the data selector D5 is the twelfth input voltage, and the output terminal of the data selector D5 is connected to The first port of the analog switch OP1, the second port of the analog switch OP1, the second port of the first voltage detection module, and the first port of the switch G1 are combined and connected to the DP interface and all the first port of the switch G2, the charging logic control module is connected to the control port of the data selector D5 and the control port of the analog switch OP1;

The input voltage of the first input terminal of the data selector D6 is the thirteenth input voltage, the input voltage of the second input terminal of the data selector D6 is the fourteenth input voltage, and the output terminal of the data selector D6 is connected to The first port of the analog switch OP2, the second port of the analog switch OP2, the second port of the second voltage detection module, and the first port of the switch G3 are combined and connected to the DM interface and all The second port of the switch G2, the charging logic control module is connected to the control port of the data selector D6 and the control port of the analog switch OP2.
The multi-fast charging protocol control circuit according to claim 1, wherein the multi-fast charging protocol control circuit further comprises: a resistor R1, a resistor R2, an NMOS transistor N1, and an NMOS transistor N2;

The first port of the resistor R1, the second port of the first voltage detection module, and the first port of the switch G1 are combined to connect to the DP interface and the first port of the switch G2, and the resistor The second port of R1 is connected to the drain of the NMOS transistor N1, and the source of the NMOS transistor N1 is grounded;

The first port of the resistor R2, the second port of the second voltage detection module, and the first port of the switch G3 are combined to connect to the DM interface and the second port of the switch G2, and the resistor The second port of R2 is connected to the drain of the NMOS transistor N2, and the source of the NMOS transistor N2 is grounded;

The charging logic control module is connected to the gate of the NMOS transistor N1 and the gate of the NMOS transistor N2;

The charging logic control module is also used to control the gate voltage of the NMOS transistor N1 and the gate voltage of the NMOS transistor N2.
The multi-fast charging protocol control circuit according to claim 1, wherein the charging logic control module comprises an S0 port, an S1 port, and an S2 port;

The S0 port is connected to the control port of the switch G1, the S1 port is connected to the control port of the switch G2, and the S2 port is connected to the control port of the switch G3;

The charging logic control module is configured to control the on-off of the switch G1 through the S0 port, control the on-off of the switch G2 through the S1 port, and control the on-off of the switch G3 through the S2 port.
The multi-fast charging protocol control circuit according to claim 3, wherein the charging logic control module comprises an S3 port, an S4 port, an S5 port, and an S6 port;

The S3 port is connected to the control port of the data selector D1, the S4 port is connected to the control port of the data selector D2, the S5 port is connected to the control port of the data selector D3, and the S6 port is connected the control port of the data selector D4;

The charging logic control module is used to control the voltage selected by the data selector D1 through the S3 port, control the voltage selected by the data selector D2 through the S4 port, and control the input voltage through the S5 port. The data selector D3 selects the input voltage, and controls the data selector D4 to select the input voltage through the S6 port.
The multi-fast charging protocol control circuit according to claim 5, wherein the charging logic control module comprises an S7 port, an S8 port, an S9 port, and an S10 port;

The S7 port is connected to the control port of the data selector D5, the S8 port is connected to the control port of the analog switch OP1, the S9 port is connected to the control port of the data selector D6, and the S10 port is connected to all The control port of the analog switch OP2;

The charging logic control module is used to control the voltage of the data selector D5 to select the input through the S7 port, to control the voltage of the data selector D6 to select the input through the S9 port, and to control the voltage of the data selector D6 to select the input through the S8 port. The on-off of the analog switch OP1 is controlled, and the on-off of the analog switch OP2 is controlled through the S10 port.
The multi-fast charging protocol control circuit according to claim 6, wherein the charging logic control module comprises an S11 port and an S12 port;

The S11 port is connected to the gate of the NMOS transistor N1, and the S12 port is connected to the gate of the NMOS transistor N2;

The charging logic control module is configured to control the gate voltage of the NMOS transistor N1 through the S11 port, and control the gate voltage of the NMOS transistor N2 through the S12 port.
A method for controlling a multi-quick charging protocol control circuit, wherein the multi-quick charging protocol control circuit comprises the multi-quick charging protocol control circuit according to any one of claims 1-10, and the method comprises the following steps :

When performing fast charging protocol communication with the load device through the multi-fast charging protocol control circuit, the charging logic control module adopts the DCP fast charging protocol by default, and controls the channel state of the multi-fast charging protocol control circuit to be the first state;

When the charging logic control module determines the voltage change of the DP interface or the DM interface according to the voltage detection result of the first voltage detection module or the second voltage detection module, the timer module starts to count the time t1;

If the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the t1 time period, the charging logic control module controls the multi-fast charging protocol control circuit after the t1 time period The channel state of , is the second state, the switch G2 is closed, and the DP interface and the DM interface are short-circuited;

When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines, according to the voltage detection result of the first voltage detection module, that the DP interface voltage is Within the set voltage range, the timer module starts to count the time t2;

If within the time t2, the charging logic control module determines that the voltage of the DP interface is always within the preset voltage range according to the voltage detection result of the first voltage detection module;

Then after the time t2, the charging logic control module controls the channel state of the multi-fast charging protocol control circuit to be the third state, the switch G2 is turned off, and the short circuit between the DP interface and the DM interface is disconnected. ;

The charging logic control module controls the switch G1 and the switch G3 to close, and judges whether the DM interface is less than a first preset voltage value according to the voltage detection result of the second voltage detection module;

If so, the timer module starts timing t3 time;

If within the time t3, the charging logic control module determines that the voltage of the DM interface is always less than the first preset voltage value according to the voltage detection result of the second voltage detection module, then the QC handshake is successful; otherwise, the QC handshake is successful. , QC handshake failed;

If the QC handshake is successful, then after the time t3, detect whether the AFC/SCP/FCP data packet is received on the DM interface;

If received, communicate with the load device through AFC/SCP/FCP protocol through the AFSCP sending module;

If not received, the charging logic control module adopts the QC fast charging protocol, and adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module;

If the QC handshake fails, after the time t3, the charging logic control module detects whether the current of the VBUS interface is greater than the preset current value;

If so, the timer module starts timing t4 time;

If within the time t4, the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value, the VOOC sending module communicates with the load device through the VOOC protocol.
The method according to claim 11, wherein the method further comprises:

When the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines the DP interface according to the voltage detection result of the first voltage detection module The voltage is not within the preset voltage range; or,

If within the time t2, the charging logic control module determines that the voltage of the DP interface is not within the preset voltage range according to the voltage detection result of the first voltage detection module;

Then, the charging logic control module controls the channel state of the multi-fast charging protocol control circuit to be the second state.
The method according to claim 11 or 12, wherein when the voltage change of the DP interface or the DM interface is determined, after the timer module starts to count time t1, the method further comprises:

If the voltage detection results of the first voltage detection module and the second voltage detection module change within the time t1, the timer module is set to zero, and the time t1 is restarted.
The method according to claim 11, wherein the charging logic control module adopts a QC fast charging protocol, and adjusts the output voltage of the VBUS interface according to the voltage detection result of the voltage detection module, comprising:

The charging logic control module determines whether the voltage of the DM interface is greater than a second preset voltage value according to the voltage detection result of the second voltage detection module;

If not, adjusting the output voltage of the VBUS interface to the first output voltage value;

If so, determine whether the voltage of the DP interface is greater than a third preset voltage value according to the voltage detection result of the first voltage detection module;

If not, adjusting the output voltage of the VBUS interface to the second output voltage value;

If so, determine whether the voltage of the DM interface is greater than a fourth preset voltage value according to the voltage detection result of the second voltage detection module;

If so, adjust the output voltage of the VBUS interface to a third output voltage value;

If not, adjusting the output voltage of the VBUS interface to be the fourth output voltage value;

After each adjustment of the output voltage of the VBUS interface, determine whether the voltage of the DP interface is greater than a fifth preset voltage value according to the voltage detection result of the first voltage detection module;

If so, execute the step of judging whether the voltage of the DM interface is greater than the second preset voltage value according to the output signal of the first voltage comparator;

If not, the charging logic control module adopts the DCP fast charging protocol, and controls the channel state of the multi-fast charging protocol circuit to be the first state.
A multi-quick charging protocol control chip, characterized in that it includes the multi-quick charging protocol control circuit according to any one of claims 1-10.
An electronic device, characterized in that, the electronic device comprises the multi-fast charge protocol control chip as claimed in claim 15 .