CN112803558A

CN112803558A - Multi-quick-charging-protocol control circuit, control method, chip and electronic equipment

Info

Publication number: CN112803558A
Application number: CN202110385000.8A
Authority: CN
Inventors: 汤厚涛
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-05-14
Anticipated expiration: 2041-04-09
Also published as: CN112803558B; WO2022214083A1; CN115207999A

Abstract

The application provides a how fast protocol control circuit that fills, including the logical control module that charges, first voltage detection module, second voltage detection module, AFSCP send module, VOOC send module, the DP interface, the DM interface, the VBUS interface, the GND interface, the timer module, switch G1, switch G2, switch G3, the logical control module that charges is used for controlling voltage detection module to detect the DP interface, the voltage of DM interface, time through the timer module, according to the voltage detection result, the break-make of each switch of current control of timing result and VBUS interface, and adopt corresponding communication protocol and load equipment to communicate, and charge to load equipment through the VBUS interface. The multi-fast-charging protocol control circuit can achieve fast charging of various fast-charging protocols, can be applied to a fast-charging protocol chip to enable a single chip to support various fast-charging protocols, is flexible to apply, and saves cost.

Description

Multi-quick-charging-protocol control circuit, control method, chip and electronic equipment

Technical Field

The present application relates to the field of fast charging technologies, and in particular, to a multi-fast charging protocol control circuit, a control method, a chip, and an electronic device.

Background

With the rapid popularization of the fast-charging technology, more and more mobile phone manufacturers provide their own private fast-charging protocols. Currently, the mainstream protocols in the market include various Fast Charging protocols such as a Fast Charging (QC) 3.0/2.0 Protocol, a Dedicated Charging Port (DCP) Protocol, a Fast Charging Protocol (FCP) Protocol, a Super Fast Charging (SCP) Protocol, and an Adaptive Fast Charging (AFC) Protocol. However, the conventional fast charging protocol chip usually only supports a single fast charging protocol, and fast charging of multiple fast charging protocols cannot be realized through a single fast charging protocol chip, so that partial mobile phones or electronic devices cannot be fast charged, and the problem of protocol compatibility exists.

Disclosure of Invention

The application provides a multi-fast-charging protocol control circuit, a control method, a chip and electronic equipment, and aims to solve the problem of protocol compatibility caused by the fact that a single fast-charging protocol chip cannot support multiple fast-charging protocols in a traditional fast-charging protocol chip.

In a first aspect, an embodiment of the present application provides a multi-fast charging protocol control circuit, which includes a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module, a VOOC sending module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, a switch G1, a switch G2, and a switch G3;

the charging logic control module is connected with the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module and the first port of the AFSCP transmission module, the first port of the VOOC transmission module, the control port of the switch G1, the control port of the switch G2 and the control port of the switch G3, the second port of the first voltage detection module is combined with the first port of the switch G1 and then connected to the DP interface and the first port of the switch G2, a second port of the switch G1 is connected to the second port of the VOOC sending module, a second port of the second voltage detecting module and the first port of the switch G3 are combined and then connected to the DM interface and the second port of the switch G2, the second port of the switch G3 is connected with the second port of the AFSCP sending module;

the DP interface, the DM interface, the VBUS interface and the GND interface are used for connecting a load device, the VOOC sending module is used for carrying out VOOC protocol communication with the load device under the control of the charging logic control module, the AFSCP sending module is used for carrying out AFC/SCP/FCP protocol communication with the load device under the control of the charging logic control module, the charging logic control module is used for controlling the first voltage detection module to detect the voltage of the DP interface and controlling the second voltage detection module to detect the voltage of the DM interface, timing is carried out through the timer module, the on-off of the switch G1, the switch G2 and the switch G3 is controlled according to the voltage detection result, the timing result and the current of the VBUS interface so as to adjust the on-off state of the multi-fast-charging protocol control circuit, and the corresponding communication protocol is adopted for communication with the load device, and charging the load device through the VBUS interface.

In a second aspect, the present application provides a control method for a multi-fast-charge protocol control circuit, where the multi-fast-charge protocol control circuit includes the multi-fast-charge protocol control circuit according to the first aspect, and the control method includes the following steps:

when the multi-rapid charging protocol control circuit is in rapid charging protocol communication with load equipment, a charging logic control module defaults to adopt a DCP rapid charging protocol and controls the access state of the multi-rapid charging protocol control circuit to be a first state;

when the charging logic control module determines the voltage change of the DP interface or the DM interface according to the voltage detection result of the first voltage detection module or the second voltage detection module, the timer module starts to time t 1;

if the voltage detection results of the first voltage detection module and the second voltage detection module are unchanged within the time t1, after the time t1, the charging logic control module controls the access state of the multi-fast-charging protocol control circuit to be a second state, a switch G2 is closed, and the DP interface and the DM interface are in short circuit;

when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the voltage of the DP interface is within a preset voltage range according to the voltage detection result of the first voltage detection module, the timer module starts to time t 2;

if the voltage of the DP interface is within the preset voltage range within the time t2, the charging logic control module determines that the voltage of the DP interface is always within the preset voltage range according to the voltage detection result of the first voltage detection module;

after the time t2, the charging logic control module controls the access state of the multi-fast charging protocol control circuit to be a third state, and the switch G2 is turned off to disconnect the short circuit between the DP interface and the DM interface;

the charging logic control module controls the switch G1 and the switch G3 to be closed, and judges whether the DM interface is smaller than a first preset voltage value or not according to the voltage detection result of the second voltage detection module;

if yes, the timer module starts to time t 3;

if the charging logic control module determines that the voltage of the DM interface is always smaller than the first preset voltage value according to the voltage detection result of the second voltage detection module within the time t3, the QC handshake is successful, otherwise, the QC handshake fails;

if the QC handshake is successful, detecting whether an AFC/SCP/FCP data packet is received on the DM interface after the time t 3;

if the AFSCP protocol is received, AFC/SCP/FCP protocol communication is carried out between the AFSCP sending module and the load equipment;

if the voltage is not received, the charging logic control module adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module by adopting a QC quick charging protocol;

if the QC handshake fails, after the time t3, the charging logic control module detects whether the current of the VBUS interface is larger than a preset current value;

if yes, the timer module starts to time t 4;

and if the charging logic control module detects that the current of the VBUS interface is always larger than the preset current value in the t4 time, performing VOOC protocol communication with the load equipment through a VOOC sending module.

In a third aspect, the present application provides a multi-fast-charging protocol control chip, including the multi-fast-charging protocol control circuit according to the first aspect.

In a fourth aspect, the present application provides an electronic device, including the multi-fast charge protocol control chip according to the third aspect.

It can be seen that the present application provides a multi-fast charging protocol control circuit, which includes a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module, a VOOC sending module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, a switch G1, a switch G2, and a switch G3, where the charging logic control module is configured to control the first voltage detection module and the second voltage detection module to detect voltages of the DP interface and the DM interface, respectively, perform timing through the timer module, control on/off of the switch G1, the switch G2, and the switch G3 according to a voltage detection result, a timing result, and a current of the VBUS interface, communicate with a load device by using a corresponding communication protocol, and charge the load device through the VBUS interface. Therefore, the multi-fast-charging protocol control circuit can realize fast charging of various fast-charging protocols, can be applied to a fast-charging protocol chip to support various fast-charging protocols by a single chip, is flexible to apply and saves cost.

Drawings

FIG. 1 is a circuit schematic diagram of a multi-fast charge protocol control circuit provided herein;

FIG. 2 is a schematic circuit diagram of a voltage detection module provided herein;

FIG. 3 is a circuit schematic of another multi-rapid-charge protocol control circuit provided herein;

FIG. 4 is a circuit schematic diagram of a data voltage output module provided herein;

FIG. 5 is a circuit schematic of another multi-rapid-charge protocol control circuit provided herein;

FIG. 6 is a circuit schematic of another multi-rapid-charge protocol control circuit provided herein;

fig. 7 is a schematic flowchart illustrating a control method of a multi-fast charge protocol control circuit according to the present application;

fig. 8 is a schematic flowchart of another control method of a multi-fast charge protocol control circuit provided in the present application.

The present application is further described with reference to the following drawings and examples.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

Example 1:

referring to fig. 1, the present embodiment provides a multi-fast charging protocol control circuit, which includes a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module (i.e., an FCP/SCP/AFC protocol sending module), a flash charging VOOC sending module, a Data Positive signal (DP) interface, a Data negative signal (DM) interface, a voltage Positive VBUS interface, a voltage negative GND interface, a timer module, a switch G1, a switch G2, and a switch G3;

The multi-fast-charging protocol control circuit described in the embodiment of the present application may be applied to a fast-charging protocol control chip at a power adapter end.

Specifically, in the aspect of using the corresponding fast charging protocol to communicate with the load device, the charging logic control module may be specifically configured to control the VOOC sending module to perform VOOC protocol communication with the load device through the DP interface, and control the AFSCP sending module to perform AFC/SCP/FCP protocol communication with the load device through the DM interface.

The charging logic control module controls the two voltage detection modules (the first voltage detection module and the second voltage detection module) to detect the voltages of the DP interface and the DM interface, which may include configuring the voltage detection modules to detect the voltages of different value ranges through the same voltage detection module.

In specific implementation, when the multi-rapid-charging-protocol circuit is used for rapidly charging the load device, the charging logic control module may default to use one rapid-charging protocol as an initially-used rapid-charging protocol, and subsequently may determine whether to switch to use another rapid-charging protocol according to protocol communication with the load device, for example, the charging logic control module may default to use a DCP protocol, and may perform protocol handshake with the load device to determine whether to switch the rapid-charging protocol by adjusting a path state of the multi-rapid-charging-protocol control circuit after being connected with the load device.

For example, in a case of default adopting the DCP fast charging protocol, after the charging logic control module confirms that the charging logic control module is connected to the load device according to the voltage detection result of the voltage detection module (for example, after determining that the voltage of the DP interface or the DM interface is changed and is maintained for a period of time according to the voltage detection result of the first voltage detection module or the second voltage detection module), the charging logic control module may control the switch G2 to close, so that the DP interface and the DM interface are shorted, and the load device is notified that the DCP protocol is adopted.

After the load device detects that the DP interface and the DM interface are short-circuited, it can be determined that the power adapter adopts a DCP quick-charging protocol, if the load device needs to adopt other quick-charging protocols, the voltage output to the DP interface and the DM interface can be correspondingly controlled, and the charging logic control module can determine whether to switch the adopted quick-charging protocol according to the voltage detection result.

For example, the charging logic control module determines that the voltage value on the DP interface lasts for a specific time within a preset voltage value range according to the voltage detection result of the first voltage detection module, then may control the disconnection switch G2 to disconnect the short circuit between the DP interface and the DM interface, and enable the switch G1 and the switch G3 to perform the handshake of the QC protocol with the load device, specifically, may determine whether the QC handshake is successful by detecting whether the voltage on the DM interface meets the preset condition, because the switch G1 and the switch G3 are enabled, at this time, the AFSCP sending module and the VOOC sending module may perform the corresponding fast charging protocol communication with the load device through the DP interface and the DM interface under the control of the charging logic control module, if the QC handshake is successful, it may further determine whether to use the AFC/SCP/FCP fast charging protocol or the QC fast charging protocol according to whether the DM interface receives an AFC/SCP/FCP data packet, or after the QC handshake fails, determine whether the VOOC fast-charge protocol needs to be employed based on the current value on VBUS. After the adopted fast charging protocol is determined, the charging logic control module can adjust the output voltage on the VBUS according to the voltage detection result, and then fast charging supporting various fast charging protocols is realized through the multi-fast charging logic control circuit.

Specifically, when VOOC protocol communication or AFC/SCP/FCP protocol communication is performed with the load, the AFSCP transmitting module and the VOOC transmitting module are configured to transmit a signal (specifically, the charging logic control module may control the AFSCP transmitting module to output a specific voltage signal to the DM interface, and control the VOOC transmitting module to output a specific voltage signal to the DP interface), and the charging logic control module is configured to determine a signal from the load device according to a voltage detection result.

In one possible example, referring to fig. 2, the first voltage detection module includes a voltage comparator CMP1, a voltage comparator CMP2, a voltage comparator CMP3, and the second voltage detection module includes a voltage comparator CMP4, a voltage comparator CMP5, a voltage comparator CMP 6; a first input end of the voltage comparator CMP1, a first input end of the voltage comparator CMP2, a first input end of the voltage comparator CMP3, and a first port of the switch G1 are combined and then connected to the DP interface and a first port of the switch G2; a first input end of the voltage comparator CMP4, a first input end of the voltage comparator CMP5, a first input end of the voltage comparator CMP6, and a first port of the switch G3 are combined and then connected to the DM interface and a second port of the switch G2; the output end of the voltage comparator CMP1, the output end of the voltage comparator CMP2, the output end of the voltage comparator CMP3, the output end of the voltage comparator CMP4, the output end of the voltage comparator CMP5 and the output end of the voltage comparator CMP6 are connected with the charging logic control module.

The voltage comparator CMP1, the voltage comparator CMP2, and the voltage comparator CMP3 are configured to detect a voltage on the DP interface, the voltage comparator CMP4, the voltage comparator CMP5, and the voltage comparator CMP6 are configured to detect a voltage on the DM interface, and the charging logic control module may determine voltages on the DP interface and the DM interface respectively according to voltage detection results of the comparators.

With continued reference to fig. 2, in this example, the first voltage detection module further includes: data selector D1, data selector D2, the second voltage detection module further includes: data selector D3, data selector D4;

a second input terminal of the voltage comparator CMP1 is connected to the output terminal of the data selector D1, a second input terminal of the voltage comparator CMP2 is connected to the output terminal of the data selector D2, and an input voltage of a second input terminal of the voltage comparator CMP3 is a first input voltage, an input voltage of a first input terminal of the data selector D1 is a second input voltage, an input voltage of a second input terminal of the data selector D1 is a third input voltage, an input voltage of a first input terminal of the data selector D2 is a fourth input voltage, and an input voltage of a second input terminal of the data selector D2 is a fifth input voltage;

the second input terminal of the voltage comparator CMP4 is connected to the output terminal of the data selector D3, the second input terminal of the voltage comparator CMP5 is connected to the output terminal of the data selector D4, and the input voltage at the second input terminal of the voltage comparator CMP6 is a sixth input voltage, the input voltage at the first input terminal of the data selector D3 is a seventh input voltage, the input voltage at the second input terminal of the data selector D3 is an eighth input voltage, the input voltage at the first input terminal of the data selector D4 is a ninth input voltage, and the input voltage at the second input terminal of the data selector D4 is a tenth input voltage.

The first input voltage and the sixth input voltage may be 0.325V, the second input voltage and the seventh input voltage may be 2.9V, the third input voltage, the fourth input voltage, the eighth input voltage and the ninth input voltage may be 2.0V, the fifth input voltage may be 1.2V, and the tenth input voltage may be 1.5V.

One input end of the voltage comparator is connected with the output end of one data selector, and the voltage values of the two input ends of the data selector are different, namely, one input end of the voltage comparator can be selectively connected with different input voltages, so that the voltages in different voltage value ranges can be detected by the same voltage detection module.

For example, when the input voltage of the second input terminal of the voltage comparator CMP2 is 2.0V (i.e. 2.0V selected by the data selector D2), and the input voltage of the second input terminal of the voltage comparator CMP3 is 0.325V, the detection of voltages less than 0.325V, 0.325V 2.0V, and greater than 2.0V (determined by the outputs of the voltage comparator CMP2 and the voltage comparator CMP 3) can be realized by the first voltage detection module, and when the input voltage of the second input terminal of the voltage comparator CMP2 is 1.2V (i.e. 1.2V selected by the data selector D2), the detection of voltages less than 0.325V, 0.325V 1.2V, and greater than 1.2V can be realized by the first voltage detection module.

In specific implementation, when different fast charging protocol modes are adopted to carry out fast charging on the load equipment, the voltages selected by the input ends of the voltage comparators may have differences. For example, when the DCP fast charging protocol is adopted, the input voltages at the second input terminals of the voltage comparator CMP1 and the voltage comparator CMP4 may be 2.9V, and the input voltages at the second input terminals of the voltage comparator CMP2 and the voltage comparator CMP5 may be 2.0V.

When the charging logic module and the load device QC handshake is successful and a QC fast charging protocol is confirmed to be required, the input voltages of the voltage comparator CMP1 and the voltage comparator CMP4 may be set to 2.0V. Therefore, the charging logic control module can control the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module, wherein the relationship between the voltage of the DP interface and the DM interface and the VBUS output voltage is shown in table 1 below.

The adapter voltage is VBUS output voltage, the first input end of each voltage comparator is a positive phase input end, the second input end is a negative phase input end, and when the voltage of the positive phase input end of the voltage comparator is greater than the voltage of the negative phase input end, a signal at the output end of the voltage comparator is 0, otherwise, the signal is 1.

For example, when the output signals of the voltage comparator CMP1 and the voltage comparator CMP3 are 0 and 1 respectively, and the output information of the voltage comparator CMP4 and the voltage comparator CMP6 are both 1, the charging logic control module adjusts the output voltage of the VBUS interface to 5V. When the DP interface voltage and the DM interface voltage are both 0V, the adapter voltage is defuelt, i.e., the adapter voltage is kept in the default state, and when the DP interface voltage is 0.6V, DM, the interface voltage is 3.3V, the adapter voltage is in the Continuous mode, i.e., the QC3.0 mode.

TABLE 1 QC protocol output voltage control logic table

DP	DM	CMP1、CMP3	CMP4、CMP6	Adapter voltage
					0V	0V	00	00	default
0.6V	0V	01	00	5V
					0.6V	3.3V	01	11	Continuous mode
3.3V	0.6V	11	01	9V
					0.6V	0.6V	01	01	12V
3.3V	3.3V	11	11	20V

In one possible example, referring to fig. 3, the multi-fast charge protocol control circuit further includes: the first data voltage output module and the second data voltage output module;

the charging logic control module is connected to a control port of the first data voltage output module and a control port of the second data voltage output module, a first port of the first data voltage output module, a second port of the first voltage detection module, and a first port of the switch G1 are combined and then connected to the DP interface and a first port of the switch G2, and a first port of the second data voltage output module, a second port of the second voltage detection module, and a first port of the switch G3 are combined and then connected to the DM interface and a second port of the switch G2;

the first data voltage output module is configured to provide an output voltage of the DP interface, the second data voltage output module is configured to provide an output voltage of the DM interface, and the charging logic control module is further configured to control output voltages of the first data voltage output module and the second data voltage output module.

In a specific implementation, the charging logic control module may control the two data voltage output modules to output the voltage with a specific voltage value to the DP interface or the DM interface, or control the two data voltage output modules not to output the voltage outwards.

Specifically, the DCP mode is used for charging in the multi-fast charging protocol control circuit, and the charging logic control module may notify the load device of the specifically adopted fast charging mode by controlling the output voltages of the two data voltage output modules, for example, the voltages output to the DP interface and the DM interface by the first data voltage output module and the second data voltage output module are both controlled to be 2.7V, and the load device is notified of the APPLE2.4A mode.

In this example, referring to fig. 4, the first data voltage output module includes a data selector D5, an analog switch OP1, and the second data voltage output module includes a data selector D6 and an analog switch OP 2;

an input voltage of a first input end of the data selector D5 is an eleventh input voltage, an input voltage of a second input end of the data selector D5 is a twelfth input voltage, an output end of the data selector D5 is connected to a first port of the analog switch OP1, a second port of the analog switch OP1, a second port of the first voltage detection module, and a first port of the switch G1 are combined and then connected to the DP interface and a first port of the switch G2, and the charge logic control module is connected to a control port of the data selector D5 and a control port of the analog switch OP 1;

the input voltage of the first input end of the data selector D6 is a thirteenth input voltage, the input voltage of the second input end of the data selector D6 is a fourteenth input voltage, the output end of the data selector D6 is connected to the first port of the analog switch OP2, the second port of the analog switch OP2, the second port of the second voltage detection module, and the first port of the switch G3 are combined and then connected to the DM interface and the second port of the switch G2, and the charging logic control module is connected to the control port of the data selector D6 and the control port of the analog switch OP 2.

Wherein the eleventh and thirteenth input voltages may be 2.7V, and the twelfth and fourteenth input voltages may be 2.0V.

In a specific implementation, the charging logic control module may respectively control whether the first data voltage output module and the second data voltage output module output the data voltage through the control ports of the two analog switches, and may respectively control the values of the output voltages of the two data voltage output modules by controlling the two data selectors D5 and D6. For example, the charging logic control module controls the data selector D5 to select the voltage of 2.7V and controls the analog switch OP1 to be turned on, so that the first data voltage output module can output the voltage of 2.7V to the DP interface. When a DCP fast charge protocol is adopted, the charge logic control module may control the output voltage values of the two data voltage output modules according to a specifically adopted fast charge mode, specifically, the corresponding relationship between the output voltage values of the two data voltage output modules and the fast charge mode may be: the output voltage of the first data voltage output module is 2.0V, the output voltage of the second data voltage output module is 2.7V, and the first data voltage output module corresponds to an APPLE 1A quick charging mode; the output voltage of the first data voltage output module is 2.7V, the output voltage of the second data voltage output module is 2.0V, and the first data voltage output module corresponds to an APPLE 2A quick charging mode; the output voltage of the first data voltage output module is 2.7V, and the output voltage of the second data voltage output module is 2.7V, and corresponds to an APPLE2.4A quick charging mode.

In one possible example, referring to fig. 5, the multi-fast-charge protocol control circuit further includes: a resistor R1, a resistor R2, an NMOS transistor N1 and an NMOS transistor N2;

a first port of the resistor R1, a second port of the first voltage detection module, and a first port of the switch G1 are combined and then connected to the DP interface and a first port of the switch G2, a second port of the resistor R1 is connected to a drain of the NMOS transistor N1, and a source of the NMOS transistor N1 is grounded;

a first port of the resistor R2, a second port of the second voltage detection module, and a first port of the switch G3 are combined and then connected to the DM interface and a second port of the switch G2, a second port of the resistor R2 is connected to a drain of the NMOS transistor N2, and a source of the NMOS transistor N2 is grounded;

the charging logic control module is connected with the grid electrode of the NMOS transistor N1 and the grid electrode of the NMOS transistor N2;

the charging logic control module is also used for controlling the grid voltage of the NMOS transistor N1 and the grid voltage of the NMOS transistor N2.

The resistor R1 and the resistor R2 can be used as bleeder resistors, and the resistor R1 and the resistor R2 can be set to match the impedance requirements of the DP interface or the DM interface in the charging specification corresponding to the DCP quick charging protocol.

In specific implementation, the charging logic control module may control the on-state of the NMOS transistor N1 and the NMOS transistor N2 by controlling the gate voltages of the NMOS transistor N1 and the NMOS transistor N2, so as to control whether the resistor R1 and the resistor R2 are grounded.

For example, when the DM resistor needs to be pulled down, i.e. the resistor R2 needs to be grounded, the charge logic control module can control the gate voltage of the NMOS transistor N2, so that the NMOS transistor N2 is turned on.

In one possible example, the charge logic control module includes an S0 port, an S1 port, an S2 port;

the S0 port is connected with the control port of the switch G1, the S1 port is connected with the control port of the switch G2, and the S2 port is connected with the control port of the switch G3;

the charging logic control module is used for controlling the on-off of the switch G1 through the S0 port, controlling the on-off of the switch G2 through the S1 port and controlling the on-off of the switch G3 through the S2 port.

In one possible example, the charge logic control module includes an S3 port, an S4 port, an S5 port, an S6 port;

the S3 port is connected with the control port of the data selector D1, the S4 port is connected with the control port of the data selector D2, the S5 port is connected with the control port of the data selector D3, and the S6 port is connected with the control port of the data selector D4;

the charging logic control module is used for controlling the data selector D1 to select the input voltage through the S3 port, controlling the data selector D2 to select the input voltage through the S4 port, controlling the data selector D3 to select the input voltage through the S5 port, and controlling the data selector D4 to select the input voltage through the S6 port.

In one possible example, the charge logic control module includes an S7 port, an S8 port, an S9 port, an S10 port;

the S7 port is connected with the control port of the data selector D5, the S8 port is connected with the control port of the analog switch OP1, the S9 port is connected with the control port of the data selector D6, and the S10 port is connected with the control port of the analog switch OP 2;

the charging logic control module is used for controlling the voltage selectively input by the data selector D5 through the S7 port, controlling the voltage selectively input by the data selector D6 through the S9 port, controlling the on-off of the analog switch OP1 through the S8 port and controlling the on-off of the analog switch OP2 through the S10 port.

In one possible example, the charge logic control module includes an S11 port, an S12 port;

the S11 port is connected with the grid electrode of the NMOS transistor N1, and the S12 port is connected with the grid electrode of the NMOS transistor N2;

the charging logic control module is used for controlling the grid voltage of the NMOS transistor N1 through the S11 port and controlling the grid voltage of the NMOS transistor N2 through the S12 port.

Specifically, referring to fig. 6, in practical application, the multi-fast-charging protocol control circuit may be specifically as shown in fig. 6, and the multi-fast-charging protocol control circuit includes: a charging logic control module, an analog switch OP1, an analog switch OP2, a switch G1, a switch G2, a switch G3, a data selector D1, a data selector D2, a data selector D3, a data selector D4, a data selector D5, a data selector D6, a voltage comparator CMP1, a voltage comparator CMP2, a voltage comparator CMP3, a voltage comparator CMP4, a voltage comparator CMP5, a voltage comparator CMP6, an AFSCP transmitting module, a VOOC transmitting module, a resistor R1, a resistor R2, an NMOS tube N1, an NMOS tube N2, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module; the charging logic control module comprises an S0 port, an S1 port, an S2 port, an S3 port, an S4 port, an S5 port, an S6 port, an S7 port, an S8 port, an S9 port, an S10 port, an S11 port and an S12 port.

The charging logic module is connected with the output end of the voltage comparator CMP1, the output end of the voltage comparator CMP2, the output end of the voltage comparator CMP3, the output end of the voltage comparator CMP4, the output end of the voltage comparator CMP5, the output end of the voltage comparator CMP6, a VBUS interface, a GND interface, a timer module, a first port of the VOOC sending module and a first port of the AFSCP sending module;

a port S3 of the charging logic control module is connected with a control port of a switch G1, a port S4 is connected with a control port of a switch G2, a port S8 is connected with a control port of a switch G3, a port S9 is connected with a control port of a data selector D1, a port S10 is connected with a control port of a data selector D2, a port S11 is connected with a control port of a data selector D3, a port S12 is connected with a control port of a data selector D4, a port S0 is connected with a control port of a data selector D5, a port S1 is connected with a control port of an analog switch OP1, a port S5 is connected with a control port of a data selector D6, a port S6 is connected with a control port of an analog switch OP2, a port S2 is connected with a gate of an NMOS transistor N2, and a port S2 is connected with a gate;

the input voltage of the first input terminal of the data selector D5 is 2.7V, the input voltage of the second input terminal of the data selector D5 is 2.0V, and the output terminal of the data selector D5 is connected to the first port of the analog switch OP 1; the input voltage of the first input terminal of the data selector D6 is 2.7V, the input voltage of the second input terminal of the data selector D6 is 2.0V, and the output terminal of the data selector D6 is connected to the first port of the analog switch OP 2;

a second port of the analog switch OP1, a first input end of the voltage comparator CMP1, a first input end of the voltage comparator CMP2, a first input end of the voltage comparator CMP3, a first port of the resistor R1 and a first port of the switch G1 are combined and then connected with a DP interface and a first port of the switch G2, and a second port of the analog switch OP2, a first input end of the voltage comparator CMP4, a first input end of the voltage comparator CMP5, a first input end of the voltage comparator CMP6, a first port of the resistor R2 and a first port of the switch G3 are combined and then connected with a DM interface and a second port of the switch G2;

a second input terminal of the voltage comparator CMP1 is connected to the output terminal of the data selector D1, a second input terminal of the voltage comparator CMP2 is connected to the output terminal of the data selector D2, an input voltage of the second input terminal of the voltage comparator CMP3 is 0.325V, an input voltage of the first input terminal of the data selector D1 is 2.9V, an input voltage of the second input terminal of the data selector D1 is 2.0V, an input voltage of the first input terminal of the data selector D2 is 2.0V, and an input voltage of the second input terminal of the data selector D2 is 1.2V; the second input terminal of the voltage comparator CMP4 is connected to the output terminal of the data selector D3, the second input terminal of the voltage comparator CMP5 is connected to the output terminal of the data selector D4, the input voltage of the second input terminal of the voltage comparator CMP6 is 0.325V, the input voltage of the first input terminal of the data selector D3 is 2.9V, the input voltage of the second input terminal of the data selector D3 is 2.0V, the input voltage of the first input terminal of the data selector D4 is 2.0V, and the input voltage of the second input terminal of the data selector D4 is 1.5V.

The second port of the resistor R1 is connected with the drain electrode of an NMOS tube N1, and the source electrode of the NMOS tube N1 is grounded; the second port of the resistor R2 is connected with the drain electrode of an NMOS tube N2, and the source electrode of the NMOS tube N2 is grounded;

a second port of the switch G1 is connected to a second port of the VOOC sending module, and a second port of the switch G3 is connected to a second port of the AFSCP sending module;

the charging logic control module can adjust the channel state of the multi-fast-charging protocol control circuit according to the voltage detection result of the voltage detection module, the timing result of the timer module and the current on the VBUS interface, for example, control the on/off of each switch, the output of each selector, the gate voltage of the NMOS transistor, and the like, perform protocol communication with the load device by adjusting the channel state (for example, notify the load device to adopt a DCP protocol by short-circuiting DP and DM interfaces, detect the voltage values on DP and DM and perform protocol handshake with the load device to determine the fast-charging protocol to be adopted, perform VOOC protocol communication or AFC/SCP/FCP protocol communication with the load device by controlling the VOOC sending module or the AFSCP sending module), and further perform fast charging on the load device through the VBUS interface by adopting the corresponding fast-charging protocol.

It can be seen that the multi-fast-charging protocol control circuit provided by the application comprises a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP sending module, a VOOC sending module, a DP interface, a DM interface, a VBUS interface, a GND interface, a timer module, a switch G1, a switch G2, and a switch G3, wherein the charging logic control module is configured to control the first voltage detection module and the second voltage detection module to detect voltages of the DP interface and the DM interface respectively, perform timing through the timer module, control on/off of the switch G1, the switch G2, and the switch G3 according to a voltage detection result, a timing result, and a current of the VBUS interface, communicate with a load device by using a corresponding communication protocol, and charge the load device through the VBUS interface. Therefore, the multi-fast-charging protocol control circuit can realize fast charging of various fast-charging protocols, can be applied to a fast-charging protocol chip to support various fast-charging protocols by a single chip, is flexible to apply and saves cost. The method is favorable for solving the problem of equipment compatibility caused by the fact that a single chip cannot support multiple fast charging protocols at present.

Example 2:

referring to fig. 7, this embodiment provides a control method of a multi-fast-charging protocol control circuit, which is applied to the multi-fast-charging protocol control circuit in embodiment 1, and the method includes:

s201, the charging logic control module defaults to adopt a DCP fast charging protocol, and controls the access state of the multi-fast charging protocol control circuit to be a first state.

In a specific implementation, when the multi-rapid-charging-protocol control circuit is in rapid-charging-protocol communication with the load device, the charging logic control module can default to a DCP rapid-charging protocol, and the first state of the multi-rapid-charging-protocol control circuit is the circuit state when the DCP protocol is used for rapidly charging the load device.

And S202, when the charging logic control module determines the voltage change of the DP interface or the DM interface according to the voltage detection results of the first voltage detection module and the second voltage detection module, the timer module starts to time t 1.

S203, if the voltage detection results of the first voltage detection module and the second voltage detection module do not change within the time t1, after the time t1, the charging logic control module controls the access state of the multi-fast charging protocol control circuit to be the second state.

Wherein in the second state, the switch G2 is closed, and the DP interface and the DM interface are shorted.

In S202 and S203, the charging logic control module determines that the voltage of the DP interface or the DM interface changes according to the voltage detection result, that is, it may be determined that the load device is connected, and may control the switch G2 to be closed, so that the DP interface and the DM interface are short-circuited, and the load device is notified that the fast charging protocol used by the load device is the DCP fast charging protocol.

S204, when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is within the preset voltage range according to the voltage detection result of the first voltage detection module, the timer module starts to time t 2.

S205, if the time is t2, the charging logic control module determines that the voltage of the DP interface is always within the preset voltage range according to the voltage detection result of the first voltage detection module.

In S204 and S205, the load device may notify the charging logic control module at the charging adapter end of the fast charging protocol supported by the charging logic control module by loading a voltage with a preset voltage value on the DP interface or the DM interface, and the charging logic control module determines whether the voltage applied to the DP interface by the load device is within a preset voltage range according to the voltage detection result, and further determines whether the subsequent fast charging protocol handshaking step needs to be continued. The preset voltage range can be determined by a QC quick-charge protocol, and if the charging logic control module determines that the voltage value on the DP interface is within the preset voltage range, the subsequent step of shaking hands by the QC protocol can be continuously executed. In addition, because the DP interface and the DM interface are short-circuited at this time, the voltage of the DM interface is actually changed according to the voltage of the DP interface, and the voltage of the DP interface and the DM interface is the same.

S206, after the time t2, the charging logic control module controls the access state of the multi-fast charging protocol control circuit to be a third state.

In the third state, the switch G2 is turned off, and the short circuit between the DP interface and the DM interface is cut off.

And S207, the charging logic control module controls the switch G1 and the switch G3 to be closed, and judges whether the DM interface is smaller than a first preset voltage value or not according to the voltage detection result of the second voltage detection module.

Wherein the first preset voltage value may be 0.325V.

In the specific implementation, because the short circuit of the DP interface and the DM interface is cut off, the voltage of the DM interface does not change with the voltage of the DM interface any more, the NMOS transistor N2 is turned on, and the voltage value of the DM interface drops.

And S208, if yes, the timer module starts to time t 3.

S209, if the charging logic control module determines that the voltage of the DM interface is always smaller than the first preset voltage value according to the voltage detection result of the second voltage detection module within the time t3, the QC handshake is successful, otherwise, the QC handshake fails.

And S210, if the QC handshake is successful, detecting whether an AFC/SCP/FCP data packet is received on the DM interface after the time t 3.

In a specific implementation, the AFC data packet, the SCP data packet, and the FCP data packet correspond to different voltage pulse sequences, and the charging logic module detects whether the AFC/SCP/FCP data packet is received on the DM interface, specifically, the charging logic module determines the voltage pulse sequence on the DM interface according to the voltage detection result of the second voltage detection module, and decodes the voltage pulse sequence to determine whether the AFC/SCP/FCP data packet is received.

And S211, if the AFSCP protocol is received, carrying out AFC/SCP/FCP protocol communication with the load equipment through the AFSCP sending module.

In the specific implementation, when three fast charging protocols of AFC/SCP/FCP are adopted, the voltages applied to the DM interface by the load device are different, and the charging logic control module can determine what kind of fast charging protocol communication needs to be performed with the load device according to the detected data packet.

And S212, if the voltage is not received, the charging logic control module adjusts the output voltage of the VBUS interface according to the voltage detection results of the first voltage detection module and the second voltage detection module by adopting a QC quick charging protocol.

And S213, if the QC handshake fails, after the time t3, the charging logic control module detects whether the current of the VBUS interface is larger than a preset current value.

And S214, if yes, the timer module starts to time t 4.

S215, if the charging logic control module detects that the current of the VBUS interface is always greater than the preset current value within the time t4, performing VOOC protocol communication with the load device through a VOOC sending module.

In one possible example, the method further comprises: when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is not within the preset voltage range according to the voltage detection result of the first voltage detection module; or, if the voltage of the DP interface is not within the preset voltage range within the time t2, the charging logic control module determines, according to the voltage detection result of the first voltage detection module, that the voltage of the DP interface is not within the preset voltage range; the charging logic control module controls the access state of the multi-fast charging protocol control circuit to be the second state.

In specific implementation, if the voltage applied to the DP interface by the load device does not meet the relevant requirements of the QC fast charging protocol, the charging logic control module may control the access state of the multi-fast charging protocol control circuit to return to the state of short circuit between the DP interface and the DM interface, and re-detect the voltage of the DP interface, and when it is detected that the voltage of the DP interface meets the relevant requirements of the QC fast charging protocol, the subsequent steps may be continued.

In one possible example, after the timer module starts to count t1 time when the voltage of the DP interface or the DM interface is determined to be changed, the method further includes: if the voltage detection results of the first voltage detection module and the second voltage detection module change within the time t1, the timer module is set to zero, and the timer module restarts to count time t 1.

In one possible example, the adjusting of the output voltage of the VBUS interface according to the voltage detection result of the voltage detection module by the charge logic control module using a QC fast charge protocol includes:

the charging logic control module judges whether the voltage of the DM interface is greater than a second preset voltage value according to the voltage detection result of the second voltage detection module;

if not, adjusting the output voltage of the VBUS interface to be a first output voltage value;

if so, judging whether the voltage of the DP interface is greater than a third preset voltage value according to the voltage detection result of the first voltage detection module;

if not, adjusting the output voltage of the VBUS interface to be a second output voltage value;

if yes, judging whether the voltage of the DM interface is larger than a fourth preset voltage value according to the voltage detection result of the second voltage detection module;

if so, adjusting the output voltage of the VBUS interface to be a third output voltage value;

if not, adjusting the output voltage of the VBUS interface to be a fourth output voltage value;

after the output voltage of the VBUS interface is adjusted every time, whether the voltage of the DP interface is larger than a fifth preset voltage value is determined according to the voltage detection result of the first voltage detection module;

if yes, executing the step of judging whether the voltage of the DM interface is larger than a second preset voltage value according to the voltage detection result of the second voltage detection module;

if not, the charging logic control module adopts a DCP fast charging protocol to control the access state of the multi-fast charging protocol circuit to be the first state.

In a specific implementation, the second preset voltage value and the fifth preset voltage value may be 0.325V, the third preset voltage value and the fourth preset voltage value may be 2V, the first output voltage value may be 5V, the second output voltage value may be 12V, the third output voltage value may be 20V, and the fourth output voltage value may be 9V.

In practical applications, referring to fig. 8, the control method of the multi-fast-charge protocol control circuit of the present application may specifically include the following steps, which may specifically be applied to the multi-fast-charge protocol control circuit shown in fig. 6:

step 1, start, execute step 2.

And 2, adopting an APPLE2.4A mode by default, and executing the step 3.

When the APPLE2.4A mode is adopted by default, the charging logic controller controls the voltages at the input ends of the analog switch OP1 and the analog switch OP2 to select 2.7V by default, the voltages at the second input ends of the voltage comparator CMP1 and the voltage comparator CMP4 both select 2.9V, the voltage at the second input end of the voltage comparator CMP5 is 1.5V, and the analog switch OP1 and the analog switch OP2 are turned on.

When the analog switch is turned on, the voltage can be output to the DP interface or the DM interface by controlling the data selectors D5 and D6, and when the analog switch is turned off, the voltage is not output to the DP interface or the DM interface. The charging logic module controls each component through a port corresponding to each component, for example, controls the data selector D1 and the data selector D3 through an S9 port and an S11 port, so that the voltages at the second inputs of the voltage comparator CMP1 and the voltage comparator CMP4 are both selected to be 2.9V. In practical applications, the voltage at the second input terminal of the voltage comparator CMP5 may also be 2.0V, and the charging logic control module may determine whether a load device is inserted according to the output signal of each voltage comparator through the voltage setting at the input terminal of the voltage comparator.

For the fast charging by using the DCP fast charging protocol, the multi-fast charging protocol control module may specifically notify the load device of the fast charging mode adopted by the load device by controlling the voltages output by the two analog switches to the DP interface and the DM interface, for example, the voltages output by the analog switch OP1 and the analog switch OP2 to the DP interface and the DM interface are both 2.7V, that is, notify the load device of the application 2.4A fast charging mode adopted by the load device.

And 3, detecting the voltage change of the DP interface or the DM interface, and executing the step 4.

In a specific implementation, the charging logic control module detects a voltage change of the DP interface or the DM interface through an output signal of each voltage comparator, and when the voltage change of the DP interface or the DM interface is detected, that is, as long as an output signal of one voltage comparator jumps, it may be determined that a load device is connected.

And 4, starting a timer module to start timing t1 time, and executing the step 5.

In a specific implementation, when the output signal of any one of the voltage comparators jumps, the timer module is set to 0 to restart to count the time t 1.

And 5, judging whether the time t1 counted by the timer module is ended, if so, executing the step 6, otherwise, continuing to execute the step 5.

And 6, adjusting the access state of the multi-fast charging protocol control circuit, enabling the DP interface and the DM interface to be in short circuit, and executing the step 7.

In specific implementation, the charging logic control module controls the switch G2 to be closed, the DP interface and the DM interface to be short-circuited, and also controls the analog switch OP1 and the analog switch OP2 to be closed, controls the voltage of the second input terminal of the voltage comparator CMP2 to be selected to be 1.2V, controls the voltage of the second input terminal of the voltage comparator CMP4 to be selected to be 2.0V, and controls the voltage of the second input terminal of the voltage comparator CMP5 to be selected to be 1.5V.

In addition, in step 6, the charge logic control module may further control the gate voltage of the NMOS transistor N1 to turn on the NMOS transistor N1, turn on the DP resistor pull-down, and ground the resistor R1.

The selection of the voltages at the second inputs of the voltage comparator CMP4 and the voltage comparator CMP5 can be used to detect whether the FCP/SCP/AFC data packet is received at the DM interface subsequently, because the voltages applied to the DM interface by the load device are different when the above-mentioned three fast charging protocols of FCP, SCP and AFC are used, different fast charging protocols can be identified by the voltage comparator CMP4 and the voltage comparator CMP 5.

And 7, judging whether the DP interface voltage is greater than 0.325V and less than 2V, if so, executing a step 8, and otherwise, returning to execute the step 6.

In this example, step 7 is performed when a jump in the voltage of the DP interface or the DM interface is detected.

And 8, starting a timer module to start timing for 1.25S, and executing the step 9.

And 9, judging whether the DP interface voltage is greater than 0.325V and less than 2V, if so, executing the step 10, and otherwise, returning to execute the step 6.

And step 10, judging whether the timer module reaches the timing time of 1.25S, if so, executing step 11, otherwise, returning to execute step 9.

In steps 7 to 10, it is determined whether the voltage of the DP interface is greater than 0.325V and less than 2V for 1.25S, and if the detected DP voltage is always greater than 0.325V and less than 2.0V within 1.25S counted by the timer module, the subsequent step 11 is executed after the timer module reaches the timing time of 1.25S.

In the specific implementation, the charging adapter end short-circuits the DP interface and the DM interface, and after notifying the DCP protocol adopted by the load device, the load device may also perform protocol communication with the charging adapter end through voltages on the DP interface and the DM interface, and in the above steps 7 to 10, it may be determined that the voltage loaded on the DP interface by the load device is greater than 0.325V and less than 2.0V, where, because the DP interface and the DM interface are short-circuited, voltages of the DP interface and the DM interface are the same.

And step 11, disconnecting the short circuit of the DP interface and the DM interface, controlling the N2 of the NMOS tube to be conducted, starting the DM resistor to pull down, and executing the step 12.

In the specific implementation, in step 11, the charging logic control module controls the switch G2 to be turned off, that is, the short circuit between the DP interface and the DM interface is cut off, so that the voltage of the DM interface does not change with the voltage of the DM interface, the charging logic control module controls the gate voltage of the NMOS transistor N2 to turn on the NMOS transistor N2, the resistor R2 is grounded, and the detected voltage value of the DM interface is maintained at a low level.

And step 12, judging whether the DM interface voltage is less than 0.325V, if so, executing step 13.

And step 13, judging whether the QC protocol handshake is successful, if so, executing step 14, and if not, executing step 23.

Wherein, judging whether the QC protocol handshake is successful may specifically include: and starting a timer module to start timing 10mS, detecting whether the voltage of the DM interface is less than 0.325V during the timing 10mS, if so, determining that the QC protocol handshake is successful after the timer timing t3 is finished, otherwise, identifying that the QC protocol handshake fails.

Step 14, judging whether an AFC/SCP/FCP data packet is received on the DM interface, if so, executing step 27; otherwise step 15 is performed.

In the specific implementation, the steps 15 to 21 are processes of communicating with the load device to determine the VBUS output voltage when the load device is rapidly charged by adopting the QC fast charging protocol.

And 15, judging whether the DM interface voltage is greater than 0.325V or not, if so, executing a step 17, and otherwise, executing a step 16.

And step 16, determining that a QC quick charge request of the load device is received, requesting 5V charging voltage, and executing step 22.

In a specific implementation, the charging logic control module may determine the charging voltage requested by the load device according to the detected voltage values on the DP interface and the DM interface, and further may control the VBUS to output the requested charging voltage to perform fast charging on the load device.

And step 17, judging whether the DP interface voltage is greater than 2V, if so, executing step 19, otherwise, executing step 18.

And step 18, determining that a QC quick charge request of the load device is received, requesting 12V charging voltage, and executing step 22.

And step 19, judging whether the DM interface voltage is greater than 2V, if so, executing step 20, otherwise, executing step 21.

And step 20, determining that a QC quick-charge request of the load device is received, requesting 20V charging voltage, and executing step 22.

And step 21, determining that a QC quick charge request of the load device is received, requesting 9V charging voltage, and executing step 22.

And step 22, judging whether the DP interface voltage is greater than 0.325V, if so, executing step 15, otherwise, returning to execute step 1.

In a specific implementation, if the charging logic control module determines that the voltage of the DP interface is not greater than 0.325V according to the voltage detection result, the QC fast charging mode will be exited, and the access state of the multi-fast charging protocol control circuit is controlled to return to the initial APPLE2.4A mode.

And step 23, judging whether the VBUS interface current is larger than 1A, if so, executing step 24, otherwise, continuing to execute step 23.

Step 24, the timer module is started to start timing 2S, and step 25 is executed.

And 25, judging whether the timer module reaches the timing time 2S, if so, executing the step 26, otherwise, continuing to execute the step 25.

And 26, carrying out VOOC protocol communication with the load equipment through the VOOC sending module.

And 27, carrying out AFC/SCP/FCP protocol communication with the load equipment through an AFSCP sending module.

Therefore, the control method of the multi-fast-charging-protocol control circuit is applied to the design of the charging chip, and the single protocol chip can be compatible with various fast charging protocols, so that the chip design cost and the chip application cost are saved.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A multi-fast-charge protocol control circuit, comprising: the device comprises a charging logic control module, a first voltage detection module, a second voltage detection module, an AFSCP (automatic frequency control point) protocol module, a VOOC (Voltage over optical Circuit) protocol module, a DP (data processing) interface, a DM (media data) interface, a VBUS (visual bus) interface, a GND (ground) interface, a timer module, a switch G1, a switch G2 and a switch G3;

the charging logic control module is connected with the first port of the first voltage detection module, the first port of the second voltage detection module, the VBUS interface, the GND interface, the timer module, the first port of the AFSCP transmission module, the first port of the VOOC transmission module, the control port of the switch G1, the control port of the switch G2 and the control port of the switch G3, the second port of the first voltage detection module is combined with the first port of the switch G1 and then connected to the DP interface and the first port of the switch G2, a second port of the switch G1 is connected to the second port of the VOOC sending module, a second port of the second voltage detecting module and the first port of the switch G3 are combined and then connected to the DM interface and the second port of the switch G2, the second port of the switch G3 is connected with the second port of the AFSCP sending module;

2. The control circuit of claim 1, wherein the first voltage detection module comprises a voltage comparator CMP1, a voltage comparator CMP2, a voltage comparator CMP3, and the second voltage detection module comprises a voltage comparator CMP4, a voltage comparator CMP5, a voltage comparator CMP 6;

a first input end of the voltage comparator CMP1, a first input end of the voltage comparator CMP2, a first input end of the voltage comparator CMP3, and a first port of the switch G1 are combined and then connected to the DP interface and a first port of the switch G2;

a first input end of the voltage comparator CMP4, a first input end of the voltage comparator CMP5, a first input end of the voltage comparator CMP6, and a first port of the switch G3 are combined and then connected to the DM interface and a second port of the switch G2;

the output end of the voltage comparator CMP1, the output end of the voltage comparator CMP2, the output end of the voltage comparator CMP3, the output end of the voltage comparator CMP4, the output end of the voltage comparator CMP5 and the output end of the voltage comparator CMP6 are connected with the charging logic control module.

3. The multi-fast-charge protocol control circuit of claim 2, wherein the first voltage detection module further comprises: data selector D1, data selector D2, the second voltage detection module further includes: data selector D3, data selector D4;

4. The multi-fast-charge protocol control circuit of claim 1, further comprising: the first data voltage output module and the second data voltage output module;

5. The control circuit of claim 4, wherein the first data voltage output module comprises a data selector D5, an analog switch OP1, and the second data voltage output module comprises a data selector D6 and an analog switch OP 2;

6. The multi-fast-charge protocol control circuit of claim 1, further comprising: a resistor R1, a resistor R2, an NMOS transistor N1 and an NMOS transistor N2;

7. The multi-fast-charge protocol control circuit of claim 1, wherein the charge logic control module comprises an S0 port, an S1 port, an S2 port;

8. The multi-fast-charge protocol control circuit of claim 3, wherein the charge logic control module comprises an S3 port, an S4 port, an S5 port, an S6 port;

9. The multi-fast-charge protocol control circuit of claim 5, wherein the charge logic control module comprises an S7 port, an S8 port, an S9 port, an S10 port;

10. The multi-fast-charge protocol control circuit of claim 6, wherein the charge logic control module comprises an S11 port, an S12 port;

11. A method of controlling a multi-fast-charge protocol control circuit, the multi-fast-charge protocol control circuit comprising a multi-fast-charge protocol control circuit according to any one of claims 1 to 10, the method comprising the steps of:

if yes, the timer module starts to time t 3;

if yes, the timer module starts to time t 4;

12. The method of claim 11, further comprising:

when the voltage detection result of the first voltage detection module or the second voltage detection module changes, if the charging logic control module determines that the DP interface voltage is not within the preset voltage range according to the voltage detection result of the first voltage detection module; alternatively, the first and second electrodes may be,

if the voltage of the DP interface is not within the preset voltage range within the time t2, the charging logic control module determines, according to the voltage detection result of the first voltage detection module, that the voltage of the DP interface is not within the preset voltage range;

the charging logic control module controls the access state of the multi-fast charging protocol control circuit to be the second state.

13. The method according to claim 11 or 12, wherein after a timer module starts to count t1 time when the voltage of the DP interface or the DM interface is determined to be changed, the method further comprises:

if the voltage detection results of the first voltage detection module and the second voltage detection module change within the time t1, the timer module is set to zero, and the timer module restarts to count time t 1.

14. The method according to claim 11, wherein the charging logic control module adjusts the output voltage of the VBUS interface according to the voltage detection result of the voltage detection module by using a QC fast charging protocol, which includes:

if yes, executing the step of judging whether the voltage of the DM interface is larger than a second preset voltage value according to the output signal of the first voltage comparator;

15. A multi-fast-charging protocol control chip, characterized by comprising a multi-fast-charging protocol control circuit according to any one of claims 1 to 10.

16. An electronic device, characterized in that the electronic device comprises a multi-fast-charge protocol control chip according to claim 15.