WO2022213865A1 - 计算机设备、虚拟化加速设备、数据传输方法及存储介质 - Google Patents

计算机设备、虚拟化加速设备、数据传输方法及存储介质 Download PDF

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WO2022213865A1
WO2022213865A1 PCT/CN2022/084279 CN2022084279W WO2022213865A1 WO 2022213865 A1 WO2022213865 A1 WO 2022213865A1 CN 2022084279 W CN2022084279 W CN 2022084279W WO 2022213865 A1 WO2022213865 A1 WO 2022213865A1
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Prior art keywords
serial port
virtualized
physical machine
data
serial
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PCT/CN2022/084279
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English (en)
French (fr)
Inventor
吴斌斌
张献涛
傅俊康
文敢
任晋奎
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阿里云计算有限公司
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Publication of WO2022213865A1 publication Critical patent/WO2022213865A1/zh
Priority to US18/377,249 priority Critical patent/US20240037059A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a computer device, a virtualization acceleration device, a data transmission method, and a storage medium.
  • UART Universal Asynchronous Receiver/Transmitter
  • serial transceivers usually used in embedded systems, and is responsible for realizing asynchronous communication between the physical machine where it is located and external devices.
  • some information such as system logs, can be output through the UART.
  • UART is a low-speed data communication protocol, and its data output rate is relatively slow, especially when the UART output data will trigger the CPU to shut down the interrupt, it will also cause the CPU to shut down the interrupt for a long time and reduce the CPU usage.
  • Various aspects of the present application provide a computer device, a virtualization acceleration device, a data transmission method, and a storage medium, so as to improve the utilization rate of the CPU and ensure the stability of the service performance of the physical machine.
  • An embodiment of the present application provides a computer device, including: a physical machine and a virtualization acceleration device; the virtualization acceleration device is connected to the physical machine through a high-speed serial bus; the virtualization acceleration device is provided with a serial port device that implements virtualization oriented to the physical machine , which is used to cooperate with the physical machine to send and receive serial port data; the physical machine is used to identify the virtualized serial port device and send and receive serial port data through the virtualized serial port device.
  • Embodiments of the present application further provide a virtualization acceleration device, including: a high-speed serial bus and a virtualized serial port device oriented to physical machine implementation; the virtualization acceleration device is connected to the physical machine through the high-speed serial bus and the virtualized serial port device for cooperating with the physical machine to send and receive serial port data when the virtualized acceleration device is connected to the physical machine through the high-speed serial bus.
  • a virtualization acceleration device including: a high-speed serial bus and a virtualized serial port device oriented to physical machine implementation; the virtualization acceleration device is connected to the physical machine through the high-speed serial bus and the virtualized serial port device for cooperating with the physical machine to send and receive serial port data when the virtualized acceleration device is connected to the physical machine through the high-speed serial bus.
  • the embodiments of the present application further provide a physical machine, including: a memory and a processor; the memory is used to store a computer program; the processor is coupled to the memory and used to execute the computer program, so as to: identify a virtualized serial port device, The serial port data is sent and received through a virtualized serial port device; wherein, the virtualized serial port device is implemented on a virtualized acceleration device connected to the physical machine through a high-speed serial bus.
  • the embodiments of the present application also provide a data transmission method, which is suitable for a virtualization acceleration device, and a virtualized serial port device oriented to a physical machine is implemented on the virtualization acceleration device.
  • the data of the first serial port and output the data of the first serial port; or receive the data of the second serial port from the outside, and send the data of the second serial port to the physical machine through the virtualized serial port device; wherein, the virtualized acceleration device and the physical machine pass through High-speed serial bus connection.
  • the embodiments of the present application further provide a computer-readable storage medium storing a computer program, and when the computer program is executed by the processor, the processor causes the processor to implement the steps in the data transmission method provided by the embodiments of the present application.
  • Embodiments of the present application further provide a computer program product, including computer programs/instructions, which, when executed by a processor, cause the processor to implement the steps in the data transmission method provided by the embodiments of the present application.
  • a virtualized acceleration device is deployed for a physical machine, the physical machine and the virtualized acceleration device are interconnected through a high-speed serial bus, and the serial device can be virtualized by means of the virtualized
  • the physical machine can realize the sending and receiving of serial port data through the virtualized serial port device.
  • the physical machine For the physical machine, it only needs to transmit the data to the virtualized serial port through the high-speed serial bus.
  • the serial port device is enough, and the subsequent transmission action is completed by the virtualization acceleration device.
  • the rate of serial data transmission of the physical machine can be greatly improved, especially when the serial port data is transmitted.
  • the time window for shutting down the interrupt caused by the serial port data transmission of the physical machine is greatly shortened, which is beneficial to improve the utilization rate of the CPU of the physical machine and ensure the stability of the service performance of the physical machine.
  • FIG. 1a is a schematic structural diagram of a computer device according to an exemplary embodiment of the present application.
  • FIG. 1b is a schematic structural diagram of another computer device provided by an exemplary embodiment of the present application.
  • FIG. 1c is a schematic structural diagram of another computer device provided by an exemplary embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of still another computer device provided by an exemplary embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a data transmission method provided by an exemplary embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a physical machine according to an exemplary embodiment of the present application.
  • FIG. 1a is a schematic structural diagram of a computer device according to an exemplary embodiment of the present application.
  • the computer device 100 at least includes: a physical machine 10 and a virtualization acceleration device 20 .
  • the device form of the physical machine 10 is not limited, and it can be any physical device with certain computing, storage and communication capabilities, such as a desktop computer, a notebook computer, a smart phone, or an IOT device and other terminal devices. It can also be a server-side device such as a conventional server, a host, and a server array. In addition, this embodiment does not limit the implementation structure of the physical machine 10, which may include internal components such as a processor, a memory, a network card chip, an IO bus, and audio and video components. The physical machine 10 may also include non-volatile storage resources such as hard disks and SSD cards.
  • the physical machine 10 may also not include non-volatile storage resources such as hard disks and SSD cards, but instead use the virtualization acceleration device 20 Realize the virtualization of storage resources, and connect to cloud storage resources such as cloud disks and network attached storage devices (NetWork Attached Storage, NAS).
  • non-volatile storage resources such as hard disks and SSD cards
  • virtualization acceleration device 20 Realize the virtualization of storage resources, and connect to cloud storage resources such as cloud disks and network attached storage devices (NetWork Attached Storage, NAS).
  • an operating system (Operating System, OS), one or more application programs, etc. may also run on the physical machine 10 , wherein the OS, application programs and related program data etc. may be stored in a local computer of the physical machine 10 Non-volatile storage resources or storage resources on the cloud.
  • the physical machine 10 in this embodiment may further include some external devices, such as a keyboard, a mouse, an input pen, a printer, a display, and the like.
  • the internal components or external devices included in the physical machine 10 such as audio and video components, displays, etc., may vary due to different device forms. For example, if the physical machine 10 is a terminal device, it may include audio and video components, displays, etc., and if the physical machine 10 is a server device, it may not include audio and video components, displays, and the like.
  • the virtualization acceleration device 20 is a device that can implement virtualization technology, and can help the interconnected physical machine 10 to realize at least part of the virtualization function, that is, the physical machine 10 can implement part or all of the virtualization functions It is offloaded to the virtualization acceleration device 20 to obtain performance acceleration.
  • This embodiment does not limit the implementation form of the virtualization acceleration device 20, and the implementation form may be a board card or a chip.
  • the virtualization acceleration device 20 has an external interface, such as a high-speed serial bus 203, including but not limited to: a peripheral component interconnect standard (Peripheral Component Interconnect) bus, a peripheral component interconnect expansion bus standard (Peripheral Component Interconnect) Interconnect Express, PCIE) bus.
  • a peripheral component interconnect standard Peripheral Component Interconnect
  • PCIE peripheral component interconnect expansion bus standard
  • the virtualization acceleration device 20 has its own computing resources, such as a processor 201, wherein the processor 201 may be a CPU, a GPU, a SAIC chip or a SOC chip, etc., which is not limited .
  • the virtualization acceleration device 20 may also have its own storage resources, for example, may include local storage resources such as memory and hard disk, and may also include cloud storage resources such as cloud disk and NAS.
  • the memory cache 204 shown in FIG. 1 b to FIG. 2 is the local storage resource of the virtualization acceleration device 20 .
  • the virtualization acceleration device 20 also has a network card and its own network resources, which are not shown in FIG. 1a.
  • the virtualization acceleration device 20 adopts an integrated design of software and hardware, which not only includes some hardware resources mentioned above, but also includes software resources running on the hardware resources, such as an operating system, which is used to implement virtualization technology.
  • software and related hardware drivers are used to implement the virtualization technology.
  • the software used to implement the virtualization technology can be adopted but not limited to: Hypervisor, also known as virtual machine monitor (English: virtual machine monitor).
  • Hypervisor is a kind of intermediate software running between hardware and operating system. This software allows multiple operating systems and applications to share a set of basic physical resources. Therefore, it can also be regarded as a "meta" operating system in a virtual environment. It is the core of realizing virtualization technology.
  • the virtualization acceleration device 20 is interconnected with the physical machine 10 through the high-speed serial bus 203, that is, the physical machine 10 is equipped with the virtualization acceleration device 20, which can ensure the reliability and efficiency of information transmission between the two, which is Conditions are provided for offloading part or all of the virtualized logic of computing, storage, network, etc. implemented on the physical machine 10 to the virtualization acceleration device 20 .
  • part of the virtualized logic such as computing, storage, and network originally implemented on the physical machine 10 can be offloaded to the virtualization acceleration device 20, It can not only improve the performance of virtualization and reduce costs, but also ensure that the physical machine 10 has virtual machine functions, can connect to cloud disks and VPC networks like a virtual machine, and can also ensure that the physical machine 10 can use its own computing, storage and other resources alone. There is no problem that multiple virtual machines share resources, thereby turning the physical machine 10 into a computing device that has both the elasticity of the virtual machine and the performance of the physical machine.
  • the computing device has high isolation, and has both the advantages of virtual machine migration and the value of elastic cloud deployment.
  • the virtualization acceleration device 20 is interconnected with the physical machine 10 through the high-speed serial bus 203, which can ensure the reliability and efficiency of information transmission between the two.
  • the virtualization acceleration device 20 may also be interconnected with the physical machine 10 in other ways, such as network interconnection.
  • the physical machine 10 In practical applications, the physical machine 10 often needs to output some information, such as system logs, through a physical serial device, such as a UART device. However, the output rate of the serial device built in the physical machine 10 is slow, especially in some In the application scenario, when the physical machine 10 outputs data through the physical serial port device, the processor of the physical machine 10 may be triggered to be shut down. Experience declines.
  • the virtualized serial port device 205 oriented to the physical machine 101 can be implemented by means of the virtualization acceleration device 20 , for example, the first processing chip of the virtualization acceleration device 20 can be implemented for the physical machine 101 .
  • the virtualized serial port device 205 so that the physical machine 10 can realize the sending and receiving of serial port data through the virtualized serial port device 205.
  • it only needs to transmit the serial port data to be sent to the virtualized serial port device 205; Or it only needs to read the serial port data to be received from the virtualized serial port device 205 through the high-speed serial bus 203, and other processing actions related to the sending and receiving of serial port data are all completed on the virtualized acceleration device 20.
  • the advantage of the bus in transmission speed can greatly improve the transmission rate of serial port data, especially in the case that the CPU is interrupted when the serial port data is transmitted. It is beneficial to improve the utilization rate of the CPU and ensure the stability of the service performance of the physical machine 10 .
  • the virtualization acceleration device 20 is interconnected with the physical machine 10 by using PCI or PCIE.
  • the virtualization acceleration device 20 can be regarded as a PCI or PCIE mounted on the physical machine 10. Therefore, the virtualization acceleration device 20 has its own configuration space, and the configuration space is used to store some description information of the virtualization acceleration device 20, for example, the manufacturer of the virtualization acceleration device, the attributes of the virtualization acceleration device (virtual acceleration device What is the device) or the functions that can be implemented by the virtualization acceleration device 20, etc.
  • the virtualized serial port device 205 when the virtualized serial port device 205 is implemented on the virtualization acceleration device 20, it may specifically be to configure multiple registers required by the serial port device on the virtualization acceleration device 20, and map the multiple registers to the virtualization acceleration device. 20 in the configuration space to implement virtualized serial device 205.
  • the physical machine 10 when it identifies the virtualized serial device 205, it can specifically enumerate the devices on the high-speed serial bus 203. Enumeration refers to traversing all the devices mounted on the high-speed serial bus 203. , and the process of acquiring information in the configuration space corresponding to the device. During the whole process, the physical machine 10 can discover all devices mounted on the high-speed serial bus 203 according to the information in the configuration space of each device. Optionally, the physical machine 10 can enumerate the devices on the high-speed serial bus according to a specified time period, and the time period can be 1 second, 1 minute, or 1 hour, etc.; , to enumerate devices on a high-speed serial bus.
  • the virtualization acceleration device 20 can be identified first, and further, when the virtualization acceleration device 20 is found, the virtualized serial device 205 can be identified according to the value of at least some registers in its configuration space, And load the driver of the virtualized serial port device 205 .
  • the registers may be some registers related to the serial port device 205, or may be all the registers related to the serial port device 205, which are not limited.
  • the physical machine 10 in order to facilitate the physical machine 10 to send and receive serial port data through the virtualized serial port device 205, the built-in serial port device is no longer used.
  • the physical machine 10 can name the virtualized serial port device 205, for example, according to the default naming method of the serial port device, for example, the name of the virtualized serial port device 205 It can be serial port identifier + number, for example, ttyS0, ttyS1 or ttyS2, etc.; and after naming the virtualized serial port device, change the serial port name in the default serial port output parameter of the operating system to the name of the virtualized serial port device, In order to facilitate serial data transmission and reception through the virtualized serial device 205 in the future.
  • a method of modifying the serial port name in the serial port output parameters includes: when the physical machine is powered on, entering the operating system startup interface
  • the virtualization acceleration device 20 further includes: a memory cache 204, as shown in FIG. 1b-FIG. 2 .
  • the memory cache 204 is used to cache serial port data sent and received by the physical machine 10 through the virtualized serial port device 205 .
  • the serial port data that the physical machine 10 needs to send out is called the first serial port data
  • the serial port data that the physical machine 10 needs to receive is called the second serial port data.
  • the process in which the physical machine 10 sends the first serial port data through the virtualized serial port device 205 First, the physical machine 10 sends the first serial port data to the virtualized serial port device 205 through the high-speed serial bus, and the virtualized serial port device 205 sends the first serial port data to the virtualized serial port device 205.
  • a serial port data is output to the memory cache 204, and the processor 201 reads the first serial port data from the memory cache 204 and outputs it.
  • the virtualized serial port device 205 can output the first serial port data to the memory cache 204 bit by bit, and the processor 201 can read the data bits already stored in the memory cache 204 and output the data bits before the memory cache 204 overflows. .
  • the processor 201 can read data from the memory cache 204 according to a fixed data size, for example, read one byte from the memory cache 204 at a time, until all the first serial port data is read and output. .
  • the output of the first serial port data to the target device 30 is taken as an example for illustration.
  • the target device 30 may be, but is not limited to, a host in a VPC network, a cloud storage device, or a management device.
  • the first serial port data is log data
  • the log data can be output to the console of the management device, and the administrator of the computer device 100 can analyze and debug through the console.
  • the process in which the physical machine 10 receives the second serial port data through the virtualized serial port device 205 the processor 201 receives the second serial port data from the outside, and writes the second serial port data into the memory cache 204, and the virtualized serial port device 205 is stored in the memory cache 204.
  • the second serial port data is read from the memory cache 204 , and the second serial port data is sent to the physical machine 10 through the high-speed serial bus 203 .
  • the registers required by the virtualized serial device 205 at least include: a transmit holding register (Transmitter Holding Register, THR), a receive buffer register (Receiver Buffer Register, RBR) and a line status register (Line Status Register, LSR).
  • THR is mainly used to cache the first serial port data output by the physical machine 101
  • RBR is mainly used to cache the second serial port data to be received by the physical machine 101
  • LSR is mainly used to reflect the state of the serial port data when it is sent or received. Whether the serial port data is read, whether the THR can receive data, and whether the processor is in a read or write state, etc.
  • the virtualized serial port device 205 may also include: an interrupt enable register (Interrupt Enable Register, IER), an interrupt identification register (Interrupt Identification Register, IIR), wherein, the IER is used for the virtualized serial port device 205 to be sent to the physical When the machine 10 sends the second serial port data, it sends an interrupt signal to the physical machine 10, so that the physical machine 10 can respond to the interrupt signal and read the second serial port data; IIR is used to identify the current state change information of the virtualized serial port device 205, Some state change information can trigger the virtualized serial device 205 to send an interrupt signal to the physical machine 10. For example, the state change information generated due to the state change of the RBR may trigger the virtualized serial device 205 to send an interrupt to the physical machine 10. Signal.
  • IER interrupt enable register
  • IIR Interrupt Identification Register
  • the registers required by the virtualized serial device 205 may also include: a first in first out control register (First in first out Control Register, FCR), a line control register (Line Control Register, LCR), a modem control register (Modem Control Register, MCR), Modem Status Register (MSR), Erase Register (SCratch Register, SCR) and so on.
  • the serial port device 205 implemented in this embodiment of the present application is virtualized. Some of the registers listed above are used to realize the integrity of the serial port device 205 . In practical applications, the physical machine uses the virtualized serial port device 205 to send and receive serial port data. Actions may not be performed during the process.
  • the physical machine 10 can write the first serial port data into the THR through the high-speed serial bus.
  • the virtualized serial port device 205 detects that data is written into the THR, it will The data of the first serial port is output to the memory cache 204 bit by bit, and the THR state of the LSR is set to 1, indicating that the THR is empty, and the next data to be sent can be received.
  • the THR status bit of the LSR remains 0, and the physical machine 10 will not Continue writing data to THR.
  • the processor 201 reads the existing data in the memory cache 204 and outputs the data to the target device 30 .
  • the processor 201 When the external device (such as the target device 30 ) needs to send the second serial port data to the physical machine 10 , that is, when the physical machine 10 needs to receive the second serial port data, the processor 201 first receives the externally input second serial port data and sends the second serial port data to the physical machine 10 .
  • the second serial port data is written into the memory cache 204 for reading by the virtualized serial port device 205; the virtualized serial port device 205 sequentially reads the second serial port data from the memory cache 204, and writes the second serial port data into the RBR , and then set the data preparation status of LSR to 1, indicating that the serial port data in the RBR is ready, and the physical machine 10 can read the serial port data in the RBR at any time through the high-speed serial bus.
  • the physical machine 10 When the physical machine 10 detects that the data preparation status of the LSR is set to 1, it reads the second serial port data from the RBR through the high-speed serial bus; after the second serial port data is read, the virtualized serial port device 205 will The data preparation status position is 0, indicating that the physical machine 10 has read the data, and the virtualized serial port device 205 can continue to read data from the memory cache 204 and write it into the RBR, and cycle in turn until all the second serial port data transmission is completed.
  • the hardware implementation structure of the virtualization acceleration device 20 is not limited.
  • the virtualization acceleration device 20 may be implemented as a pluggable board structure, as shown in FIG. 1b and FIG. 1c.
  • the board implemented by the virtualization acceleration device 20 includes a first processing chip 20a and a programmable logic device 20b.
  • the programmable logic device 20b may be a field programmable gate array (Field-Programmable Gate Array, FPGA) or a complex programmable logic device (Complex Programmable Logic Device, CPLD) or the like.
  • the first processing chip 20a may be an ASIC chip or an SOC. As shown in FIG.
  • the processor 201 and the memory cache 204 are implemented on the first processing chip 20a; the virtualized serial port device 205 is implemented on the programmable logic device 20b.
  • the programmable logic device 20b is illustrated by taking an FPGA as an example.
  • the virtualized serial device 205 implemented on the programmable logic device 20b such as FPGA mainly refers to the registers required to realize these serial devices 202 on the programmable logic device 20b, and the processor 201 maps these registers to the virtualized In the PCI or PCIE configuration space of the acceleration device 20 .
  • the virtualization acceleration device 20 includes a second processing chip 20c; the processor 201, the memory cache 204 and the virtualized serial port device 205 are all implemented on the second processing chip 20c.
  • the second processing chip 20c may use an ASIC chip or an SOC.
  • the implementation of the virtualized serial device 205 on the virtualization acceleration device 20 mainly refers to the registers required to realize these serial devices 205 on the second processing chip 20c, and the processor 201 maps these registers to the virtualization acceleration device in the PCI or PCIE configuration space of device 20 .
  • the second processing chip 20c may adopt a customized chip, such as a customized ASIC chip or SOC chip.
  • the virtualization acceleration device 20 includes a first processing chip 20a and a third processing chip 20d.
  • the first processing chip 20a may use an ASIC chip or an SOC; the third processing chip 20d may use a customized chip, for example, a customized ASIC chip or an SOC.
  • the processor 201 and the memory cache 204 are implemented on the first processing chip 20a; the virtualized serial port device 205 is implemented on the third processing chip 20d.
  • the virtualized serial device 205 implemented on the third processing chip 20d mainly refers to the registers required to implement these serial devices 205 on the third processing chip 20d, and the processor 201 maps these registers to the virtualization acceleration in the PCI or PCIE configuration space of device 20 .
  • the hardware modules or devices with various functions can be implemented on the virtualization acceleration device 20 as needed, for example, virtualization can be implemented
  • the hardware modules or devices required by the acceleration device 20 may also implement the hardware modules or devices required by the physical machine 10, and are not limited to virtualized serial port devices.
  • the physical machine can realize the sending and receiving of serial port data through the virtualized serial port device.
  • it only needs to transmit data to the virtualized serial port device through the high-speed serial bus, or only need to transmit the data to the virtualized serial port device through the high-speed serial bus.
  • the serial bus can read data from the virtualized serial port device. Other actions related to the sending and receiving of serial port data are completed by the virtualized acceleration device.
  • the serial port on the physical machine can be greatly improved.
  • the data transmission rate is beneficial to improve the CPU usage of the physical machine and ensure the stability of the service performance of the physical machine.
  • the embodiment of the present application also provides a data transmission method, which is suitable for a virtualization acceleration device, and a virtualized serial port device oriented to a physical machine is implemented on the virtualization acceleration device. As shown in FIG. 3 , the method includes:
  • step 301 and step 302 are and/or relationship, and the data transmission method may only include step 301, may only include step 302, or may include both step 301 and step 302.
  • the transmission method simultaneously includes step 301 and step 302 for illustration, but is not limited thereto.
  • a virtualized acceleration device is deployed for a physical machine, the physical machine and the virtualized acceleration device are interconnected through a high-speed serial bus, and the serial port device can be virtualized by means of the virtualized acceleration device, that is, in the virtualization
  • the virtualized serial port device oriented to the physical machine is realized on the acceleration device.
  • the physical machine can realize the sending and receiving of serial port data through the virtualized serial port device.
  • the virtualized serial port device is enough, and the subsequent transmission actions are completed by the virtualized acceleration device.
  • the speed of serial port data transmission by the physical machine can be greatly improved, especially when transmitting serial port data.
  • the time window for the shutdown of the physical machine caused by the transmission of serial port data is greatly shortened, which is beneficial to improve the utilization rate of the physical machine CPU and ensure the stability of the physical machine service performance.
  • the execution subject of each step of the method provided in the above-mentioned embodiments may be the same device, or the method may also be executed by different devices.
  • the execution subject of steps 301 to 302 may be device A; for another example, the execution subject of step 301 may be device A, and the execution subject of step 302 may be device B; and so on.
  • an embodiment of the present application also provides a virtualization acceleration device.
  • the virtualized acceleration device 20 is connected to the physical machine 10 through the high-speed serial bus 203; the virtualized serial device 205 cooperates with the physical machine 10 when the virtualization acceleration device 20 is connected to the physical machine 10 through the high-speed serial bus 203.
  • the physical machine 10 transmits and receives serial port data.
  • the virtualization acceleration device further includes: a processor 201; the processor is used to implement a virtualized serial port device oriented to the physical machine on the virtualization acceleration device, and cooperate with the physical machine to pass the virtualized serial port device. Send and receive serial data.
  • the processor when the processor implements a virtualized serial port device on the virtualization acceleration device, it is specifically used for: configuring multiple registers required by the serial port device on the virtualization acceleration device, and transferring the multiple registers to the virtualized acceleration device.
  • the registers are mapped into the configuration space of the virtualized acceleration device to realize the virtualized serial device.
  • the virtualization acceleration device 20 further includes: a memory cache 204 .
  • the memory cache can cache the serial port data sent and received by the physical machine through the virtualized serial port device; when the processor cooperates with the physical machine to send and receive serial port data through the virtualized serial port device, it is specifically used to: read the physical machine from the memory cache.
  • the first serial port data written by the virtualized serial port device is output, or the second serial port data that the physical machine needs to receive is written to the memory cache data, so that the virtualized serial port device can read and send it to the physical machine.
  • the plurality of registers at least include: THR and LSR; the virtualized serial port device can write the first serial port data in the THR after the physical machine writes the first serial port data into the THR through the high-speed serial bus. Output to the memory cache and set the THR status bit of the LSR to 1.
  • the plurality of registers at least include: RBR and LSR; the virtualized serial port device writes the second serial port data read from the memory cache into the RBR, and sets the data preparation status of the LSR to 1 to For the physical machine to read the second serial port data from the RBR through the high-speed serial bus; and after the second serial port data is read, the data preparation state of the LSR is set to 0.
  • the virtualization acceleration device in the embodiment of the present application is interconnected with the physical machine through a high-speed serial bus, and the serial port device can be virtualized with the help of the virtualization acceleration device, that is, the virtualized serial port oriented to the physical machine can be realized on the virtualization acceleration device.
  • the physical machine can send and receive serial port data through the virtualized serial port device.
  • it only needs to transmit the data to the virtualized serial port device through the high-speed serial bus.
  • the completion of the virtualization acceleration device with the advantage of the high-speed serial bus in transmission speed, can greatly improve the transmission rate of serial port data, especially when the serial port data will be triggered to shut down the CPU and greatly shorten the physical machine because the serial port is transmitted.
  • the time window for shutting down interrupts caused by data is conducive to improving the utilization rate of the CPU and ensuring the stability of the service performance of the physical machine.
  • the embodiments of the present application further provide a computer-readable storage medium storing a computer program.
  • the processor can implement the steps in the data transmission method provided by the embodiments of the present application.
  • the embodiments of the present application also provide a computer program product, including computer programs/instructions, when the computer programs/instructions are executed by a processor, the processor is caused to implement the data transmission method provided by the embodiments of the present application.
  • an embodiment of the present application also provides a physical machine, and the physical machine can be connected to the virtualization acceleration device in the foregoing embodiment through a high-speed serial bus, such as PCI or PCIE; as shown in FIG. 4
  • the physical machine includes: a memory 44 and a processor 45 .
  • Memory 44 stores computer programs and may be configured to store various other data to support operations on the physical machine. Examples of such data include instructions for any application or method operating on the physical machine.
  • Memory 44 may be implemented by any type of volatile or non-volatile storage device or combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read only memory
  • EPROM erasable Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Magnetic or Optical Disk any type of volatile or non-volatile storage device or combination thereof.
  • the processor 45 coupled with the memory 44, is used for executing the computer program in the memory 44, so as to: identify the virtualized serial port device, and carry out the sending and receiving of serial port data through the virtualized serial port device; wherein, the virtualized serial port device It is implemented on a virtualized acceleration device connected to the physical machine through a high-speed serial bus.
  • the processor 45 when the processor 45 identifies the virtualized serial device, it is specifically used to: enumerate the devices on the high-speed serial bus, and in the case of finding the virtualized acceleration device, according to the virtualized acceleration device.
  • the value of at least some registers in the configuration space of the device identifies the virtualized serial device.
  • the processor 45 is also used to: when identifying the virtualized serial port device for the first time, name the virtualized serial port device, and modify the serial port name in the serial port output parameter in the operating system to be virtualized. The name of the serial device.
  • the processor 45 when the processor 45 transmits and receives serial port data through the virtualized serial port device, it is specifically used to: write the first serial port data into the THR on the virtualized serial port device through the high-speed serial bus, to For the virtualized serial device to read and write to the memory cache on the virtualized acceleration device; or when the data preparation status of the LSR of the virtualized serial device is detected to be 1, from the virtualized serial device through the high-speed serial bus.
  • the RBR reads the second serial port data.
  • the physical machine further includes: a communication component 46 , a display 47 , a power supply component 48 , an audio component 49 and other components. Only some components are schematically shown in FIG. 4 , which does not mean that the physical machine only includes the components shown in FIG. 4 . It should be noted that the components in the dotted box in FIG. 4 are optional components, not mandatory components, which may depend on the product form of the physical machine.
  • the above-mentioned communication components in FIG. 4 are configured to facilitate wired or wireless communication between the device where the communication components are located and other devices.
  • the device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, a mobile communication network such as 2G, 3G, 4G/LTE, 5G, or a combination thereof.
  • the communication component receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel.
  • the communication assembly further includes a near field communication (NFC) module to facilitate short-range communication.
  • the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.
  • RFID radio frequency identification
  • IrDA infrared data association
  • UWB ultra-wideband
  • Bluetooth Bluetooth
  • the above-mentioned display in FIG. 4 includes a screen, and the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user.
  • the touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or swipe action, but also detect the duration and pressure associated with the touch or swipe action.
  • a power supply assembly in FIG. 4 above provides power for various components of the equipment where the power supply assembly is located.
  • a power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the equipment in which the power supply assembly is located.
  • the audio components in FIG. 4, described above, may be configured to output and/or input audio signals.
  • the audio component includes a microphone (MIC) that is configured to receive external audio signals when the device in which the audio component is located is in operating modes, such as call mode, recording mode, and speech recognition mode.
  • the received audio signal may be further stored in memory or transmitted via the communication component.
  • the audio assembly further includes a speaker for outputting audio signals.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.
  • a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
  • processors CPUs
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include forms of non-persistent memory, random access memory (RAM) and/or non-volatile memory in computer readable media, such as read only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
  • RAM random access memory
  • ROM read only memory
  • flash RAM flash memory
  • Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology.
  • Information may be computer readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
  • computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

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Abstract

本申请实施例提供一种计算机设备、虚拟化加速设备、数据传输方法及存储介质。在本申请实施例中，为物理机部署虚拟化加速设备，物理机与虚拟化加速设备通过高速串行总线互联，借助于虚拟化加速设备可对串口设备进行虚拟化，即在虚拟化加速设备上实现面向物理机的虚拟化的串口设备，基于此，物理机可通过该虚拟化的串口设备实现串口数据的收发，对物理机来说，只需通过高速串行总线将数据传输至虚拟化的串口设备即可，后续传输动作由虚拟化加速设备完成，借助于高速串行总线在传输速度上的优势，可大大提高物理机串口数据传输的速率，有利于提高物理机CPU的使用率，保证物理机服务性能的稳定性。

Description

计算机设备、虚拟化加速设备、数据传输方法及存储介质
本申请要求2021年04月06日递交的申请号为202110365740.5、发明名称为“计算机设备、虚拟化加速设备、数据传输方法及存储介质”中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种计算机设备、虚拟化加速设备、数据传输方法及存储介质。
背景技术
通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)是串口收发的逻辑电路，通常用于嵌入式系统，负责实现其所在物理机与外部设备之间的异步通信。在物理机运行过程中，可以通过UART输出一些信息，例如系统日志等。但是，UART是一种低速数据通信协议，其数据输出速率较慢，尤其是在UART输出数据会触发CPU关中断的情况下，还会导致CPU关中断时间较长，降低CPU使用率。
发明内容
本申请的多个方面提供一种计算机设备、虚拟化加速设备、数据传输方法及存储介质，用以提高CPU的使用率，保证物理机服务性能的稳定性。
本申请实施例提供一种计算机设备，包括：物理机和虚拟化加速设备；虚拟化加速设备通过高速串行总线与物理机连接；虚拟化加速设备上实现有面向物理机的虚拟化的串口设备，用于配合物理机进行串口数据的收发；物理机，用于识别虚拟化的串口设备，并通过虚拟化的串口设备进行串口数据的收发。
本申请实施例还提供一种虚拟化加速设备，包括：高速串行总线和面向 物理机实现的虚拟化的串口设备；所述虚拟化加速设备通过所述高速串行总线与所述物理机连接；以及所述虚拟化的串口设备，用于在所述虚拟化加速设备通过所述高速串行总线与所述物理机连接的情况下，配合所述物理机进行串口数据的收发。
本申请实施例还提供一种物理机，包括：存储器和处理器；存储器，用于存储计算机程序；处理器，与存储器耦合，用于执行计算机程序，以用于：识别虚拟化的串口设备，并通过虚拟化的串口设备进行串口数据的收发；其中，虚拟化的串口设备是在与物理机通过高速串行总线连接的虚拟化加速设备上实现的。
本申请实施例还提供一种数据传输方法，适用于虚拟化加速设备，在虚拟化加速设备上实现有面向物理机的虚拟化的串口设备，方法包括：接收物理机通过虚拟化的串口设备发送的第一串口数据，并将第一串口数据输出；或者接收来自外部的第二串口数据，并通过虚拟化串口设备将第二串口数据发送给物理机；其中，虚拟化加速设备与物理机通过高速串行总线连接。
本申请实施例还提供一种存储有计算机程序的计算机可读存储介质，当计算机程序被处理器执行时，致使处理器实现本申请实施例提供的数据传输方法中的步骤。
本申请实施例还提供一种计算机程序产品，包括计算机程序/指令，当计算机程序/指令被处理器执行时，致使处理器实现本申请实施例提供的数据传输方法中的步骤。
在本申请实施例中，为物理机部署虚拟化加速设备，物理机与虚拟化加速设备通过高速串行总线互联，借助于虚拟化加速设备可对串口设备进行虚拟化，即在虚拟化加速设备上实现面向物理机的虚拟化的串口设备，基于此，物理机可通过该虚拟化的串口设备实现串口数据的收发，对物理机来说，只需通过高速串行总线将数据传输至虚拟化的串口设备即可，后续传输动作由 虚拟化加速设备完成，借助于高速串行总线在传输速度上的优势，可大大提高物理机进行串口数据传输的速率，尤其是在传输串口数据时会触发CPU关中断的情况下大大缩短物理机因为传输串口数据而引起的关中断的时间窗口，有利于提高物理机CPU的使用率，保证物理机服务性能的稳定性。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1a为本申请示例性实施例提供的一种计算机设备的结构示意图；
图1b为本申请示例性实施例提供的另一种计算机设备的结构示意图；
图1c为本申请示例性实施例提供的又一种计算机设备的结构示意图；
图2为本申请示例性实施例提供的再一种计算机设备的结构示意图；
图3为本申请示例性实施例提供的一种数据传输方法的流程示意图；
图4为本申请示例性实施例提供的一种物理机的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
以下结合附图，详细说明本申请各实施例提供的技术方案。
图1a为本申请示例性实施例提供的一种计算机设备的结构示意图。如图1a所示，该计算机设备100至少包括：物理机10和虚拟化加速设备20。
在本实施例中，并不对物理机10的设备形态进行限制，可以是任何具有一定计算、存储和通信能力的实体设备，例如可以是台式电脑、笔记本电脑、智能手机或IOT设备等终端设备，也可以是常规服务器、主机、服务器阵列等服务端设备。另外，本实施例也不对物理机10的实现结构进行限制，可以包括处理器、内存、网卡芯片、IO总线、音视频组件等内部组件。其中，物理机10还可以包括硬盘、SSD卡等非易失性存储资源，当然，物理机10也可以不包括硬盘、SSD卡等非易失性存储资源，而是借助于虚拟化加速设备20实现存储资源的虚拟化，对接云盘、网络附属存储设备(NetWork Attached Storage，NAS)等云上存储资源。
除上述内部组件之外，物理机10上还可以运行操作系统(Operating System，OS)、一个或多个应用程序等，其中，OS、应用程序以及相关程序数据等可存储在物理机10本地的非易失性存储资源或云上存储资源中。进一步，本实施例的物理机10还可以包括一些外部设备，例如键盘、鼠标、输入笔、打印机、显示器等。需要说明的是，物理机10所包含的内部组件或外部设备，例如音视频组件、显示器等，会因为设备形态的不同而有所不同。例如，如果物理机10为终端设备，则可以包含音视频组件、显示器等，如果物理机10是服务端设备，则可以不包含音视频组件、显示器等。
在本实施例中，虚拟化加速设备20是一款可以实现虚拟化技术的设备，且可以帮助与其互联的物理机10实现至少部分虚拟化功能，即物理机10可以将部分或全部虚拟化功能卸载到虚拟化加速设备20上，从而获得性能上的加速。本实施例并不限定虚拟化加速设备20的实现形态，其实现形态可以是板卡或芯片。如图1a所示，虚拟化加速设备20具有对外接口，例如高速串行总线203，包括但不限于：外设部件互连标准(Peripheral Component Interconnect)总线、外设部件互联扩展总线标准(Peripheral Component Interconnect Express，PCIE)总线。可选地，如图1a所示，该虚拟化加速设 备20具有自己的计算资源，例如处理器201，其中，处理器201可以是CPU、GPU、SAIC芯片或SOC芯片等，对此不做限定。可选地，虚拟化加速设备20还可以有自己的存储资源，例如可以包括内存、硬盘等本地存储资源，也可以包括云盘、NAS等云存储资源。图1b-图2中所示的内存缓存204即为虚拟化加速设备20的本地存储资源。进一步，虚拟化加速设备20还具有网卡和自己的网络资源，未在图1a中示出。
在本实施例中，虚拟化加速设备20采用软硬一体化设计，不仅包括上文提到的一些硬件资源，还包括运行在硬件资源上的软件资源，例如操作系统、用于实现虚拟化技术的软件以及相关硬件的驱动程序等。其中，用于实现虚拟化技术的软件可以采用但不限于：Hypervisor，又称虚拟机监视器(英语：virtual machine monitor)。Hypervisor是一种运行在硬件和操作系统之间的中间软件，该软件可以让多个操作系统和应用共享一套基础物理资源，因此，也可以看作是虚拟环境中的“元”操作系统，是实现虚拟化技术的核心。
在本实施例中，虚拟化加速设备20通过高速串行总线203与物理机10互联，即物理机10搭载虚拟化加速设备20，可以保证两者之间信息传输的可靠性和高效性，为将物理机10上实现的计算、存储、网络等虚拟化的部分或全部逻辑卸载到虚拟化加速设备20上提供了条件。在此基础上，借助于虚拟化加速设备20的软硬件资源，可以将原本在物理机10上实现的计算、存储、网络等虚拟化的部分逻辑卸载(offload)到虚拟化加速设备20上，不仅可以提升虚拟化的性能，降低成本，而且能够保证物理机10具有虚拟机功能，能够像虚拟机一样对接云盘和VPC网络，还能保证物理机10独自使用自己的计算、存储等资源，不存在多个虚拟机共享资源的问题，从而将物理机10变成一种兼具虚拟机弹性和物理机性能的计算设备。该计算设备具有较高的隔离性，且兼具虚拟机的迁移优势和弹性云化部署价值，还可以支持快速交付、兼容虚拟机镜像、云存储设备启动、挂接云存储设备、物理 机故障的迁移恢复、自动化运维等优势，具有很高的应用价值。另外，虚拟化加速设备20通过高速串行总线203与物理机10互联，可以保证两者之间信息传输的可靠性和高效性。当然，虚拟化加速设备20也可以通过其它方式与物理机10互联，例如网络互联。
在实际应用中，物理机10经常需要通过物理的串口设备，例如，UART设备，输出一些信息，例如系统日志，但是，物理机10上自带的串口设备的输出速率较慢，尤其是在一些应用场景中，物理机10通过物理串口设备输出数据时，可能会触发物理机10的处理器关中断，在处理器关中断期间，可能会造成处理器响应不及时，造成服务性能的波动，用户体验下降。鉴于此，在本申请实施例中，借助于虚拟化加速设备20可实现面向物理机101的虚拟化的串口设备205，例如，在虚拟化加速设备20的第一处理芯片上实现面向物理机101的虚拟化的串口设备205，使得物理机10可通过该虚拟化的串口设备205实现串口数据的收发，对物理机10来说，只需要将要发送的串口数据传输至虚拟化的串口设备205；或者只需要通过高速串行总线203从虚拟化的串口设备205上读取要接收的串口数据即可，关于串口数据收发的其它处理动作均在虚拟化加速设备20上完成，借助于高速串行总线在传输速度上的优势，可大大提高串口数据的传输速率，尤其是在传输串口数据时会触发CPU关中断的情况下大大缩短物理机10因为传输串口数据而引起的关中断的时间窗口，有利于提高CPU的使用率，保证物理机10服务性能的稳定性。
在一可选实施例中，虚拟化加速设备20采用PCI或PCIE与物理机10互联，相对于物理机10而言，虚拟化加速设备20可视为挂载于物理机10上的PCI或PCIE设备，故虚拟化加速设备20具有自己的配置空间，该配置空间用于存储虚拟化加速设备20的一些描述信息，例如，虚拟化加速设备的生产厂商、虚拟化加速设备的属性(虚拟化加速设备是什么设备)或者 虚拟化加速设备20可以实现的功能等。基于此，在虚拟化加速设备20上实现虚拟化的串口设备205时，具体可以是在虚拟化加速设备20上配置串口设备所需的多个寄存器，并将多个寄存器映射到虚拟化加速设备20的配置空间中，以实现虚拟化的串口设备205。
基于上述，物理机10在识别虚拟化的串口设备205时，具体可以对高速串行总线203上的设备进行枚举，枚举是指对挂载到高速串行总线203上的所有设备进行遍历，并获取设备对应的配置空间中信息的过程，整个过程中，物理机10根据每个设备的配置空间中的信息，可发现挂载到高速串行总线203上的所有设备。可选地，物理机10可以按照指定的时间周期，对高速串行总线上的设备进行枚举，该时间周期可以是1秒、1分钟或者1小时等；也可以在每次上电的时候，对高速串行总线上的设备进行枚举。在本实施例中，首先可以识别到虚拟化加速设备20，进一步，在发现虚拟化加速设备20的情况下，可根据其配置空间中至少部分寄存器的值，识别到虚拟化的串口设备205，并加载该虚拟化的串口设备205的驱动。其中，至少部分寄存器可以是与串口设备205相关的部分寄存器，也可以是与串口设备205相关的全部寄存器，对此不做限定。
在本申请一些可选实施例中，考虑到物理机10上具有自带的串口设备，为了便于物理机10能够通过虚拟化的串口设备205进行串口数据收发，而不再使用自带的串口设备，因此在首次识别到虚拟化的串口设备205时，物理机10可以为该虚拟化的串口设备205命名，例如，可以按照默认的串口设备的命名方式，例如，虚拟化的串口设备205的名称可以是串口标识符+数字，例如，ttyS0、ttyS1或者ttyS2等；以及在为虚拟化的串口设备命名后，将操作系统默认的串口输出参数中的串口名称修改为虚拟化的串口设备的名称，以便于在后续能够通过虚拟化的串口设备205进行串口数据收发。可选地，一种修改串口输出参数中的串口名称的方式包括：在给物理机上电时， 进入操作系统启动界面，通过命令行的方式，修改串口输出参数中的串口名称，但不限于此。
在一可选实施例中，虚拟化加速设备20还包括：内存缓存204，如图1b-图2所示。该内存缓存204用于缓存物理机10通过虚拟化的串口设备205进行收发的串口数据。为了便于描述和区分，将物理机10需要向外发送的串口数据称为第一串口数据，将需要物理机10接收的串口数据称为第二串口数据。下面对虚拟化加速设备20配合物理机10通过虚拟化的串口设备205进行串口数据收发的过程进行描述：
物理机10通过虚拟化的串口设备205发送第一串口数据的过程：首先，物理机10通过高速串行总线将第一串口数据发送给虚拟化的串口设备205，虚拟化的串口设备205将第一串口数据输出至内存缓存204，由处理器201从内存缓存204中读取第一串口数据并输出。可选地，虚拟化的串口设备205可以一位一位的将第一串口数据输出至内存缓存204，处理器201可以在内存缓存204溢出之前读取内存缓存204中已经存储的数据位并输出。进一步可选地，处理器201可以按照固定的数据大小，从内存缓存204中读取数据，例如每次从内存缓存204中读取一个字节，直至将第一串口数据全部读取并输出为止。在图2中以将第一串口数据输出给目标设备30为例进行图示，目标设备30可以是但不限于：VPC网络内的主机、云存储设备或者管理设备等。例如，若第一串口数据为日志数据，则可以将该日志数据输出给管理设备的控制台(console)，计算机设备100的管理人员通过控制台进行分析以及调试。
物理机10通过虚拟化的串口设备205接收第二串口数据的过程：处理器201接收来自外部的第二串口数据，并将第二串口数据写入内存缓存204中，虚拟化的串口设备205在识别到内存缓存204中具有待传输的数据时，从内存缓存204读取第二串口数据，并通过高速串行总线203将第二串口数 据发送给物理机10。
在一可选实施例中，虚拟化的串口设备205需要的寄存器至少包括：发送保持寄存器(Transmitter Holding Register，THR)、接收缓冲寄存器(Receiver Buffer Register，RBR)和线路状态寄存器(Line Status Register，LSR)。THR主要用于缓存物理机101输出的第一串口数据，RBR主要用于缓存物理机101将要接收的第二串口数据，LSR主要用于体现串口数据发送或接收时的状态，例如，RBR中的串口数据是否被读走、THR是否可以接收数据以及处理器处于读状态还是写状态等等。进一步，虚拟化的串口设备205还可以包括：中断使能寄存器(Interrupt Enable Register，IER)、中断识别寄存器(Interrupt Identification Register，IIR)，其中，IER用于在虚拟化的串口设备205需要向物理机10发送第二串口数据时，向物理机10发送中断信号，以供物理机10响应该中断信号，读取第二串口数据；IIR用于识别虚拟化的串口设备205的当前状态改变信息，一些状态改变信息可以触发虚拟化的串口设备205向物理机10发送中断信号，例如，由于RBR的状态发生改变而产生的状态改变信息，就可能触发虚拟化的串口设备205向物理机10发送中断信号。
进一步可选地，虚拟化的串口设备205需要的寄存器还可以包括：先进先出控制寄存器(First in first out Control Register，FCR)、线控寄存器(Line Control Register，LCR)、调制解调器控制寄存器(Modem Control Register，MCR)、调制解调器状态寄存器(Modem Status Register，MSR)、擦除寄存器(SCratch Register，SCR)等等。本申请实施例实现的串口设备205是虚拟化的，在上述列举的寄存器中有一些是为了实现串口设备205的完整性，在实际应用中，物理机通过虚拟化的串口设备205进行串口数据收发过程中可能并不会进行动作。
基于具有上述寄存器结构的串口设备205，物理机10通过该串口设备 205进行串口数据收发的详细过程如下：
当物理机10要发送第一串口数据时，物理机10可以通过高速串行总线向THR中写入第一串口数据，虚拟化的串口设备205检测到有数据写入THR中时，将THR中的第一串口数据一位一位地输出至内存缓存204中，并将LSR的THR状态位置1，表示THR为空，可接收下一个要发送的数据。当物理机10通过高速串行总线向THR中写入数据之后，但THR还未将写入的数据传输至内存缓存204中时，LSR的THR状态位保持为0，此时物理机10不会继续向THR中写入数据。第一串口数据被输出至内存缓存204之后，处理器201读取内存缓存204中已有的数据并输出至目标设备30。
当外部设备(如目标设备30)需要向物理机10发送第二串口数据时，亦即，物理机10需要接收第二串口数据时，处理器201先接收外部输入的第二串口数据并将第二串口数据写入内存缓存204中，以供虚拟化的串口设备205进行读取；虚拟化的串口设备205依次从内存缓存204中读取第二串口数据，并将第二串口数据写入RBR中，接着将LSR的数据准备状态位置1，表示RBR中的串口数据已经准备就绪，物理机10随时可以通过高速串行总线将RBR中的串口数据读走。物理机10在检测到LSR的数据准备状态位置1时，通过高速串行总线从RBR中读取第二串口数据；在第二串口数据被读取完毕后，虚拟化的串口设备205将LSR的数据准备状态位置0，表示物理机10已经将数据读走，虚拟化的串口设备205可以继续从内存缓存204中读取数据并写入RBR中，依次循环，直至所有第二串口数据传输完毕。
在本申请实施例中，并不限定虚拟化加速设备20的硬件实现结构。可选地，虚拟化加速设备20可实现为可插拔的板卡结构，如图1b和图1c所示。进一步，如图1b所示，虚拟化加速设备20实现的板卡上包括第一处理芯片20a和可编程逻辑器件20b。其中，可编程逻辑器件20b可以是现场可 编程门阵列(Field-Programmable Gate Array，FPGA)或复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)等。第一处理芯片20a可以是ASIC芯片或SOC。如图1b所示，处理器201和内存缓存204位于第一处理芯片20a上实现；虚拟化的串口设备205位于可编程逻辑器件20b上实现。在图1b中，以FPGA为例对可编程逻辑器件20b进行图示。其中，在可编程逻辑器件20b如FPGA上实现虚拟化的串口设备205，主要是指在可编程逻辑器件20b实现这些串口设备202所需的寄存器，并由处理器201将这些寄存器映射到虚拟化加速设备20的PCI或PCIE配置空间中。
或者，如图1c所示，虚拟化加速设备20包括第二处理芯片20c；处理器201、内存缓存204以及虚拟化的串口设备205均位于第二处理芯片20c上实现。可选地，第二处理芯片20c可以采用ASIC芯片或SOC。其中，在虚拟化加速设备20上实现虚拟化的串口设备205，主要是指在第二处理芯片20c上实现这些串口设备205所需的寄存器，并由处理器201将这些寄存器映射到虚拟化加速设备20的PCI或PCIE配置空间中。在图1c所示实施例中，第二处理芯片20c可采用定制化芯片，如定制化的ASIC芯片或SOC芯片。
或者，如图2所示，虚拟化加速设备20包括第一处理芯片20a和第三处理芯片20d。其中，第一处理芯片20a可以采用ASIC芯片或SOC；第三处理芯片20d可以采用定制化芯片，例如可以采用定制化的ASIC芯片或SOC。如图2所示，处理器201和内存缓存204位于第一处理芯片20a上实现；虚拟化的串口设备205位于第三处理芯片20d上实现。其中，在第三处理芯片20d上实现虚拟化的串口设备205，主要是指在第三处理芯片20d上实现这些串口设备205所需的寄存器，并由处理器201将这些寄存器映射到虚拟化加速设备20的PCI或PCIE配置空间中。
需要说明的是，基于上述可编程逻辑器件20b、第二处理芯片20c或第 三处理芯片20d，可按需在虚拟化加速设备20上实现各种功能的硬件模块或设备，例如可以实现虚拟化加速设备20所需的硬件模块或设备，也可以实现物理机10所需的硬件模块或设备，并不限于虚拟化的串口设备。
在本实施例中，物理机可通过该虚拟化的串口设备实现串口数据的收发，对物理机来说，只需通过高速串行总线将数据传输至虚拟化的串口设备，或者只需要通过高速串行总线从虚拟化的串口设备上读取数据即可，关于串口数据收发的其它动作由虚拟化加速设备完成，借助于高速串行总线在传输速度上的优势，可大大提高物理机进行串口数据传输的速率，有利于提高物理机CPU的使用率，保证物理机服务性能的稳定性。
本申请实施例还提供一种数据传输方法，该方法适用于虚拟化加速设备，该虚拟化加速设备上实现有面向物理机的虚拟化的串口设备，如图3所示，该方法包括：
301、接收物理机通过虚拟化的串口设备发送的第一串口数据，并将第一串口数据输出；
302、接收来自外部的第二串口数据，并通过虚拟化串口设备将第二串口数据发送给物理机；其中，虚拟化加速设备与物理机通过高速串行总线连接。
在本实施例中，步骤301与步骤302为和/或关系，数据传输方法可以只包含步骤301，也可以只包含步骤302，还可以同时包含步骤301和步骤302，在图3中，以数据传输方法同时包含步骤301和步骤302为例进行图示，但并不限于此。
本申请实施例的数据传输方法，为物理机部署虚拟化加速设备，物理机与虚拟化加速设备通过高速串行总线互联，借助于虚拟化加速设备可对串口设备进行虚拟化，即在虚拟化加速设备上实现面向物理机的虚拟化的串口设备，基于此，物理机可通过该虚拟化的串口设备实现串口数据的收发，对物 理机来说，只需通过高速串行总线将数据传输至虚拟化的串口设备即可，后续传输动作由虚拟化加速设备完成，借助于高速串行总线在传输速度上的优势，可大大提高物理机进行串口数据传输的速率，尤其是在传输串口数据时会触发CPU关中断的情况下大大缩短物理机因为传输串口数据而引起的关中断的时间窗口，有利于提高物理机CPU的使用率，保证物理机服务性能的稳定性。
需要说明的是，上述实施例所提供方法的各步骤的执行主体均可以是同一设备，或者，该方法也由不同设备作为执行主体。比如，步骤301至步骤302的执行主体可以为设备A；又比如，步骤301的执行主体可以为设备A，步骤302的执行主体可以为设备B；等等。
另外，在上述实施例及附图中的描述的一些流程中，包含了按照特定顺序出现的多个操作，但是应该清楚了解，这些操作可以不按照其在本文中出现的顺序来执行或并行执行，操作的序号如301和302等，仅仅是用于区分开各个不同的操作，序号本身不代表任何的执行顺序。另外，这些流程可以包括更多或更少的操作，并且这些操作可以按顺序执行或并行执行。需要说明的是，本文中的“第一”、“第二”等描述，是用于区分不同的消息、设备、模块等，不代表先后顺序，也不限定“第一”和“第二”是不同的类型。
除了上述计算机设备，本申请实施例还提供的一种虚拟化加速设备，如图1a-图2所示，该虚拟化加速设备20包括：高速串行总线203和面向物理机10实现的虚拟化的串口设备205；虚拟化加速设备20通过高速串行总线203与物理机10连接；虚拟化的串口设备205在虚拟化加速设备20通过高速串行总线203与物理机10连接的情况下，配合物理机10进行串口数据的收发。其中，关于虚拟化加速设备20、物理机10、高速串行总线203和虚拟化的串口设备205的详细内容可参见前述实施例，在此不再赘述。
在一可选实施例中，虚拟化加速设备还包括：处理器201；处理器用于， 在虚拟化加速设备上实现面向物理机的虚拟化的串口设备，并配合物理机通过虚拟化的串口设备进行串口数据的收发。
在一可选实施例中，所述处理器在虚拟化加速设备上实现虚拟化的串口设备时，具体用于：在虚拟化加速设备上配置串口设备所需的多个寄存器，并将多个寄存器映射到虚拟化加速设备的配置空间中，以实现虚拟化的串口设备。
在一可选实施例中，虚拟化加速设备20还包括：内存缓存204。内存缓存可缓存物理机通过虚拟化的串口设备进行收发的串口数据；处理器在配合物理机通过虚拟化的串口设备进行串口数据的收发时，具体用于：从内存缓存中读取物理机经虚拟化的串口设备写入的第一串口数据并输出，或向内存缓存数据写入物理机需要接收的第二串口数据，以供虚拟化的串口设备读取并发送给物理机。
在一可选实施例中，多个寄存器至少包括：THR和LSR；虚拟化的串口设备可在物理机通过高速串行总线将第一串口数据写入THR之后，将THR中的第一串口数据输出至内存缓存中，并将LSR的THR状态位置1。
在一可选实施例中，多个寄存器至少包括：RBR和LSR；虚拟化的串口设备将从内存缓存中读取的第二串口数据写入RBR，并将LSR的数据准备状态位置1，以供物理机通过高速串行总线从RBR中读取第二串口数据；以及在第二串口数据被读取完毕后将LSR的数据准备状态位置0。
本申请实施例的虚拟化加速设备，与物理机通过高速串行总线互联，借助于虚拟化加速设备可对串口设备进行虚拟化，即在虚拟化加速设备上实现面向物理机的虚拟化的串口设备，基于此，物理机可通过该虚拟化的串口设备实现串口数据的收发，对物理机来说，只需通过高速串行总线将数据传输至虚拟化的串口设备即可，后续传输动作由虚拟化加速设备完成，借助于高速串行总线在传输速度上的优势，可大大提高串口数据的传输速率，尤其是 在传输串口数据时会触发CPU关中断的情况下大大缩短物理机因为传输串口数据而引起的关中断的时间窗口，有利于提高CPU的使用率，保证物理机服务性能的稳定性。
相应地，本申请实施例还提供一种存储有计算机程序的计算机可读存储介质，当计算机程序被处理器执行时，致使处理器能够实现本申请实施例提供的数据传输方法中的步骤。
相应地，本申请实施例还提供一种计算机程序产品，包括计算机程序/指令，当所述计算机程序/指令被处理器执行时，致使所述处理器实现本申请实施例提供的数据传输方法中的步骤。
除了上述计算机设备和虚拟化加速设备，本申请实施例还提供一种物理机，该物理机可以通过高速串行总线，如PCI或PCIE与前述实施例中的虚拟化加速设备连接；如图4所示，该物理机包括：存储器44和处理器45。
存储器44，用于存储计算机程序，并可被配置为存储其它各种数据以支持在物理机上的操作。这些数据的示例包括用于在物理机上操作的任何应用程序或方法的指令。
存储器44可以由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。
处理器45，与存储器44耦合，用于执行存储器44中的计算机程序，以用于：识别虚拟化的串口设备，并通过虚拟化的串口设备进行串口数据的收发；其中，虚拟化的串口设备是在与物理机通过高速串行总线连接的虚拟化加速设备上实现的。
在一可选实施例中，处理器45在识别虚拟化的串口设备时，具体用于：对高速串行总线上的设备进行枚举，在发现虚拟化加速设备的情况下，根据 虚拟化加速设备的配置空间中至少部分寄存器的值，识别到虚拟化的串口设备。
在一可选实施例中，处理器45还用于：在首次识别到虚拟化的串口设备时，为虚拟化的串口设备命名，并修改操作系统中串口输出参数中的串口名称为虚拟化的串口设备的名称。
在一可选实施例中，处理器45在通过虚拟化的串口设备进行串口数据收发时，具体用于：通过高速串行总线将第一串口数据写入虚拟化的串口设备上的THR，以供虚拟化的串口设备读取并写入虚拟化加速设备上的内存缓存；或者在检测到虚拟化的串口设备的LSR的数据准备状态位置1时，通过高速串行总线从虚拟化的串口设备的RBR中读取第二串口数据。
进一步，如图4所示，该物理机还包括：通信组件46、显示器47、电源组件48、音频组件49等其它组件。图4中仅示意性给出部分组件，并不意味着物理机只包括图4所示组件。需要说明的是，图4中虚线框内的组件为可选组件，而非必选组件，具体可视物理机的产品形态而定。
上述图4中的通信组件被配置为便于通信组件所在设备和其他设备之间有线或无线方式的通信。通信组件所在设备可以接入基于通信标准的无线网络，如WiFi，2G、3G、4G/LTE、5G等移动通信网络，或它们的组合。在一个示例性实施例中，通信组件经由广播信道接收来自外部广播管理系统的广播信号或广播相关信息。在一个示例性实施例中，所述通信组件还包括近场通信(NFC)模块，以促进短程通信。例如，在NFC模块可基于射频识别(RFID)技术，红外数据协会(IrDA)技术，超宽带(UWB)技术，蓝牙(BT)技术和其他技术来实现。
上述图4中的显示器包括屏幕，其屏幕可以包括液晶显示器(LCD)和触摸面板(TP)。如果屏幕包括触摸面板，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、 滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。
上述图4中的电源组件，为电源组件所在设备的各种组件提供电力。电源组件可以包括电源管理系统，一个或多个电源，及其他与为电源组件所在设备生成、管理和分配电力相关联的组件。
上述图4中的音频组件，可被配置为输出和/或输入音频信号。例如，音频组件包括一个麦克风(MIC)，当音频组件所在设备处于操作模式，如呼叫模式、记录模式和语音识别模式时，麦克风被配置为接收外部音频信号。所接收的音频信号可以被进一步存储在存储器或经由通信组件发送。在一些实施例中，音频组件还包括一个扬声器，用于输出音频信号。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储 器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这 种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (25)

  1. 一种计算机设备，其特征在于，包括：物理机和虚拟化加速设备；所述虚拟化加速设备通过高速串行总线与所述物理机连接；
    所述虚拟化加速设备上实现有面向所述物理机的虚拟化的串口设备，用于配合所述物理机进行串口数据的收发；
    所述物理机，用于识别所述虚拟化的串口设备，并通过所述虚拟化的串口设备进行串口数据的收发。
  2. 根据权利要求1所述的设备，其特征在于，在所述虚拟化加速设备上配置串口设备所需的多个寄存器，并将所述多个寄存器映射到所述虚拟化加速设备的配置空间中，以实现虚拟化的串口设备。
  3. 根据权利要求2所述的设备，其特征在于，所述物理机具体用于：对所述高速串行总线上的设备进行枚举，在发现所述虚拟化加速设备的情况下，根据所述配置空间中至少部分寄存器的值，识别到所述虚拟化的串口设备。
  4. 根据权利要求3所述的设备，其特征在于，所述物理机还用于：
    在首次识别到所述虚拟化的串口设备时，为所述虚拟化的串口设备命名，并修改操作系统中串口输出参数中的串口名称为所述虚拟化的串口设备的名称。
  5. 根据权利要求2所述的设备，其特征在于，所述虚拟化加速设备包括：处理器和内存缓存；所述内存缓存，用于缓存所述物理机通过所述虚拟化的串口设备进行收发的串口数据；
    所述处理器，用于从所述内存缓存中读取所述物理机经所述虚拟化的串口设备写入的第一串口数据并输出，或向所述内存缓存写入所述物理机需要接收的第二串口数据，以供所述虚拟化的串口设备读取并发送给所述物理机。
  6. 根据权利要求5所述的设备，其特征在于，所述多个寄存器至少包括：发送保持寄存器THR和线路状态寄存器LSR；
    所述物理机具体用于：通过所述高速串行总线向THR写入第一串口数据；
    所述虚拟化的串口设备，用于将THR中的第一串口数据输出至所述内存缓存中，并将LSR中的THR状态位置1。
  7. 根据权利要求5所述的设备，其特征在于，所述多个寄存器至少包括：接收缓冲寄存器RBR和线路状态寄存器LSR；
    所述虚拟化的串口设备，用于将从所述内存缓存中读取的第二串口数据写入RBR，并将LSR的数据准备状态位置1，以及在所述第二串口数据被读取完毕后将所述LSR的数据准备状态位置0；
    所述物理机具体用于：在检测到LSR的数据准备状态位置1时，通过所述高速串行总线从RBR中读取所述第二串口数据。
  8. 根据权利要求5所述的设备，其特征在于，所述虚拟化加速设备包括可编程逻辑器件和第一处理芯片；所述虚拟化的串口设备位于所述可编程逻辑器件上，所述处理器和内存缓存位于所述第一处理芯片上。
  9. 根据权利要求8所述的设备，其特征在于，所述可编程逻辑器件为现场可编程逻辑门阵列FPGA或复杂可编程逻辑器件CPLD；所述第一处理芯片为集成电路ASIC芯片或系统级芯片SOC。
  10. 根据权利要求5所述的设备，其特征在于，所述虚拟化加速设备包括第二处理芯片；所述虚拟化的串口设备、所述处理器和所述和内存缓存均位于所述第二处理芯片上。
  11. 根据权利要求10所述的设备，其特征在于，所述第二处理芯片为ASIC芯片或SOC。
  12. 根据权利要求1-11任一项所述的设备，其特征在于，所述高速串行总线为外设部件互连标准PCI总线或外设部件互联扩展总线标准PCIE总 线。
  13. 一种虚拟化加速设备，其特征在于，包括：高速串行总线和面向物理机实现的虚拟化的串口设备；所述虚拟化加速设备通过所述高速串行总线与所述物理机连接；以及所述虚拟化的串口设备，用于在所述虚拟化加速设备通过所述高速串行总线与所述物理机连接的情况下，配合所述物理机进行串口数据的收发。
  14. 根据权利要求13所述的设备，其特征在于，还包括：处理器；所述处理器用于，在所述虚拟化加速设备上实现面向物理机的虚拟化的串口设备，并配合所述物理机通过所述虚拟化的串口设备进行串口数据的收发。
  15. 根据权利要求14所述的设备，其特征在于，所述处理器在虚拟化加速设备上实现虚拟化的串口设备时，具体用于：
    配置串口设备所需的多个寄存器，并将所述多个寄存器映射到所述虚拟化加速设备的配置空间中，以实现虚拟化的串口设备。
  16. 根据权利要求15所述的设备，其特征在于，还包括：内存缓存，用于缓存所述物理机通过所述虚拟化的串口设备进行收发的串口数据；
    所述处理器在配合物理机通过所述虚拟化的串口设备进行串口数据的收发时，具体用于：从所述内存缓存中读取所述物理机经所述虚拟化的串口设备写入的第一串口数据并输出，或向所述内存缓存写入所述物理机需要接收的第二串口数据，以供所述虚拟化的串口设备读取并发送给所述物理机。
  17. 根据权利要求16所述的设备，其特征在于，所述多个寄存器至少包括：发送保持寄存器THR和线路状态寄存器LSR；
    所述虚拟化的串口设备，用于在所述物理机通过所述高速串行总线将所述第一串口数据写入THR之后，将THR中的第一串口数据输出至所述内存缓存中，并将LSR的THR状态位置1。
  18. 根据权利要求16所述的设备，其特征在于，所述多个寄存器至少 包括：接收缓冲寄存器RBR和线路状态寄存器LSR；
    所述虚拟化的串口设备，用于将从所述内存缓存中读取的第二串口数据写入RBR，并将LSR的数据准备状态位置1，以供所述物理机通过所述高速串行总线从RBR中读取所述第二串口数据；以及在所述第二串口数据被读取完毕后将所述LSR的数据准备状态位置0。
  19. 一种物理机，其特征在于，包括：存储器和处理器；
    所述存储器，用于存储计算机程序；
    所述处理器，与所述存储器耦合，用于执行所述计算机程序，以用于：识别虚拟化的串口设备，并通过所述虚拟化的串口设备进行串口数据的收发；其中，所述虚拟化的串口设备是在与所述物理机通过高速串行总线连接的虚拟化加速设备上实现的。
  20. 根据权利要求19所述的物理机，其特征在于，所述处理器在识别虚拟化的串口设备时，具体用于：
    对所述高速串行总线上的设备进行枚举，在发现所述虚拟化加速设备的情况下，根据所述虚拟化加速设备的配置空间中至少部分寄存器的值，识别到所述虚拟化的串口设备。
  21. 根据权利要求20所述的物理机，其特征在于，所述处理器还用于：
    在首次识别到所述虚拟化的串口设备时，为所述虚拟化的串口设备命名，并修改操作系统中串口输出参数中的串口名称为所述虚拟化的串口设备的名称。
  22. 根据权利要求21所述的物理机，其特征在于，所述处理器在通过所述虚拟化的串口设备进行串口数据收发时，具体用于：
    通过所述高速串行总线将第一串口数据写入所述虚拟化的串口设备上的发送保持寄存器THR，以供所述虚拟化的串口设备读取并写入所述虚拟化加速设备上的内存缓存；
    或者
    在检测到所述虚拟化的串口设备的LSR的数据准备状态位置1时，通过所述高速串行总线从所述虚拟化的串口设备的RBR中读取第二串口数据。
  23. 一种数据传输方法，其特征在于，适用于虚拟化加速设备，所述虚拟化加速设备上实现有面向物理机的虚拟化的串口设备，所述方法包括：
    接收所述物理机通过所述虚拟化的串口设备发送的第一串口数据，并将所述第一串口数据输出；
    或者
    接收来自外部的第二串口数据，并通过所述虚拟化串口设备将所述第二串口数据发送给所述物理机；其中，所述虚拟化加速设备与所述物理机通过高速串行总线连接。
  24. 一种存储有计算机程序的计算机可读存储介质，其特征在于，当所述计算机程序被处理器执行时，致使所述处理器实现权利要求23所述方法中的步骤。
  25. 一种计算机程序产品，包括计算机程序/指令，其特征在于，当所述计算机程序/指令被处理器执行时，致使所述处理器实现权利要求23所述方法中的步骤。
PCT/CN2022/084279 2021-04-06 2022-03-31 计算机设备、虚拟化加速设备、数据传输方法及存储介质 WO2022213865A1 (zh)

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