WO2022213649A1 - 天线网络及相关电子装置 - Google Patents

天线网络及相关电子装置 Download PDF

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WO2022213649A1
WO2022213649A1 PCT/CN2021/137429 CN2021137429W WO2022213649A1 WO 2022213649 A1 WO2022213649 A1 WO 2022213649A1 CN 2021137429 W CN2021137429 W CN 2021137429W WO 2022213649 A1 WO2022213649 A1 WO 2022213649A1
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terminal
positive
negative
antenna
coupled
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PCT/CN2021/137429
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English (en)
French (fr)
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刘诗雨
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深圳市汇顶科技股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H04B7/0426—Power distribution
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station

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  • the present application relates to the field of signal transmission, and in particular, to an antenna network for near field communication and a near field communication device.
  • the antenna In the field of near field communication, when designing an antenna, it is necessary to consider the impedance matching between the near field communication control chip and the antenna. When the impedance is more matched, the reflected signal generated when the signal enters the antenna from the chip is lower, and the The higher the power output by the antenna, the higher the efficiency. In order to achieve impedance matching, it is necessary to set up a matching network between the antenna and the chip, and tune the values of each device in the matching network.
  • the antenna together with the matching network may be referred to as an antenna network.
  • the network impedance of the antenna network will change accordingly. At some specific frequency points, the network impedance of the antenna network will be pure resistance. At this time, the output power to the antenna network is the highest, and the antenna radiation The magnetic field is the strongest.
  • the so-called tuning is to make the network impedance of the antenna network pure resistance at the operating frequency.
  • the general tuning method is mostly asymmetric tuning, that is, although the ideal value of each device tuned can make the antenna network and the chip achieve impedance matching at the operating frequency, in fact, it will cause detuning due to errors.
  • the antenna network is detuned, the impedance seen from the chip to the antenna network will be asymmetrical on the Smith chart based on the real axis, as shown in Figure 1.
  • the bandwidth and antenna quality factor (Q value) obtained by asymmetric tuning are less than ideal, resulting in limited communication distance and need to be further improved.
  • One of the objectives of the present application is to disclose an antenna network and related electronic devices to solve the above problems.
  • An embodiment of the present application discloses an antenna network, which is used for receiving a positive terminal signal of a chip transmitting end and a negative terminal signal of a chip transmitting terminal from a chip to generate an antenna signal, including: an electromagnetic compatibility (EMC) filter, including a positive input terminal, a negative terminal an input terminal, a positive output terminal and a negative output terminal, wherein the positive input terminal is used for receiving the positive terminal signal of the chip transmitting terminal, the negative input terminal is used for receiving the negative terminal signal of the chip transmitting terminal, the EMC filter
  • EMC filter The equivalent model includes: the first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter; the first negative end inductance is equivalent to is coupled between the negative input end of the EMC filter and the negative output end of the EMC filter; the first positive end capacitor is equivalently coupled to the positive end of the EMC filter between the output terminal and the ground voltage; and the first negative terminal capacitor is equivalently coupled between the negative output terminal of the
  • An embodiment of the present application discloses an antenna network, which is used for receiving a positive terminal signal of a chip transmitting end and a negative terminal signal of a chip transmitting terminal from a chip to generate an antenna signal, including: an electromagnetic compatibility (EMC) filter, including a positive input terminal, a negative terminal an input terminal, a positive output terminal and a negative output terminal, wherein the positive input terminal is used for receiving the positive terminal signal of the chip transmitting terminal, the negative input terminal is used for receiving the negative terminal signal of the chip transmitting terminal, the EMC filter
  • EMC filter The equivalent model includes: the first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter; the first negative end inductance is equivalent to is coupled between the negative input end of the EMC filter and the negative output end of the EMC filter; the first positive end capacitor is equivalently coupled to the positive end of the EMC filter between the output terminal and the ground voltage; and the first negative terminal capacitor is equivalently coupled between the negative output terminal of the
  • the equivalent model of the antenna includes: a fourth capacitance is equivalently coupled between the positive input terminal of the antenna and the negative input terminal of the antenna; and a first resistance and an antenna inductance equivalent connected in series between the positive input terminal of the antenna and the negative input terminal of the antenna; wherein the fourth capacitor has a capacitance value C a , the first resistor has a resistance value R a , the The antenna inductance has an inductance value La; wherein the operating angular frequency of the antenna network is ⁇ , the target impedance is the resistance value R t , the EMC filter has a cut-off angular frequency ⁇ r0
  • An embodiment of the present application discloses an electronic device, including a chip, having a positive output terminal and a negative output terminal, the positive output terminal is used for outputting a positive terminal signal of the chip transmitting terminal, and the negative output terminal is used for outputting a chip transmitting terminal negative terminal signal; and the above-mentioned antenna network, wherein the positive output terminal of the chip is coupled to the positive input terminal of the EMC filter of the antenna network, and the negative output terminal of the chip is coupled to the negative input of the EMC filter of the antenna network.
  • the antenna network and related electronic devices of the present application can obtain larger bandwidth and higher antenna Q value through innovative component arrangement, thereby realizing a longer communication distance.
  • Figure 1 shows the Smith chart of the impedance of an asymmetrically tuned antenna network.
  • Figure 2 shows the impedance of a symmetrically tuned antenna network on a Smith chart.
  • FIG. 3 is a schematic diagram of a first embodiment of an antenna network of the present application.
  • FIG. 4 is a schematic diagram of a second embodiment of the antenna network of the present application.
  • first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact.
  • present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • the symmetric tuning method can make the impedance of the antenna network roughly symmetrical on the Smith chart based on the real axis, as shown in Figure 2, the horizontal axis is the real axis, and the vertical axis is the imaginary axis. axis.
  • the advantage of this is that the antenna network can obtain a larger bandwidth and a higher antenna Q value (quality factor), thereby realizing a longer communication distance.
  • the symmetrical tuning method proposed in the present application enables developers to quickly and correctly obtain the values of each element when designing an antenna network, without manual trial-and-error adjustment, which can save time and development costs.
  • FIG. 3 is a schematic diagram of the first embodiment of the antenna network of the application, and the antenna network is used to generate an antenna signal according to the positive terminal signal of the chip transmitter and the negative terminal signal of the chip transmitter.
  • the antenna network 100 includes an electromagnetic compatibility (EMC) filter 102 , a matching circuit 104 and an antenna 108 .
  • EMC electromagnetic compatibility
  • the EMC filter 102, the matching circuit 104, and the antenna 108 are all shown in FIG. 1 as equivalent models of resistance, capacitance, and inductance.
  • any components or structures can be used to implement them, for example, multiple components are connected in series. Or take values in parallel, as long as there are equivalent models of resistance, capacitance, and inductance as shown in Figure 1.
  • the EMC filter 102 is used to filter out unwanted higher harmonics from the signal source.
  • the EMC filter 102 includes a positive input terminal Ip0, a negative input terminal In0, a positive output terminal Op0, and a negative output terminal On0, wherein the positive input terminal Ip0 is used for receiving the positive terminal signal of the chip transmitter, and the negative input terminal In0 is used for receiving the
  • the chip transmits the negative terminal signal
  • the equivalent model of the EMC filter 102 includes a first positive terminal inductor 1022 , a first negative terminal inductor 1024 , a first positive terminal capacitor 1026 and a first negative terminal capacitor 1028 .
  • the first positive terminal inductor 1022 is equivalently coupled between the positive input terminal Ip0 of the EMC filter 102 and the positive output terminal Op0 of the EMC filter 102; the first negative terminal inductor 1024 is equivalently coupled to the EMC filter between the negative input terminal In0 of the EMC filter 102 and the negative output terminal On0 of the EMC filter 102; the first positive terminal capacitor 1026 is equivalently coupled between the positive output terminal Op0 of the EMC filter 102 and the ground voltage; and the first negative terminal The terminal capacitor 1028 is equivalently coupled between the negative output terminal On0 of the EMC filter 102 and the ground voltage; wherein the first positive terminal inductor 1022 and the first negative terminal inductor 1024 both have inductance values L 0 , the first positive terminal Both the terminal capacitor 1026 and the first negative terminal capacitor 1028 have a capacitance value C 0 .
  • the matching circuit 104 is used to make the target impedance of the antenna network 100 purely resistive.
  • the matching circuit 104 includes a positive input terminal Ip1, a negative input terminal In1, a positive output terminal Op1 and a negative output terminal On1.
  • the positive input terminal Ip1 of the matching circuit 104 is coupled to the positive output terminal Op0 of the EMC filter 102
  • the negative input terminal In1 of the matching circuit 104 is coupled to the negative output terminal On0 of the EMC filter 102
  • the equivalent model of the matching circuit 104 is It includes a second positive terminal capacitor 1042 , a second negative terminal capacitor 1044 , a third positive terminal capacitor 1046 and a third negative terminal capacitor 1048 .
  • the second positive terminal capacitor 1042 is equivalently coupled between the positive input terminal Ip1 of the matching circuit 104 and the positive output terminal Op1 of the matching circuit 104 ;
  • the second negative terminal capacitor 1044 is equivalently coupled to the negative terminal of the matching circuit 104 between the input terminal In1 and the negative output terminal On1 of the matching circuit 104;
  • the third positive terminal capacitor 1046 is equivalently coupled between the positive output terminal Op1 of the matching circuit 104 and the ground voltage;
  • the third negative terminal capacitor 1048 Equivalently coupled between the negative output terminal On1 of the matching circuit 104 and the ground voltage; wherein the second positive terminal capacitor 1042 and the second negative terminal capacitor 1044 both have capacitance values C 1 , and the third positive terminal capacitor 1046 and The third negative terminal capacitors 1048 all have a capacitance value C 2 .
  • the antenna 108 includes a positive input terminal Ip3 and a negative input terminal In3.
  • the positive input terminal Ip3 of the antenna 108 is coupled to the positive output terminal Op1 of the matching circuit 104, and the negative input terminal In3 of the antenna 108 is coupled to the negative output terminal On1 of the matching circuit 104.
  • the equivalent model of the antenna 108 includes a fourth capacitor 1082 , a first resistor 1084 and an antenna inductance 1086 .
  • the fourth capacitor 1082 is equivalently coupled between the positive input terminal Ip3 of the antenna 108 and the negative input terminal In3 of the antenna 108 ; and the first resistor 1084 and the antenna inductance 1086 are equivalently connected in series with the positive input terminal of the antenna 108 Between Ip3 and the negative input terminal In3 of the antenna 108; wherein the fourth capacitor 1082 has a capacitance value Ca , the first resistor 1084 has a resistance value Ra , and the antenna inductance 1086 has an inductance value La .
  • the antenna network 100 can be coupled to the chip to achieve various applications, for example, the positive input terminal Ip0 and the negative input terminal In0 of the EMC filter 102 of the antenna network 100 are coupled to the near field communication (NFC) chip 110, so as to realize NFC support of electronic devices.
  • NFC near field communication
  • the positive output terminal of the NFC chip 110 outputs the positive terminal signal of the chip transmitting terminal to the positive input terminal Ip0 of the EMC filter 102
  • the negative output terminal of the NFC chip 110 outputs the negative terminal signal of the chip transmitting terminal to the EMC filter 102 .
  • the negative input terminal In0 of the filter 102 The negative input terminal In0 of the filter 102 .
  • the structure and various parameters of the antenna 108 are first determined according to the requirements of the application.
  • the target impedance and the working angular frequency ⁇ of the antenna network 100 will also be determined according to application requirements.
  • the working frequency of the NFC chip is 13.56MHz
  • the corresponding angular frequency is 2 ⁇ *13.56MHz.
  • the method for determining the target impedance is based on the required NFC minimum transmission distance or minimum output power, the supply voltage of the NFC chip, and the limitation of the maximum output current of the NFC chip.
  • the target impedance will be set to make the NFC chip have the maximum output power under the premise of not exceeding the maximum output current of the NFC chip.
  • the target impedance can also be set to make the NFC chip have a minimum output current under the premise of not being less than the minimum output power of the NFC.
  • the target impedance determined according to the requirements of the application only includes the resistance value R t , that is, the resistance value is not 0 and the reactance value is 0.
  • FIG. 2 shows a schematic diagram of the impedance curve of the antenna network 100 under the condition that the antenna network 100 satisfies the symmetrical tuning, and the impedance curve represents the change of the impedance of the antenna network 100 with the change of frequency.
  • the impedance curve of Figure 2 intersects the real axis of the Smith chart at three resonant frequencies, angular frequencies ⁇ , ⁇ 1 and ⁇ 2 .
  • the angular frequency ⁇ is the working angular frequency ⁇
  • the corresponding impedance is the target impedance (which is a pure resistance, and the resistance value is R t ).
  • the impedances corresponding to the angular frequencies ⁇ 1 and ⁇ 2 are the same and are also pure resistances, but their resistance values are different from the target impedance. After derivation, the range of the cut-off angular frequency ⁇ r0 of the EMC filter 102 that can satisfy the above conditions is obtained as
  • the inductance value satisfying the above conditions can be obtained Capacitance value and capacitance value
  • an angular frequency is selected within the range of the above-mentioned cut-off angular frequency ⁇ r0 according to known requirements, and the inductance value L 0 , the capacitance value C 0 and the capacitance value C can be quickly obtained 2 .
  • the capacitance value C 1 can be set as where R 1 , G 2 and X 1 can be obtained via the following equations:
  • FIG. 4 is a schematic diagram of the second embodiment of the antenna network of the present application.
  • the difference between the antenna network 200 and the antenna network 100 is that the antenna network 200 additionally adds a Q value reduction circuit 106 to control the Q value.
  • the Q reduction circuit 106 includes a positive input terminal Ip2 , a negative input terminal In2 , a positive output terminal Op2 and a negative output terminal On2 , and the positive input terminal Ip2 of the Q reduction circuit 106 is coupled to the positive output terminal of the matching circuit 104 .
  • the negative input terminal In2 of the Q-drop circuit 106 is coupled to the negative output terminal On1 of the matching circuit 104 .
  • the equivalent model of the Q-drop circuit 106 includes a second positive terminal resistance 1062 and a second negative terminal resistance 1064 .
  • the second positive terminal resistor 1062 is equivalently coupled between the positive input terminal Ip2 of the Q-drop circuit 106 and the positive output terminal Op2 of the Q-drop circuit 106 ; and the second negative terminal resistor 1064 is equivalently coupled to Between the negative input terminal In2 of the drop-Q value circuit 106 and the negative output terminal On2 of the drop-Q value circuit 106 ; the second positive terminal resistor 1062 and the second negative terminal resistor 1064 both have resistance values R q .
  • the inductance value L 0 the capacitance value C 0 , the capacitance value C 1 , and the capacitance value C 2
  • the range of the cut-off angular frequency ⁇ r0 of the EMC filter 102 is obtained as Inductance value Capacitance value and capacitance value and setting the capacitance value C1 as where R 1 , G 2 and X 1 can be obtained via the following equations:
  • the present application also provides an electronic device, which includes a chip and an antenna network 100/200, wherein a positive output terminal of the chip is coupled to a positive input terminal Ip0 of an EMC filter 102 of the antenna network 100/200, and a positive output terminal of the chip The negative output terminal is coupled to the negative input terminal In0 of the EMC filter 102 of the antenna network 100/200.

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Abstract

本申请公开了一种天线网络，包括：电磁兼容性滤波器、匹配电路以及天线。本申请还公开了一种天线网络，包括：电磁兼容性滤波器、匹配电路、降品质因数电路以及天线。本申请还公开了一种电子装置，包括：芯片，具有正输出端及负输出端；以及上述的天线网络，其中所述芯片的所述正输出端耦接所述天线网络的所述电磁兼容性滤波器的所述正输入端，所述芯片的所述负输出端耦接所述天线网络的所述电磁兼容性滤波器的所述负输入端。

Description

天线网络及相关电子装置
交叉引用
本申请基于申请号为“202110378200.0”、申请日为2021年04月08日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及信号传输领域，尤其涉及一种用于近场通信的天线网络及近场通信装置。
背景技术
在近场通信领域，当设计天线时，需要考量到近场通信控制芯片与天线之间的阻抗匹配的问题，当阻抗越匹配时，信号从芯片进入天线时产生的反射信号越低,芯片向天线输出的功率越高，效率越高。为了达到阻抗匹配，需要在天线和芯片之间设置匹配网络，并对匹配网络中的各器件的值进行调谐。天线连同匹配网络可称为天线网络。根据电路原理，随着信号源频率变化，天线网络的网络阻抗将随之改变，在某些特定频点，天线网络的网络阻抗将为纯电阻，这时对天线网络的输出功率最高，天线辐射磁场最强。所谓调谐，即是要使天线网络的网络阻抗在工作频率下为纯电阻。
一般的调谐方法多为非对称式调谐，即调谐出的各器件的理想值虽然能够使天线网络与芯片在工作频率达到阻抗匹配，但实际上多少会因误差造成失谐，当非对称式调谐的天线网络发生失谐时，会使从芯片往天线网络方向看出去的阻抗在史密斯圆图上基于实轴呈现不对称的型态，如图1所示。然而，非对称式调谐得到的带宽和天线品质因数(Q值)较不理想，从而造成通信距离受限，需要被进一步改 善。
发明内容
本申请的目的之一在于公开一种天线网络及相关电子装置，来解决上述问题。
本申请的一实施例公开了一种天线网络，用于从芯片接收芯片发射端正端信号及芯片发射端负端信号以产生天线信号，包括：电磁兼容性EMC滤波器，包括正输入端、负输入端、正输出端及负输出端，其中所述正输入端用于接收所述芯片发射端正端信号，所述负输入端用于接收所述芯片发射端负端信号，所述EMC滤波器的等效模型包括：第一正端电感等效的耦接于所述EMC滤波器的所述正输入端和所述EMC滤波器的所述正输出端之间；第一负端电感等效的耦接于所述EMC滤波器的所述负输入端和所述EMC滤波器的所述负输出端之间；第一正端电容等效的耦接于所述EMC滤波器的所述正输出端和地电压之间；以及第一负端电容等效的耦接于所述EMC滤波器的所述负输出端和所述地电压之间；其中所述第一正端电感和所述第一负端电感皆具有电感值L 0，所述第一正端电容和所述第一负端电容皆具有电容值C 0；匹配电路，包括正输入端、负输入端、正输出端及负输出端，所述匹配电路的所述正输入端耦接于所述EMC滤波器的所述正输出端，所述匹配电路的所述负输入端耦接于所述EMC滤波器的所述负输出端，其中所述匹配电路的等效模型包括：第二正端电容等效的耦接于所述匹配电路的所述正输入端和所述匹配电路的所述正输出端之间；第二负端电容等效的耦接于所述匹配电路的所述负输入端和所述匹配电路的所述负输出端之间；第三正端电容等效的耦接于所述匹配电路的所述正输出端和所述地电压之间；以及第三负端 电容等效的耦接于所述匹配电路的所述负输出端和所述地电压之间；其中所述第二正端电容和所述第二负端电容皆具有电容值C 1，所述第三正端电容和所述第三负端电容皆具有电容值C 2；天线，包括正输入端及负输入端，所述天线的所述正输入端耦接于所述匹配电路的所述正输出端，所述天线的所述负输入端耦接于所述匹配电路的所述负输出端，其中所述天线的等效模型包括：第四电容等效的耦接于所述天线的所述正输入端和所述天线的所述负输入端之间；以及第一电阻以及天线电感等效的串接于所述天线的所述正输入端和所述天线的所述负输入端之间；其中所述第四电容具有电容值C a，所述第一电阻具有电阻值R a，所述天线电感具有电感值L a；其中，所述天线网络的工作角频率为ω，目标阻抗为电阻值R t，所述EMC滤波器具有截止角频率ω r0，且
Figure PCTCN2021137429-appb-000001
本申请的一实施例公开了一种天线网络，用于从芯片接收芯片发射端正端信号及芯片发射端负端信号以产生天线信号，包括：电磁兼容性EMC滤波器，包括正输入端、负输入端、正输出端及负输出端，其中所述正输入端用于接收所述芯片发射端正端信号，所述负输入端用于接收所述芯片发射端负端信号，所述EMC滤波器的等效模型包括：第一正端电感等效的耦接于所述EMC滤波器的所述正输入端和所述EMC滤波器的所述正输出端之间；第一负端电感等效的耦接于所述EMC滤波器的所述负输入端和所述EMC滤波器的所述负输出端之间；第一正端电容等效的耦接于所述EMC滤波器的所述正输出端和地电压之间；以及第一负端电容等效的耦接于所述EMC滤波器的所述负输出端和所述地电压之间；其中所述第一正端电感和所述第 一负端电感皆具有电感值L 0，所述第一正端电容和所述第一负端电容皆具有电容值C 0；匹配电路，包括正输入端、负输入端、正输出端及负输出端，所述匹配电路的所述正输入端耦接于所述EMC滤波器的所述正输出端，所述匹配电路的所述负输入端耦接于所述EMC滤波器的所述负输出端，其中所述匹配电路的等效模型包括：第二正端电容等效的耦接于所述匹配电路的所述正输入端和所述匹配电路的所述正输出端之间；第二负端电容等效的耦接于所述匹配电路的所述负输入端和所述匹配电路的所述负输出端之间；第三正端电容等效的耦接于所述匹配电路的所述正输出端和所述地电压之间；以及第三负端电容等效的耦接于所述匹配电路的所述负输出端和所述地电压之间；其中所述第二正端电容和所述第二负端电容皆具有电容值C 1，所述第三正端电容和所述第三负端电容皆具有电容值C 2；降品质因数(Q值)电路，包括正输入端、负输入端、正输出端及负输出端，所述降Q值电路的所述正输入端耦接于所述匹配电路的所述正输出端，所述降Q值电路的所述负输入端耦接于所述匹配电路的所述负输出端，其中所述降Q值电路的等效模型包括：第二正端电阻等效的耦接于所述降Q值电路的所述正输入端和所述降Q值电路的所述正输出端之间；以及第二负端电阻等效的耦接于所述降Q值电路的所述负输入端和所述降Q值电路的所述负输出端之间；其中所述第二正端电阻和所述第二负端电阻皆具有电阻值R q；天线，包括正输入端及负输入端，所述天线的所述正输入端耦接于所述降Q值电路的所述正输出端，所述天线的所述负输入端耦接于所述降Q值电路的所述负输出端，其中所述天线的等效模型包括：第四电容等效的耦接于所述天线的所述正输入端和所述天线的所述负输入端之间；以及第一电阻以及天线电感等效的串接于所述天线的所述正输入端和所述天线的所述负输 入端之间；其中所述第四电容具有电容值C a，所述第一电阻具有电阻值R a，所述天线电感具有电感值L a；其中，所述天线网络的工作角频率为ω，目标阻抗为电阻值R t，所述EMC滤波器具有截止角频率ω r0，且
Figure PCTCN2021137429-appb-000002
本申请的一实施例公开了一种电子装置，包括芯片，具有正输出端及负输出端，所述正输出端用于输出芯片发射端正端信号，所述负输出端用于输出芯片发射端负端信号；以及上述的天线网络，其中所述芯片的所述正输出端耦接所述天线网络的所述EMC滤波器的所述正输入端，所述芯片的所述负输出端耦接所述天线网络的所述EMC滤波器的所述负输入端。
本申请的天线网络及相关电子装置通过创新的元件设置，可以获得更大的带宽和更高的天线Q值，从而实现更远的通信距离。
附图说明
图1为非对称式调谐的天线网络的阻抗在史密斯圆图上的表现。
图2为对称式调谐的天线网络的阻抗在史密斯圆图上的表现。
图3为本申请的天线网络的第一实施例的示意图。
图4为本申请的天线网络的第二实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示 内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
相比于传统的非对称式调谐方式，对称式调谐方式可以使天线网络的阻抗在史密斯圆图上基于实轴大致地对称，如图2所示，其横轴为实轴，纵轴为虚轴。这样做的好处在于能够使天线网络获得更大的带宽和更高的天线Q值(品质因数)，从而实现更远的通信距离。此外，本申请提出的对称式调谐方式能够使研发人员在设计天线网络时，快速且正确地得到的各元件的值，不需经过人工试错调整，可节省时间与开发成本。
图3为本申请的天线网络的第一实施例的示意图，天线网络用于 依据芯片发射端正端信号及芯片发射端负端信号产生天线信号。如图3所示，天线网络100包含电磁兼容性(EMC)滤波器102、匹配电路104以及天线108。应注意的是，EMC滤波器102、匹配电路104以及天线108在图1皆以电阻、电容、电感的等效模型示意，实际上可使用任何的元件或构造来实现，例如以多个元件串联或并联的方式取值，只要具有如图1的电阻、电容、电感的等效模型即可。
EMC滤波器102用于滤除来自信号源的不需要的高次谐波。EMC滤波器102包括正输入端Ip0、负输入端In0、正输出端Op0、负输出端On0，其中正输入端Ip0用于接收所述芯片发射端正端信号，负输入端In0用于接收所述芯片发射端负端信号，且EMC滤波器102的等效模型包括第一正端电感1022、第一负端电感1024、第一正端电容1026以及第一负端电容1028。其中第一正端电感1022等效的耦接于EMC滤波器102的正输入端Ip0和EMC滤波器102的正输出端Op0之间；第一负端电感1024等效的耦接于EMC滤波器102的负输入端In0和EMC滤波器102的负输出端On0之间；第一正端电容1026等效的耦接于EMC滤波器102的正输出端Op0和地电压之间；以及第一负端电容1028等效的耦接于EMC滤波器102的负输出端On0和所述地电压之间；其中第一正端电感1022和第一负端电感1024皆具有电感值L 0，第一正端电容1026和第一负端电容1028皆具有电容值C 0。
匹配电路104用于使天线网络100的目标阻抗为纯电阻。匹配电路104包括正输入端Ip1、负输入端In1、正输出端Op1及负输出端On1。匹配电路104的正输入端Ip1耦接于EMC滤波器102的正输出端Op0，匹配电路104的负输入端In1耦接于EMC滤波器102的负输出端On0，且匹配电路104的等效模型包括第二正端电容1042、第二负端电容1044、第三正端电容1046以及第三负端电容1048。其中第二正端电容1042等效的耦接于匹配电路104的正输入端Ip1和匹配电路104的正输出端Op1之间；第二负端电容1044等效的耦接于匹配电路104的负输入端In1和匹配电路104的负输出端On1之间；第三正端电容1046等效的耦接于匹配电路104的正输出端Op1 和所述地电压之间；以及第三负端电容1048等效的耦接于匹配电路104的负输出端On1和所述地电压之间；其中第二正端电容1042和第二负端电容1044皆具有电容值C 1，第三正端电容1046和第三负端电容1048皆具有电容值C 2。
天线108包括正输入端Ip3及负输入端In3，天线108的正输入端Ip3耦接于匹配电路104的正输出端Op1，天线108的负输入端In3耦接于匹配电路104的负输出端On1。且天线108的等效模型包括第四电容1082、第一电阻1084以及天线电感1086。其中第四电容1082等效的耦接于天线108的正输入端Ip3和天线108的负输入端In3之间；以及第一电阻1084以及天线电感1086等效的串接于天线108的正输入端Ip3和天线108的负输入端In3之间；其中第四电容1082具有电容值C a，第一电阻1084具有电阻值R a，天线电感1086具有电感值L a。
天线网络100可耦接至芯片以达成各式应用，例如将天线网络100的EMC滤波器102的正输入端Ip0及负输入端In0耦接至近场通信(NFC)芯片110，以实现可支持NFC的电子装置。如图3所示，NFC芯片110的正输出端输出所述芯片发射端正端信号至EMC滤波器102的正输入端Ip0，NFC芯片110的负输出端输出所述芯片发射端负端信号至EMC滤波器102的负输入端In0。
在设计天线网络100时，会先依据应用的需求确定天线108的构造和各参数，包含电容值C a、电阻值R a及电感值L a。除此之外，还会依据应用的需求确定天线网络100的所述目标阻抗以及工作角频率ω，例如NFC芯片的工作频率为13.56MHz，对应的角频率为2π*13.56MHz。具体来说，所述目标阻抗的确定方法是依据所需的NFC最小传输距离或最低输出功率、NFC芯片的供应电压及NFC芯片的最大输出电流之限制。所述目标阻抗越小，芯片的最大输出电流越大，即输出功率越大，NFC传输距离越远；反之亦然。一般来说，所述目标阻抗会设定成在不超过NFC芯片最大输出电流的前提下使NFC芯片有最大的输出功率。但在某些应用中，所述目标阻抗亦可设 定成在不小于NFC最低输出功率的前提下使NFC芯片有最小的输出电流。在本实施例中，依据应用的需求确定的所述目标阻抗仅包含电阻值R t，即电阻值不为0电抗值为0。
图2绘示了天线网络100在满足对称式调谐的情况下，其中阻抗曲线代表天线网络100的阻抗随频率的改变而变化的示意图。图2的阻抗曲线会在三个谐振频点和史密斯圆图的实轴交会，分别为角频率ω、ω 1及ω 2。其中角频率ω为工作角频率ω，对应的阻抗即为所述目标阻抗(为纯电阻，电阻值为R t)。而角频率ω 1及ω 2对应的阻抗相同，且亦为纯电阻，但其阻值和所述目标阻抗不同。经过推导后，得到能够满足上述条件的EMC滤波器102的截止角频率ω r0的范围为
Figure PCTCN2021137429-appb-000003
接着，再经由EMC滤波器102的截止角频率ω r0和电感值L 0、电容值C 0以及电容值C 2的对应关系，可以得到满足上述条件的电感值
Figure PCTCN2021137429-appb-000004
电容值
Figure PCTCN2021137429-appb-000005
以及电容值
Figure PCTCN2021137429-appb-000006
这样一来，在设计天线网络100时，依据已知的需求在上述的截止角频率ω r0的范围内选择一个角频率，即可快速地得到电感值L 0、电容值C 0以及电容值C 2。
除此之外，由于电容值C 1仅用于平衡阻抗不匹配，对实现对称式调谐没有影响。在本实施例中，可将电容值C 1设为
Figure PCTCN2021137429-appb-000007
其中R 1、G 2和X 1可经由以下方程式得到：
Figure PCTCN2021137429-appb-000008
Figure PCTCN2021137429-appb-000009
在某些情况下，可能需要控制天线网络100的Q值，例如当Q值过高时，需要对Q值进行降低。图4为本申请的天线网络的第二实施例的示意图，天线网络200和天线网络100差别在于，天线网络200额外增加了降Q值电路106以控制Q值。具体来说，降Q值电路106包括正输入端Ip2、负输入端In2、正输出端Op2及负输出端On2，降Q值电路106的正输入端Ip2耦接于匹配电路104的正输出端Op1，降Q值电路106的负输入端In2耦接于匹配电路104的负输出端On1。且降Q值电路106的等效模型包括第二正端电阻1062以及第二负端电阻1064。其中第二正端电阻1062等效的耦接于降Q值电路106的正输入端Ip2和降Q值电路106的正输出端Op2之间；以及第二负端电阻1064等效的耦接于降Q值电路106的负输入端In2和降Q值电路106的负输出端On2之间；其中第二正端电阻1062和第二负端电阻1064皆具有电阻值R q。
在具有降Q值电路106的情况下，要让天线网络200满足对称式调谐的截止角频率ω r0、电感值L 0、电容值C 0、电容值C 1以及电容值C 2会和天线网络100不同。经过相似于前述的推导后，得到EMC滤波器102的截止角频率ω r0的范围为
Figure PCTCN2021137429-appb-000010
电感值
Figure PCTCN2021137429-appb-000011
电容值
Figure PCTCN2021137429-appb-000012
以及电 容值
Figure PCTCN2021137429-appb-000013
以及将电容值C 1设为
Figure PCTCN2021137429-appb-000014
其中R 1、G 2和X 1可经由以下方程式得到：
Figure PCTCN2021137429-appb-000015
Figure PCTCN2021137429-appb-000016
本申请还提供了一种电子装置，其包括芯片和天线网络100/200，其中所述芯片的正输出端耦接天线网络100/200的EMC滤波器102的正输入端Ip0，所述芯片的负输出端耦接天线网络100/200的EMC滤波器102的负输入端In0。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (11)

  1. 一种天线网络，用于从芯片接收芯片发射端正端信号及芯片发射端负端信号以产生天线信号，其特征在于，包括：
    电磁兼容性EMC滤波器，包括正输入端、负输入端、正输出端及负输出端，其中所述正输入端用于接收所述芯片发射端正端信号，所述负输入端用于接收所述芯片发射端负端信号，所述EMC滤波器的等效模型包括：
    第一正端电感等效的耦接于所述EMC滤波器的所述正输入端和所述EMC滤波器的所述正输出端之间；
    第一负端电感等效的耦接于所述EMC滤波器的所述负输入端和所述EMC滤波器的所述负输出端之间；
    第一正端电容等效的耦接于所述EMC滤波器的所述正输出端和地电压之间；以及
    第一负端电容等效的耦接于所述EMC滤波器的所述负输出端和所述地电压之间；
    其中所述第一正端电感和所述第一负端电感皆具有电感值L 0，所述第一正端电容和所述第一负端电容皆具有电容值C 0；
    匹配电路，包括正输入端、负输入端、正输出端及负输出端，所述匹配电路的所述正输入端耦接于所述EMC滤波器的所述正输出端，所述匹配电路的所述负输入端耦接于所述EMC滤波器的所述负输出端，其中所述匹配电路的等效模型包括：
    第二正端电容等效的耦接于所述匹配电路的所述正输入端和所述匹配电路的所述正输出端之间；
    第二负端电容等效的耦接于所述匹配电路的所述负输入端和所述匹配电路的所述负输出端之间；
    第三正端电容等效的耦接于所述匹配电路的所述正输出端和所述地电压之间；以及
    第三负端电容等效的耦接于所述匹配电路的所述负输出端和所述地电压之间；
    其中所述第二正端电容和所述第二负端电容皆具有电容值 C 1，所述第三正端电容和所述第三负端电容皆具有电容值C 2；
    天线，包括正输入端及负输入端，所述天线的所述正输入端耦接于所述匹配电路的所述正输出端，所述天线的所述负输入端耦接于所述匹配电路的所述负输出端，其中所述天线的等效模型包括：
    第四电容等效的耦接于所述天线的所述正输入端和所述天线的所述负输入端之间；以及
    第一电阻以及天线电感等效的串接于所述天线的所述正输入端和所述天线的所述负输入端之间；
    其中所述第四电容具有电容值C a，所述第一电阻具有电阻值R a，所述天线电感具有电感值L a；
    其中，所述天线网络的工作角频率为ω，目标阻抗为电阻值R t，所述EMC滤波器具有截止角频率ω r0，且
    Figure PCTCN2021137429-appb-100001
  2. 如权利要求1所述的天线网络，其特征在于，所述电感值
    Figure PCTCN2021137429-appb-100002
  3. 如权利要求1所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100003
  4. 如权利要求1所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100004
  5. 如权利要求1所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100005
    其中
    Figure PCTCN2021137429-appb-100006
    以及
    Figure PCTCN2021137429-appb-100007
  6. 一种天线网络，用于从芯片接收芯片发射端正端信号及芯片发射端负端信号以产生天线信号，其特征在于，包括：
    电磁兼容性EMC滤波器，包括正输入端、负输入端、正输出端及负输出端，其中所述正输入端用于接收所述芯片发射端正端信号，所述负输入端用于接收所述芯片发射端负端信号，所述EMC滤波器的等效模型包括：
    第一正端电感等效的耦接于所述EMC滤波器的所述正输入端和所述EMC滤波器的所述正输出端之间；
    第一负端电感等效的耦接于所述EMC滤波器的所述负输入端和所述EMC滤波器的所述负输出端之间；
    第一正端电容等效的耦接于所述EMC滤波器的所述正输出端和地电压之间；以及
    第一负端电容等效的耦接于所述EMC滤波器的所述负输出端和所述地电压之间；
    其中所述第一正端电感和所述第一负端电感皆具有电感值L 0，所述第一正端电容和所述第一负端电容皆具有电容值C 0；
    匹配电路，包括正输入端、负输入端、正输出端及负输出端，所述匹配电路的所述正输入端耦接于所述EMC滤波器的所述正输出端，所述匹配电路的所述负输入端耦接于所述EMC滤波器的所述负输出端，其中所述匹配电路的等效模型包括：
    第二正端电容等效的耦接于所述匹配电路的所述正输入端和所述匹配电路的所述正输出端之间；
    第二负端电容等效的耦接于所述匹配电路的所述负输入端和所述匹配电路的所述负输出端之间；
    第三正端电容等效的耦接于所述匹配电路的所述正输出端和所述地电压之间；以及
    第三负端电容等效的耦接于所述匹配电路的所述负输出端和所述地电压之间；
    其中所述第二正端电容和所述第二负端电容皆具有电容值C 1，所述第三正端电容和所述第三负端电容皆具有电容值C 2；
    降品质因数(Q值)电路，包括正输入端、负输入端、正输出端及负输出端，所述降Q值电路的所述正输入端耦接于所述匹配电路的所述正输出端，所述降Q值电路的所述负输入端耦接于所述匹配电路的所述负输出端，其中所述降Q值电路的等效模型包括：
    第二正端电阻等效的耦接于所述降Q值电路的所述正输入端和所述降Q值电路的所述正输出端之间；以及
    第二负端电阻等效的耦接于所述降Q值电路的所述负输入端和所述降Q值电路的所述负输出端之间；
    其中所述第二正端电阻和所述第二负端电阻皆具有电阻值R q；
    天线，包括正输入端及负输入端，所述天线的所述正输入端耦接于所述降Q值电路的所述正输出端，所述天线的所述负输入端耦接于所述降Q值电路的所述负输出端，其中所述天线的等效模型包括：
    第四电容等效的耦接于所述天线的所述正输入端和所述天线的所述负输入端之间；以及
    第一电阻以及天线电感等效的串接于所述天线的所述正输入端和所述天线的所述负输入端之间；
    其中所述第四电容具有电容值C a，所述第一电阻具有电阻值R a，所述天线电感具有电感值L a；
    其中，所述天线网络的工作角频率为ω，目标阻抗为电阻值R t，所述EMC滤波器具有截止角频率ω r0，且
    Figure PCTCN2021137429-appb-100008
  7. 如权利要求6所述的天线网络，其特征在于，所述电感值
    Figure PCTCN2021137429-appb-100009
  8. 如权利要求6所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100010
  9. 如权利要求6所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100011
  10. 如权利要求6所述的天线网络，其特征在于，所述电容值
    Figure PCTCN2021137429-appb-100012
    其中
    Figure PCTCN2021137429-appb-100013
    以及
    Figure PCTCN2021137429-appb-100014
  11. 一种电子装置，其特征在于，包括：
    芯片，具有正输出端及负输出端，所述正输出端用于输出芯片发射端正端信号，所述负输出端用于输出芯片发射端负端信号；以及
    如权利要求1至10中任一项所述的天线网络，其中所述芯片的所述正输出端耦接所述天线网络的所述EMC滤波器的所述正输入端，所述芯片的所述负输出端耦接所述天线网络的所述EMC滤波器的所述负输入端。
PCT/CN2021/137429 2021-04-08 2021-12-13 天线网络及相关电子装置 WO2022213649A1 (zh)

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CN102999670A (zh) * 2012-11-30 2013-03-27 复旦大学 13.56MHz RFID读卡器近场天线的设计方法
CN108399345A (zh) * 2017-02-06 2018-08-14 恩智浦有限公司 具有自动调谐器的nfc读取器
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